diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180J484_devkit/ddr3_controller.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180J484_devkit/ddr3_controller.vh new file mode 100644 index 0000000000000000000000000000000000000000..6071a69babf8603642e62a67dbc153dd4c23fab8 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180J484_devkit/ddr3_controller.vh @@ -0,0 +1,49 @@ +`define DDR3_MODE 2 +`define READ_ENABLE_PIPELINE 7 +`define RAM_IDLE 9'd0 +`define RAM_ACT 9'd3 +`define RAM_WR 9'd8 +`define RAM_RD 9'd10 +`define RAM_RD2PREA 9'd12 +`define RAM_WR2PREA 9'd18 +`define RAM_ACT2PREA 9'd28 +`define RAM_WR2RD 9'd38 +`define RAM_RD2WR 9'd45 +`define RAM_PREA2REF 9'd48 +`define RAM_REF 9'd58 +`define RAM_NOP 9'd130 +`define RAM_WPAW 9'd132 +`define RAM_WPAR 9'd148 +`define RAM_RPAW 9'd164 +`define RAM_RPAR 9'd173 +`define RAM_SRE 9'd182 +`define RAM_SR 9'd184 +`define RAM_SRX 9'd186 +`define RAM_RZQS 9'd258 +`define RAM_INIT 9'd291 +`define RAM_WAITING 9'd380 +`define BRAM_LEN 384 +`define BRAM_I_WIDTH 9 +`define BRAM_D_WIDTH 72 +`define MICRO_SEC 400 +`define REF_INTERVAL 3120 +`define DRAM_WIDTH 16 +`define GROUP_WIDTH 8 +`define DRAM_GROUP 2 +`define DM_BIT_WIDTH 16 +`define ROW 16 +`define COL 10 +`define BANK 3 +`define BA_BIT_WIDTH 8 +`define WFIFO_WIDTH 128 +`define BL 8 +`define usReset 200 +`define usCKE 500 +`define tZQinit 512 +`define tZQCS 16'd1024 +`define ODTH8 6 +`define tRL 5 +`define tWL 5 +`define ARBITER_INIT 1 +`define ARBITER_COUNT 4 +`define RAM_FILE "ddr3_controller.bin" diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180J484_devkit/example_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180J484_devkit/example_top.v new file mode 100644 index 0000000000000000000000000000000000000000..079de7421d32fa3f0278c2d4fac7369606b59391 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180J484_devkit/example_top.v @@ -0,0 +1,425 @@ +`include "ddr3_controller.vh" + +module example_top +( +input clk, +input ddr_core_clk, +input ddr_twd_clk, +input ddr_tdqss_clk, +input ddr_tac_clk, +input reset_n, //active_low +input pll_lock, //pll_lock +input pll1_lock, //pll1_lock + +output ddr_pll_rstn, +output sys_pll_rstn, + +output ddr_reset, +output ddr_cs, +output ddr_ras, +output ddr_cas, +output ddr_we, +output ddr_cke, +output [15:0]ddr_addr, +output [2:0]ddr_ba, +output ddr_odt, +output [`DRAM_GROUP-1'b1:0] o_ddr_dm_hi, +output [`DRAM_GROUP-1'b1:0] o_ddr_dm_lo, + +input [`DRAM_GROUP-1'b1:0]i_ddr_dqs_hi, +input [`DRAM_GROUP-1'b1:0]i_ddr_dqs_lo, +output [`DRAM_GROUP-1'b1:0]o_ddr_dqs_hi, +output [`DRAM_GROUP-1'b1:0]o_ddr_dqs_lo, +output [`DRAM_GROUP-1'b1:0]o_ddr_dqs_oe, + +input [`DRAM_GROUP-1'b1:0] i_ddr_dqs_n_hi, +input [`DRAM_GROUP-1'b1:0] i_ddr_dqs_n_lo, +output [`DRAM_GROUP-1'b1:0] o_ddr_dqs_n_hi, +output [`DRAM_GROUP-1'b1:0] o_ddr_dqs_n_lo, +output [`DRAM_GROUP-1'b1:0] o_ddr_dqs_n_oe, + +input [`DRAM_WIDTH-1'b1:0] i_ddr_dq_hi, +input [`DRAM_WIDTH-1'b1:0] i_ddr_dq_lo, + +output [`DRAM_WIDTH-1'b1:0] o_ddr_dq_hi, +output [`DRAM_WIDTH-1'b1:0] o_ddr_dq_lo, + +output [`DRAM_WIDTH-1'b1:0] o_ddr_dq_oe, + +output [2:0] ddr_shift, +output [4:0] ddr_shift_sel, +output ddr_shift_ena, + +output wire ddr_cal_done, +output wire ddr_cal_pass, +output wire pass, +output wire done +); + +//parameter DDR3_MODE = `DDR3_MODE; //1-Native, 2-AXI4 + +assign ddr_pll_rstn = 1'b1; +assign sys_pll_rstn = 1'b1; + +wire w_nrst; +assign w_nrst = (reset_n && pll_lock && pll1_lock); + +wire [2:0] cal_shift_val; +wire [7:0] cal_fail_log; +wire w_wr_busy; +wire [`WFIFO_WIDTH-1'b1:0]w_wr_data; +wire [`DM_BIT_WIDTH-1'b1:0]w_wr_datamask; +wire [31:0]w_wr_addr; +wire w_wr_en; +wire w_wr_ack; + +wire w_rd_busy; +wire [31:0] w_rd_addr; +wire w_rd_en; +wire [`WFIFO_WIDTH-1'b1:0]w_rd_data; +wire w_rd_valid; + +wire w_cal_done; + +assign ddr_cal_done = w_cal_done; + +parameter START_ADDR = 32'h000000; +`ifdef RTL_SIM + parameter END_ADDR = 32'h0000100; +`else + parameter END_ADDR = 32'h1ffffff; +`endif + +generate + if (`DDR3_MODE == 1) //Native + begin + memory_checker_native #( + .START_ADDR(START_ADDR), + .END_ADDR(32'h0008000) + ) u0( + .clk (clk), + .reset_n (w_nrst), + .test_start (w_cal_done), + .wr_busy (w_wr_busy), + .wr_data (w_wr_data), + .wr_datamask(w_wr_datamask), + .wr_addr (w_wr_addr), + .wr_en (w_wr_en), + .wr_ack (w_wr_ack), + + .rd_busy (w_rd_busy), + .rd_addr (w_rd_addr), + .rd_en (w_rd_en), + .rd_data (w_rd_data), + .rd_valid (w_rd_valid), + + .test_pass (pass), + .test_done (done) + ); + + DdrCtrl u1 + ( + .clk (clk), + .core_clk (ddr_core_clk), + .tac_clk (ddr_tac_clk), + .twd_clk (ddr_twd_clk), + .tdqss_clk (ddr_tdqss_clk), + .reset_n (w_nrst), + + .reset (ddr_reset), + .cs (ddr_cs), + .ras (ddr_ras), + .cas (ddr_cas), + .we (ddr_we), + .cke (ddr_cke), + .addr (ddr_addr), + .ba (ddr_ba), + .odt (ddr_odt), + .o_dm_hi (o_ddr_dm_hi), + .o_dm_lo (o_ddr_dm_lo), + + .i_dq_hi (i_ddr_dq_hi), + .i_dq_lo (i_ddr_dq_lo), + + .o_dq_hi (o_ddr_dq_hi), + .o_dq_lo (o_ddr_dq_lo), + .o_dq_oe (o_ddr_dq_oe), + .i_dqs_hi (i_ddr_dqs_hi), + .i_dqs_lo (i_ddr_dqs_lo), + .i_dqs_n_hi (i_ddr_dqs_n_hi), + .i_dqs_n_lo (i_ddr_dqs_n_lo), + + .o_dqs_hi (o_ddr_dqs_hi), + .o_dqs_lo (o_ddr_dqs_lo), + .o_dqs_n_hi (o_ddr_dqs_n_hi), + .o_dqs_n_lo (o_ddr_dqs_n_lo), + + .o_dqs_oe (o_ddr_dqs_oe), + .o_dqs_n_oe (o_ddr_dqs_n_oe), + + .wr_busy (w_wr_busy), + .wr_data (w_wr_data), + .wr_datamask(w_wr_datamask), + .wr_addr (w_wr_addr), + .wr_en (w_wr_en), + .wr_addr_en (w_wr_en), + .wr_ack (w_wr_ack), + + .rd_busy (w_rd_busy), + .rd_addr (w_rd_addr), + .rd_addr_en (w_rd_en), + .rd_en (1'b1), + .rd_data (w_rd_data), + .rd_valid (w_rd_valid), + .rd_ack (), + + .shift(ddr_shift), + .shift_sel(ddr_shift_sel), + .shift_ena(ddr_shift_ena), + .cal_ena(1'b1), + .cal_done(w_cal_done), + .cal_pass(ddr_cal_pass) + ); + end + else //AXI4 + begin + wire reset; + wire io_systemReset; + wire io_memoryReset; + + wire io_memoryResetn; + wire [1:0] io_ddrA_b_payload_resp=2'b00; + wire axi4Interrupt; + wire [7:0] axi_awid; + wire [31:0] axi_awaddr; + wire [7:0] axi_awlen; + wire [2:0] axi_awsize; + wire [1:0] axi_awburst; + wire axi_awlock; + wire [3:0] axi_awcache; + wire [2:0] axi_awprot; + wire [3:0] axi_awqos; + wire [3:0] axi_awregion; + wire axi_awvalid; + wire axi_awready; + wire [31:0] axi_wdata; + wire [3:0] axi_wstrb; + wire axi_wvalid; + wire axi_wlast; + wire axi_wready; + wire [7:0] axi_bid; + wire [1:0] axi_bresp; + wire axi_bvalid; + wire axi_bready; + wire [7:0] axi_arid; + wire [31:0] axi_araddr; + wire [7:0] axi_arlen; + wire [2:0] axi_arsize; + wire [1:0] axi_arburst; + wire axi_arlock; + wire [3:0] axi_arcache; + wire [2:0] axi_arprot; + wire [3:0] axi_arqos; + wire [3:0] axi_arregion; + wire axi_arvalid; + wire axi_arready; + wire [7:0] axi_rid; + wire [31:0] axi_rdata; + wire [1:0] axi_rresp; + wire axi_rlast; + wire axi_rvalid; + wire axi_rready; + wire userInterrupt_0; + wire [15:0] io_apbSlave_0_PADDR; + wire io_apbSlave_0_PSEL; + wire io_apbSlave_0_PENABLE; + wire io_apbSlave_0_PREADY; + wire io_apbSlave_0_PWRITE; + wire [31:0] io_apbSlave_0_PWDATA; + wire [31:0] io_apbSlave_0_PRDATA; + wire io_apbSlave_0_PSLVERROR; + wire [7:0] m_aid_0; + wire [31:0] m_aaddr_0; + wire [7:0] m_alen_0; + wire [2:0] m_asize_0; + wire [1:0] m_aburst_0; + wire [1:0] m_alock_0; + wire m_avalid_0; + wire m_aready_0; + wire m_awready_0; + wire m_arready_0; + wire m_atype_0; + wire [7:0] m_wid_0; + wire [`WFIFO_WIDTH-1'b1:0] m_wdata_0; + wire [`DM_BIT_WIDTH-1'b1:0] m_wstrb_0; + wire m_wlast_0; + wire m_wvalid_0; + wire m_wready_0; + wire [7:0] m_rid_0; + wire [`WFIFO_WIDTH-1'b1:0] m_rdata_0; + wire m_rlast_0; + wire m_rvalid_0; + wire m_rready_0; + wire [1:0] m_rresp_0; + wire [7:0] m_bid_0; + wire [1:0] m_bresp_0; + wire m_bvalid_0; + wire m_bready_0; + wire m_awvalid_0; + wire m_arvalid_0; + wire m_pass_0; + wire m_start_0; + wire io_axiMasterReset_0; + wire io_ddrA_arw_valid; + wire io_ddrA_arw_ready; + wire [31:0] io_ddrA_arw_payload_addr; + wire [7:0] io_ddrA_arw_payload_id; + wire [7:0] io_ddrA_arw_payload_len; + wire [2:0] io_ddrA_arw_payload_size; + wire [1:0] io_ddrA_arw_payload_burst; + wire [1:0] io_ddrA_arw_payload_lock; + wire io_ddrA_arw_payload_write; + wire [7:0] io_ddrA_w_payload_id; + wire io_ddrA_w_valid; + wire io_ddrA_w_ready; + wire [127:0] io_ddrA_w_payload_data; + wire [15:0] io_ddrA_w_payload_strb; + wire io_ddrA_w_payload_last; + wire io_ddrA_b_valid; + wire io_ddrA_b_ready; + wire [7:0] io_ddrA_b_payload_id; + wire io_ddrA_r_valid; + wire io_ddrA_r_ready; + wire [127:0] io_ddrA_r_payload_data; + wire [7:0] io_ddrA_r_payload_id; + wire [1:0] io_ddrA_r_payload_resp; + wire io_ddrA_r_payload_last; + wire dyn_pll_phase_en; + wire [2:0] dyn_pll_phase_sel; + + + assign io_memoryResetn = w_nrst; + + memory_checker_axi #( + .START_ADDR(START_ADDR), + .STOP_ADDR(END_ADDR), + .ALEN(63), + .WIDTH(`WFIFO_WIDTH) + ) memcheck_0 ( + .axi_clk(clk), + .rstn(io_memoryResetn), + .start(w_cal_done), + .aid(m_aid_0), + .aaddr(m_aaddr_0), + .alen(m_alen_0), + .asize(m_asize_0), + .aburst(m_aburst_0), + .alock(m_alock_0), + .avalid(m_avalid_0), + .aready(m_aready_0), + .atype(m_atype_0), + .wid(m_wid_0), + .wdata(m_wdata_0), + .wstrb(m_wstrb_0), + .wlast(m_wlast_0), + .wvalid(m_wvalid_0), + .wready(m_wready_0), + .rid(m_rid_0), + .rdata(m_rdata_0), + .rlast(m_rlast_0), + .rvalid(m_rvalid_0), + .rready(m_rready_0), + .rresp(m_rresp_0), + .bid(m_bid_0), + .bvalid(m_bvalid_0), + .bready(m_bready_0), + .pass(pass), + .done(done) + ); + + + + DdrCtrl inst_ddr3_axi + ( + .core_clk (ddr_core_clk), + .tac_clk (ddr_tac_clk), + .twd_clk (ddr_twd_clk), + .tdqss_clk (ddr_tdqss_clk), + + + .reset (ddr_reset), + .cs (ddr_cs), + .ras (ddr_ras), + .cas (ddr_cas), + .we (ddr_we), + .cke (ddr_cke), + .addr (ddr_addr), + .ba (ddr_ba), + .odt (ddr_odt), + .o_dm_hi (o_ddr_dm_hi), + .o_dm_lo (o_ddr_dm_lo), + + .i_dq_hi (i_ddr_dq_hi), + .i_dq_lo (i_ddr_dq_lo), + + .o_dq_hi (o_ddr_dq_hi), + .o_dq_lo (o_ddr_dq_lo), + + .o_dq_oe (o_ddr_dq_oe), + + .i_dqs_hi (i_ddr_dqs_hi), + .i_dqs_lo (i_ddr_dqs_lo), + .i_dqs_n_hi (i_ddr_dqs_n_hi), + .i_dqs_n_lo (i_ddr_dqs_n_lo), + + + .o_dqs_hi (o_ddr_dqs_hi), + .o_dqs_lo (o_ddr_dqs_lo), + .o_dqs_n_hi (o_ddr_dqs_n_hi), + .o_dqs_n_lo (o_ddr_dqs_n_lo), + + .o_dqs_oe (o_ddr_dqs_oe), + .o_dqs_n_oe (o_ddr_dqs_n_oe), + + .clk(clk), + .reset_n(io_memoryResetn), + .axi_avalid(m_avalid_0), + .axi_aready(m_aready_0), + .axi_aaddr(m_aaddr_0), + .axi_aid(m_aid_0), + .axi_alen(m_alen_0), + .axi_asize(m_asize_0), + .axi_aburst(m_aburst_0), + .axi_alock(m_alock_0), + .axi_atype(m_atype_0), + + .axi_wid(m_wid_0), + .axi_wvalid(m_wvalid_0), + .axi_wready(m_wready_0), + .axi_wdata(m_wdata_0), + .axi_wstrb(m_wstrb_0), + .axi_wlast(m_wlast_0), + + .axi_bvalid(m_bvalid_0), + .axi_bready(m_bready_0), + .axi_bid(m_bid_0), + .axi_bresp(), + + .axi_rvalid(m_rvalid_0), + .axi_rready(m_rready_0), + .axi_rdata(m_rdata_0), + .axi_rid(m_rid_0), + .axi_rresp(m_rresp_0), + .axi_rlast(m_rlast_0), + + .shift(ddr_shift), + .shift_sel(ddr_shift_sel), + .shift_ena(ddr_shift_ena), + .cal_ena(1'b1), + .cal_done(w_cal_done), + .cal_pass(ddr_cal_pass) + ); + end +endgenerate + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180J484_devkit/memory_checker_axi.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180J484_devkit/memory_checker_axi.v new file mode 100644 index 0000000000000000000000000000000000000000..d02695fbba92325548d896f5ca89c30ab10f2c57 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180J484_devkit/memory_checker_axi.v @@ -0,0 +1,343 @@ +module memory_checker_axi #( + parameter WIDTH = 32, + parameter ALEN = 23, + parameter START_ADDR = 32'h00000000, + parameter STOP_ADDR = 32'h00100000, + parameter ADDR_OFFSET = (ALEN + 1)*(WIDTH/8) +) ( +input axi_clk, +input rstn, +input start, +output reg [7:0] aid, +output reg [31:0] aaddr, +output reg [7:0] alen, +output reg [2:0] asize, +output reg [1:0] aburst, +output reg [1:0] alock, +output reg avalid, +input aready, +output reg atype, + +output reg [7:0] wid, +output reg [WIDTH-1:0] wdata, +output [WIDTH/8-1:0] wstrb, +output reg wlast, +output reg wvalid, +input wready, + +input [7:0] rid, +input [WIDTH-1:0] rdata, +input rlast, +input rvalid, +output reg rready, +input [1:0] rresp, + +input [7:0] bid, +input bvalid, +output reg bready, +output pass, + +output reg done + +); + +/////////////////////////////////////////////////////////////////////////////// +localparam ASIZE = (WIDTH == 256)? 5 : + (WIDTH == 128)? 4 : + (WIDTH == 64)? 3 : 2; + +//Main states +localparam COMPARE_WIDTH = WIDTH; +localparam IDLE = 4'b0000, + WRITE_ADDR = 4'b0001, + PRE_WRITE = 4'b0010, + WRITE = 4'b0011, + POST_WRITE = 4'b0100, + READ_ADDR = 4'b0101, + PRE_READ = 4'b0110, + READ_COMPARE = 4'b0111, + POST_READ = 4'b1000, + DONE = 4'b1001; + +//reg [3:0] states, nstates; +reg fail; +//reg done; +reg [3:0] states; +reg [3:0] nstates; +reg bvalid_done; +reg [1:0] start_sync; +reg [8:0] write_cnt, read_cnt; +reg [WIDTH-1:0] rdata_store; +reg wburst_done, + rburst_done, + write_done, + read_done; + +/////////////////////////////////////////////////////////////////////////////// + //assign aid = 8'h00; + assign wstrb = {WIDTH/8{1'b1}}; + //assign wid = 8'h00; + assign pass = done & ~fail; + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + start_sync <= 2'b00; + end else begin + start_sync[0] <= start; + start_sync[1] <= start_sync[0]; + end + end + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + states <= IDLE; + end else begin + states <= nstates; + end + end + + always @(states or start_sync[1] or write_cnt or rburst_done or write_done or read_done or bvalid_done or aready) + begin + case(states) + IDLE : + if (start_sync[1]) + nstates = WRITE_ADDR; + else + nstates = IDLE; + WRITE_ADDR : + if (aready) + nstates = PRE_WRITE; + else + nstates = WRITE_ADDR; + PRE_WRITE : + nstates = WRITE; + WRITE : + if (write_cnt == 9'd0) + nstates = POST_WRITE; + else + nstates = WRITE; + POST_WRITE : + if (write_done & bvalid_done) + nstates = READ_ADDR; + else if (bvalid_done) + nstates = WRITE_ADDR; + else + nstates = POST_WRITE; + READ_ADDR : + if (aready) + nstates = PRE_READ; + else + nstates = READ_ADDR; + PRE_READ : + nstates = READ_COMPARE; + READ_COMPARE : + if (rburst_done) + nstates = POST_READ; + else + nstates = READ_COMPARE; + POST_READ : + if (read_done) + nstates = DONE; + else + nstates = READ_ADDR; + DONE : + nstates = DONE; + default : + nstates = IDLE; + endcase + end + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + aaddr <= START_ADDR; + avalid <= 1'b0; + atype <= 1'b0; + aburst <= 2'b00; + asize <= 3'b000; + alen <= 8'd0; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + write_done <= 1'b0; + wdata <= {WIDTH{1'b0}}; + aid <= 3; + wid <= 0; + wburst_done <= 1'b0; + wlast <= 1'b0; + bready <= 1'b0; + fail <= 1'b0; + done <= 1'b0; + rready <= 1'b0; + bvalid_done <=1'b0; + end + else + begin + if (states == IDLE) + begin + aaddr <= START_ADDR; + avalid <= 1'b0; + atype <= 1'b0; + aburst <= 2'b00; + asize <= 3'b000; + alen <= 8'd0; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + wdata <= {WIDTH{1'b0}}; + aid <= aid; + wid <= 0; + wburst_done <= 1'b0; + wlast <= 1'b0; + bready <= 1'b0; + rready <= 1'b0; + bvalid_done <= 1'b0; + //fail <= 1'b0; + done <= 1'b0; + end + if (states == WRITE_ADDR) + begin + avalid <= 1'b1; + atype <= 1'b1; + asize <= ASIZE; + alen <= ALEN; + aburst <= 2'b01; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + wburst_done <= 1'b0; + bvalid_done <= 1'b0; + bready <= 1'b0; + rready <= 1'b0; + done <= 1'b0; + //fail <= 1'b0; + end + if (states == PRE_WRITE) + begin + avalid <= 1'b0; + atype <= 1'b0; + wvalid <= 1'b1; + wdata <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~write_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{write_cnt[7:0]}}}; + wid <= aid; + bready <= 1'b1; + write_cnt <= write_cnt - 1; + if(alen == 'd0) + begin + wlast <= 1'b1; + end + end + if (states == WRITE) + begin + if (wready == 1'b1) + begin + wdata <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~write_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{write_cnt[7:0]}}}; + if (write_cnt == 9'd0) + begin + wburst_done <= 1'b1; + wlast <= 1'b0; + wvalid <= 1'b0; + if (aaddr >= STOP_ADDR) + begin + write_done <= 1'b1; + end else + begin + write_done <= 1'b0; + end + end + if (write_cnt == 9'd1) + begin + wlast <= 1'b1; + write_cnt <= write_cnt - 1; + end + + else + begin + write_cnt <= write_cnt - 1; + end + end + end + if (states == POST_WRITE) + begin + if (write_done) + begin + aaddr <= START_ADDR; + end + else + begin + if (bvalid && (bid==aid)) begin + aaddr <= aaddr + ADDR_OFFSET; + aid <= aid + 1; + end + end + if (wready == 1'b1) + begin + wlast <= 1'b0; + wvalid <= 1'b0; + end + if (bvalid && (bid==aid)) + begin + bvalid_done <= 1'b1; + bready <= 1'b0; + end + end + if (states == READ_ADDR) + begin + avalid <= 1'b1; + read_cnt <= ALEN + 1; + + end + if (states == PRE_READ) + begin + avalid <= 1'b0; + rburst_done <= 1'b0; + rdata_store <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~read_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{read_cnt[7:0]}}}; + read_cnt <= read_cnt - 1'b1; + end + if (states == READ_COMPARE) + begin + rready <= 1'b1; + if (read_cnt != 9'd0) + begin + if (rvalid == 1'b1) + begin + rdata_store <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~read_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{read_cnt[7:0]}}}; + read_cnt <= read_cnt - 1'b1; + if (rdata[COMPARE_WIDTH-1:0] !== rdata_store[COMPARE_WIDTH-1:0]) + fail <= 1'b1; + end + + end + end + if (read_cnt == 9'd0) + begin + if (rvalid == 1'b1) + begin + if (rdata[COMPARE_WIDTH-1:0] !== rdata_store[COMPARE_WIDTH-1:0]) + begin + fail <= 1'b1; + end + if (aaddr >= STOP_ADDR && (rid==aid)) + begin + read_done <= 1'b1; + end + else + begin + read_done <= 1'b0; + end + rburst_done <= 1'b1; + end + end + if (states == POST_READ) + begin + aaddr <= aaddr + ADDR_OFFSET; + rready <= 1'b1; + end + if (states == DONE) + begin + done <= 1'b1; + end + end + end +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/DdrCtrl.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/DdrCtrl.v new file mode 100644 index 0000000000000000000000000000000000000000..19245f7ff3e5255d6a750df855069494b1c0cd93 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/DdrCtrl.v @@ -0,0 +1,2862 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.1.150 +// IP Version: 5.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _759dabd995c04ec98cc1efefa92c75d4 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module DdrCtrl ( +input clk, +input core_clk, +input twd_clk, +input tdqss_clk, +input tac_clk, +input reset_n, +output reset, +output cs, +output ras, +output cas, +output we, +output cke, +output [15:0] addr, +output [2:0] ba, +output odt, +output [2:0] shift, +output [4:0] shift_sel, +output shift_ena, +input cal_ena, +output cal_done, +output cal_pass, +output [6:0] cal_fail_log, +output [2:0] cal_shift_val, +output [1:0] o_dm_hi, +output [1:0] o_dm_lo, +input [1:0] i_dqs_hi, +input [1:0] i_dqs_lo, +input [1:0] i_dqs_n_hi, +input [1:0] i_dqs_n_lo, +output [1:0] o_dqs_hi, +output [1:0] o_dqs_lo, +output [1:0] o_dqs_n_hi, +output [1:0] o_dqs_n_lo, +output [1:0] o_dqs_oe, +output [1:0] o_dqs_n_oe, +input [15:0] i_dq_hi, +input [15:0] i_dq_lo, +output [15:0] o_dq_hi, +output [15:0] o_dq_lo, +output [15:0] o_dq_oe, +input [7:0] axi_aid, +input [31:0] axi_aaddr, +input [7:0] axi_alen, +input [2:0] axi_asize, +input [1:0] axi_aburst, +input [1:0] axi_alock, +input axi_avalid, +output axi_aready, +input axi_atype, +input [7:0] axi_wid, +input [127:0] axi_wdata, +input [15:0] axi_wstrb, +input axi_wlast, +input axi_wvalid, +output axi_wready, +output [7:0] axi_rid, +output [127:0] axi_rdata, +output axi_rlast, +output axi_rvalid, +input axi_rready, +output [1:0] axi_rresp, +output [7:0] axi_bid, +output [1:0] axi_bresp, +output axi_bvalid, +input axi_bready +); +`IP_MODULE_NAME(efx_ddr3_soft_controller) u_efx_ddr3_soft_controller( +.clk ( clk ), +.core_clk ( core_clk ), +.twd_clk ( twd_clk ), +.tdqss_clk ( tdqss_clk ), +.tac_clk ( tac_clk ), +.reset_n ( reset_n ), +.reset ( reset ), +.cs ( cs ), +.ras ( ras ), +.cas ( cas ), +.we ( we ), +.cke ( cke ), +.addr ( addr ), +.ba ( ba ), +.odt ( odt ), +.shift ( shift ), +.shift_sel ( shift_sel ), +.shift_ena ( shift_ena ), +.cal_ena ( cal_ena ), +.cal_done ( cal_done ), +.cal_pass ( cal_pass ), +.cal_fail_log ( cal_fail_log ), +.cal_shift_val ( cal_shift_val ), +.o_dm_hi ( o_dm_hi ), +.o_dm_lo ( o_dm_lo ), +.i_dqs_hi ( i_dqs_hi ), +.i_dqs_lo ( i_dqs_lo ), +.i_dqs_n_hi ( i_dqs_n_hi ), +.i_dqs_n_lo ( i_dqs_n_lo ), +.o_dqs_hi ( o_dqs_hi ), +.o_dqs_lo ( o_dqs_lo ), +.o_dqs_n_hi ( o_dqs_n_hi ), +.o_dqs_n_lo ( o_dqs_n_lo ), +.o_dqs_oe ( o_dqs_oe ), +.o_dqs_n_oe ( o_dqs_n_oe ), +.i_dq_hi ( i_dq_hi ), +.i_dq_lo ( i_dq_lo ), +.o_dq_hi ( o_dq_hi ), +.o_dq_lo ( o_dq_lo ), +.o_dq_oe ( o_dq_oe ), +.axi_aid ( axi_aid ), +.axi_aaddr ( axi_aaddr ), +.axi_alen ( axi_alen ), +.axi_asize ( axi_asize ), +.axi_aburst ( axi_aburst ), +.axi_alock ( axi_alock ), +.axi_avalid ( axi_avalid ), +.axi_aready ( axi_aready ), +.axi_atype ( axi_atype ), +.axi_wid ( axi_wid ), +.axi_wdata ( axi_wdata ), +.axi_wstrb ( axi_wstrb ), +.axi_wlast ( axi_wlast ), +.axi_wvalid ( axi_wvalid ), +.axi_wready ( axi_wready ), +.axi_rid ( axi_rid ), +.axi_rdata ( axi_rdata ), +.axi_rlast ( axi_rlast ), +.axi_rvalid ( axi_rvalid ), +.axi_rready ( axi_rready ), +.axi_rresp ( axi_rresp ), +.axi_bid ( axi_bid ), +.axi_bresp ( axi_bresp ), +.axi_bvalid ( axi_bvalid ), +.axi_bready ( axi_bready ) +); + +endmodule + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Ymj2DTlbQ+q2+jIGCla0e+DIRaR+VTgkZZHZqOzTxQcmlfe2Cebd8Zl11ie3atgQ +cRmqB2Ylkhc0KQeeYKXY3W3lt3P49ypUrtjMb5xgMFFe6pV5Ywc8j1X2wgG5v5p3 +JGjoMVkr2EYg7m7C5IDADe4CXSLNOdb7C4PN8pknO7la2v1idiAz4UH6RDkq0xWt +AJIGlfjR4FFvhFJs7lzxXejidGmHNHX71A4fdvBXIQxP9msZVGN0XZ6pptddLJ0B +3a9V7m2kNZ1978rDo1C/2d8XRwRlRLG4EIl8soadt+G8RUq0E/yON4BJ9pZ+i94X +WwQqWrkz60DXpCLqZbeQeQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 672 ) +`pragma protect data_block +fFDA4MxIMtGkUXiomLt3KDtOAG3CYn38FuyI49EAwpqwbsiOSVLiCUfe34aXlJuC +8eY1ZKq6HVsxB4dWYgmYfSR4X/pO62mql8sMw7eeTiIhpEWquEWeVhS6la22IkNo +pWb1RRXQMkduvji5iolaP/IoVXOQr1os15e7WyTi49Mfo1bngwX91xWMHXGI70dG +f76tDYc8OCywiy1b+r5vB0RwUGAoJ9XSfiJ4m9txIR8tpUxIsT1KAeJ47N/UpbB2 +LcOrQWESqQBLhCf5FrjETg2HY/kvcNrUha9VgOpj8KwF1HJ+JpQTi6fiACltyV9/ +Ju9NDskpi3gvw9EjChPpqjUhhAr/hCotJimjkEuTBQoueoe97h89438VYcex/6b4 +aTELuXa4GKYGcPx3lPdu2tlv3DeXpJ6oxh7IQSgiriKudOJvJQgygXLqQZjHeu5a +VKYQyV7/oHpXjQpa75/MEBeC/JQ5/BrkNwKuFzm/I6ilGWiqsXVXdHaohBDMa+b+ +uBjOlqS5SbUvgnStO+C3r/WAzwEtYKNeOsKMY4nP1n/fNMHVAPHb+YjOf6jlNviJ +Nw2RLG1ehPxybQFxEclrwtrG6aMu4Fs5zEesweQG6bv6UL98u9UW4jFOfVJasExt +kBcPR/k04SqUe+0jwMOHIP2UjscwVhD/sJcAe2flvlI2712hfFqc5tOMIoG7v32w +JSBGAuiaC7ULQIHQuCDp+q1hxgRXCE2Vo33ddr/d5MvUNzyQACseFbdz4QLi3l9n +tEEjwhuH2dig6cOwkZeWkv+tww/q58h2AaGtnjiRzky2jeoqfsXKILAM0z1UV5lS +pAQ4heWzzfb/TAjf7mHZtVC6ieIuIliNrMPGPaE3UiBOEgab2vXXl/FfTCkILinh +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Rb1iv6T4IMO5N0H/7mGpvIza+liSN+03Jyg5KwAKqR5rBNlEaYOF7vA5dx9vT2Pz +0JeCfBgUfXSbGQrPMT8tvAP5plh+Q1Ee0gpJrklQK4HtysZt7J7KyZMPNItm4dp2 +tI+dck4Q6irKwNbOv9iDyzkZhVp76Ad/b+SdHBbJ2DTy2mxw/V9JblFZSE20eR8C +GgvgcHpXYWGUZY3mtgrsvv0vIYRLFPXHopLgV9wXVNb0waCOOktvV535mBvsptGo +11miPZ8inWT0PGbCo68POKJPqM1hnCvVwzknIHU2x4l1nDUeHiI+4TqeRqxRI6c/ +IKalXd9iLTx1cY7aQvu5Bg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 672 ) +`pragma protect data_block +v9KZuk7EvUUXKMPs+Fq7gARsVn4RkZMAeebIDgaNkw0fTA4zLnPhrZ909jdTYbRK +CZglfVyhaPGINHW8A6tyln9oiXfR09+VFH/eCdXdvTJfS6t7M6cwiIKuCw3lv7EC +/Trosr7vm9W4jTly7Fc0inVQj3cnU0oJ50GVAsFWp7I6fMQiCh1B1VaCYAJJ3H3O +YgDx/mZHQjyJZyuENFTsumCyMT1qOvjP5srUhqjou/LcrTNRYw+DD2MGoN8loJx2 +BTXePFvtVjN3ryqxJWYRAzq4APVCLGZPiOPJ+Oc6puJgRFeWxnvFAD06etjoC8w+ +bBbJgy0Vfm623UAiLL8hJWPNByjKBiw6wUZlQVCpkNSUWN2JTdjk8XvH75epCCTr +qtas0oqMMsi8AjKoIPlGBTwB5R3TfVlu24Y+3wnbkungGDo7VtaU5GQKtmcMPOCh +n/bZSSrm2IvW0i5rsYVyUKT5R7K4Lhrvn8Bh0shj+u6minOqwlXYuM2WvENSbqGk +N0BDBQkCvv9xucY4nOyIGMkbRpBY9SkUORayrkSW1FYMvMtxt7+MArX+4WlCTVm2 +/qxmn18sMdXM23lm5gh7qtlVp5BnntRxCV30iRwmzkAfsDDpdGe0pda5xpCa9w7K +kevVWRjIGZTappuhkrMGXHTc/ij8DZqc0NzfeFVXj5WYeT/DD+plctGjbFcngIB9 +oJED2MSSTungoddch3i6KdldUP3J1jRh8UNFlXvJCCfD1xdg2oAq5/AA2WTnBYmQ +oS0iH2qJWLXPG5XhVcha7NVQGbdrj6CxPYvpLcxiv1jDe11lWx7Hryc3/aNFEjd2 +zvnllVTRx45OjK7M5TpxHCNgjT+4I9H2zIzAJoaQPD2exEg8h1q9leCcJms5kAzr +`pragma protect end_protected + +//pragma protect end + + +`include "ddr3_controller.vh" +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Yugc8IBRAqwYweEftHb2MRHj4RTc/bXO4yWpGmLDYlJEDZYOsyhyvaPsJQk+yHUH +arv8IdlGqbuNGkmLTWVAiuOTGqe9R/KxJNxqZPWi4OvVG2OHF53zcpTZFWme+OY6 +umQ26J8lkLDnrandFh4LqPdLSzbpLf1jfBOxa2g2S270aOOIWSWxgc3zwuxdyGAI +0XI8LLxIQ/i/2utMiF97vX6gxsO08+NYEg0wngUfsUXwsLTqwSRfywLXH2lm49g8 +a9vApvPdenfMVEQ5jCXy+2q7Sm2yAPS2ZOzNa4cK9j0Drf5acBig//rTD9D05Bs1 +7nVvKdZwZ7WSaNQfJr1+MQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 13504 ) +`pragma protect data_block +i8U3Zc1nhaMlPB58mRIuYgX6jR4nLTd1PJVUmmfQaO4czUtRt7yPq4z+5H3vCt+6 +Rr3v13t5h/9HBcFE8kcGrU1J+AAw4+gKOnxwlPpzRj41goCUn9jd9OtT71pHhJcO +8HjjneidReM6xlLffuhNGg8NIx+0kUd3Q1U330bt2HmY78f8rt14EVSrjstjOha1 +9jnqP8V9cXAroU7PeNMbI2ZCEmyGvERGE0cnhQi7hbmEPSFsiGQYR38l3ZHjbPPO +595GfIsxduCp0o+wd//O4Nwl4YGXjppYH5eSI7NYRzgyMSaHJAWDLnHpuI+j8VK7 +WEHvyMTeCS4D82nKQU14Y6OMJPE8qfFCEuiJEHNPAlpQwJxciSN39nNOXx1Y9NCU +ZL0mo4iNE8rH+VxPG0q8lc1a9ILxFyw1mcZwtrvru5Z/B+Xrwr8lIjbgv8+aRNie +ljtMcdZWikJs7b8eRaeBisLF/hE5ZianVN+s2YRjQmarfxijxrDfKp5+CuwEWV9L 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+Ny05v4lzS8v195nE1zQ0FLhRvZUZkOA90pxoIQ0B4ruFU5bLrcBIKnQ0HZLf2uh4 +rv5jm9RmoV4Qt4m82kGilhQ/akC+Mci7BWIXTjTsszQLfKQFk9AS+qWdXvrxqtht +D1dRMOnVzP56n8dd8XiwZCrhUtqSnlDYCX7EvrK00B1/roFpGYtORttyg4JCH37R +eJoU8dPc9mcMBuYqjLU68EPSqAllIGQeOm5loZUP5PZ36loM90X008uxg4kKh5y3 +whVuxZZcc4BvPiUmFKCBNwy/1/4K8E7NntX/rpmcihNa4nr3veTLkDX1qFEL9Glo +NaSF931bIMyCGxG1miiBXMZucsoyV2sso/ywSkFc3HK0U5I9N1v7NG+zAQhIaW6A +3vk7Vw31MB/V0eKF0/hepOP5Y8SibI7d5wRK9rrLKHHjnEvFlgY6oT0nSGUcJmQg ++fJkkuN9XtpqsAMcsNxFpOVOT9CLxTVbQoz7jHmC4dy/wFLdenzHu2v0x4w3mTA/ +sdaMq3BnNZlAUWfiyA2KDtdLXREWFcxUiLSECQIe9hAmF4BL07KUoQ3uG983oAzD +Iea0PrgJCjvFKp5HZtIh8c7Zzk9pJeF6EUYw1NaT/M/MWGFR6jDF9yO6KjcjE/wi +XAHnyWM6xUgsm9x1gebtMSYZnwIopKjGvJ/DGc9cGvsZ2Kcr1RKyltD9CfCdkXFm +XW5XrdBYyIHQoLpFQhHhRthcySYXJtE8XHVSyEC9BaYh+3jkYJcDfHEWpP7m6byU +QQEXLBpFuOddfmR9lm/6EQSMD9uc6z0UU2MlXDkrNe4568OYPRlx9NC2Qqlv6LDN +4+mxURDvSDJ7NIgSwUFMfz6mAGTM8j9mKVfbcmRdMjb+3oDtDy7Rm3wyrqWWEOp0 +XVTyETu+xZ2wy2RJ5PeHts84g3i3ZHIBPc28d/YsGc2AL2UtKwjKWJTpMv40nBqO +nNryoy9Qkz9BM50aeRvPQ/J8Darjb9QO5K7PYZOwj6wLNfFcSPrL8Jtlnzqd6afU +AKNhxDRUwCSbtiqbxwY8TohQCdsRKbF5SmC/MqspbBSPUnyisbFR7qjoDoHpTmWl +tY7TfJ2t4cZF2yoDwykW8NnIF7JgMjdc1l/uciOTwF5kVkhC3DTVyDr0I4kCr8a2 +FMkEV6EScYv+BE5RjqYOCiolfJeDQtQCTI7J+MaLv2oLchumECkaswQ1Ux1mohUo +CdfqNTbFa3tds9dcs/KYS2EZ+j+7/Rs1VDUGLX5iYP0euhiWmDMZxasP80SdZCG/ +xVPTpBO5S3Ol9jQWeesmUlCGjbgxhwwhN4C569SgIbP89kP27Y3pWIO4KFYZFPpt +u8bAug7rsPSW5ok0gKXcFQK+rjSJo/AHw5Ek0xYh+j5gBHzYVyeQVGHHqCuIm0n8 +tMvv5PP0YkSLcRJDMYWzIYfkCKv1k4FCS7Cjb78kF9TPgB+wMJqGgvBL3KzB+h3t +otgeY4uIrmdjM4cKr0cRftiJV8BjugwN9O9rTxm/cb3b5tBSOhIq+lbhMxA8qU2L +7vOe7hYszjJn7+xmMTEH0ajx44NQrl5tTNxpUoVCe8m07Zd2kOsJ3MtIRKonQ6QO +2LWKJxwrB027ticxrr7PH0BN6XIYLpAOWuyQxtMvUj/C7WAD2Y6volgrwXkcOKZ9 +fGIHCpnrIH8MAGE6HqzRIEhHuXAhVTbxBhxjvykeN54RIKz8t2mtetonj9UtSjeC +dMvR+W7BBZVRV+Nq4Zb2H9P7cHDUPezOKoUXD+Fy3l1+9D7Djgf2jVQD5qOlokaU +NH7V0W2Ks1oQYZwsoTmtP5edL7QE3GlWkSkliC+5MVLUmzJOgSnPTggdESYwI4el +2Daps0A6HCc/rbeGFhV7H1UGQdwfQV7jey/jA5jP81glhyhF1hadMy7fqnky8I4R +5YoVeOhQwJ98jAIF4iH5+iOIy5i8J+bcQpz3YxAT1GKeZItSeWurgfp1bot7MVfZ +VwRWh7CDbhcSGAN4YiKbyVXRndA2JJfeVtBbq2lTCHt/wdK0I+oiy46bbbBPQemt +hrNPx7Os2UBvyPi850p47qpGxJA/oAhBZ7xQMgA1SJ435IBXsgmb7xJ5BnWQwYKi +XWexr3TuPApwMyhC7yYIAQ== +`pragma protect end_protected + +//pragma protect end + + +`include "ddr3_controller.vh" +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +QAbe2Xj4hTRaBeehzHb3hPu02D6Lc1ZLor6+HkwOD7gAGLNHLaUupItAu8crRSJ/ +9bcpHoQMMIjq3+Csko5cHZNvpsf5Glx5fOReUpX/Ew700WCEjAkIO0BAbOJEGBkB +BWNCwfK2CkuEaew4duJJhL13fRMHkwxY5lp9v+WpDtmntv/cVj1LtAc/iu2A/9nl +RGuaT9XqzuPMgQPD2yGcPccPPPX2YU+T7y4aGEtsqQjeuo0CV5ZTsup1jQ72L1Q2 +x83gq74onO7VLsS5HT+0E6XZ2Mhc3w0otMuvomGYmcds5yjoLapnBoDp4Nj/fYBQ +G8iekfcRLN0DDdIIxDCflg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 39184 ) +`pragma protect data_block +TMRi7Sr/NCbUolH14qCk9o3qDMKFa1Jx59vbeOz9UrnA1i3XktgI5OvAmD3NuP+E +06/LjLVx6Fj1d11PSz1qGML77DgaG8W+MVQxiABqI4/Vb4VFF4hpfnItBcYg7f4w +q4XQY/+FJYMXY769xgeu9wQSz5rfDNUVOB8U8q9pW7LGdD0aHBzYg50teGq5q7Kt +nw7k+ca2Qc1wmML7Ixdd70dUBdFmqjyKSTUD3Z5Dii138Gqr3ukKWLZX7yg/ZoGp +/LpbZGLAzM6oDoDzHEpZwDjuEkUoq6c0XPanl0U0AKNoEpAnnnYkM1A3dut1TgAF +9c3hMo0SFbUR+mxUKspTkl4DOWfhAJYSln9+Hj2zNV8mshK2pEAygOzzWxFVhSHR +eLiLCuKswHZAjDKTRk9LSRhGxLXu0X1dlXm5Bm/0rSkxvp95Lm9pdaB54+VQNsby +T977iSbJRVNgP6JjiDgRtP28ZW7vLMpqQ1FD6AVPe508j5mYa72+1msP6SojlJpS +GiVnqFLmJlbV0OxPpai80mxVxsPgC1CoZHAekZbFMokbD5CymYcW+kGUHS9+7PjM +PaNCbnAm1SX14LFZjBFkeQiIbcTuL8xBmHcptQHk4+J0DL1ThgJCtEB7MvDdOCXK +KYiXxAme6XCf0eY/HiYIA9ICP6xUGA5P0LKxNTv1GwxAqSaooTeRvalft2WvCS+n +me8HiH/l2HmcJC4N+DzXilBgn1Arzpj2Ocwf1wXtU9Cg8XKyCtEwK4SOb5pprvq0 +puNedIm4M352R6I2dhEMwvvjvdoNjby77seUByFtCndTpeetRU+OAZWEFPtLAGKK +HC1v7v5QFt7YSmOHBIxl9SlkfHxOXavrkGMOr2oeycrbEJ/5UU7gSy/L5V4htMp1 +DcagqaSysTnR40KV5mkcyqqA8S+U4bkT/k1nXZxGAmU/Sb0rLnShj9ad+YQrljVY +BGhVCcD3QnTENeEIgjF/ezJLXoVEvw/QdB4hO7VuGYhIPUqQ+I1fEBRCNwxi1FRv +4/G1uZSLOpWYB+Bh1zTFlj6eHP1uUA8TTTf6CUvl+UImosi5Zzjgb5MsoArmCVM6 +FbtnZ9s2EjICcV3bJbpK1ODtgx9G/vSmLzVHxDItSDnFxhHA98bRKzpARgtCzBY/ +lfDHqNP6qNs3tF/jAsCdO3ovgOcXllwZh6rKSAF5SgubHfyTIt8TDkdhcLfc6E6/ +BiooZVjFxBhivFuktnFOjHow33AJdRvEWoALf5fdY0uJyEgzuJl/OZTKNzsa1auL +qAkTTlOs9s8549k/wX6RrvSbnfdFqhehxiaK/XxLhtzUVv6soVcqsbdE0X7gRWKX +pM+f5uIXUpACgX89dKfJw8xdKKlCZReZ4EmAcoQvJ2EoFSkWMWRSbPESUfkiUsw+ +O3duwrfzipzVlwkZ80fijVQEuOjjwqq2FLIb/clkw5P2XE6ABeex/cawp8NkqXqx +p1j1uU5VSC1e+8zHZvIceAn1x3QselzrkPIIi0LYNsGypNBCTxYFvb6x0J2mIkgd +D3aQZ47pr+bhwvYVR4Vuce6HWDlnuRteu6OOtMz8Duc9BK4uNmHvgv1B9bd41xlb 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+6X3htMVhglfRnkNPVe2m8jpkFqu1Pd6c01yXinkKAXbIS5kU5hgva1u3a+24Z0PD +lmf4VSbaE21pomzp6KoCMDpDtoxaweFKZSKFvnTL3yy9EtfiLTQcW0anhGKsEXeS +oN2A7agyZybfMb5NaL8joOLKGq2AnqmRc6Z+7soBeTukIs60Bs0/cRQ6+I669An+ +PRC0DDGhZEo4sL+L29lg6tTLPKbal3Jo6PkN9u7eUs6dBJPndPGVgKSNqdLgHuvD +FdLXPg3MlL6HVFRlvtKL41eG5eCmkrWAo++bXGRd4YmgvPog9HwB44cqEDmgCGDn +GheUxRF2rprkTvu7uBfNfNE0d1vI/M6JhNWmyN05Dv+TsYvbCk42C/i79ORxJBoc +O3xFqY17nYGEDVrzYTO1v5mSsqKM+2JBVwsrSAPA/VtQPY6osOY6xgGCFEnwUnV0 +D3al4GbJFTvKs90smRQ4zD2xrZ9CpmL3NzgayHZeL3VNzEnrb6y3QkO6766AQwCf +Evp2/iQW3qYmqhagNUEgUqiArfacaegT/0lEJwEgIk6Lpt1KZ6Gg3rautp3VsRRL +N2dk5wnek7BkDzrE2SCVzi4cSB1tjtsK0xJxy/yslpTpStA8BPmbk7j3m4pGh/9g +0GTOQADVxb74P5CSSxprS+8eW99URbiB71FMXEUMgNrQDYkWQQAUdCUAu0Z+Ag87 +4Bsdi1JXGbs3iDa6LoV6LQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +eYFymb2WMzqsKoMbPCd0RU44pYCXUJuqKB3ZEuxDNbJdX/qZuNPXgO+jqHz56FPy +OZucEX71fBByK3Cu/sBy6ylQcS+PFPRaG9xpuww15TYm93ZTe3CdizLCQ4LMWQCC +hG0DSL8KMq0bZebRU6kBTyGDQOGaaY9rZFdD0UWR79xvlDiF7D/8ban8UjYQsE+T +H48yGdrUmRD2WCJIueUG4JVa72JuQPhGm1YV6bJfULU3gykxENL+9+uPov6BfGMj +DcC4OsRDjwjMDl8wdRzP2GPIVE7p6qVV4V6LC43RwFXMhY3gi6QDBCoKd8NVJPs5 +xSo/UZiVU8kqBNEbxzaZsw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5424 ) +`pragma protect data_block +C3MkQeZzXLX/iiMZxMxuJxtDgG3OhAi8XYVTVee1uVbY5U5/pEQMg0VQNZPobHbK +ymUqnJd+vIJj+NOj+me5l66WHqzvr0PV38HjO1OBL1/0Q5NQ4dcW8f5jKx0QJWxs +jXLyr2FfWRk/6fOn7Qf5rOGKyhbfSc7b1hVtqbL8PSYd7VloncdhXbWkJkMShkaZ +FuxMaNF/126RWGiTSq9+nCJ7oRPGMppB6iQRDstgbss+pGWicRZ8jawyU74Ef7xy +Ky1HxNj5Vp5gLp5LS43ph2LZJAJQLL0YsCXLIJHR9acHl+uqNs/Jb6vd89q248AR +pPcq7LVj6FWLPItvKC1Xogs8jUSZfpW0SlWSJU8osCqxKVTC81jDeJhmtc4G+apt +vU6Wf5uVBz2JFhi50cEtuLT/amjGEOce0Ns17AR9XB7SqyNou4s04bZxR0XZmCaa +2gu90cNeQaO+zE+R/1I2Qj5tY2opQP9X7XkSQs9ihIu6l5q4CDTEaJN4XJbhWj+I +E5djMSZx98YaJnAWyxP0Wu85RWvoLoFn5bMlFoXyvL5mcFJloxba8aCrWTIjHkoJ +jTS+q+CeYk4IKILBj8n4miiKskFpR1KGyqcOmFqzD4IV9hFLi5lXhhkqm/lDKGKC +XHQ9R6sve1z4ZX9GRAEbruYFU/6o2kTWh4qXqOL9ACkngI7h6CuG4DtLDoakibjj +D/4dBWgbFKhbPoJ7Y1UH0Xlq5ujfpnfnzpouU60KMJkMHHbWtJmtB8agIXKi37lR +IrUDtiUnfoIr1to5pP/YP/Qb3OTx0rs7diaZr0Hb1aQSE2w1C9ywxj1E5IkIGlky +tNz7IrC3dZ/nmyv70ywPVCPe1mP3hPi5W0e8LLWF+TLJeXYZBYLewQYI6CrU7ntz +Ec431PED+ca0HNfMPkhrdM4zY24VpW+eiBLv4WU1pAmIz1tvTpqr2wT861Sye6xd +kfWmSQKjbIwVDNF94XorOYBTF2Zm/B+r3ekbxO9aCKeGBqXBTt6p76+KyJsAMex9 ++b+r+y5Y5XJBn+k6SfBp0kxROTn/9SAAEbqMRCbni1eqAz1F9jyM27q3heeD5wyh +sPDWhr0kMynMPijsQl3tQJKzehRWPGc2DnvAH3k5d1pB9mdYVsfC/yMGuLmMOT+d +wO8YSTOwwRM6GkzeH7AQVBig5VjpW/++Vxvkn4SPeP2q5YGW5UY40n71OE2Uo0tx +i9JuIw0VGOH/JwNvnd2xhT6GuL0WofrdwL1STB20L93pe8pFq5cI0AsbeS5aBe8H +ubamPXmoNG338JWDxAn3SYA3UVuVytukXF2ix/QFv2D4CrAMn0KSCTPSKurlxteo +u0FGEKMrI9Q2a6vQ7hzPqYpVWNrvjpodX5LLfo0ASIVYi+PY2uYm6eXm80ZFMZhI +yS/LHCll52USqrjj4wZmVfJYd0A8CqQobjekvA7TRG2sfGFAgreZzV4HKB5fEdfX +zL6vtKKGweM8amm53V8ubkuZ/gaz0+0pscequSmoi5HP7XSiDj4ohrs7E3SrssM1 +dFLXR6lS4lpHHlgZkRo5dldu9/kmM0B4r25iI7NVKylwM3iw8Su5jKovVGnBRqw0 +ysz52Q/Dm5A2uFQoy9l7tonextMJiY+/5kUz//rVDORN5K/eCzSM4pIyAypYftwM +GWWRZOD+3/AJqCTB89wpEUvWC3wkpWNexEsdiuh1nOPM3LfiubWKZCXt2UjHFOmR +LOK5tV7ENTs83UzobEyfNnWVPGi2jpjgsfwyIfI2+u1ezJN4wKSo2p44BapoQcSB +InpGL6OKvVVJAYlGkAt42wUY+mdCgWBgw798Jcf/BS7NLxZo+WogCcNeEApAdJLu +T/Ws/DqJqV36Xb7lEJSWKsHRaKMy6om9nMKd0ICeTYDLZnuZhPii/wwGfNC0gWP+ +DoSfhi7tLvr5sOLBmlMVjxbhCa3C6w308qJEoBW5kQ3OfyWEUxVIV2wrU+Cf5UDk +1H57mhybf498js6Ru2vrlw/7OM6XIldWRgfkJ6asJj4ElreXKCyv3F7N0Pjs1QiK +i2ktUHewwQNtLM7Rd2m8f8Nm0FYdGzzKjZksMihsEGcIwtUrOXgazRmDWrom7xDg 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+z0nJ2fwKxmplDeO8wOXNkQpZnBKzTOgAJzx96XjtSSjpGj3Q4CNcmyQUjC0EmnoH +fRNL89tqQ/b2pMSRMB47ZFjooEx5M07DKqwFDAkOQ961YFaqLCLGyHuZVxtvZ86U ++8HpzA5bB5lKY9c4gMlk7Dep/3/itATv/X6aXcMTFX6kLmoAgu2bkAAj/jnF+YNm +2OL0hJHoheAC3Ca99OLWSPTqShfg5HbM/0+mjsPEcIbwO9kG9V4xwTbX7B2o95aP +h2P/eJ5Kq5OC/tyWzuLNigRl+BtYFWAJsV+BNh8wBmTqX9LFEZHcPTbq5WqnHroW +jL+stV9wAxeF+fSGR4rv9R2Usgjq2XDr7v0MworybLP/lWeg/vgAFVm/a8MjDM1+ +GjAJasDTomgv3TjEJ7/FVjzWDznYcCJ2bO1VfCNryc5bNvsnIE6P26gsnkeXzFu0 +lH8gLm2JT04KqFf3Zc+ssWGkFZUXwrTWgNWpbQeUbZKCLD+3bcwLITZRYUgwAOhi +iqDNfWqTxEKcbsslsP5IJEA5qv1qLuKKN0XKPBtufDP38XURAQBIQX3qhhdIvtw5 +SvbMUCwYjEkeBLt656gEvb8flxwLL1MLg10/YUhORK+Eiyc/xQrwqMHmxaG0Mc9M +9hs0rP7fTWPxYDtysdAJasejcgTwy6pTdh7oSeSL5m3+0A6PVzclitRWI814hzOz +jPKk9d1VFqq9fFNxDUQaUSbdMkPkIJ5r0rmzL1rCfm5rRlsY08Npmd84u63l983m +uTHXV9Y93CCDjCKG0lcOPgHeMnW9L0oYOt28xh4qr8PLeqMHia4NPv/+ltJiP5db +yoHeiwWmFtQm4crnJl4yQxvIlzH82ldLRZIoTa6mu+AQxUVUu0mPEzEUT8BtrgZ5 +IZarJ49dBa1bhFeN2fMfY3l0cFXvAf8IsjuGULdyl0PO39lqD8zA9rfPmV4PHcGt +WE+XYJMOaffh7ZQ9QfVW9P6T0ZltpnbkvZMcDs4fUlQFtKSltHY+LFHorrmqvoBT +iRngj+9GMRjmt7rC3Ny8gmI7Xk6mI8rMmqNqJsPIXUDWkEvKc1VzXe4PikjGgAbc +/rV6tMhJofOKi9d0Jp3qG+QW6cf0tloQyujFiJtFiu1FMIe1pYa36kvpQlwqhnVU +jSVBJhQBKSxqJGa3q6hgi47BRYM6y3U7Y5DHaS3ONMEifam3kjjs5xKDTtjy+TmK +0G7+m9ojHkFT7XAyQnr028MPm370fl74RhdxcbfsXl5QL1SFD7Xe+9xWFCNEqcUj +AL8TdPjp3uoAGyarZi7hBKWth+Pjlx+jR6UrMKhL7xtWtDUqsZL3ydJZrzyXAnLy +4zrLOeZwjxGDykIR6Hufka2hj8sCNcu0RhKqxeoteV92Wte/imf2Njkin+j/6ifB +ZZTuPeBY5anAGG7wo2qiktmfRkUSo3Pb5ytMFCabzMWyby/gJO3eVE9J3KBtusL4 +uX/0xdexKlYqVhKSaJOgjTy7XLcLCJiZ9qT7yFJZNMvfGpPWJygR8dMDFF2ceGVJ +DXbI/gCB/BE6dInD++/CaFLBMfvBGX2dKGb7LjA6uW8fWCx4T4LxCnuiGNn7SPiJ +tH9no2K04JYmlNVh0Z4W2l2HyMpJChmVEJ6etPFOk4P42reJPED+ffpLOX9jjpXp +1bSstZ0ImBxEXmfnWSb6QRBMCVdLXUeehWEGpdIgqnkF0EGe4WaFotf+xyn9B0ZW +QExkRveWfKqMQ5YlVOe8a50HlGG6pVnrQcILvdJCz+iDZCPRQKWjRyIEYT2CA4jj +8s9cMgaNgFhbv0UGXjw7tfBmTu9Syd9hwhEMdpEPSPE5fbQoolAlZLf+PmhXfGv1 +0TV0VkkvP9ISLh6U7RB3oqZeyVYhsZJKSwttsSbWJKsxDZqtTJYS/d6BzzTTnhhn +ZlmG6GIxgYcmJO07YhdeqRK6pprxA2/muI7lVMwHiM74jd9p8Jl4KwDGmbBtx8cj +ZsmFRJcvi1KxSEkAQuf1eE5X9m/trXna42rPKn3lQu8RzSJNnHkLZ8Jtf9h8er0R +usTZcZbQ/+j74SIZhOhjLeb6IQfR8d2UikfBICND7IhmnQv5j1rAgHTfrLA3CE2d +GIxGc6UpXc3a1uKiDxwU4BdlAxPP9l7peCNYuA2S2n6RTnyzIhZ86qncVjbY0QLk +CJVOWbSk6D2QBZIzd0/LsWv5iJ3Gf2E4C1g3sxA+JI9r/GiL4c5LKlILRuK3yY8p +`pragma protect end_protected + +//pragma protect end + + +`include "ddr3_controller.vh" +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TF9rLIjO/HDm4IfLDAt62emoA41d9ONkzsrAc1GmCmjJgORFeX/vV4OW/nN2Aqjr +lSp94excu2Uv6F9Sn+P1wiEFdD2n0+nQGgh8NFN2KBC9eTk2Duhv7utqI85A4Q4w +fmJV3xQQeFryw6WHsZYfcznfA5o9cNWbMq3nOmX+fHFRXPuucaNs92OwpI+hCH22 +LsG+jpPQn0SShE1MEYp4kPPbbDsqxZu6VsYkca6B1KgD9J2unO15XJjrqh5nllAN +ZCxHE0Ng4hm7FwYCPkgZjjTrNkw1oPVlabZicxIkCVd75n2y/iDTjABFoZ3R7gIb +j4OLKES8tRxoa0Mmqj44+Q== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1776 ) +`pragma protect data_block +PrBz7rmAUy0NBsbfvzfNLVG8CWn+EMr1OuPiIiN7dbFAREaawahkJKrRmdQYklEN +JxFraZ2S0td+BtTmUTjg5RxybzMNeHbENgMjULBhxA3P/uONAu6FjTVNN7X+VSiR +7uHi+8Oo0keeCUcf035A6qLMcoBcEDzlm/ohNOX2g9OlLRqJXxIHkvWe3/8N0Fgs +RZy07F2FMeVzHPxyINz+wDRDBtT3rljohgXdEjLxJ5/6j/a00QecXiCVyBo8KsRu +kOb1A8Ka6qBDEmPS748Im/N04UFoX0Qb4itPkwtMjek7MmBarTn5zzPaE0hbCkny +X/FI+6fLaMFl73DXgoJsV6LIRYFRhInIyhLRc6z+cXFa5Zmr46uh/JTIQSHqp7I+ +6L8RuYgR+YjbvCGHcfj1Q0cLnm+YNYDD2jAdAMhxwot8CUXW9XDaRFoYMegGlRNW +3NT3he5NSXbiFt6wZ3sDtpTLqVuJwsAw3y6kt/RPHJZTkC0JIHc9uAEXQTHkdI+v +39B2uoiMoALXLTCn1Tr2QnfPk3rOzhr0HD3d3EJZTj29/6U0+tHF5CQQhjYP82Ip +LdkpoqCWTIeA1oxaLGVaS1e4bEAVm+10wMv25L0vFPuOrYWcdOsBPNr3+NUJKy5q +LIgIZCMs1nIS5bKgT5/zLnKvEVdExYHfvt8yc82qD1kgFozyjfIYcK7HZcHPuohP +4fF+6gPPk8mSIa6i4od7dSUoiLBcneqP34BlVUlYn+veOOCm8oD598bXADNjwSiU +0GYz4/Tpzfw0bWy5h+kZGLLL8vJ4sq6QsIuwoMFfSsmNMvJ7Dsh7f2YE2kq3o/rg +Sj7JOD5jv/HI5ArL6Wqjv5bYxqJDQ+q/44WYFWDDxh0A8saGvR1nmOk6u/b4bBP7 +jlv7cD/kkmlTGfivPgR+f4bwuBopSagQvgbMxPP9qkc902FDOObGLiAPpMjGd3je +FRey3wblMPzO7lI7V6MWFRJD8LI5SNkwGIiX8GP8eNrAmlgBjNxKx17TXH63YjHw +zuhkTwV822s9PXgsFapiCOXFQokZ45DDW4R+heU/HGhzSxsqGSKhrY0QXLmt+1cC +zI4otH18HR9/4sxvlaBewbVi2k5nycQlFtNkGPbX9qrEPyO/0JnDVhI5QGlo8GFk +iMbSFEiiPU4dm6IISeuTXQu5trAciF/mHLJbCOyJ5i1VkA8Oo6Fn56cqPI+TCZBk +YgeRqsSo1CSzu1gAqnj32cK7AT9MH2UPGV7T4HlJ61oLrTdFw2dLwLSJlzDn3F28 +SDDSV67EBE5mygKkxAnOuFMAXUwbp8xiE43Wy962hYxo77ZuHvo3En7Lbdd5fhc1 +dsaUA/Z8kez8598Y/I44aDHjVr+ZX4dLIMOZuuRd8OdeNZoq4D7VsFwzQtv6T9Ih +qeACbS7SQH3BLquGsLGmiEkMX8vAfCdiyssCe1LpxsxP5FHI9D/QSzFjxzKdYqhh +WGGzNbJhjB2TNBew2hbmqLlvXzUfSYkelBER14ZIQ1hytQYIGxyhcPYW6zj/1VOW +r0XB4zC6yyfR/UHXLkGFVBtXnY3aNvRND8LQSUCA0aQJR1dyUCQXGJsUSJy2kwSB +N7rVenI1rOBXGWi1yETJrS8K9fBrg1EKTmdEP5nMp4CQdhx0PxKb4aS6lw0xZv0l +ye8SVxQXHaZHscdbGxWcWsV3zne20HCmwSVOPHeh8z36YPShbGD5m3t/K1OZTcYG +9jTXPhaQSjPyLrQMjMmy8ZqXyDvObDzHR37iwH9OFrQLuTcDY+qZNIjNKAKOlt/U +TLwcBxErwuPsAJVbuj1+yPfPoCcOvWs+inTdXO3YEn0zN5EkVcr6fwR6vafAfotl +V+hgiJRj3zsh2YNBVZx6GGh/0u6kjE7UrwhrIv4J9A0FpXw4ZUmWLZyRg0YJfIjl +RURtxyjNBPK2SoY0nMibI4h3LehrYtukDvZzqYkl2nCyWBGz3cYbPEy/r6l7k0qv +4/AAwlnF9uhqeAzIZetXtc0sp5Ny5kOrXmpzSjnEXMmB63NX3C+vvAbnc+IrPBoY +1j1ULudk197YSmWTMsQ23rOeDc3LRqoVAR8plB5ByoPOd4mQoDHMS+uWzNgLEDMF +5RUmJm7zvCvZslrVqSHvoqpqB7sulBB8zkqLwvtG+vDrHNfFKewJraLeGRF/bwJz +EtV30LgTMfGOKGpY+Zvz6rlksdAuapQxfqM4253lcD+1UPz2fyAlw7gB6BmnWfAu +/Z6jVb4eoCNz8POp3j6QY3cW5IlDB7HsUP8NcGG5s4kOisGwLxqfQcS5Pdx23uoj +4ylR/xzh8X1HHCrDZneqlCbsH9zn6Mcu3EuZYQilVxbUixGYIuwOkfBVP7mCwvsh +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +CtoJLvl10dObcdt+DMHj0guDEzsoXHzMbsywiuFYWMyIATGPsr6HacUSETbX2oy0 +gvH4lYMTN4/7CAQ/UepofjW0sdUZfVZthR13BAg/Yqi2oHaZKrvSZGqQQs//kU3P +5gp1QIrpe0PjRiG3qyK3ZJ67PAax0v3z/5uF0/uLZxeEfLhuMNrpcwYwQSlebGHu +Om1pqwOCjcVyQGNfW0b6u5rc1QOREST0pFFOWxKnYaMisZQR489G3s2jk6o9+37A +qHqZtP04V2mq+gZjpodG4NT1um0HEPUcSAiQiylle/dI6z4q1RcfGgpdYUzWzt4b +ewX+RuJ2e42XptCBqLx9TA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1760 ) +`pragma protect data_block +gGvfa63Oh1aHUdRzsOKOjaa0etKue+GWCwsTL9e7Ipz0eeEd0LM4cP74Jdb4vRUG +itWVTQhbIxMwS95k/vfAAGFQNaioUOJHCkjdug5ta8s1LiWixbuB3lihmCPe6gmZ +UjT4LPHdgW4VkPgfgnyBGuyljLqnUqArXyBD0bqYYnjM6bWiwGySNlZySxz3mbtO +iAYy6rF4e0CGK4/KviRZkQuU5IUX4/P/jXy9UiNYLLwgHcetyW9jPgfnoWJrKgdU +Dd7uTeeWOOVx/0UPj6+VLeE0HzlFRv4Vj61dB1D7IsNB0wy5Lwrx6/bj6JQ9KCQS +JSTI0xmMSDcaaV6sOeyBZNgqDKs2xfOhkfT3tmjCpQYdvI5myMXuAYze6O952yUJ +CAx+XLppVkeB552326JoY5zGujjyIGaknAQEs8Mnl4S9ewmBpwRkYwE40xnpKvQt +n6xo6kYN6xj22Zgc62blcvtFFhefGh2Bw/MOPmUe00z4sVT0JAEvD5+LkApAv58K +5anZUSb2Wm1rEqN3slttGkuZQGdvL4JlPssX/LHAz5ZOk7uFaTiUoD4CJG9y9qTa +YtyyZlUb4njTYeMeqG1xuYahgodHl/31/52OXZng52TQMjInB5OuLG9bT0/bUkUi +FSh3E5xp3LEvw4+E4vWd1AxyypMXSY4nNp2IbGbB72OaQUI9VkpfS1P1nexyHhOr +Ne9mjd4uE1UgdUjXxe2foNo2kqb/wFxZ4SRBKANmpK/bEOnEYw22loY593d/5bT2 +nRxJkiBMQ2EfUbFJpTN59GrEyFkMSmD+1UrgCrf3PGmyA0oQdm3ULME2Zd17n5SC +3HzLZDEj3jUwPIv/P4kh07jqxC2ULHzywqDLHCH+/ZlRUmC+ScG8VRpCuSg0bzOP +McFs1AK07DXpCQlJhaLOO1vaaV0AbwZ9sXPVZUKN0B09jt8rRRKHp/dPUG4+lntU +SN8TNkDyQJo4GBj2qkKpJ1eoMFmSeyxXXEM3PvREOZ8BK7H7V1OGWu+nZw3HCUXJ +mJYdNquTZ0Za1x0xDLb/3ljdfwhCI7MRafRp+IIqpzBYdgNOdqeukWlvFZ6aXO+2 +uaw9aF4eyxvY2nnUL+Sk8imhLYBoDfYoLWePcKHMGuvjzmX1/kB2t27KdiEhykeU +MgFO3V7M12VeZ59cjpFLBsO3nP2bhBs5dZ7mGtlGJVeScf6mi63Y7NI4bSw/rVYh +3LS5fwI70KNp5Om2e3vAwNNAHzkVCYRGgF0rXJwBm6c2mrz997BUWE+FXJsEO5qf +ts/jcJm/NC+/2u9k7toya0MuJVwj6N9A5WnIb4KHfjlO126nVubvkU3IJdEEQ54r +ATBTVVUq8cb4N8hjNw4G0UG+gWmQPDl/FOEIsfUQ9vHqzG8ZEORmr3VPEZ/nRY41 +SdnLLmRNZttT1XlINOfdikN97JMqG2+o2quAtxioSj1MP6AqN6CWBrCKlP6vxnjh +Hb8NAyQu1pg5GS4W2oQqrEZEHfWdUz63VsQGOhqSTllDOL4bvGSpSnmxDccBOgQC +Q6QIn88Y3XoVnvesvYGHmycxmofgHT14hkcrumGsNF1Be/bwuruJYEE+tX4RKHvx +sIUl34V+oVnM3kKvPAOitwifgE0OhRG6JOm6helqFNZgZhsQiWvY00/1zvJljzTu +11rz1D2w3LB5DmN10eNhGRdXMeKSIKCrWbIWYM/f5IiCmX/j14XK/8R5tBK8uAU4 +SAbGRBtVsV0UNNSVmmmwQhtNyGDxmXdks587tUHOHExviSc0acydGbwpwdHH/srk +z2AMmVdsupZ/f7JhQwvf65EFTUo8qol8B0wTufM7CoCe+KWb2UrAmmlTnIFErPkd +/kfnQx+EMdht8LxPgZXkin1eKTyf8u+hZctDP7g4MddNTlbUHLfgm2SztG2czwp+ +b9aXdmbrTj79/XfBBReKXSvx09ot6pq3TUaalJZv6GT1r8E1Xwiy/TjMvcAnzVdj +U9QJCVGxN08MGBnBGdRNg2Ri1t70iV5n5xeWMuX0L0a01BIw/CgV2I2mtU4UfaHN +YgGsrDqCoDAMGQ9QT0v5wtmo1KbQcz/h77GJ09ZpzWVjD43gwz0F0xg8m/v55sNF +zB3D1WD3u+JYOv2zCpK2IOcTuWnJpO/2oCdglCyS0vO+eCf97N+p/Pmbsba8CI04 +W8pOlLtDdsEGZB2H2VnRkEE1SIxX+U8fr5Ke3/nyKrQimUMKg3VKgUblTtZBTpJ3 +VBXAsj8bTVwwVjujKeDPUfxy/62oX55cmnwvXtSkL9ixBj4s58XliCsxk+GHkoOF +Dl+hBpRLc1KBTRPW669elnYyxbrSysS9RnD/HiYvMfE= +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +JvydbCs+8a7exAzgsIga0uoOw7lJAonWRvjy13mkL0OA6Vk10PZm9svxIQoiLlmM +2UgbID8JScRKum74D78Gb85UT5Y4IR+qTx6xcIHsPILdxpd8pJ7fe5K2jgQXFqKZ +zsq/i3lTFOZhVXqIaN+t0Un4+tMjXflAEr6+u38owUAlFd8dVLTSk33gcasAyJt1 +qt1SUUpKTdkm2wfqgHXboRcsxBvdkF/q32cAybQkz77AtAaSzNcL3Mz/NGfQk12c +NRr5g8CfmUQ9pXDDZ+63aywN/yCEEIlimSV2RXTZgRyBzzWGu3/wBvQgHSGltK9u +jMmgM3bacAYZGpSWJu5t7A== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1600 ) +`pragma protect data_block +wIokSCftD3m+1rFR42+Jbp4wZ4Dq0ycIAGKB8bCPztX5v+kOtKI2ruMiWqmwhcY8 +/9hqyMoHxYtHBJIRvQ5jYtOXPGKg+5pXTwaxHCq/zvIFM8248hc4svtG5Qbo4oo2 +F+Pc1tZV12Acqa4//fA4ia3VNp6T3PkIc8N1NNfOQhcUW6Y9JbkbcSDpExemrhfP +c6GM2UPXQeWzsfKS3T7EWDHOWkTxY/i6Lrp89w+VscS3ALkVtzmKDuShCKCF7YKx +xvdzvubJywsYGNvZfFvkqNILybM8pPqy/ESfj9pF2LmowciBgp77NoqFD7MZ2bsO +8PzBYYt9BTuc7y9KsJvK5/SyKhkj07ob4xI4jCHvPiwvzK+finlrAwoINNfjqVBH +cd/nyIwf36K8QJv9BSkF3cFUalj/E7YbPRxmR/wrdXX4heYQBhDn1IHBmBB+S616 +MQm6vqycWK3ix3jF5LcCschLKnq21D7xSUqnzmCSq1An46w5+brcczXGel1rFMR5 +3ejN63WdTQf3A8fiBjARXPdMnXhEITq49+j3hj+KXV0dV/QwRXXYhcfKQpqiqFm+ +d2BMSyw7LkdznIkjFsASf6NJGutjcVBDoP6tf5r5yU5XoCLoZVXRs4nKyV/r+y5w +ebBipmEroStBbR915u0AvREWBHxfX0eLVY4qkIlPT6h1T5qFn8H14CbOuo7+QJhO +21dqQUOZ3DHaQd7h7AZS9BczFAgd6X8J1eGz+2D9uX9hRH4pE+TJ4G4lyDpzrteG +n4sRaYlDVEF35A9Eb5aP6im8O6HRNT16vanDv/Cm+vzWYUe77fme+IYBES47wVQo +JzCUXoqwFsW+O8QJvYfLxUwvtOYBOAjyCb1UmQ2zNSLwShZNy4I/RyUOIguZxwpX +Xj7LG6hwcnBSgw7Wa4Wu7pe3QlWhHrD2/FScQVeFJPXvdTrridjpMvsIdCdtz3gN +8N8mpvDp3J8kwZd6rUBxfOyWjap4iv5oBiYl4px+gctK5BAHhID7wER8OgsZZ/q7 +sIDwhE5tOCo0WS3R7frBGWFtFkK8KvYPXbyg8u9UY9d8I92LEQJyHo57EYAMwtVG +uIXTZjWbjhpXC2owom/XZbpqYiYkbBrasSsGSvU42ufX3xrL1QlLbXURJsuJaP2Q +29h4ZhBuNXuScbZibtExZ4sRVU0W0NQD5/3SaZyWRvnnCeF+AJ4giCIEQ2rg97+7 +i4UbbZ7baWf6l6Z/0BrRStyppY5VUyeSDS7lxnL1tjCQ1FNLSC1GFbXipuvULyuQ +JuCpQYPi7xDRb6EXmSRzSDpuncrs777BHDUdd/hoEuTtsEcwTG+e26vyx8Ig1E+V +d5duAVaAoO2id9tfis2QP2RQ9NsDEGKHSw0ut7h0e4NFu4RqARGUjY6aUMfG2Lsr +iNZgqB5ADnZWt+QsoG+PhtavAGRQnI7+ocDwRJ6ct12WXvzfdAvZhpN0EHUGNyNu +yRkhyLV2wUGnYKadT1qIXXNFvNgDC8pkE9AM3/bSHEgXIdoHPf6CPoUR2gO6Q5yo +gyuy8Iimv2imisbwpj040Z0Y2gvd2BRr7QWW5otqedF2DVRrCh2Fq60ppBkpEclN +lqDoqDPMR1p+FRCREzyG6yDaezbQjDzDJe1FyTkqesfZoC6YfHTYnMAf5VHahZe1 +/6kzh/twWpuAmGjm3wA7jZf5xPoROywVudgoC8zrMLTaW8n0pDu94jCw3s5Jdcy2 +ey2YIt6tD4dmrZaoKCgv4ZS7WhzdSgojmuyOH+rVhfhK7oZ0CKYRl7FzfEX8Ob7W +Yieu9BT9czqh3o7PfocniHrX+OjnX3H2x0Y75SEa4fM2XO4fQGidIZusVp31Trn4 +HOOrkj7ZHnc68CRxsuLRZ1HFsHmOX3iTWhGaCYcndLsO9ZFQEper5o4tDTleRDeV +4GTllFFJELJ/nUmy8Y+jZY7PQu4KtnLmUu3kl9c5amyIJIpNKkmrFN5qBRLuufh0 +qCj/me3GekH1KP99WGSFvcW+FxohX1pXioU6NdO5q9IZ/z3JOsT/NenXtoy0/RMZ +pV3ALgyIta7piEF9bYBDaxL2Rf+aKf6mswln8av5bSkP59SsMh7KUfdxI5IMdIsa +HGD+WZ5qqrSAivgO9KMJ/A== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ERJokoxXuDI3BdFXFea62pn/U4b9/6zoy1+NT/5JqdrMscFain1XmM1I4yzCK6xn +zy5p0nDhSB8uwnUuiReF6z74oK+OJ+fFREUrG8N4ZlMYCCFr92clDrxXzqdpNADv +S1vVVMdtpfal8RguWXbzQCzqCg/o49SXTvrNiWIXsyjII5umjgfvWFvcLSOoUjuT +QTWBja+FowDt/69WPwy4QOPUQJt7tbhy+bEuW+Sfn1cSQC/sJ3tRWTWmDOtxr/k8 +kWjjRzJOj36P6IlPS6K53yEOfcRDuDNyeU47RE3UKOXicFsxJPrN/eR5iVEG5V5H +2ZGwe134+vYuEXrd54Zjyw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1952 ) +`pragma protect data_block +uZji2jSsWV+KWGpO9qqVsW8lNvLheemDwCo2yM2q4uE9xU1/md8/DCRA7a+f1ged +Y+eTSmAXVbnIvOMF/cmRgtGfXzb05BwS0WRdMEzK5h4cRFxpELhV++4Pa2qgaz57 +jvHCTRdpXk9PsnCF9CTtTLgCN1cjUbmf8ko58KADOWdodPc6N09cv1uqCbpRVp+t +RF1phpWfaYSXv970wasJdwA401gfUbdkx9eBPbaopS5zQgjQi1IpDYB30KgXSb1z +9khwpM+GWehX0z+RoXy4lWtXzBqv1HDtSidZVDbtAX/3vrlzggpY5D23+7EgRq9w +ckvP83D+kiNgYudOx0rZBo9NLl6n9qaM9UcWL3TEcMgrdV3y9SlsN6KU9XVweBWq +uD+3HtZax9ohKshu+2PUkUaj8gCQi97HA2lWo3W1EgA6kbJF77HRij2oqLBqe6Ju +bgT9spI77tqF8l5lMZyh0/hTTdzMFLmkD5TAO0ceGUGZcHXbK8KxEvaakVmke7tI +f5TK3Pve2kmFj8FhksgClGKkhwHCpKHaJEQa2nGRQKz0+vEFRQZFtW2K6+Ejr0Ku +fAjFzW8xdntgI7AxcCjk0FHHkwmiC2nCetdJHIAzllF9J18g/lBRAXWMSk4THbLp +clFKqIaD4qMexU8tNQUduiktUtcCrn8lO1OH4xpD+ZM2FyokE/3z2MdJxMIUbb7b +Me/klIBej+6j3E0RmO8J4n2WqxGGOcojgJwg0XAI5SWLit7mtfUN/O/w+VSL2Alh +pjt+GoAx/dIKHTclJMeY+AQzkQsrvuLFHiTgTDMoyxRhh0FeYm90P/dkubIp0pMY +FZViAfgVGonGYX7l9ECLSCqeWu0VSEAEs+c43C3z0pi1w2lppBg5wqeIMUk6MidD +u24dEa76puySZSm7aEVzFJwnrD40fv2Jc/+LjyCPxb7po/iKqb3RXjeSIFwNePnZ +ZGY0h2waQWE85LWLRTxFKnZxoHosuid+qSAmpWudFIMTfmnh+LHfRa/4RXS99yNF +OXvOvomQ+HiDx6hbRDDBYCPmPqP+jdg+WBp+Qthy/h8AYh4LpGPMT0q5VD3VL0rD +djWJp+2Fe5Z/oWvdjWhiJCgS2i9Eyu904SGTO8+viLsSGHieoA6RxS9ycKk/R7JG +S17ELmG9ZjNh4jo4Hyj7bPme2FpYqofihZPHFaDtH9ooTtR0s6mCsWNtjLpZhokG +pdQD8w6jXJ6C6xxUYhPRc6e0pVAMMc+RaWg0RaNUtOz3Tynsx4nVYdgW87amduVO +pfK88e9y8wyXVQtDoaTs4n8VfqSdgPwewkwF1Ct7ayPYT4lKmhcohVDKtMnDy7nF +PVfxO4Gmi3QZAowg3h27v0u78uBgsTqWFxDvTwg4x3HvK2+WFLF1nd2VAxacuAPB +sTBOe9wg3gacqc0x1Fio9oO2QZz0+6S/ZjIu1P32fJriqq9ZvtZ8mwhyUNjKaKOC +fkuDYd8IUhpEl58fA05riabbWNgjUxUqtmowarvWw6Ip2Gdp12vdVw6lChl5O4V+ +ZcUnaS7sJSyDIHjbfkSdOYkwTI6rp3Z43xgBq75/d9V9gnnY8426CvcjpODjf5zt +P4XId5VRwP9FBAbFTEZix2r8fftpllcTpe5RQx8pFGRYgHzpuZf4f86xRrOUNr2j +l6jWvQQKiXI6bfTywt8nZQhuV2vf/Emj4hgCagwwtg470xuXX3SiY3P+Fg8yyuvd +W/CeogpmTX2WD4BFWYH0afLLEpXQaW4HUVbTgJIGuEkBPGFRNPj2dZEFFaiqHvGX +YMNEoBHPoM+1qHO7M+KBB3M5dwF/qI1GAbs4TDG+R+RgdOd88J8/L2I5ZlMTN+5x +4Td97dnjg9Cmzar5haF9bPWgT1dEdVSnfutPTaHop5Z5zDub/AOe6dDedsbWWDdT +gsyV8XJedpUNCFqFXqGvb2aSZDWAVT9pZ3gz/BwUxQh6qD4KyNoTTISWEIy+I2rY +Jk0YcIbhYgatgfv1nj8YTM2rbroysItCE+jo2eGZZpuajPonkwvF50OLD5P6NE0s +MtZNw66KT7oT1AuevD8meeCYbedZ+syIrIm/os8F0VvIZ1E3DnCI4PG6vWlH23Yn +N5NjLTkSoCYjwnQxi+8aiRHXNbu6xGbJHI2DXxCzQCMzZJhoGQKv585SXlr90+s0 +I6crAj1iq4WH2fDLbxm1EKDFVR6eBsfO0IiVuERiKuhmlmk0zfwBAN4aQCM0TGG9 +nRGtz5x1d3zzelZGfHWBMDoKNoLLKGSgi+UtpE7kR+u/4hPPvXV7LfOBkr4mZZ0P +cmwP/thzk1lzytFhTk6U/r9Bc8YKjkdiRWVscDcQGAByEKZKlCRki/OHcPbTK2HB +2ECGarDiSO+Ly/f5CQ7Jr4SnVgNFad6ykKj+Suc0hRiwltvKvxhAGKPEae9Vhitz +KK+YStB0+Eozs7ceerJ8jbE0vRus0DVAWYXjdjJFt6YYSmpRB76gucJUvLAnfW5a +O1mHlQP8x5v1mYahLVvus50yImsRoT32G+YkT7Dnu/3kN28fK+J25dpqGtoqFgX+ +ShHcBVsHIHGTOvrEeR4+qX/z4EeYIm0cQRONg7o0Xb4= +`pragma protect end_protected + +//pragma protect end + + +`include "ddr3_controller.vh" +module `IP_MODULE_NAME(efx_ddr3_soft_controller) +( +clk, +core_clk, +twd_clk, +tdqss_clk, +tac_clk, +reset_n, +reset, +cs, +ras, +cas, +we, +cke, +addr, +ba, +odt, +o_dm_hi, +o_dm_lo, +i_dqs_hi, +i_dqs_lo, +i_dqs_n_hi, +i_dqs_n_lo, +o_dqs_hi, +o_dqs_lo, +o_dqs_n_hi, +o_dqs_n_lo, +o_dqs_oe, +o_dqs_n_oe, +i_dq_hi, +i_dq_lo, +o_dq_hi, +o_dq_lo, +o_dq_oe, +wr_busy, +wr_data, +wr_datamask, +wr_addr, +wr_en, +wr_addr_en, +wr_ack, +rd_busy, +rd_addr, +rd_addr_en, +rd_en, +rd_data, +rd_valid, +rd_ack, +shift, +shift_sel, +shift_ena, +cal_ena, +cal_done, +cal_pass, +cal_fail_log, +cal_shift_val, +axi_aid, +axi_aaddr, +axi_alen, +axi_asize, +axi_aburst, +axi_alock, +axi_avalid, +axi_aready, +axi_atype, +axi_wid, +axi_wdata, +axi_wstrb, +axi_wlast, +axi_wvalid, +axi_wready, +axi_rid, +axi_rdata, +axi_rlast, +axi_rvalid, +axi_rready, +axi_rresp, +axi_bid, +axi_bvalid, +axi_bresp, +axi_bready +); +input clk; +input core_clk; +input twd_clk; +input tdqss_clk; +input tac_clk; +input reset_n; +output reset; +output cs; +output ras; +output cas; +output we; +output cke; +output [15:0]addr; +output [2:0]ba; +output odt; +output [`DRAM_GROUP-1'b1:0] o_dm_hi; +output [`DRAM_GROUP-1'b1:0] o_dm_lo; +input [`DRAM_GROUP-1'b1:0]i_dqs_hi; +input [`DRAM_GROUP-1'b1:0]i_dqs_lo; +input [`DRAM_GROUP-1'b1:0]i_dqs_n_hi; +input [`DRAM_GROUP-1'b1:0]i_dqs_n_lo; +output [`DRAM_GROUP-1'b1:0]o_dqs_hi; +output [`DRAM_GROUP-1'b1:0]o_dqs_lo; +output [`DRAM_GROUP-1'b1:0]o_dqs_n_hi; +output [`DRAM_GROUP-1'b1:0]o_dqs_n_lo; +output [`DRAM_GROUP-1'b1:0]o_dqs_oe; +output [`DRAM_GROUP-1'b1:0]o_dqs_n_oe; +input [`DRAM_WIDTH-1'b1:0] i_dq_hi; +input [`DRAM_WIDTH-1'b1:0] i_dq_lo; +output [`DRAM_WIDTH-1'b1:0] o_dq_hi; +output [`DRAM_WIDTH-1'b1:0] o_dq_lo; +output [`DRAM_WIDTH-1'b1:0] o_dq_oe; +output wr_busy; +input [`WFIFO_WIDTH-1'b1:0] wr_data; +input [`DM_BIT_WIDTH-1'b1:0] wr_datamask; +input [31:0] wr_addr; +input wr_en; +input wr_addr_en; +output wr_ack; +output rd_busy; +input [31:0] rd_addr; +input rd_addr_en; +input rd_en; +output [`WFIFO_WIDTH-1'b1:0] rd_data; +output rd_valid; +output rd_ack; +output [2:0]shift; +output [4:0]shift_sel; +output shift_ena; +input cal_ena; +output cal_done; +output cal_pass; +output [6:0]cal_fail_log; +output [2:0]cal_shift_val; +input wire [7:0] axi_aid; +input wire [31:0] axi_aaddr; +input wire [7:0] axi_alen; +input wire [2:0] axi_asize; +input wire [1:0] axi_aburst; +input wire [1:0] axi_alock; +input wire axi_avalid; +output wire axi_aready; +input wire axi_atype; +input wire [7:0] axi_wid; +input wire [`WFIFO_WIDTH-1:0] axi_wdata; +input wire [15:0] axi_wstrb; +input wire axi_wlast; +input wire axi_wvalid; +output wire axi_wready; +output wire [7:0] axi_rid; +output wire [`WFIFO_WIDTH-1:0] axi_rdata; +output wire axi_rlast; +output wire axi_rvalid; +input wire axi_rready; +output wire [1:0] axi_rresp; +output wire [7:0] axi_bid; +output wire axi_bvalid; +output wire [1:0] axi_bresp; +input wire axi_bready; +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IXOlIlqPmh16SX+jLoI7zQScxLphkDyN2fmYDhN9mKFQgUAvmitt/QYTArLwSJIC +Yt/+1emkOvqKN/cko36eMvDDjpXjIMU30TjrhLFFoNG2HVhr4tH4ibsyfEluR+9E +7qqdEQq/dZwN1mOCWFyDE22K2KVWi59W5lFETD5hVVCSWt+2Xnmve8MxlmwL9+6a +Etrgzq/h8ILweuz9aJuSVROcck9nUfW4HjYTUB0MBILbR/vUmPqD8apZe7ewwilY +ia3Sr/f4FeImAKoiToYWeiZX1Pz/L1BIgOaA3Yf1PL15+EWl/Uxj6bLj3RwkP85w +rENKIb/J+pF8NbEb3+sr1Q== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 3264 ) +`pragma protect data_block +lqYfIfedpQb1mReBQPAX/u8dwzT13gJfg83zLwXw6ulT4+JKLw80+XEzOnXr7UtX +clxiRTn6xwzbdSVG+RGIN39bcOawfP2wcrTwpUCHU/kSqvyFZ25jhybcH9RgdMIE +SU/FK8cGDaVlih6paDNn4F6VLnMSWibLEPcTNxmoK8CLegDGpJRAaHjnQorZFpPW +mMqkXtb631mGez5/5xuYE270zMptLXrxuuArB7/Zmv4KXLcjGHAdUcpK/sQMu4Wt +ycFMQJdc+oPciUOFYO77zygGBeAGqz43JYaTetplK+xTvOD5judMAPZLwYyaAsfz +9UL+zbdiSsqh4eXTk0vncbmRxvKME4kHzrTblml3I9MMsBM68UOC0y22L5xTV/l0 +GVart2p5JN94QWkzdMbuJOHe85jWmm/rYctQCH9lQPLzPvVY78f9Z45tSNCcKtP9 +dqWjaC9hLmi4HrRGmAZRq+Ov91IjO35ZAav2Hdp2c2osZlrwz83EMmg1zbi5Xq4Y +OkefdfwbgX7IaHgTDvksT4ZGXMTdHc+8IuO8Tk66hKiKC+jLXXKT7ZddAmirTC8y +KHHgK5ljVYl64CYYwukNUepQZP0pCtdwbNDBxPK4y3ozZgsLOGyCqN3LcjhUqGGV +to4dVWVF/NEywVQRRs07zCQpEhjQ27V6sY+wtNfL9wJf2QTMu7Dl5L5/uHNQJhbe +sNUeiJyF+OFwqwFA8SBigkqwojVvlsIYuH6qMlonv7iRS+t2PFLEajKgsyz9rfb+ +2DLFnK6Jl4gUUFmQTXv0LXCqv7+Ic9ed9SpzjKOvCGY+Rqaukh1rlEcvWGxHt3MG +sVueBcrp7AULvjA5rIVNTscvJmrWSjGRgIS6Si5XWxp/uupLSpZjA4Gi4bpl3zhy +XgNeWiwrkmsKj7GP069QGdjF79pIp38sjh+OahOiHz+lvsODl9uF5smaWRiyiW1k +sMQ8QS75RV4zsw7eXBGnX+DCOvIZZhq9ncY479RcT00Ju5MTW0QpxEXd/tsrspZa +mziE3YYy2w9f/QWu814Yx/3KjMdpMqJBBimbVWvUx0xNAtQgIhW4OtWihIkmU13D +1kSGlZnbWu8bW3X3ParwOKBU18trwEGHA5PECIf2ZRSvFgdcmTltBpse1TJRVyPJ ++Y3392QPf/hSxR5srtJJ1L3sNL0nftzpk2o3Kuu1iW1xpq2A7goGYnC3jIeVqxA9 +Nz1Vx8rNMNF/sNS0BBLnUmeV7RczGUA9NBehYfADpdWNoZZ557p4EYxm6Z/HFleY +ZvqCTBx8EFywtg4NaGuC+Cj7SR+5r+f/EYLwDEzLRUtKJ01ZLxF3OSOytmGn/jpU +VWQJCbTxN6ezYhzlSpoySMhTto2rAIBvogPtF3kyr9XIuBqKyA78t91xSLRp8B2r +XoBjr/cWKzOdao14Y4iYJu5Z0AwpJlIsG9KbTlwpbYiDnv6kd6iy42Xil+3gaD55 +ALblwwJCnNYlmC4wWAG+C0SShYhPWTc58SrtRhQ4DbiaKZSx5VAakhrGInPLNe0G +/LGryCTfkPnmEcgPxhdOkuu/jszQRd0VebtBhsy1DRBYMCjbGZGNJMEs8gZpM1WN +WDmkZLbCFYNUD373vjofRDogxXqKlPCNteZLRS1y/Z2TJkD9Ywz23ZHsSSP/WGwm +8ZevTijkFHr2oEwlR50TZnea0+2g0xuVo9oZDb8KjvYZffdriZ1HhRL5+Oj3sNBI +5PZpM/qlDBMqKIWbNoWJrx/GLMnQUDMTChYB0GGSzfRPF0KLBLm3BXmzfc7p8u3e +5W/UJAGsOSka6GgfXk6QYPZp0mjI64vZzGAll4ZHsblccXFs3pyCUCrq71tq6LMv +/qAioglxHnAiX2+mD2bPuht4HTJi+u9aTJt2kvnt2ITvgxAxExL5PFDB+dgf0wSG +qBVjSUJwswckJIKcvLnmmr21QXQ5zvTjvQvDihIYXqSEq73gvBqn+HW5aiWU4Eyb +j9jmZKO3Cs7KUKPv0ApCChNwspfYEMcO8qDxS48QxpDSntngeKi47+Z+OJSgKJdY +RKUmWQSGs58vWOUeh6evKMrlEef7xIF33OjQmOw4nxq/+YGwmOsliTwCjpaWVL+z +c2SGpOOrP+rbPv2qTuQeS9RdDhpyb2wZ0YBHtw4h9vwJLDdjcfYiE5SCg8Wvk8t1 +9VHliU6MulawnKIyYTGFztfoqPGT7siqvrt7Rpy2Y6m0T5A86/LlLNe42UbbP8q0 +yWUXyB0sRW452PB8pc/L8g2bVuUpaj+SrQqsYJnJNVUK3NzkkcQjoAm4tKiZhfVF +3OZ9t15hIEN5Qx+ePi63++BvRucABEjKgBrB9BIL6eaC8GmHd3Rp3K4T3JPesVwn +wavjtOiQtMvAMgKKykuiLiL5aG5lbkzDq2dbTjbkXdGtica633A6EVBqC4+o5fJp +ljZEKaMPfiOKB3fLtekT+wu3yuDKR22YmpP4pkGto7MmbbUTulV59csOEPvnsGPG +Cat99m/r9PsKvYTKM7OqJe+c9CrWb9Qzv7wcz9biRXQh14j8ClCjoUKrpUOod+60 +RrvU4Boep0ikrEtRJpLXlpRl9nclFOXvuR9gjQjWeU8dkLM331AwPVw84Z60PsXe +Hkc/LDgXXH5leh2ST1/4drviQ6+HV6hnVYKoLmpaWl8QirJ/KLiHKOF4bWGzpUPZ +EotLKP80nFfV0rGGGS/+bDbbGFrfUaqPr/hFfLIzVd9SiF0deXPcHdcGKYOY+SUN +E/DfhhF37ebAJCGZkIizFWNXTc+2N8OT5EK2sRqsuP1q64ujK9rw9XqIl6TtxDRm +75ps/zK5VALVBvSLO8BNcxuSciDucLpzcvstT0P/s+nzaPdLP3+WtWX5FIkjuOgY +T7mLWE+qlrdnRUq23KyWu+IldVBmTdKcXqvtlrJSG0S7WxnMboORJ9esRGSBg1sG +UhqJjkhD6sgP0kTGrTokk28RnWA4syVKVNePchRdH81jVtSCKIVz1bpc70r3YGrB +pWziFoDLM/hI3WnWJomz7d30i5ZHS3Lq5NDoiQPPBn4z4CMNen7rWGKvx245Cfje +jTwoYUmbHrFpVBN8mCUeow7q+Cu8V6pGVzsnjXKcuNVcS95jG8XzOIbZBM1FIX7Y +qK/ADeiwNdNJY4+XZVxqH0ph3ImTEi8xz5cI6uDSvdwOjGVjzEOLgYKCLjHAsYSX +caVPmlFlI13M/sqAtXztHW4hw/CQEY2uirKWcVXHUBWivyhNS76AqcpUH5RgYyVI +COLcahy7wsdiw/XUtzWXbtTV3ivpzamWvTCnDO8Q9/SRrbN36qz3w6luDvNrW95U +sLYQCn2I1Dabu69pPwgewvtoCB2IE2pYyfM9504ZuwJC1x0VBOsRM5MiyLR/8wAg +zcW6MYAiR24AVydWBtqRaEaeuJF2hHIgvduK5rZWxqSoDb1Br8cQv+4hFQFyl3gt +wVTtKYqJyCZNXaZ3BeS6O/eQWEetaE9wFmzziC4uP6EPqgyanpxlOvw3t0MjQboQ ++t7wzJGCLMrrhimQMKC7O5XFSf/YkjMffV7OsgARNUoU9g/D+eIU3ttL52gIbQ/D +mczVZ7Uk7tmGGTUPPOAYTFZ7XL0BRFVscbHt2qC3dMmBzxPY+AwpRVFiB4cdPW5O +GcBoIJLazL7Hy/rbXEhr/+jiXCUPHkHzG58HCTxhgpvzVNVhaWdyhC3yU8DIxWpy +do535B5DsqK+KPokJJkA09RGFdI36a9doseApQew/Up5gbgTldFJd/DoWljQ3qU4 +b29QTpzUy4VtwaEYiLrXCZ/YGtCoerExWX/JLi3p1LSmQsCILomTTQBQPXoT/vkx +CAHpVU4WJDCo506YDPJx4e5DRR79p3v/BS/1QtvncFUV1mKRnvW7Y0hcgV47YhU1 +55pSCECAqIvlmgGh7W4Fu0hXLA+Uxu2Oh79xLPym9T5ivdJU9rateN3yz/aCakdf +XKHSljpZq3LIl7sf7LSzAhlTnnRUkNh1IBvc732XH/QqIfykmqHvREioXgI3/ueg +Ir93gUP9aHy4XbOMueWFNhPad0tWUH5KjOpJQNjpVwu4naqUST6fs3EAHp4/NXwY +AJqXZIfQ3ObiddNL9WmEiHIy9x/Ku+/1vL3YB/VQlZB+J2L5lGNPU3uwh9nXffSv +H/cJRPsMYoiQ4tamOuken7WtOWXhJWxaV4WMZkhySKyQ7Md83ZN1aqgl4IE/abBF +mcdMklnQugK4KlVXbIBSgQ1GukTTLCc7nwQd2LPJoU81C6uI+HgnLsp4rgGqyhbL +XJ6kSScUXun6AOEoJPhS4+d/ScyZfexmcCKKERw6bOjgBXa+DU+SqZH9Edrc6pOG +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +HKW1WYWkGTSYpOy0oUhnSBPlANuFrYp+JePHSB7NqxyHRg6EwwOG9xZI/L3PLczx +SjOjGRKCnPeP4PewQ/AOLE4usl40F/AR99bXHVEQrO9nBrtT/7sAlcol2bmfEHDg +7RmNM/rshBxhaF8AE5Fwi6fO3ygxksSH/CqrgMwZJSObwtqtn1Xm0ArF7TqFT+d7 +Da9wyKX40PZd8moac3v3pKLymMTDMEKWiZomQ9iqr8eP62RsOOCbsMA/XpqejTA3 +PSofF3ZSbF4/SazH/YkRmEQS9T5J3UWpGCAF1XLD2SftFj/KLDuI5AJwt2sYf1+q +FeGyMBplPvnfDoW+PnwvBA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 992 ) +`pragma protect data_block +Aac8c7eLwpNNmsICOE+w90h0S87kOXL5d/+Wsf0ppZNEQ7APi2FqC790G3SCl6m5 +sBWb+vHC8OM272W+5p0NtCn4c93LWADxGcw2z4Zd2aPhyK/PRmvgajdAsfDM/dNO +sbAgQdRYDavoPgXzkSz0N1ev2iI+J7mVidyW7tky72aHHUEfnU3neG9Aso//QdAU +hBpp+TyUEbQ7CNQVwtofUn0EktIebu1R9cK1QY1F89dyEFDarlz7hZuJ41gfG+IJ +xXDS/KdVgSSmOFkrkZEsxCF+X1wrhYBK8FN7vofkFOeqJgtqXq2n/gGxm+4DtyVW +dWSMixfAGEi2SSLr8mwD7sgb1TyhSrk3Z12q4wOj8huTN32emIscxTDVb5ZCWZP9 +5TfWd5+LkQyZGs2sOY1uymNVUlqkO+SgVCun5uDBMMfmFQ9Kl+HtjEWjY9Gnhj4b +DM9rxgo/HV3Fx5SFq0NEuBejY3+oitSKJocolNWoKaFjJhA6xRMCXqA/GHzbSinW +nOzBt0qoRhVC3fX/72Zya+jJtCxNMo/+rSeQX8AwrKoMRo7WyGJ/t/dFZzRYfA5g +Fe6u4hK2vu8yHLwcUWT+pV9tDKuzQ6KI0x6uuXGEVocILGysykTFRSPdkB6NwiSJ +SRISr+CT7sIijpe8bc649JSrqJOF6D9gzSx2YIvM5uejneg9rlxg5MSWslUaI6no +quAoSceq5G6a32FHwQMAsea/LYAa0XRtDabzeYdkR0jXCYz4tzt5Dl9UkIiulwSv +S26zrAV7XLvk4PSamfb2IIpeuEmHgZ4727kJCFWFnSVstHeiiWR4GqN44ljzWl2V +qMDcKIqNU7l5OWTpDgymQNeg9FsUo67IOQqkM3ZD3pNbDoX30lGy4RE4BgaykiH+ +/HyDmjkwCVOFIhNLuC0eSQtnYzdQ6okRUyUUqklgML3pipG4QyQtCDwNt14WLEUD +NzCrjuf7vbDN2ggfNoX5qOqN3vjZR/Y0c+4sgvwBku3pykMc5Q456Aj6L2h3+WFM +B9M8Y9kjhZjy+zB7MOaS6RnQOfFTNpLMTOMPquNs+GzQotTEQplsr96R5QnMkGs+ +oYQRFmF0Z/9EbTcDpKv2diwaFY5JgDTN6qsUE9VAD8uoi2dLmkyTRzBf33DXnXBg +KUTdOcGdGF14a8mIT4WnOkaRnEKs1uKm5r+uBi6Szs04U7x4fFAe70pssfaXFSDm +2Cc32uNxS0l/jzgGySgtX9+rb2S6qNboAt6a7mvIfHii8sNH4VfJaFISE5Zp30sO +tvTqigu4dcGH/lU9cYy96I4bMMnwR4xZzlpLuZukQ5U= +`pragma protect end_protected + +//pragma protect end + + +`include "ddr3_controller.vh" +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +UdqdeYUmtxz/vI2QhVleuv0x3gKfYJjIh8QShJjDP7fM2gpIpYF6qAqtI2vxGPOt +ML7Y9feR78N2WYWpWi2mzlrR8iBgi2ITwzCBBjKFceAenW+Ra4th7ehfXjG1Dt4Z +0R6hoj1ihTnPOw8JfjfckDsuxPH8X2T34kfwOwxk6RNUT4XmUrHeCZzQnc6FPyi+ +kV/4EuPmppa15iiN4obNjtyHNAz57T1ypXJkWXUf8Tr31FLlDHF2RsEgMvFr32TM +UPQZWRypbldpfOA91XduBWcfvZC0kjyM2Saz2yZD773jYmWdUXLglARL/ESjDrre +MZ8YkvPzLViABrbttz9h3w== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 14704 ) +`pragma protect data_block +CsFS5HOEx+6UZBbykQAPnwiQiSpO8C6BHYbq5Mq18TtQqFDMEZbj5oqv1ddV4H/6 +O/SFeE3LMf5096g1xWShPPC28cAMTz6flMPGFlCiF3hciTHcoUFpYXtYklIo0jnk +4qCjPWL3IvFw7xB2ZOFnLeFNvq/3r+dqy9Ovn5qRQTFKLug0XhAI5Bh48rmThNgA +d/9q1K35mWC6wscnUsqKbJgDCExFg+DsnSlwrLi2RwLCA43OzM+y9Uo3IHm63hvk +OHWj/meBOwjcFmigRsptwWNNp6jpWcxe9W5csag2Ycow9pmlc/1D6g0TJjS+lz3f +HTrc5jNivSv+f7cWgwmpx/EYiH+M6eTdG3MTyoWhQ9iPEJ+Xtn7JqNnPgjKOLJaP +aZsUInwFSeY63P21MDEBVrJxG+T1zXvfnTYi82/D4hxpw/AGASNy0z+kkST0hdhS +MrAD98NHc+nSOPMMQGRbkRcejAkSOj7AshK5lv8G4O8ruLLNCXRGJeynZoNFHE1F +jbiGH/GE6Uu9Yw05LlCahlpttHmYfbtzU11c4dOxJ/wmMp/9Rc1U1HPLRG6jJ4ZL +WN+gsdYIqkz2AKopq3fkvrz9U8TBlPkA7xhyB4rxNstARN/GZidbdrsuj6s6l3QW +1o/MT+1qugJITOezGsbHmjRGNwQsc8sr8eI/sHbvqyEuW66AAEAY1g4aYx3PldaM +2ShYtO7rn2k/pe0cIFrXiZ2qkF1egRy6dTz6Tn8mf0H5KQWfrksiQFwdWmuELu6d +XSJW9BhVxwaaill9EKs1TY9du1N4/psJX0teTQWOasQNJcgakCQ8kMrActzMlaJq +ldNGAHW+x5z9udogX0RIIIqkl98mX42IwKzf1dpc79YVOFQQRwNY7HGFqHdrEHUb +kt35TNq2TPNJlOBgd1yZQyvIGqOHUp41X2H7zAsEJRZS3gcK91HYGVmbJeHqr5Wa +7r662DJ7L3ZZS2U1ErfCxbXmDLQUZS5VLTQo5hO0h9M3TFZP4BpxWhmjVNVZrsQr +ufbGGR6Zx8WMLATDzT5WHtrVxQ1ASBi2zbNKg6u8wVvRKdug+kBgTqQdV0Kv74Tp +TOMKd5e0UVszJMRHs98wJZSrabrIOez9kdVvVIbz+Hpf7NDUJPe0gFV8HA2omLzb +/GlNUIsysLU3Znx18IMHGIGtwG4JNrCfqwH0aPWKTa/nBVANcagpq6iiTO2PhX4R +CPF1A0y+QalPn0YvsIYbVB1OEKwgWu1ZtugGi6z2OuaGgO6POiXEADkUkeTeHjz+ +pPATHMfMLJTbEUSAcWymxCRlUM1mig9Ls9jJOliUlSEJH372fj/xaSJ36EqYkWhR +RZ7B8qgUDwky0HfkVXzx8I0YYcbu6KEp1fibnG5xgxNWG1aAp3iAy2wDlTft1yMJ +jLBTB720mN8DZAdcyQ6q4+TtbiYZYUJ0/7EESmmYvQzFyWzwmDFh/xio4IkT5HX3 +bylg1ppREYeLr4huCtv2zE318jSIvNj0M1llrHznCHXnlORLGouOU79pxMVdfeQd +Hj4oig8j9N4Ub5dxKihpWiw88tQuA50iZW42cesn8+nR1xOCiZstgJc+KhE8a1BI +Zpk0OyZgoRgDT9LCw8no/Mdx1yOErQFavyBITGVJmpUrJii5LbCHKE130H2cyPwK +6+OyKYYK5Pwk7bk+wU3v95+cBDlU8O0P9HHZ1YTZZC5XqtvGKZAaemfCJTbmNFPt +UP9csEmrln0izfaVM/abZUwyakjoVFJ7f96bywFOBn6osqtJq7kafrFYLTy3rUzO +VKHeVuGYIDJdj2gVE1Q5qCVF+rFLQ9GfDVEUoXKvAdBJIpY3oJtdlJij1Qu66Mtv +B0wE4IWRT4GlVXvTve5RS6f9qqIbFA0e9p9/mrjpq0Gyz6Yll9lq13IeZb5uZ/Jq +RG5gSwNxX5FLwpXt4+uu3rxsRjmZv7Ib9TFH0m8PnYdjgUfSisE0QxWIKcX+5OMm +q8+ARR+KHXjjbjVSW4eERkIkSCKqfd6iuEhbvm05czAtpFUrLhevzINUyAgoXSkj +ITuHDeMwoSYw8Fkq8C3PjdkndxG9DtY0C0IdvYKax6TiayRKlm7YCkFQQnxha+dr +wjEW5EPGKGJO6XNb9sVJTIVsBg9BY1DG+QHl2qFZMOYgpkcfYVnGwP3McE16ItAR +26+i96So1tPc2q7ujuCs+zmfDm69Pd7gNZo9zvr6VTZ98Q4H/iUzEahW0+U6PY/Z +LYyToOzPUGZ5U4+6tCcSjuNbdFFZIuqHaIx3bZ9JekXu25cEBAEazMz+mf4wVfPC +6sy5VXk1NU+Zfp5/RjfpvSYwpha8gEwPZaVJtRI3c+drv00s6kvg4ZH8X1g27KuY +0h2BtJwEOm3I8IQrAvkL0Shz+5Aw8zZabaZKfA/KRM/4QVkTF6aubqddZmPyLpn0 +Y9zx71sKU6rWrqNz5jjqD709KNuEDuIUAZI2C+zFO8CMpZwkhwupaDLCYhnhQ5gJ +8nXwpT9Va+ZQcY+DLWKodDq8uyNHEj/qUiVw40NH5iIr/oIrgQql9iOIxjFxfv1i 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+yQZlINvosrllyFILSGvLwtD9506F7pQwIvDYeppwOwel6IyqGNRvvYEYdiXizhzf +LQ2R1QR9ojMRC8MXqi00jYidrT16jnaa/FUOO8BUIdjW3EdDgdrCjEfcTg7FmgCT +THcuzzVF0bBaHyRvCQa9Rl8D1JVXWUPPcRdn4HbRsPpCpNRuVL3YzjPCUQ8b1WSC +nZ7FL1dXaRmAhoewg1EOh/SqoBVWGxGiyymgDFlOCCnORQbqcbccr0MtHJhu1q3y +Tp/U2sluR2mkjwCT4o73AZcs8rRGo2wkjmqEhsJFxCIDVHn8lBHG2ebwdHN24qz4 +WRuQD2rQi8K+DA/xTihQ4frEvO4RXY0FFvQH/sYK6OuKlUdaZpHaOZv/2KrzCBqY +xiQKCNoOWQzZsK9z/604XE3bBJgeYZM67SY0Th9YFkRDrtiKVG4Z280OLdnoh053 +hs+8a+ixMpKtVhRw9N3cnPPxMHIGNHsq/wSV8YQ/SvM3QnY621sBkO7hw8ZJlg4w +Mw4HkvYLOS5ZAoJZNKl/jJUFoxXbQToiF8VbNin7ntITVBQst46kjLwlTRjiRs03 +FkADtRMzx8xKDG9rEAYRNrmW4VB9Q2NbsAowmpG9uinT+ix4o125vYvTwVYRbDEc +IXa9Hb0iakb2f9yhsDrnt7gVXsGCMp76MpkVxOE4/TRBEwgupnTaRHDapH83S3Nr +Uoq4JMIFkY7X+wleaTO5B7t3OIu6Th4TdBQp4dGfhxtDhoEBLEQzGavy2v3XRsOG +6olxGZ+dKy55DOwJZkvftfPkA3GKRYQt0daXFCKimhOVds/IOzVa9HaomrdxSRLd +2tklL5MPKGnR8BR37u3se9xP7purmAW9K7N7nOAsElNibYRfrGYlv3Qb4pezEQ0h +6VIzQWLGdYa/6+z6jHb8iOxl/U3pGhZV2L/6yYi++JjBphtalfRhK+dQkhzUD6+b +vZzYbyD2lyZy+YouFuSs44faM+k/fYpiFG3VRUm15ch6XvPAQSZ1npn+PvJJf/+2 +U2F5PPSyKe6pRC9Yo8l+PRy0AOsjETEjfdeZVZCgFybF61WR3Jgge5T6m3eJBL7H +si3A3FKoRTm3V8YEq2FOz1b6RbH3KID2uauzNu09NX4EbDaC0J2DwjxnrUFX62XS +g5qJxzwcsfayoNef+3UOPgmEZCoOj5RtFrk4POFjVid+QdrL9HgO0A4EfspXVbAp +m/vGX85PZCtgDaKbAr7dVevtRtVSS+htUh5JKbLWDwKMd+Wpju+W38E4PRtmyiH/ +jmPq8H7ybx7SfkNjpU9sd/b8Zbmw/X9uc8Dr4yav83AQ6OmlClyLVObEXJxocxAD +m7ULqBTKsQy35J3WFhYSarCBLKoBMl7aCVPiWu8OqNI8j/nh5mEtR8YR5zcmdJpM +FBP/dAN1EzKxWhjrtVbCH2eFYGoTHQv7d4q4qD20jVJLhcn2p1I+L5PPfxQ4zMIA +egXBEWxl9QqbSCOA7ypRO01MGRo/aQ7TYz4r5q22vHbVhNXwHrn40m1vCgUWmUGo +jc+CTMfm4dQStCNi1XwMOKx9VF/dC04DsO3yFvPmXxIQhzy0ZGSemQ5gddHSHbiS +UOjYKMyfjrBqnGPXXRrnDQTsf4fNLW3Gl1FOPgt3/LFc8WQeEAP4I+J6Lk8MWFNM +jXs19pdolLY8SuUUbbUMrQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +QxLAAx1mDR8C9DRSL1hJt3Fm3vHS7md8b+89aCn/9d3nR5RH4dtO/8mRT1t3Kjkz +8Bl6WyyHSeFeQqCGJarDxX9bJxXV2dkDDf9r1AiOsGx6UIJk8EkOpg3RNH0aP9OD +TMJLvA4N6E2z5xEpDADPL+SrAHN/UnLD7eQydD1LQSlLVHhKxQoMTMvwhB2kYM01 +BDeCWeTjTrr0/qtifTooiEbn9TouwOW6Ia6icgk1gZo8wI6t3ppX7rKDHYQjIAEW +hcNZXuVaU9FKhVydCAutJ0LuoLqp/upZrQQXVr9aaIvyfg/nAoOEBu83pd2GaBhA +nXkXlrZnBdeF4DLrFfwqDQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4256 ) +`pragma protect data_block +N7kA2Aw1KHYTvyYZ5jk2hDoFzhwW22m0iborj/oSqosAZ3Y0JL4yAT5O/swF//F8 +9N0rRDWeI1sgKL+AfsWTQvblcWvWVYgopy6S2LHmWbs5nTFAZrgffVo5lRu7RXhT +ajpbxrpEMeNRCnKBSVDocLKtCiCVmHXg33sPeufU9YNarKOExvPbBTj1DfaMtbxl +IsBv8PVCGG1FYa+Jjh5Lry5JErnbD7QcUpG/gOz9RoQXrcqqBnRo7oWe/fxOoMkj +ZoeyslZb9zFRQUCqmPgEPPtAWkQONvWyyAnf56fOBUnGI8gg63ZS+PLXxQKMs8s6 +shIXmSz+cuUiV8c1msUd/LRk/6S1uhzljiqD9KsYhG0PcC1YfM0shriMDZ8HZ6rS +tJEzkLx3pxQUcIO/HjctnH03omNP4UOe05Ht9vQ7bEyYIHcwyBZqpdp5x/aN1mhz +vpRL5Ak7rWBjMa5r6Kz7/69HMn6E6i/PvRd9LGuYz7C6NV+flcYSD/2/e7HISlrL +CuyAgPJ+5IncljDCfuf2C0nCS8LXA2fcmDoro7UnqzeoG/ABOHE7szD1DjuxgVS+ +dScCALv2ZsUJTG4RZLoZ8tMkA8sUSHb0YOaTSfuTWwLyf2oPfLLq9T2mPWyiEUal +z9Qd/+9fTh8JdvG5sFNwqxE5btVLZSwelHLWrnClNlH0efQFOjlDdYinQim1gG2i +mC0H6aKR4nV5UwwUd1mjSyLQsXimBMjz8g871e1Zar1ZvdVwsr2+ZzwXDVhqi/H+ ++rRq/oLmQ4Ft/Iz8F8IrghbbvQ5oCF+WG3tzcwZgB66cQvXMdn2HSgTug/r2qkWU +w5Q2xRPsQmGuwxWcKA3jTXpeIYVzc0a+nzI008zDujBRHC33yLX2JojBxDAPGMyg +6FFAJy1KrAxjIOvsCiGCV3S/6sOzCHd1SScXhbnFCOWj/EC42Lvtjrtq+ron3fSv +pyAzrEQ5qyj3vNqtmDFVLWwEdAic74hvinuutBROzUny9x9l/WcvPVA+xp6tZYjH +y94m3nAmCdnTE6wSRJRTKUFuS1kIsc6h6sBshbQ9k6KttcNVc+sjglhEdU5cmYGt +oiyhYqtC4++bjeGJP9sL2k0Ij8Sw/ntcxLPtxfIMW2iGuaoNp0l5BIQQ+KbpxIzY +8hwRqLT+zIDVe+mq4DwCs1qTqQDSu+t1o7h8bTcnRS61GV3fKWauyrOmSxLXeKn/ +AE4XNY/Dmvgv7I9VPDNlxwP/cwnQlkggY3m39A0aOk2BmSVGyt+Z8l9ObX2JuePL +qW3EueqwaG2qzVMF/UgqGyyjt2v1rskYGaHtTzsAHWMh9pJMxmjuz2NHohDT4SLR +oXesztSTZsSSW5k13kjELml1I/v+TW+fFkl+WEOBCu+2iFLwfqbDww+uO9bxaPiv +VYToiQHHPZNWWVFTM8/OQiygxqRFRmoQUBWFZwgh6t4I8TWDy4aJCDY6C8LeyEOT +DK7SlDJqTMkqxV/3lNrx1Bl6K5NJvH6KU9uyBBrmdsIx5VTTeO9gWGDUxJxIvUtP +Rv3yOX0mWxuqEPAtlJKvhjk61iNr3FNQPGiik7VfqS81zlsjst8C252hMCRoL/9g +ceUXnyok5bV69csmAGpW9phJsgIIxllADhsoPckdEX4nJLPV+PS11x4aZF64y4WV +nWyVawhgTYJo4z9/a78AFNyvopIstNkw7r+Q9XxvePwNj+ZXNGqii0kFk8ULHB6A +Skg3rMbIMkjcZFcrl+bEMSB+aCRT4f/VeCIoE0XNKVfOtCb4txETpTjiJhjZxqCK +JLTEeBCaMtM+ag7r2zeeSj3Ur2cOll0dl4tDR17MNawAVW0eo8dJDYOmWP6Hlu37 +44ojLGKvZtN6aU8eKhFq0VRoC8JQVdLw5wYLJiFl00gjezQWo5prMIkZZ0ovXrfp +8a8EfV+txBB7Sw2qvaLaf6kNmJKXOHjthw2a+3S47Lg5ogLijyqwOricbnxlOuWb +vLnKVKaS3+Ni3k2Kw+yjdaP35FMPjpD+0z1bFbC3MyoNAgMWysempeZ7PHH8t1ys +22ttpunniEC62Og5iJy60oPgpjFlTdUUSpFuGA85ub4IR3VD06WkVstHvhjDFt0s +TNK6/AA1jAVDezSAXtLwAtxpQFuKc0tv1yn7G35QytIfTVSvTJDl0obf6rF/vqBu +MSX0rtkqxLCCQ0uzZO1du/GxLXEz5fZnItin6wSjaEEpdrI9Rx1jBMTwgAC4ege1 +6IrCjcBf5i8PmcebWb7S5JZ71YSsegXT8UPeAByH+FDeJn4ve2cfXmaP+ysVaoh1 +phlBPSmbcibUUzHMc52y3hkJvo7jAfFCv8FW3QMXB5FgdN9mc0mKHrLiUXfEHJBt +aAcfA6H8u985OYiyL4/MVD4iHFaZuoTSsE2xWdKLwIa2hoYx9eC+LkfkTrBjwrXM +E289sD+mEtcJuOssNQdKRKJMdhOa8DsCISeAkscr5GBNhDndHmJm4vHQaJdoRn2o +mNNwI+XbRhoF3rl0tsepq4NtpIv10edZlMqDyO1qx8ZpyKU/MQn+t66LiKxsdgxF +PZloHUkc5gC4NhXqSqtdh0g5mQY7kuA+Cc4Idj1UrzjeHI2jKGnkZvBJc3u6mHuZ +pT23WOBA0kKQjghLhxZ+Yc1dUDPbyRgKIZwJhsKENcOkhF95nGTYD13YIKiaWm+D +v8qIzLxicBJlFJdh+bEo1V+nNfbba8Ku4kLoutnFr2IRF61gTV+gZR5znhP93soJ +lCQh7za3Fliv9jmCm1TXSKv88atIBEldgO8wrz6JGBzSQn6zg2NsSFRVpFBJNJzb +kvkhHhe0PAGpPgP0L7BHtSA9GG1yzwmF77UftM3gPbO8/z1c9fYIltx7T5hkiMkh +OCFAh/cukUNZa8JZqUBfoEHf0ULqoDkn0vPYK8kqHZKri+rENgGnV+Srsa+g6sXO +EWwidHBg5affuFrZALyblOBbtDjNDLiwHPiuNJWjUgtfYA21kqmdji8G7g+6HGc/ +1tEPrywDy1uWGmpDevTIuEu6KRN3Tu0o7Vg1dgfFI5FC9hiVyfi9PXpZw3PkEf8P +vfeSq6lEPk0V5DxV2YiJ/VmYhWVlwve44nXwAI5ZeNuoIx+p72LH2aEf/j80sqMa +msMccG3q/iejV3AfDdYbBeFbCmNg008ST3k8oDIYmNs69e/Eeh2BpnT433UOsIpU +iiehPjezqNdMoN3mzXHvxnHTbGRukJfCoAmcnNiMXNZZZsM3jxK08/QcoJsPOBeo +3tN0yr70C/BBVg4r8A04LH5BjTTPwZkYM68oJ3jxDyCwBw+1L+FQ0gQUQfaBSd/9 +jUUFtQ8jZY9NiDS1MoiQYBKhqrVGIt2misyeoEic5X7GghSFA1XWkkcLf5bJECgC +6iJWZOiDQ8QnXKqiH1HJLEG9lHauoN8J+r//0xcwgffR7tH/Wphyhd85a1V76aM4 +v1wZGmXgvdyTuhs/2U3WxSRXgPbmaT1YwwJGSzSDJcDAGHNPmTXQoYQ/rv2AxbPL +MuQB1h9qAJaEhUJezQNey/9phSLa/gMlMOzHK3JpdHgqLRg8m/TIIBwCdBSsiBfz +ixNkKARP6KBK1roco/GBrxqTBn5JoBuXjovThqHr15NK24bK59ID4ovPrtpSAqnQ +rm0P94Wpa0CooQ3NsoX3wH3cxmnyxy71IggWqVFOC3WR3vRbBFwym9SiA+/44uFe +I2Y7AMrTluCyjFYy+hIQrdKz+pBTxLb8Wk1zD5JXLlqqCTSc79jEurvjL45xKJuZ ++3JwgwNpoRnMXaSG/2SyJZhSXoR4MfNSi/LuReLwxRwBHEaYsexds01W7ZDmK3AM +OP6MqTBeAaY+mLVez+o/yu5GE8mBDeM+oH9d4v5GSngSwMvobM1HwSyp5ML4JU1d +g0inNwsoaMqyA9ASBbaAvr/f/SIzXMmgCg05nd2TqUb7aJsGix/3A7Dv7u4uaS3t +b1m8vnIdRRCqvByi6Vtu24pZxQW4k39Rqbj3FfWe1WdhBK4V/58iPEZqdzkGMnuq +Dnr+iIbPLthz43KVGefNxH+BBWxwPDrGPbf3R0CRtznqZ0bjQK85+NYaFNCrlas+ +aBBKWzAWmIuAeMzYsApX+JMXHFbdx178nE+ubOWx1MELhGQ+HccUiuva+PuOo0xs +dw9AXciv98gWBGDyszldTDP7VbF0tZ5Xug3vq3VEW3FmHxNbeGqbC5YuvXQHhKqc +/UAhtrNouQrjzb9Lvgm4Cir27Z8LemtuTPbnbXBtijl0Rz7NdMUNR76zhGAPLXeB +FXv6SLGY8P9evLfalONwaMek1n7v8coJH2OGHxntHIspOtt/wGeVfqY7ayCJUGwb +WQRRrSlRU7Ufzqx60yiqxnUudAjYmXttotkqMyyemtXWikDvg2oHmhJXpXapu2yc +eoHQ8vQ5lyMLX0pJKWYcv7Jf6rapiq7f+m73LwPHyXGkl2t28K1TDRdHHxo6nvuA +xO9QXYW+SqH8cZhb1/Q536Ef9PxTD2IZtZhn8nmiI7VvZtk+9HDh9SaziArtYHqS +0CL7FpkUxuSA2RFKY5ILPofW/zuxDSmOO5vyoVtWAbminsRd7xzINZUXsEBT0H7+ +96hl3LQGqq3icsf/ihv90QdcSuBUMJh4/AgRU2k2wJ1Rr0YXmcVljFskn0VrEHAl +zjteVkSERLI0PSiAA94tLBxPpZSBESf8TAnzcjNLL10TsXji4RrxAjxbRIc8NGuM +nyORQHNOD+MaWedMMnnSJC+svCUrvqWywz+Ds0hnH2UpFPDSaT/RY6nSZGiOhRH2 +4Y0XwDN0ZpxeylgN4mDFnIUDoz8an/Olr5ztX2st/02yuRYpm2Ja6pJ6t80zzQtT +JyGkR8aTnO1NxruOEBJMzByo8RAmROxYVJRUToTlAL2p4TxjYBnr/OOCtNiMjIIA +nH59jlneHC1Jz0g87/JALSriTFR682PFJhzekYcuXEQPbLp2g3INdDB3B10yBYUK +T4rRbVUN/oqChUiTDCmYLyjqxmQcHEV1ORaCr5cOjw7dEb6pVV2fbWe7o61+54RB +2PJVivmEBynhOdBd/JdC6mNoTlqgov6GVVSJi1mvs+M0OcW+9yFciHvbw4qGbSoi +fq11p4pwhFlf23piO1e3x3otlB3CtVr4Bux8nLTPr+SqEVgunVH7Kq6GgvnYqmS2 +8P2iZwamjEobkyIFaeBUp7wysCXQzG8xkYLZ9bCRKFGYZC7MGGW3Fl3mBr/jYIXD +S0yWpRleFencBoVCf/EJgbuqrenStyLHMvI6wyNRpnNOKHetkfRs2LpsgXeBxMaS +XjzzEO5BAuemACS5yk8OUY6N5IX9Qhmw/ilafE5GoguHuTzWy3p8JO+Vu8uyOVjt +c8RLkljlAvD/qJaCEGg1vHRq8XyS69Osv7d0JLqMiKpgv/x3NzhZI8oc1z5Ixvza +wjqlNC3TA30yXhraqYQYFhA1PwFmcv4MD8lPTZFQhm8z41oC6kEgwoKgCVU/0VqX +bZit2TY4c5BAMZdGsoUfeRFkUaiutUKJXxuTCWWik0vaQ7LKP1fCRluG+sYRpvdR +D2FnjqML0PLac+TLVoO4c0EtuMaMeJSxr43kVvn/51klvHlshU+Jnmq/Ashrz+oH +o06PI1ykofLIL+tANPotTMETbeStkBmY2DrnUQyNA48= +`pragma protect end_protected + +//pragma protect end + + +`include "ddr3_controller.vh" +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +KU4pgR0YsvIe0iMXLwugOA0+azH35SPA4J1nOlSYzMd0YcV97c8LtG2mTNN/Ly8D +cyvikz3qUuXBVccbpuScrmfDfLpEnG1RQ9TcozGo3JATb33lT47Xe8Md0wuVK9t1 +XBdhPPVeGEswa5dBMOk0evxWhndZ8YiU2dl+qwtPpikQKZz23m3dBV+cwq7waE0s +p7oCF/PzWWhBpA8V6TSYsCE4hRETiThK9962/AqP/ALWB3mjzlOoNLcJ7kgTXRph +GFcwnem+CbB+lqQG6paNKkEGJlFyFoz8/2ei0hf2joVUtH+bVY123xy5ZWvt08mu +jYPUtKnAPpvIQi4nNozkzQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 12960 ) +`pragma protect data_block ++k0iagFHCXthAwwE1daG98ZATas/4c9CHGIun6DrgTw/4jSH6Yli7cNd9EXMVTN4 +iMqJA3TVG/zePf8hq2ykmzf49+kSw81gwilDnZ1+vOac8pGXu9zkNeq0cPQd3LRM +wQrFD5kKUqW3HpHO7Ny0wP0nAynAMK2mkpnMzjv/9vYX+6AIFm7FIP76DUpMDBUW +tppsI357Gf/bjlfMoZeL5J1wyQAcyN8HZp7Jsu1jklOsP6nDQu1uhp7bIaVIXu47 +y0xJoyk8d7ZVDL7/Cjv9V+kmnboQ1GfjZZiP8OfiJUvdYAucNQxZ7b0RZHSryLoJ +WZL3I6Jb5JowNICAgeQezW0wOw0z5tuZrzHekCqn+ZPC9Y4A2ylunAPRBp1PW2iT +m/Am9Kv6TP/FyzAcB1Wyt3YL6B8e4a6vdL5kSsDeaPTKmp5b08KjVHh173CvA6Qk +uJzQcr0h26kZHPmDJ1Se/LLD0roySIcx3rgVv215g9oFJvVsJoT+B/RTpII/9Kht +QJq0eSdlCP4mx5GvVP8fNOKEycyg+XNNKWkltib8aN0GLpam2Y8E529xvPKYTcM5 +4rPywmJz/Gtp0oYW4SJL1cd6POLLXsJKS2tvVvrI8cPaKl25/ihg6Y27c0UriMAU +uGkvvj6TFHyUJ1za0ZuPjp/HN0D5CQbt52jllhtAeEJA4eBFgoTjOVyD+8BrDjp5 +eWOi38aTSjC/C2tF2Eiyjq12QZMw5RWoN+bJG9KXteFpVX6JqjwizrrV9RVa69gP +gXSd1C2mEYYeJTAO8eHquyuq/POhG9oqlaLifUIjxT1k3wpHw9K7DEjAkntPYUij +wrpXap2j18b9ppkTkpVSP1rDM/YbNuV1wSQC3uMiYULvWaISUSD0wm8+4IRn+r7H +LZeptInT7mJf6BmWtKkv7Z3fWot+OOVohuozzPe7HHuJ5YEt6SvUgj1UHDnugnNS +CftWtPfGUTwfvqP5s1LEmqAp4Clq1j5EJiPV53pA5cdMxb6onfS33k6vHQJKQu1d +ZjocBv3aJRxEnggc3JLEefEiE2c9OrWNDcyYEixCgvjih3vtT8BlQ7Hq/qgCwlZM ++Phd7ZNeO97uz7GlFy3E2pN+BvH9cG5UWdROwftwyBGVYbT+tj6+osGFudVvIgNf +uI9UaFvfH2XpHg2lwcVSANjVaK3g+Jbkf+j12fxlXg8KXtLVPZI3etY6detViGfe +o5fONSgkvUVD+4j8xg+K66Fl4WTs3zt1DO+504Vi9rCBqwpNPspFbBx6mnZtjudP +z06+U4BRLoffFLfcj/VY4cViDQSThFTgxmX0BoXV/D+gnoW0D2zQ6tVW9+BtzxvV +0B+s2CqGS6wVrSVzKQsVTS6MkcVIqveeusb7QzAYvwaBdojy5XmF0Ke0rfM9J86C +dfoABzgu7mJdoPP2SBKNva/YoZFUR9pRQNEK+hBkdlhRC1ecTnd7mGU7znUYV4iL +X0whpJB8vS6jNwdvryx0PDRgLBOOSVEMSgynVT0vXj31e3YAwoZchSwoL0wmFw93 +mTvz5bgEDh6zIPY3Rs/7iJl5oxnsQSewrBv6FM8ZNV6vQKczx9LdzuhUCe6bMFqj +6BQdJILc9h9Y153PjouOAJnEMMTxRkVbOkz7zwzT/STuNHPhWLUBAvpTYuf678ey +6h92LDPldk7TCf+T0UenXVAAlXfjyi/Ryku87Gv0uik6ds27L/elJj8Dpu8RVt5v +uDel6RSJpaqBl8x05fjhRtEN95m3I1LLM9DuboCv6PLMNKlXOjFg0e8v9Z2s2L7V +dCtBRvgIz7xBf2nelFwB1NeCq3krNLTCAPkiEKkMRT7wMOxe1+wljS8wgB+wTJ/s +jK4YhErYsx+QqejGxD2499XUaIU1XDiCbk7v2Pc/KIdUoCaZHoAW3QanoFPL6nr6 +ZFrSI57LRablUPA4zLbA6jrL7XcTpS2SslxiLK8Ik/k/wX1shIy45gxr9cJjIveU +/JSpTJPFYJi1EM8TjKUjnEj1bZSkYsP1IbF+C3oT3PtxG4x36SzyGF4U/7C0fmro +1077CPZ8mdE0xwE9Bl/wQho86rHJ498FyyFx0Y7ZXvFgJ5I9wkiZMLB5/FAEiEwn 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+rmcoGnzZlqh36GrctdgsoDazVtPMwGM0gOymliHIrX/x1uSWzo/t8eqZEA3T1aDC +sQo42IA6XQoF0qCDr93/u4QBUWmMUZOU4/SfJaul5h9OBfDqlMZrU/vtuotEUm2p +wea8mJZQiwCJmokKr7YEOFqPrBOWJec1AuLvzseyZAZQDxLcUn/4iFlZVptIPKsT +gs4LO5DI6aSRSdDNQcwfY1Mguht+dteUNvSEhSHvgB0rKWTprbE//rqGp6Fg/5gm +TZHEslc5nCpob13E7iAhM1JQXzvdO4lrgx3zoZ2rssbKl4WqwjcvLE0vBDQcsamm +kk/TLzA0JkvsQLdcSMGvrWdH9Hzll66qhjCTNt/syJGE9bOmPYNifl6BVzaBCAAa +ThWa8XlIVuJIMUyIB1HoZPFI07Nn9hSThNnGa+34gmW1xbBEUbjR4et9g/qBMtD+ +nJoQC6l0zW/gLl4GMyAYlfkOwiGOXX9H2fKUp/akDtZ445qWy4Cl1f/u6h1Mhspk +RJXzUyJzmCZoClRjMm0eID9LWiWZgG5exP0G9zhjWFh8PowKGwACeNwEpFTPXNfD +4M67xuSCN0UvPPN93Hgxz7jBRL8VJLKhvduG/ADbiUnwloCXTx5WopeDQBvU4a05 +IHLODlf1+hbRF7LfsfpVegOqFUkK0XMw/EZl4pvVGH2TPZe5BVnS7W6roiBOhFd3 +UTo6yme4nD33C6+vbZcojDqFSUJmZcrsw+sLeCJLNlyA0WoyzSIhOf27musXflw9 +`pragma protect end_protected + +//pragma protect end + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/DdrCtrl_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/DdrCtrl_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..6cb462a9e0ed56918fec6e0f8dbea201af8f4b72 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/DdrCtrl_define.vh @@ -0,0 +1,45 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.1.150 +// IP Version: 5.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/constraint.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/constraint.sdc new file mode 100644 index 0000000000000000000000000000000000000000..ca702cdc89b0fd12016dfcdce14dda9bd2ee85bc --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/constraint.sdc @@ -0,0 +1,271 @@ + +# Efinity Interface Designer SDC +# Version: 2023.M.7 +# Date: 2023-01-13 20:46 + +# Copyright (C) 2017 - 2023 Efinix Inc. All rights reserved. + +# Device: Ti180M484 +# Project: ti180_ddr3_controller +# Timing Model: C4 (preliminary) +# NOTE: The timing data is not final + +# PLL Constraints +################# +create_clock -period 10.0000 clk +create_clock -period 20.0000 sys_clk_100mhz +create_clock -period 2.5000 ddr_tdqss_clk +create_clock -period 5.0000 ddr_core_clk +create_clock -period 2.5000 ddr_tac_clk +create_clock -waveform {0.6250 1.8750} -period 2.5000 ddr_twd_clk +create_clock -period 20.0000 pll_inst1_CLKOUT4 + +# HSIO GPIO Constraints +######################### +# set_input_delay -clock [-reference_pin ] -max [get_ports {reset_n}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {reset_n}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~421}] -max 0.263 [get_ports {ddr_addr[0]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~421}] -min -0.140 [get_ports {ddr_addr[0]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~420}] -max 0.263 [get_ports {ddr_addr[1]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~420}] -min -0.140 [get_ports {ddr_addr[1]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~384}] -max 0.263 [get_ports {ddr_addr[2]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~384}] -min -0.140 [get_ports {ddr_addr[2]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~385}] -max 0.263 [get_ports {ddr_addr[3]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~385}] -min -0.140 [get_ports {ddr_addr[3]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~360}] -max 0.263 [get_ports {ddr_addr[4]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~360}] -min -0.140 [get_ports {ddr_addr[4]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~359}] -max 0.263 [get_ports {ddr_addr[5]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~359}] -min -0.140 [get_ports {ddr_addr[5]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~349}] -max 0.263 [get_ports {ddr_addr[6]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~349}] -min -0.140 [get_ports {ddr_addr[6]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~348}] -max 0.263 [get_ports {ddr_addr[7]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~348}] -min -0.140 [get_ports {ddr_addr[7]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~336}] -max 0.263 [get_ports {ddr_addr[8]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~336}] -min -0.140 [get_ports {ddr_addr[8]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~337}] -max 0.263 [get_ports {ddr_addr[9]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~337}] -min -0.140 [get_ports {ddr_addr[9]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~329}] -max 0.263 [get_ports {ddr_addr[10]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~329}] -min -0.140 [get_ports {ddr_addr[10]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~328}] -max 0.263 [get_ports {ddr_addr[11]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~328}] -min -0.140 [get_ports {ddr_addr[11]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~305}] -max 0.263 [get_ports {ddr_addr[12]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~305}] -min -0.140 [get_ports {ddr_addr[12]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~304}] -max 0.263 [get_ports {ddr_addr[13]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~304}] -min -0.140 [get_ports {ddr_addr[13]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~294}] -max 0.263 [get_ports {ddr_addr[14]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~294}] -min -0.140 [get_ports {ddr_addr[14]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~293}] -max 0.263 [get_ports {ddr_addr[15]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~293}] -min -0.140 [get_ports {ddr_addr[15]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~279}] -max 0.263 [get_ports {ddr_ba[0]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~279}] -min -0.140 [get_ports {ddr_ba[0]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~280}] -max 0.263 [get_ports {ddr_ba[1]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~280}] -min -0.140 [get_ports {ddr_ba[1]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~269}] -max 0.263 [get_ports {ddr_ba[2]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~269}] -min -0.140 [get_ports {ddr_ba[2]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {ddr_cal_done}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {ddr_cal_done}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {ddr_cal_pass}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {ddr_cal_pass}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~257}] -max 0.263 [get_ports {ddr_cas}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~257}] -min -0.140 [get_ports {ddr_cas}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~245}] -max 0.263 [get_ports {ddr_cke}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~245}] -min -0.140 [get_ports {ddr_cke}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~246}] -max 0.263 [get_ports {ddr_cs}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~246}] -min -0.140 [get_ports {ddr_cs}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~253~1}] -max 0.263 [get_ports {o_ddr_dm_lo[0] o_ddr_dm_hi[0]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~253~1}] -min -0.140 [get_ports {o_ddr_dm_lo[0] o_ddr_dm_hi[0]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~229~1}] -max 0.263 [get_ports {o_ddr_dm_lo[1] o_ddr_dm_hi[1]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~229~1}] -min -0.140 [get_ports {o_ddr_dm_lo[1] o_ddr_dm_hi[1]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {done}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {done}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~234}] -max 0.263 [get_ports {ddr_odt}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~234}] -min -0.140 [get_ports {ddr_odt}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {pass}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {pass}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~256}] -max 0.263 [get_ports {ddr_ras}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~256}] -min -0.140 [get_ports {ddr_ras}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~235}] -max 0.263 [get_ports {ddr_reset}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~235}] -min -0.140 [get_ports {ddr_reset}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~268}] -max 0.263 [get_ports {ddr_we}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~268}] -min -0.140 [get_ports {ddr_we}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~322~1}] -max 0.414 [get_ports {i_ddr_dq_lo[0] i_ddr_dq_hi[0]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~322~1}] -min 0.276 [get_ports {i_ddr_dq_lo[0] i_ddr_dq_hi[0]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~324~1}] -max 0.263 [get_ports {o_ddr_dq_lo[0] o_ddr_dq_hi[0]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~324~1}] -min -0.140 [get_ports {o_ddr_dq_lo[0] o_ddr_dq_hi[0]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~324~1}] -max 0.263 [get_ports {o_ddr_dq_oe[0]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~324~1}] -min -0.140 [get_ports {o_ddr_dq_oe[0]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~323~1}] -max 0.414 [get_ports {i_ddr_dq_lo[1] i_ddr_dq_hi[1]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~323~1}] -min 0.276 [get_ports {i_ddr_dq_lo[1] i_ddr_dq_hi[1]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~325~1}] -max 0.263 [get_ports {o_ddr_dq_lo[1] o_ddr_dq_hi[1]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~325~1}] -min -0.140 [get_ports {o_ddr_dq_lo[1] o_ddr_dq_hi[1]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~325~1}] -max 0.263 [get_ports {o_ddr_dq_oe[1]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~325~1}] -min -0.140 [get_ports {o_ddr_dq_oe[1]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~313~1}] -max 0.414 [get_ports {i_ddr_dq_lo[2] i_ddr_dq_hi[2]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~313~1}] -min 0.276 [get_ports {i_ddr_dq_lo[2] i_ddr_dq_hi[2]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~315~1}] -max 0.263 [get_ports {o_ddr_dq_lo[2] o_ddr_dq_hi[2]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~315~1}] -min -0.140 [get_ports {o_ddr_dq_lo[2] o_ddr_dq_hi[2]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~315~1}] -max 0.263 [get_ports {o_ddr_dq_oe[2]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~315~1}] -min -0.140 [get_ports {o_ddr_dq_oe[2]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~314~1}] -max 0.414 [get_ports {i_ddr_dq_lo[3] i_ddr_dq_hi[3]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~314~1}] -min 0.276 [get_ports {i_ddr_dq_lo[3] i_ddr_dq_hi[3]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~316~1}] -max 0.263 [get_ports {o_ddr_dq_lo[3] o_ddr_dq_hi[3]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~316~1}] -min -0.140 [get_ports {o_ddr_dq_lo[3] o_ddr_dq_hi[3]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~316~1}] -max 0.263 [get_ports {o_ddr_dq_oe[3]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~316~1}] -min -0.140 [get_ports {o_ddr_dq_oe[3]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~305~1}] -max 0.414 [get_ports {i_ddr_dq_lo[4] i_ddr_dq_hi[4]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~305~1}] -min 0.276 [get_ports {i_ddr_dq_lo[4] i_ddr_dq_hi[4]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~307~1}] -max 0.263 [get_ports {o_ddr_dq_lo[4] o_ddr_dq_hi[4]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~307~1}] -min -0.140 [get_ports {o_ddr_dq_lo[4] o_ddr_dq_hi[4]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~307~1}] -max 0.263 [get_ports {o_ddr_dq_oe[4]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~307~1}] -min -0.140 [get_ports {o_ddr_dq_oe[4]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~304~1}] -max 0.414 [get_ports {i_ddr_dq_lo[5] i_ddr_dq_hi[5]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~304~1}] -min 0.276 [get_ports {i_ddr_dq_lo[5] i_ddr_dq_hi[5]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~306~1}] -max 0.263 [get_ports {o_ddr_dq_lo[5] o_ddr_dq_hi[5]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~306~1}] -min -0.140 [get_ports {o_ddr_dq_lo[5] o_ddr_dq_hi[5]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~306~1}] -max 0.263 [get_ports {o_ddr_dq_oe[5]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~306~1}] -min -0.140 [get_ports {o_ddr_dq_oe[5]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~295~1}] -max 0.414 [get_ports {i_ddr_dq_lo[6] i_ddr_dq_hi[6]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~295~1}] -min 0.276 [get_ports {i_ddr_dq_lo[6] i_ddr_dq_hi[6]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~297~1}] -max 0.263 [get_ports {o_ddr_dq_lo[6] o_ddr_dq_hi[6]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~297~1}] -min -0.140 [get_ports {o_ddr_dq_lo[6] o_ddr_dq_hi[6]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~297~1}] -max 0.263 [get_ports {o_ddr_dq_oe[6]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~297~1}] -min -0.140 [get_ports {o_ddr_dq_oe[6]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~296~1}] -max 0.414 [get_ports {i_ddr_dq_lo[7] i_ddr_dq_hi[7]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~296~1}] -min 0.276 [get_ports {i_ddr_dq_lo[7] i_ddr_dq_hi[7]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~298~1}] -max 0.263 [get_ports {o_ddr_dq_lo[7] o_ddr_dq_hi[7]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~298~1}] -min -0.140 [get_ports {o_ddr_dq_lo[7] o_ddr_dq_hi[7]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~298~1}] -max 0.263 [get_ports {o_ddr_dq_oe[7]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~298~1}] -min -0.140 [get_ports {o_ddr_dq_oe[7]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~287~1}] -max 0.414 [get_ports {i_ddr_dq_lo[8] i_ddr_dq_hi[8]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~287~1}] -min 0.276 [get_ports {i_ddr_dq_lo[8] i_ddr_dq_hi[8]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~289~1}] -max 0.263 [get_ports {o_ddr_dq_lo[8] o_ddr_dq_hi[8]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~289~1}] -min -0.140 [get_ports {o_ddr_dq_lo[8] o_ddr_dq_hi[8]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~289~1}] -max 0.263 [get_ports {o_ddr_dq_oe[8]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~289~1}] -min -0.140 [get_ports {o_ddr_dq_oe[8]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~288~1}] -max 0.414 [get_ports {i_ddr_dq_lo[9] i_ddr_dq_hi[9]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~288~1}] -min 0.276 [get_ports {i_ddr_dq_lo[9] i_ddr_dq_hi[9]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~290~1}] -max 0.263 [get_ports {o_ddr_dq_lo[9] o_ddr_dq_hi[9]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~290~1}] -min -0.140 [get_ports {o_ddr_dq_lo[9] o_ddr_dq_hi[9]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~290~1}] -max 0.263 [get_ports {o_ddr_dq_oe[9]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~290~1}] -min -0.140 [get_ports {o_ddr_dq_oe[9]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~279~1}] -max 0.414 [get_ports {i_ddr_dq_lo[10] i_ddr_dq_hi[10]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~279~1}] -min 0.276 [get_ports {i_ddr_dq_lo[10] i_ddr_dq_hi[10]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~281~1}] -max 0.263 [get_ports {o_ddr_dq_lo[10] o_ddr_dq_hi[10]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~281~1}] -min -0.140 [get_ports {o_ddr_dq_lo[10] o_ddr_dq_hi[10]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~281~1}] -max 0.263 [get_ports {o_ddr_dq_oe[10]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~281~1}] -min -0.140 [get_ports {o_ddr_dq_oe[10]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~278~1}] -max 0.414 [get_ports {i_ddr_dq_lo[11] i_ddr_dq_hi[11]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~278~1}] -min 0.276 [get_ports {i_ddr_dq_lo[11] i_ddr_dq_hi[11]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~280~1}] -max 0.263 [get_ports {o_ddr_dq_lo[11] o_ddr_dq_hi[11]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~280~1}] -min -0.140 [get_ports {o_ddr_dq_lo[11] o_ddr_dq_hi[11]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~280~1}] -max 0.263 [get_ports {o_ddr_dq_oe[11]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~280~1}] -min -0.140 [get_ports {o_ddr_dq_oe[11]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~270~1}] -max 0.414 [get_ports {i_ddr_dq_lo[12] i_ddr_dq_hi[12]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~270~1}] -min 0.276 [get_ports {i_ddr_dq_lo[12] i_ddr_dq_hi[12]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~272~1}] -max 0.263 [get_ports {o_ddr_dq_lo[12] o_ddr_dq_hi[12]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~272~1}] -min -0.140 [get_ports {o_ddr_dq_lo[12] o_ddr_dq_hi[12]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~272~1}] -max 0.263 [get_ports {o_ddr_dq_oe[12]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~272~1}] -min -0.140 [get_ports {o_ddr_dq_oe[12]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~260~1}] -max 0.414 [get_ports {i_ddr_dq_lo[13] i_ddr_dq_hi[13]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~260~1}] -min 0.276 [get_ports {i_ddr_dq_lo[13] i_ddr_dq_hi[13]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~262~1}] -max 0.263 [get_ports {o_ddr_dq_lo[13] o_ddr_dq_hi[13]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~262~1}] -min -0.140 [get_ports {o_ddr_dq_lo[13] o_ddr_dq_hi[13]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~262~1}] -max 0.263 [get_ports {o_ddr_dq_oe[13]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~262~1}] -min -0.140 [get_ports {o_ddr_dq_oe[13]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~261~1}] -max 0.414 [get_ports {i_ddr_dq_lo[14] i_ddr_dq_hi[14]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~261~1}] -min 0.276 [get_ports {i_ddr_dq_lo[14] i_ddr_dq_hi[14]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~263~1}] -max 0.263 [get_ports {o_ddr_dq_lo[14] o_ddr_dq_hi[14]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~263~1}] -min -0.140 [get_ports {o_ddr_dq_lo[14] o_ddr_dq_hi[14]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~263~1}] -max 0.263 [get_ports {o_ddr_dq_oe[14]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~263~1}] -min -0.140 [get_ports {o_ddr_dq_oe[14]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~252~1}] -max 0.414 [get_ports {i_ddr_dq_lo[15] i_ddr_dq_hi[15]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~252~1}] -min 0.276 [get_ports {i_ddr_dq_lo[15] i_ddr_dq_hi[15]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~254~1}] -max 0.263 [get_ports {o_ddr_dq_lo[15] o_ddr_dq_hi[15]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~254~1}] -min -0.140 [get_ports {o_ddr_dq_lo[15] o_ddr_dq_hi[15]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~254~1}] -max 0.263 [get_ports {o_ddr_dq_oe[15]}] +set_output_delay -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~254~1}] -min -0.140 [get_ports {o_ddr_dq_oe[15]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~243~1}] -max 0.414 [get_ports {i_ddr_dqs_lo[0] i_ddr_dqs_hi[0]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~243~1}] -min 0.276 [get_ports {i_ddr_dqs_lo[0] i_ddr_dqs_hi[0]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~245~1}] -max 0.263 [get_ports {o_ddr_dqs_lo[0] o_ddr_dqs_hi[0]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~245~1}] -min -0.140 [get_ports {o_ddr_dqs_lo[0] o_ddr_dqs_hi[0]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~245~1}] -max 0.263 [get_ports {o_ddr_dqs_oe[0]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~245~1}] -min -0.140 [get_ports {o_ddr_dqs_oe[0]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~246~1}] -max 0.263 [get_ports {o_ddr_dqs_n_oe[0]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~246~1}] -min -0.140 [get_ports {o_ddr_dqs_n_oe[0]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~234~1}] -max 0.414 [get_ports {i_ddr_dqs_lo[1] i_ddr_dqs_hi[1]}] +set_input_delay -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~234~1}] -min 0.276 [get_ports {i_ddr_dqs_lo[1] i_ddr_dqs_hi[1]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~236~1}] -max 0.263 [get_ports {o_ddr_dqs_lo[1] o_ddr_dqs_hi[1]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~236~1}] -min -0.140 [get_ports {o_ddr_dqs_lo[1] o_ddr_dqs_hi[1]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~236~1}] -max 0.263 [get_ports {o_ddr_dqs_oe[1]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~236~1}] -min -0.140 [get_ports {o_ddr_dqs_oe[1]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~237~1}] -max 0.263 [get_ports {o_ddr_dqs_n_oe[1]}] +set_output_delay -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~237~1}] -min -0.140 [get_ports {o_ddr_dqs_n_oe[1]}] + +# Clockout Interface +###################### +# ddr_addr[0] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~421}] +# ddr_addr[10] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~329}] +# ddr_addr[11] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~328}] +# ddr_addr[12] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~305}] +# ddr_addr[13] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~304}] +# ddr_addr[14] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~294}] +# ddr_addr[15] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~293}] +# ddr_addr[1] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~420}] +# ddr_addr[2] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~384}] +# ddr_addr[3] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~385}] +# ddr_addr[4] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~360}] +# ddr_addr[5] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~359}] +# ddr_addr[6] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~349}] +# ddr_addr[7] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~348}] +# ddr_addr[8] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~336}] +# ddr_addr[9] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~337}] +# ddr_ba[0] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~279}] +# ddr_ba[1] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~280}] +# ddr_ba[2] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~269}] +# ddr_cas -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~257}] +# ddr_cke -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~245}] +# ddr_cs -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~246}] +# ddr_dm[0] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~253~1}] +# ddr_dm[1] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~229~1}] +# ddr_dq[0] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~322~1}] +# ddr_dq[0] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~324~1}] +# ddr_dq[10] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~279~1}] +# ddr_dq[10] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~281~1}] +# ddr_dq[11] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~278~1}] +# ddr_dq[11] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~280~1}] +# ddr_dq[12] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~270~1}] +# ddr_dq[12] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~272~1}] +# ddr_dq[13] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~260~1}] +# ddr_dq[13] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~262~1}] +# ddr_dq[14] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~261~1}] +# ddr_dq[14] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~263~1}] +# ddr_dq[15] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~252~1}] +# ddr_dq[15] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~254~1}] +# ddr_dq[1] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~323~1}] +# ddr_dq[1] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~325~1}] +# ddr_dq[2] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~313~1}] +# ddr_dq[2] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~315~1}] +# ddr_dq[3] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~314~1}] +# ddr_dq[3] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~316~1}] +# ddr_dq[4] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~305~1}] +# ddr_dq[4] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~307~1}] +# ddr_dq[5] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~304~1}] +# ddr_dq[5] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~306~1}] +# ddr_dq[6] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~295~1}] +# ddr_dq[6] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~297~1}] +# ddr_dq[7] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~296~1}] +# ddr_dq[7] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~298~1}] +# ddr_dq[8] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~287~1}] +# ddr_dq[8] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~289~1}] +# ddr_dq[9] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~288~1}] +# ddr_dq[9] -clock ddr_twd_clk -reference_pin [get_ports {ddr_twd_clk~CLKOUT~290~1}] +# ddr_dqs[0] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~243~1}] +# ddr_dqs[0] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~245~1}] +# ddr_dqs[0] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~246~1}] +# ddr_dqs[1] -clock ddr_tac_clk -reference_pin [get_ports {ddr_tac_clk~CLKOUT~234~1}] +# ddr_dqs[1] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~236~1}] +# ddr_dqs[1] -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~237~1}] +# ddr_odt -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~234}] +# ddr_ras -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~256}] +# ddr_reset -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~235}] +# ddr_we -clock ddr_tdqss_clk -reference_pin [get_ports {ddr_tdqss_clk~CLKOUT~333~268}] diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/ddr3_controller.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/ddr3_controller.vh new file mode 100644 index 0000000000000000000000000000000000000000..3abaf3a7d8e9904e6fbf94cf377c66565979dcef --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/ddr3_controller.vh @@ -0,0 +1,47 @@ +`define DDR3_MODE 2 +`define READ_ENABLE_PIPELINE 7 +`define RAM_IDLE 9'd0 +`define RAM_ACT 9'd3 +`define RAM_WR 9'd8 +`define RAM_RD 9'd10 +`define RAM_RD2PREA 9'd12 +`define RAM_WR2PREA 9'd18 +`define RAM_ACT2PREA 9'd28 +`define RAM_WR2RD 9'd38 +`define RAM_RD2WR 9'd45 +`define RAM_PREA2REF 9'd48 +`define RAM_REF 9'd58 +`define RAM_NOP 9'd128 +`define RAM_WPAW 9'd130 +`define RAM_WPAR 9'd146 +`define RAM_RPAW 9'd162 +`define RAM_RPAR 9'd171 +`define RAM_SRE 9'd180 +`define RAM_SR 9'd182 +`define RAM_SRX 9'd184 +`define RAM_INIT 9'd254 +`define RAM_WAITING 9'd341 +`define BRAM_LEN 345 +`define BRAM_I_WIDTH 9 +`define BRAM_D_WIDTH 72 +`define MICRO_SEC 384 +`define REF_INTERVAL 2995.2 +`define DRAM_WIDTH 16 +`define GROUP_WIDTH 8 +`define DRAM_GROUP 2 +`define DM_BIT_WIDTH 16 +`define ROW 16 +`define COL 10 +`define BANK 3 +`define BA_BIT_WIDTH 8 +`define WFIFO_WIDTH 128 +`define BL 8 +`define usReset 200 +`define usCKE 500 +`define tZQinit 512 +`define ODTH8 6 +`define tRL 5 +`define tWL 5 +`define ARBITER_INIT 1 +`define ARBITER_COUNT 4 +`define RAM_FILE "ddr3_controller.bin" diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/example_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/example_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2f7f1d76b213b2465bda2960160d6461fa2e43f5 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/example_top.v @@ -0,0 +1,425 @@ +`include "ddr3_controller.vh" + +module example_top +( +input clk, +input ddr_core_clk, +input ddr_twd_clk, +input ddr_tdqss_clk, +input ddr_tac_clk, +input reset_n, //active_low +input pll_lock, //pll_lock +input pll1_lock, //pll1_lock + +output ddr_pll_rstn, +output sys_pll_rstn, + +output ddr_reset, +output ddr_cs, +output ddr_ras, +output ddr_cas, +output ddr_we, +output ddr_cke, +output [15:0]ddr_addr, +output [2:0]ddr_ba, +output ddr_odt, +output [`DRAM_GROUP-1'b1:0] o_ddr_dm_hi, +output [`DRAM_GROUP-1'b1:0] o_ddr_dm_lo, + +input [`DRAM_GROUP-1'b1:0]i_ddr_dqs_hi, +input [`DRAM_GROUP-1'b1:0]i_ddr_dqs_lo, +output [`DRAM_GROUP-1'b1:0]o_ddr_dqs_hi, +output [`DRAM_GROUP-1'b1:0]o_ddr_dqs_lo, +output [`DRAM_GROUP-1'b1:0]o_ddr_dqs_oe, + +input [`DRAM_GROUP-1'b1:0] i_ddr_dqs_n_hi, +input [`DRAM_GROUP-1'b1:0] i_ddr_dqs_n_lo, +output [`DRAM_GROUP-1'b1:0] o_ddr_dqs_n_hi, +output [`DRAM_GROUP-1'b1:0] o_ddr_dqs_n_lo, +output [`DRAM_GROUP-1'b1:0] o_ddr_dqs_n_oe, + +input [`DRAM_WIDTH-1'b1:0] i_ddr_dq_hi, +input [`DRAM_WIDTH-1'b1:0] i_ddr_dq_lo, + +output [`DRAM_WIDTH-1'b1:0] o_ddr_dq_hi, +output [`DRAM_WIDTH-1'b1:0] o_ddr_dq_lo, + +output [`DRAM_WIDTH-1'b1:0] o_ddr_dq_oe, + +output [2:0] ddr_shift, +output [4:0] ddr_shift_sel, +output ddr_shift_ena, + +output wire ddr_cal_done, +output wire ddr_cal_pass, +output wire pass, +output wire done +); + +//parameter DDR3_MODE = `DDR3_MODE; //1-Native, 2-AXI4 + +assign ddr_pll_rstn = 1'b1; +assign sys_pll_rstn = 1'b1; + +wire w_nrst; +assign w_nrst = (reset_n && pll_lock && pll1_lock); + +wire [2:0] cal_shift_val; +wire [7:0] cal_fail_log; +wire w_wr_busy; +wire [`WFIFO_WIDTH-1'b1:0]w_wr_data; +wire [`DM_BIT_WIDTH-1'b1:0]w_wr_datamask; +wire [31:0]w_wr_addr; +wire w_wr_en; +wire w_wr_ack; + +wire w_rd_busy; +wire [31:0] w_rd_addr; +wire w_rd_en; +wire [`WFIFO_WIDTH-1'b1:0]w_rd_data; +wire w_rd_valid; + +wire w_cal_done; + +assign ddr_cal_done = w_cal_done; + +parameter START_ADDR = 32'h000000; +`ifdef RTL_SIM + parameter END_ADDR = 32'h0000100; +`else + parameter END_ADDR = 32'h1ffffff; +`endif + +generate + if (`DDR3_MODE == 1) //Native + begin + memory_checker_native #( + .START_ADDR(START_ADDR), + .END_ADDR(32'h0008000) + ) u0( + .clk (clk), + .reset_n (w_nrst), + .test_start (w_cal_done), + .wr_busy (w_wr_busy), + .wr_data (w_wr_data), + .wr_datamask(w_wr_datamask), + .wr_addr (w_wr_addr), + .wr_en (w_wr_en), + .wr_ack (w_wr_ack), + + .rd_busy (w_rd_busy), + .rd_addr (w_rd_addr), + .rd_en (w_rd_en), + .rd_data (w_rd_data), + .rd_valid (w_rd_valid), + + .test_pass (pass), + .test_done (done) + ); + + DdrCtrl u1 + ( + .clk (clk), + .core_clk (ddr_core_clk), + .tac_clk (ddr_tac_clk), + .twd_clk (ddr_twd_clk), + .tdqss_clk (ddr_tdqss_clk), + .reset_n (w_nrst), + + .reset (ddr_reset), + .cs (ddr_cs), + .ras (ddr_ras), + .cas (ddr_cas), + .we (ddr_we), + .cke (ddr_cke), + .addr (ddr_addr), + .ba (ddr_ba), + .odt (ddr_odt), + .o_dm_hi (o_ddr_dm_hi), + .o_dm_lo (o_ddr_dm_lo), + + .i_dq_hi (i_ddr_dq_hi), + .i_dq_lo (i_ddr_dq_lo), + + .o_dq_hi (o_ddr_dq_hi), + .o_dq_lo (o_ddr_dq_lo), + .o_dq_oe (o_ddr_dq_oe), + .i_dqs_hi (i_ddr_dqs_hi), + .i_dqs_lo (i_ddr_dqs_lo), + .i_dqs_n_hi (i_ddr_dqs_n_hi), + .i_dqs_n_lo (i_ddr_dqs_n_lo), + + .o_dqs_hi (o_ddr_dqs_hi), + .o_dqs_lo (o_ddr_dqs_lo), + .o_dqs_n_hi (o_ddr_dqs_n_hi), + .o_dqs_n_lo (o_ddr_dqs_n_lo), + + .o_dqs_oe (o_ddr_dqs_oe), + .o_dqs_n_oe (o_ddr_dqs_n_oe), + + .wr_busy (w_wr_busy), + .wr_data (w_wr_data), + .wr_datamask(w_wr_datamask), + .wr_addr (w_wr_addr), + .wr_en (w_wr_en), + .wr_addr_en (w_wr_en), + .wr_ack (w_wr_ack), + + .rd_busy (w_rd_busy), + .rd_addr (w_rd_addr), + .rd_addr_en (w_rd_en), + .rd_en (1'b1), + .rd_data (w_rd_data), + .rd_valid (w_rd_valid), + .rd_ack (), + + .shift(ddr_shift), + .shift_sel(ddr_shift_sel), + .shift_ena(ddr_shift_ena), + .cal_ena(1'b1), + .cal_done(w_cal_done), + .cal_pass(ddr_cal_pass) + ); + end + else //AXI4 + begin + wire reset; + wire io_systemReset; + wire io_memoryReset; + + wire io_memoryResetn; + wire [1:0] io_ddrA_b_payload_resp=2'b00; + wire axi4Interrupt; + wire [7:0] axi_awid; + wire [31:0] axi_awaddr; + wire [7:0] axi_awlen; + wire [2:0] axi_awsize; + wire [1:0] axi_awburst; + wire axi_awlock; + wire [3:0] axi_awcache; + wire [2:0] axi_awprot; + wire [3:0] axi_awqos; + wire [3:0] axi_awregion; + wire axi_awvalid; + wire axi_awready; + wire [31:0] axi_wdata; + wire [3:0] axi_wstrb; + wire axi_wvalid; + wire axi_wlast; + wire axi_wready; + wire [7:0] axi_bid; + wire [1:0] axi_bresp; + wire axi_bvalid; + wire axi_bready; + wire [7:0] axi_arid; + wire [31:0] axi_araddr; + wire [7:0] axi_arlen; + wire [2:0] axi_arsize; + wire [1:0] axi_arburst; + wire axi_arlock; + wire [3:0] axi_arcache; + wire [2:0] axi_arprot; + wire [3:0] axi_arqos; + wire [3:0] axi_arregion; + wire axi_arvalid; + wire axi_arready; + wire [7:0] axi_rid; + wire [31:0] axi_rdata; + wire [1:0] axi_rresp; + wire axi_rlast; + wire axi_rvalid; + wire axi_rready; + wire userInterrupt_0; + wire [15:0] io_apbSlave_0_PADDR; + wire io_apbSlave_0_PSEL; + wire io_apbSlave_0_PENABLE; + wire io_apbSlave_0_PREADY; + wire io_apbSlave_0_PWRITE; + wire [31:0] io_apbSlave_0_PWDATA; + wire [31:0] io_apbSlave_0_PRDATA; + wire io_apbSlave_0_PSLVERROR; + wire [7:0] m_aid_0; + wire [31:0] m_aaddr_0; + wire [7:0] m_alen_0; + wire [2:0] m_asize_0; + wire [1:0] m_aburst_0; + wire [1:0] m_alock_0; + wire m_avalid_0; + wire m_aready_0; + wire m_awready_0; + wire m_arready_0; + wire m_atype_0; + wire [7:0] m_wid_0; + wire [127:0] m_wdata_0; + wire [15:0] m_wstrb_0; + wire m_wlast_0; + wire m_wvalid_0; + wire m_wready_0; + wire [7:0] m_rid_0; + wire [127:0] m_rdata_0; + wire m_rlast_0; + wire m_rvalid_0; + wire m_rready_0; + wire [1:0] m_rresp_0; + wire [7:0] m_bid_0; + wire [1:0] m_bresp_0; + wire m_bvalid_0; + wire m_bready_0; + wire m_awvalid_0; + wire m_arvalid_0; + wire m_pass_0; + wire m_start_0; + wire io_axiMasterReset_0; + wire io_ddrA_arw_valid; + wire io_ddrA_arw_ready; + wire [31:0] io_ddrA_arw_payload_addr; + wire [7:0] io_ddrA_arw_payload_id; + wire [7:0] io_ddrA_arw_payload_len; + wire [2:0] io_ddrA_arw_payload_size; + wire [1:0] io_ddrA_arw_payload_burst; + wire [1:0] io_ddrA_arw_payload_lock; + wire io_ddrA_arw_payload_write; + wire [7:0] io_ddrA_w_payload_id; + wire io_ddrA_w_valid; + wire io_ddrA_w_ready; + wire [127:0] io_ddrA_w_payload_data; + wire [15:0] io_ddrA_w_payload_strb; + wire io_ddrA_w_payload_last; + wire io_ddrA_b_valid; + wire io_ddrA_b_ready; + wire [7:0] io_ddrA_b_payload_id; + wire io_ddrA_r_valid; + wire io_ddrA_r_ready; + wire [127:0] io_ddrA_r_payload_data; + wire [7:0] io_ddrA_r_payload_id; + wire [1:0] io_ddrA_r_payload_resp; + wire io_ddrA_r_payload_last; + wire dyn_pll_phase_en; + wire [2:0] dyn_pll_phase_sel; + + + assign io_memoryResetn = w_nrst; + + memory_checker_axi #( + .START_ADDR(START_ADDR), + .STOP_ADDR(END_ADDR), + .ALEN(63), + .WIDTH(128) + ) memcheck_0 ( + .axi_clk(clk), + .rstn(io_memoryResetn), + .start(w_cal_done), + .aid(m_aid_0), + .aaddr(m_aaddr_0), + .alen(m_alen_0), + .asize(m_asize_0), + .aburst(m_aburst_0), + .alock(m_alock_0), + .avalid(m_avalid_0), + .aready(m_aready_0), + .atype(m_atype_0), + .wid(m_wid_0), + .wdata(m_wdata_0), + .wstrb(m_wstrb_0), + .wlast(m_wlast_0), + .wvalid(m_wvalid_0), + .wready(m_wready_0), + .rid(m_rid_0), + .rdata(m_rdata_0), + .rlast(m_rlast_0), + .rvalid(m_rvalid_0), + .rready(m_rready_0), + .rresp(m_rresp_0), + .bid(m_bid_0), + .bvalid(m_bvalid_0), + .bready(m_bready_0), + .pass(pass), + .done(done) + ); + + + + DdrCtrl inst_ddr3_axi + ( + .core_clk (ddr_core_clk), + .tac_clk (ddr_tac_clk), + .twd_clk (ddr_twd_clk), + .tdqss_clk (ddr_tdqss_clk), + + + .reset (ddr_reset), + .cs (ddr_cs), + .ras (ddr_ras), + .cas (ddr_cas), + .we (ddr_we), + .cke (ddr_cke), + .addr (ddr_addr), + .ba (ddr_ba), + .odt (ddr_odt), + .o_dm_hi (o_ddr_dm_hi), + .o_dm_lo (o_ddr_dm_lo), + + .i_dq_hi (i_ddr_dq_hi), + .i_dq_lo (i_ddr_dq_lo), + + .o_dq_hi (o_ddr_dq_hi), + .o_dq_lo (o_ddr_dq_lo), + + .o_dq_oe (o_ddr_dq_oe), + + .i_dqs_hi (i_ddr_dqs_hi), + .i_dqs_lo (i_ddr_dqs_lo), + .i_dqs_n_hi (i_ddr_dqs_n_hi), + .i_dqs_n_lo (i_ddr_dqs_n_lo), + + + .o_dqs_hi (o_ddr_dqs_hi), + .o_dqs_lo (o_ddr_dqs_lo), + .o_dqs_n_hi (o_ddr_dqs_n_hi), + .o_dqs_n_lo (o_ddr_dqs_n_lo), + + .o_dqs_oe (o_ddr_dqs_oe), + .o_dqs_n_oe (o_ddr_dqs_n_oe), + + .clk(clk), + .reset_n(io_memoryResetn), + .axi_avalid(m_avalid_0), + .axi_aready(m_aready_0), + .axi_aaddr(m_aaddr_0), + .axi_aid(m_aid_0), + .axi_alen(m_alen_0), + .axi_asize(m_asize_0), + .axi_aburst(m_aburst_0), + .axi_alock(m_alock_0), + .axi_atype(m_atype_0), + + .axi_wid(m_wid_0), + .axi_wvalid(m_wvalid_0), + .axi_wready(m_wready_0), + .axi_wdata(m_wdata_0), + .axi_wstrb(m_wstrb_0), + .axi_wlast(m_wlast_0), + + .axi_bvalid(m_bvalid_0), + .axi_bready(m_bready_0), + .axi_bid(m_bid_0), + .axi_bresp(), + + .axi_rvalid(m_rvalid_0), + .axi_rready(m_rready_0), + .axi_rdata(m_rdata_0), + .axi_rid(m_rid_0), + .axi_rresp(m_rresp_0), + .axi_rlast(m_rlast_0), + + .shift(ddr_shift), + .shift_sel(ddr_shift_sel), + .shift_ena(ddr_shift_ena), + .cal_ena(1'b1), + .cal_done(w_cal_done), + .cal_pass(ddr_cal_pass) + ); + end +endgenerate + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/memory_checker_axi.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/memory_checker_axi.v new file mode 100644 index 0000000000000000000000000000000000000000..d02695fbba92325548d896f5ca89c30ab10f2c57 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/memory_checker_axi.v @@ -0,0 +1,343 @@ +module memory_checker_axi #( + parameter WIDTH = 32, + parameter ALEN = 23, + parameter START_ADDR = 32'h00000000, + parameter STOP_ADDR = 32'h00100000, + parameter ADDR_OFFSET = (ALEN + 1)*(WIDTH/8) +) ( +input axi_clk, +input rstn, +input start, +output reg [7:0] aid, +output reg [31:0] aaddr, +output reg [7:0] alen, +output reg [2:0] asize, +output reg [1:0] aburst, +output reg [1:0] alock, +output reg avalid, +input aready, +output reg atype, + +output reg [7:0] wid, +output reg [WIDTH-1:0] wdata, +output [WIDTH/8-1:0] wstrb, +output reg wlast, +output reg wvalid, +input wready, + +input [7:0] rid, +input [WIDTH-1:0] rdata, +input rlast, +input rvalid, +output reg rready, +input [1:0] rresp, + +input [7:0] bid, +input bvalid, +output reg bready, +output pass, + +output reg done + +); + +/////////////////////////////////////////////////////////////////////////////// +localparam ASIZE = (WIDTH == 256)? 5 : + (WIDTH == 128)? 4 : + (WIDTH == 64)? 3 : 2; + +//Main states +localparam COMPARE_WIDTH = WIDTH; +localparam IDLE = 4'b0000, + WRITE_ADDR = 4'b0001, + PRE_WRITE = 4'b0010, + WRITE = 4'b0011, + POST_WRITE = 4'b0100, + READ_ADDR = 4'b0101, + PRE_READ = 4'b0110, + READ_COMPARE = 4'b0111, + POST_READ = 4'b1000, + DONE = 4'b1001; + +//reg [3:0] states, nstates; +reg fail; +//reg done; +reg [3:0] states; +reg [3:0] nstates; +reg bvalid_done; +reg [1:0] start_sync; +reg [8:0] write_cnt, read_cnt; +reg [WIDTH-1:0] rdata_store; +reg wburst_done, + rburst_done, + write_done, + read_done; + +/////////////////////////////////////////////////////////////////////////////// + //assign aid = 8'h00; + assign wstrb = {WIDTH/8{1'b1}}; + //assign wid = 8'h00; + assign pass = done & ~fail; + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + start_sync <= 2'b00; + end else begin + start_sync[0] <= start; + start_sync[1] <= start_sync[0]; + end + end + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + states <= IDLE; + end else begin + states <= nstates; + end + end + + always @(states or start_sync[1] or write_cnt or rburst_done or write_done or read_done or bvalid_done or aready) + begin + case(states) + IDLE : + if (start_sync[1]) + nstates = WRITE_ADDR; + else + nstates = IDLE; + WRITE_ADDR : + if (aready) + nstates = PRE_WRITE; + else + nstates = WRITE_ADDR; + PRE_WRITE : + nstates = WRITE; + WRITE : + if (write_cnt == 9'd0) + nstates = POST_WRITE; + else + nstates = WRITE; + POST_WRITE : + if (write_done & bvalid_done) + nstates = READ_ADDR; + else if (bvalid_done) + nstates = WRITE_ADDR; + else + nstates = POST_WRITE; + READ_ADDR : + if (aready) + nstates = PRE_READ; + else + nstates = READ_ADDR; + PRE_READ : + nstates = READ_COMPARE; + READ_COMPARE : + if (rburst_done) + nstates = POST_READ; + else + nstates = READ_COMPARE; + POST_READ : + if (read_done) + nstates = DONE; + else + nstates = READ_ADDR; + DONE : + nstates = DONE; + default : + nstates = IDLE; + endcase + end + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + aaddr <= START_ADDR; + avalid <= 1'b0; + atype <= 1'b0; + aburst <= 2'b00; + asize <= 3'b000; + alen <= 8'd0; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + write_done <= 1'b0; + wdata <= {WIDTH{1'b0}}; + aid <= 3; + wid <= 0; + wburst_done <= 1'b0; + wlast <= 1'b0; + bready <= 1'b0; + fail <= 1'b0; + done <= 1'b0; + rready <= 1'b0; + bvalid_done <=1'b0; + end + else + begin + if (states == IDLE) + begin + aaddr <= START_ADDR; + avalid <= 1'b0; + atype <= 1'b0; + aburst <= 2'b00; + asize <= 3'b000; + alen <= 8'd0; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + wdata <= {WIDTH{1'b0}}; + aid <= aid; + wid <= 0; + wburst_done <= 1'b0; + wlast <= 1'b0; + bready <= 1'b0; + rready <= 1'b0; + bvalid_done <= 1'b0; + //fail <= 1'b0; + done <= 1'b0; + end + if (states == WRITE_ADDR) + begin + avalid <= 1'b1; + atype <= 1'b1; + asize <= ASIZE; + alen <= ALEN; + aburst <= 2'b01; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + wburst_done <= 1'b0; + bvalid_done <= 1'b0; + bready <= 1'b0; + rready <= 1'b0; + done <= 1'b0; + //fail <= 1'b0; + end + if (states == PRE_WRITE) + begin + avalid <= 1'b0; + atype <= 1'b0; + wvalid <= 1'b1; + wdata <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~write_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{write_cnt[7:0]}}}; + wid <= aid; + bready <= 1'b1; + write_cnt <= write_cnt - 1; + if(alen == 'd0) + begin + wlast <= 1'b1; + end + end + if (states == WRITE) + begin + if (wready == 1'b1) + begin + wdata <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~write_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{write_cnt[7:0]}}}; + if (write_cnt == 9'd0) + begin + wburst_done <= 1'b1; + wlast <= 1'b0; + wvalid <= 1'b0; + if (aaddr >= STOP_ADDR) + begin + write_done <= 1'b1; + end else + begin + write_done <= 1'b0; + end + end + if (write_cnt == 9'd1) + begin + wlast <= 1'b1; + write_cnt <= write_cnt - 1; + end + + else + begin + write_cnt <= write_cnt - 1; + end + end + end + if (states == POST_WRITE) + begin + if (write_done) + begin + aaddr <= START_ADDR; + end + else + begin + if (bvalid && (bid==aid)) begin + aaddr <= aaddr + ADDR_OFFSET; + aid <= aid + 1; + end + end + if (wready == 1'b1) + begin + wlast <= 1'b0; + wvalid <= 1'b0; + end + if (bvalid && (bid==aid)) + begin + bvalid_done <= 1'b1; + bready <= 1'b0; + end + end + if (states == READ_ADDR) + begin + avalid <= 1'b1; + read_cnt <= ALEN + 1; + + end + if (states == PRE_READ) + begin + avalid <= 1'b0; + rburst_done <= 1'b0; + rdata_store <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~read_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{read_cnt[7:0]}}}; + read_cnt <= read_cnt - 1'b1; + end + if (states == READ_COMPARE) + begin + rready <= 1'b1; + if (read_cnt != 9'd0) + begin + if (rvalid == 1'b1) + begin + rdata_store <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~read_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{read_cnt[7:0]}}}; + read_cnt <= read_cnt - 1'b1; + if (rdata[COMPARE_WIDTH-1:0] !== rdata_store[COMPARE_WIDTH-1:0]) + fail <= 1'b1; + end + + end + end + if (read_cnt == 9'd0) + begin + if (rvalid == 1'b1) + begin + if (rdata[COMPARE_WIDTH-1:0] !== rdata_store[COMPARE_WIDTH-1:0]) + begin + fail <= 1'b1; + end + if (aaddr >= STOP_ADDR && (rid==aid)) + begin + read_done <= 1'b1; + end + else + begin + read_done <= 1'b0; + end + rburst_done <= 1'b1; + end + end + if (states == POST_READ) + begin + aaddr <= aaddr + ADDR_OFFSET; + rready <= 1'b1; + end + if (states == DONE) + begin + done <= 1'b1; + end + end + end +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/work_pt/peri_res.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/work_pt/peri_res.json new file mode 100644 index 0000000000000000000000000000000000000000..da6bd0eecb6de8647b2c9670e4829cf923e1185a --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/Ti180M484_devkit/work_pt/peri_res.json @@ -0,0 +1,3 @@ +{ + "migration_launch_pt": "normal" +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/ddr3_controller.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/ddr3_controller.vh new file mode 100644 index 0000000000000000000000000000000000000000..6071a69babf8603642e62a67dbc153dd4c23fab8 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/ddr3_controller.vh @@ -0,0 +1,49 @@ +`define DDR3_MODE 2 +`define READ_ENABLE_PIPELINE 7 +`define RAM_IDLE 9'd0 +`define RAM_ACT 9'd3 +`define RAM_WR 9'd8 +`define RAM_RD 9'd10 +`define RAM_RD2PREA 9'd12 +`define RAM_WR2PREA 9'd18 +`define RAM_ACT2PREA 9'd28 +`define RAM_WR2RD 9'd38 +`define RAM_RD2WR 9'd45 +`define RAM_PREA2REF 9'd48 +`define RAM_REF 9'd58 +`define RAM_NOP 9'd130 +`define RAM_WPAW 9'd132 +`define RAM_WPAR 9'd148 +`define RAM_RPAW 9'd164 +`define RAM_RPAR 9'd173 +`define RAM_SRE 9'd182 +`define RAM_SR 9'd184 +`define RAM_SRX 9'd186 +`define RAM_RZQS 9'd258 +`define RAM_INIT 9'd291 +`define RAM_WAITING 9'd380 +`define BRAM_LEN 384 +`define BRAM_I_WIDTH 9 +`define BRAM_D_WIDTH 72 +`define MICRO_SEC 400 +`define REF_INTERVAL 3120 +`define DRAM_WIDTH 16 +`define GROUP_WIDTH 8 +`define DRAM_GROUP 2 +`define DM_BIT_WIDTH 16 +`define ROW 16 +`define COL 10 +`define BANK 3 +`define BA_BIT_WIDTH 8 +`define WFIFO_WIDTH 128 +`define BL 8 +`define usReset 200 +`define usCKE 500 +`define tZQinit 512 +`define tZQCS 16'd1024 +`define ODTH8 6 +`define tRL 5 +`define tWL 5 +`define ARBITER_INIT 1 +`define ARBITER_COUNT 4 +`define RAM_FILE "ddr3_controller.bin" diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/ddr3_device_ID.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/ddr3_device_ID.vh new file mode 100644 index 0000000000000000000000000000000000000000..61a8c8a3ba233665f0d5139ae6b9521bcb642a24 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/ddr3_device_ID.vh @@ -0,0 +1 @@ +`define sg25E diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/settings.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..603dc10538099b7760fcd3c7470104f4be76562a --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/DdrCtrl/settings.json @@ -0,0 +1,84 @@ +{ + "args": [ + "-o", + "DdrCtrl", + "--base_path", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory_controller", + "name": "efx_ddr3_soft_controller", + "version": "5.7.1" + } + ], + "conf": { + "data_width": "1", + "freq": "400", + "col": "10", + "row": "16", + "bank": "3", + "burst_length": "8", + "read_burst_type": "1'b0", + "cas_latency": "5", + "dll_reset": "1", + "precharge_pd": "1'b1", + "dll_enable": "1'b1", + "output_drive_strength": "1'b0", + "al": "0", + "qoff": "1'b1", + "rtt": "3", + "asr": "1'b0", + "srt": "1'b0", + "dynamic_odt": "0", + "mpr_rf": "0", + "mpr": "1'b0", + "tREFI": "7800", + "arbiter_init": "1", + "arbiter_count": "4", + "write_leveling": "1'b0", + "tdqs": "1'b0", + "DDR3_DATA_RATE": "1", + "DDR3_MODE": "2", + "READ_ENABLE_PIPELINE": "7" + }, + "output": { + "external_source_source": [ + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\DdrCtrl_tmpl.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\DdrCtrl.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\DdrCtrl_define.vh", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\DdrCtrl_tmpl.vhd" + ], + "external_example_example": [ + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Ti180J484_devkit\\constraint.sdc", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Ti180J484_devkit\\memory_checker_axi.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Ti180J484_devkit\\example_top.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Ti180J484_devkit\\DdrCtrl.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Ti180J484_devkit\\DdrCtrl_define.vh", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Ti180J484_devkit\\ti180_ddr3_controller.xml", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Ti180J484_devkit\\ti180_ddr3_controller.peri.xml" + ], + "external_script_generator": [], + "external_testbench_modelsim": [ + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\modelsim\\DdrCtrl.v" + ], + "external_testbench_testbench": [ + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\ddr3.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\efx_ddr3_soft_controller_tb.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\efx_iddr.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\efx_oddr.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\4096Mb_ddr3_parameters.vh", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\efx_srl8.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\modelsim.do", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\memory_checker_axi.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\example_top.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\ddr3_device_ID.vh", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\ddr3_controller.bin", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\ddr3_controller.vh", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\DdrCtrl.v", + "D:\\liulanqi\\FPGA_C\\1051\\1051\\ip\\DdrCtrl\\Testbench\\DdrCtrl_define.vh" + ] + }, + "sw_version": "2023.2.307", + "generated_date": "2024-10-05T14:27:05.726444" +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24.v new file mode 100644 index 0000000000000000000000000000000000000000..dd251e3e3d8c37264ee8dfe8e974acbe3a373291 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24.v @@ -0,0 +1,1363 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _762ea5eae3c24039aec0b216273a3aeb +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module FIFO_W48R24 ( +output full_o, +output empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [47:0] wdata, +output [9:0] wr_datacount_o, +output rst_busy, +output [23:0] rdata, +output [10:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (48), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (1024), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (3), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.full_o ( full_o ), +.empty_o ( empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..7ebe2911bbc728c0b47fa1b45e474a2fddb9fc5b --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 48; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 1024; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 3; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24_tmpl.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24_tmpl.v new file mode 100644 index 0000000000000000000000000000000000000000..022cbd36c0114d4fdc63de96b30b2667d54983a7 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24_tmpl.v @@ -0,0 +1,53 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +FIFO_W48R24 u_FIFO_W48R24( +.full_o ( full_o ), +.empty_o ( empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24_tmpl.vhd b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24_tmpl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..12efc0fd7d6c2afab3f98a12a56f81bca4056618 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/FIFO_W48R24_tmpl.vhd @@ -0,0 +1,72 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +COMPONENT FIFO_W48R24 is +PORT ( +full_o : out std_logic; +empty_o : out std_logic; +wr_clk_i : in std_logic; +rd_clk_i : in std_logic; +wr_en_i : in std_logic; +rd_en_i : in std_logic; +wdata : in std_logic_vector(47 downto 0); +wr_datacount_o : out std_logic_vector(9 downto 0); +rst_busy : out std_logic; +rdata : out std_logic_vector(23 downto 0); +rd_datacount_o : out std_logic_vector(10 downto 0); +a_rst_i : in std_logic); +END COMPONENT; +---------------------- End COMPONENT Declaration ------------ + +------------- Begin Cut here for INSTANTIATION Template ----- +u_FIFO_W48R24 : FIFO_W48R24 +PORT MAP ( +full_o => full_o, +empty_o => empty_o, +wr_clk_i => wr_clk_i, +rd_clk_i => rd_clk_i, +wr_en_i => wr_en_i, +rd_en_i => rd_en_i, +wdata => wdata, +wr_datacount_o => wr_datacount_o, +rst_busy => rst_busy, +rdata => rdata, +rd_datacount_o => rd_datacount_o, +a_rst_i => a_rst_i); +------------------------ End INSTANTIATION Template --------- diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/FIFO_W48R24.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/FIFO_W48R24.v new file mode 100644 index 0000000000000000000000000000000000000000..dd251e3e3d8c37264ee8dfe8e974acbe3a373291 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/FIFO_W48R24.v @@ -0,0 +1,1363 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _762ea5eae3c24039aec0b216273a3aeb +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module FIFO_W48R24 ( +output full_o, +output empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [47:0] wdata, +output [9:0] wr_datacount_o, +output rst_busy, +output [23:0] rdata, +output [10:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (48), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (1024), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (3), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.full_o ( full_o ), +.empty_o ( empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/FIFO_W48R24_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/FIFO_W48R24_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..7ebe2911bbc728c0b47fa1b45e474a2fddb9fc5b --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/FIFO_W48R24_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 48; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 1024; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 3; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2be121c383281fb9a99ff17fdb3d2650a14d67ac --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TRION", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/fifo_demo_T20.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/fifo_demo_T20.sdc new file mode 100644 index 0000000000000000000000000000000000000000..10a4a373f691ff2166122d5276e52a56b5e9fc84 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/fifo_demo_T20.sdc @@ -0,0 +1,3 @@ +create_clock -period 8.6 [get_ports pll_clkout_0] +create_clock -period 8.6 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..cf5dfab84cdf2dbd40ab9d5e0cff8b31c96d997a --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/T20F256_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +FIFO_W48R24 xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Testbench/FIFO_W48R24.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Testbench/FIFO_W48R24.v new file mode 100644 index 0000000000000000000000000000000000000000..dd251e3e3d8c37264ee8dfe8e974acbe3a373291 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Testbench/FIFO_W48R24.v @@ -0,0 +1,1363 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _762ea5eae3c24039aec0b216273a3aeb +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module FIFO_W48R24 ( +output full_o, +output empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [47:0] wdata, +output [9:0] wr_datacount_o, +output rst_busy, +output [23:0] rdata, +output [10:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (48), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (1024), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (3), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.full_o ( full_o ), +.empty_o ( empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Testbench/FIFO_W48R24_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Testbench/FIFO_W48R24_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..7ebe2911bbc728c0b47fa1b45e474a2fddb9fc5b --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Testbench/FIFO_W48R24_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 48; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 1024; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 3; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Testbench/fifo_tb.sv b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Testbench/fifo_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..1377647ccae685534650233373c9ac44df1e44df --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Testbench/fifo_tb.sv @@ -0,0 +1,473 @@ +`resetall +`timescale 1ns/1ps +`include "FIFO_W48R24_define.vh" + +module fifo_tb; + +`ifdef XRUN +initial begin + $shm_open("fifo_tb.shm"); + $shm_probe(fifo_tb,"ACMTF"); +end +`endif + +localparam WDATA_WIDTH_WGR = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 16 : + (ASYM_WIDTH_RATIO == 6)? 16 : + (ASYM_WIDTH_RATIO == 7)? 16 : + (ASYM_WIDTH_RATIO == 8)? 16 : 16; + +localparam WDATA_WIDTH_RGW = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 8 : + (ASYM_WIDTH_RATIO == 6)? 8 : + (ASYM_WIDTH_RATIO == 7)? 4 : + (ASYM_WIDTH_RATIO == 8)? 1 : 16; + +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,WDATA_WIDTH); +localparam RDATA_WIDTH_48 = (ASYM_WIDTH_RATIO >= 4) ? RDATA_WIDTH : 16; + +localparam WR_DEPTH = DEPTH; +localparam WADDR_WIDTH = depth2width(WR_DEPTH); +localparam RD_DEPTH = rddepthcompute(WR_DEPTH,WDATA_WIDTH,RDATA_WIDTH); +localparam RADDR_WIDTH = depth2width(RD_DEPTH); +localparam MEM_DATA_WIDTH = (WDATA_WIDTH >= RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); + +reg a_rst_i; +reg wr_clk; +reg rd_clk; +reg wr_en_i; +reg rd_en_i; +reg [WDATA_WIDTH-1:0] wdata; +reg [WADDR_WIDTH-1:0] waddr; +reg [RADDR_WIDTH-1:0] raddr; +reg [MEM_DATA_WIDTH-1:0] dynamic_a[$]; +reg [MEM_DATA_WIDTH-1:0] dynamic_b[$]; +reg [RDATA_WIDTH-1:0] monitor, monitor_temp; +reg [RDATA_WIDTH-1:0] read_lastdata; +reg temp_empty_o; + +wire [RDATA_WIDTH-1:0] rdata; +wire rd_valid_o; +wire prog_full_o; +wire almost_full_o; +wire full_o; +wire overflow_o; +wire wr_ack_o; +wire prog_empty_o; +wire almost_empty_o; +wire empty_o; +wire underflow_o; +wire [WADDR_WIDTH:0] datacount_o; +wire [WADDR_WIDTH:0] wr_datacount_o; +wire [RADDR_WIDTH:0] rd_datacount_o; +wire clk_i; +wire wr_clk_i; +wire rd_clk_i; +wire rst_busy_0; + +integer write_period; +integer read_period; +integer count; +integer wr_count; +integer rd_count; + +initial begin + wr_clk = 0; + rd_clk = 0; + write_period = 7; + read_period = 9; +end + +always begin + #(write_period) wr_clk <= ~wr_clk; +end + +always begin + #(read_period) rd_clk <= ~rd_clk; +end + +assign clk_i = wr_clk; +assign wr_clk_i = wr_clk; +assign rd_clk_i = wr_clk; + +initial begin + a_rst_i = 1'b1; + #1080 + a_rst_i = 1'b0; +end + +initial begin + wr_en_i = 1'b0; + rd_en_i = 1'b0; + wdata = 'h0; + waddr = 'd0; + raddr = 'd0; + dynamic_a = {}; + dynamic_b = {}; +end + +assign wr_count = WR_DEPTH; +assign rd_count = ASYM_WIDTH_RATIO < 4 ? wr_count * RAM_MUX_RATIO : wr_count / RAM_MUX_RATIO; + +initial begin + wait (~a_rst_i & rst_busy_0); + repeat (10) @ (negedge wr_clk_i) ; + count = WR_DEPTH; + repeat (wr_count) @ (negedge wr_clk_i) begin + wr_en_i = 1'b1; + wdata = {WDATA_WIDTH{$random}}; + end + repeat (2) @ (negedge wr_clk_i) begin + wr_en_i = 1'b0; + end + repeat (rd_count) @ (negedge wr_clk_i) begin + rd_en_i = 1'b1; + end + repeat (2) @ (negedge wr_clk_i) begin + rd_en_i = 1'b0; + end + repeat (10) @ (negedge wr_clk_i) ; + $finish; +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + waddr <= waddr +1; + end + end + end +end + +initial begin + forever begin + @(posedge rd_clk_i) begin + if (rd_en_i && ~empty_o) begin + raddr <= raddr + 1; + end + end + end +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + if (ENDIANESS == 0) begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + else begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin //downsize + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if(rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 1) begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + if (SYNC_CLK) begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if (dynamic_b.size() == RAM_MUX_RATIO) begin + monitor <= dynamic_a.pop_front(); + end + else if (rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else begin + integer i; + if (dynamic_b.size() == RAM_MUX_RATIO) begin + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + #0.1 + if (rd_en_i && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if(RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "FWFT") begin + if (SYNC_CLK == 0) begin + @ (negedge empty_o) begin + if (~rd_en_i && dynamic_b.size() != 1) begin + //integer i + if (RDATA_WIDTH <= WDATA_WIDTH) begin + monitor <= dynamic_a.pop_front(); + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + @ (negedge empty_o); + end + end + else begin + @ (negedge empty_o); + end + end +end + +always @ (posedge rd_clk_i)begin + monitor_temp <= monitor; + temp_empty_o <= empty_o; +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(negedge rd_clk_i) begin + if (rd_valid_o == 1 && ~a_rst_i) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - FAIL! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (rd_en_i && rd_valid_o) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - ERROR! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + end +end + +generate + if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO == 4) begin + FIFO_W48R24 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO == 4) begin + FIFO_W48R24 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO != 4) begin + FIFO_W48R24 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO != 4) begin + FIFO_W48R24 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end +endgenerate + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/FIFO_W48R24.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/FIFO_W48R24.v new file mode 100644 index 0000000000000000000000000000000000000000..dd251e3e3d8c37264ee8dfe8e974acbe3a373291 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/FIFO_W48R24.v @@ -0,0 +1,1363 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _762ea5eae3c24039aec0b216273a3aeb +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module FIFO_W48R24 ( +output full_o, +output empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [47:0] wdata, +output [9:0] wr_datacount_o, +output rst_busy, +output [23:0] rdata, +output [10:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (48), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (1024), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (3), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.full_o ( full_o ), +.empty_o ( empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/FIFO_W48R24_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/FIFO_W48R24_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..7ebe2911bbc728c0b47fa1b45e474a2fddb9fc5b --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/FIFO_W48R24_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 48; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 1024; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 3; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2685d9086ccd14629af6c18e5954b91ceb43ed30 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TITANIUM", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/fifo_demo_Ti60.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/fifo_demo_Ti60.sdc new file mode 100644 index 0000000000000000000000000000000000000000..a8ce31b8c3c29445879145d95ade991677e74f90 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/fifo_demo_Ti60.sdc @@ -0,0 +1,3 @@ +create_clock -period 3.125 [get_ports pll_clkout_0] +create_clock -period 6.250 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..cf5dfab84cdf2dbd40ab9d5e0cff8b31c96d997a --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/Ti60F225_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +FIFO_W48R24 xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/settings.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..e231a216d50f7e242c349c891cad21265c7700e7 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/FIFO_W48R24/settings.json @@ -0,0 +1,72 @@ +{ + "args": [ + "-o", + "FIFO_W48R24", + "--base_path", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_fifo_top", + "version": "5.1" + } + ], + "conf": { + "SYNC_CLK": "0", + "SYNC_STAGE": "3", + "DEPTH_2": "10", + "DATA_WIDTH": "48", + "MODE": "\"FWFT\"", + "OUTPUT_REG": "0", + "PROG_FULL_ASSERT": "128", + "PROGRAMMABLE_FULL": "\"NONE\"", + "PFN_INTERNAL": "127", + "PEA_INTERNAL": "2", + "PEN_INTERNAL": "3", + "PROGRAMMABLE_EMPTY": "\"NONE\"", + "OPTIONAL_FLAGS": "0", + "PIPELINE_REG": "1", + "FAMILY": "\"TRION\"", + "ASYM_WIDTH_RATIO": "3", + "BYPASS_RESET_SYNC": "0", + "ENDIANESS": "0" + }, + "output": { + "external_source_source": [ + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\FIFO_W48R24_tmpl.vhd", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\FIFO_W48R24_tmpl.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\FIFO_W48R24_define.vh", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\FIFO_W48R24.v" + ], + "external_example_example": [ + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\T20F256_devkit\\fifo_demo_top.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\T20F256_devkit\\fifo_demo_T20.sdc", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\T20F256_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\T20F256_devkit\\FIFO_W48R24.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\T20F256_devkit\\FIFO_W48R24_define.vh", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\T20F256_devkit\\fifo_demo.peri.xml", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\T20F256_devkit\\fifo_demo.xml" + ], + "external_example_2": [ + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Ti60F225_devkit\\fifo_demo_top.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Ti60F225_devkit\\fifo_demo_Ti60.sdc", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Ti60F225_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Ti60F225_devkit\\FIFO_W48R24.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Ti60F225_devkit\\FIFO_W48R24_define.vh", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Ti60F225_devkit\\fifo_demo.peri.xml", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Ti60F225_devkit\\fifo_demo.xml" + ], + "external_testbench_testbench": [ + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Testbench\\fifo_tb.sv", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Testbench\\xrun.sh", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Testbench\\msim.sh", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Testbench\\flist", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Testbench\\modelsim.do", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Testbench\\FIFO_W48R24.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp6nwptcp7\\ip\\FIFO_W48R24\\Testbench\\FIFO_W48R24_define.vh" + ] + }, + "sw_version": "2023.2.307", + "generated_date": "2024-05-19T05:34:52.982961" +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO.v new file mode 100644 index 0000000000000000000000000000000000000000..ecb17fa24c9e0a81407528867c313579c6bea4a4 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO.v @@ -0,0 +1,1363 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _cc349a1fbef24271bac248be1963b8b9 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module R0_FIFO ( +output full_o, +output empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [127:0] wdata, +output [7:0] wr_datacount_o, +output rst_busy, +output [15:0] rdata, +output [10:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (128), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (256), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (1), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.full_o ( full_o ), +.empty_o ( empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..cfc864af5be50b4e8e8173b47ea14f858bd97eed --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 128; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 256; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 1; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO_tmpl.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO_tmpl.v new file mode 100644 index 0000000000000000000000000000000000000000..16af790cd7c8f056a5b02f960fb124abb625052b --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO_tmpl.v @@ -0,0 +1,53 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +R0_FIFO u_R0_FIFO( +.full_o ( full_o ), +.empty_o ( empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO_tmpl.vhd b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO_tmpl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..46067bf6f222d12455955ae2952354d3a6e89bbe --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/R0_FIFO_tmpl.vhd @@ -0,0 +1,72 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +COMPONENT R0_FIFO is +PORT ( +full_o : out std_logic; +empty_o : out std_logic; +wr_clk_i : in std_logic; +rd_clk_i : in std_logic; +wr_en_i : in std_logic; +rd_en_i : in std_logic; +wdata : in std_logic_vector(127 downto 0); +wr_datacount_o : out std_logic_vector(7 downto 0); +rst_busy : out std_logic; +rdata : out std_logic_vector(15 downto 0); +rd_datacount_o : out std_logic_vector(10 downto 0); +a_rst_i : in std_logic); +END COMPONENT; +---------------------- End COMPONENT Declaration ------------ + +------------- Begin Cut here for INSTANTIATION Template ----- +u_R0_FIFO : R0_FIFO +PORT MAP ( +full_o => full_o, +empty_o => empty_o, +wr_clk_i => wr_clk_i, +rd_clk_i => rd_clk_i, +wr_en_i => wr_en_i, +rd_en_i => rd_en_i, +wdata => wdata, +wr_datacount_o => wr_datacount_o, +rst_busy => rst_busy, +rdata => rdata, +rd_datacount_o => rd_datacount_o, +a_rst_i => a_rst_i); +------------------------ End INSTANTIATION Template --------- diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/R0_FIFO.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/R0_FIFO.v new file mode 100644 index 0000000000000000000000000000000000000000..ecb17fa24c9e0a81407528867c313579c6bea4a4 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/R0_FIFO.v @@ -0,0 +1,1363 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _cc349a1fbef24271bac248be1963b8b9 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module R0_FIFO ( +output full_o, +output empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [127:0] wdata, +output [7:0] wr_datacount_o, +output rst_busy, +output [15:0] rdata, +output [10:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (128), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (256), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (1), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.full_o ( full_o ), +.empty_o ( empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/R0_FIFO_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/R0_FIFO_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..cfc864af5be50b4e8e8173b47ea14f858bd97eed --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/R0_FIFO_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 128; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 256; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 1; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2be121c383281fb9a99ff17fdb3d2650a14d67ac --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TRION", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/fifo_demo_T20.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/fifo_demo_T20.sdc new file mode 100644 index 0000000000000000000000000000000000000000..10a4a373f691ff2166122d5276e52a56b5e9fc84 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/fifo_demo_T20.sdc @@ -0,0 +1,3 @@ +create_clock -period 8.6 [get_ports pll_clkout_0] +create_clock -period 8.6 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..7a7d8f17da13b6a0390cdf1f4deff7bd53da72fa --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/T20F256_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +R0_FIFO xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Testbench/R0_FIFO.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Testbench/R0_FIFO.v new file mode 100644 index 0000000000000000000000000000000000000000..ecb17fa24c9e0a81407528867c313579c6bea4a4 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Testbench/R0_FIFO.v @@ -0,0 +1,1363 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _cc349a1fbef24271bac248be1963b8b9 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module R0_FIFO ( +output full_o, +output empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [127:0] wdata, +output [7:0] wr_datacount_o, +output rst_busy, +output [15:0] rdata, +output [10:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (128), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (256), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (1), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.full_o ( full_o ), +.empty_o ( empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Testbench/R0_FIFO_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Testbench/R0_FIFO_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..cfc864af5be50b4e8e8173b47ea14f858bd97eed --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Testbench/R0_FIFO_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 128; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 256; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 1; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Testbench/fifo_tb.sv b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Testbench/fifo_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..5c82b05381094b8d9ea1d8c0acf77433149db4b3 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Testbench/fifo_tb.sv @@ -0,0 +1,473 @@ +`resetall +`timescale 1ns/1ps +`include "R0_FIFO_define.vh" + +module fifo_tb; + +`ifdef XRUN +initial begin + $shm_open("fifo_tb.shm"); + $shm_probe(fifo_tb,"ACMTF"); +end +`endif + +localparam WDATA_WIDTH_WGR = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 16 : + (ASYM_WIDTH_RATIO == 6)? 16 : + (ASYM_WIDTH_RATIO == 7)? 16 : + (ASYM_WIDTH_RATIO == 8)? 16 : 16; + +localparam WDATA_WIDTH_RGW = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 8 : + (ASYM_WIDTH_RATIO == 6)? 8 : + (ASYM_WIDTH_RATIO == 7)? 4 : + (ASYM_WIDTH_RATIO == 8)? 1 : 16; + +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,WDATA_WIDTH); +localparam RDATA_WIDTH_48 = (ASYM_WIDTH_RATIO >= 4) ? RDATA_WIDTH : 16; + +localparam WR_DEPTH = DEPTH; +localparam WADDR_WIDTH = depth2width(WR_DEPTH); +localparam RD_DEPTH = rddepthcompute(WR_DEPTH,WDATA_WIDTH,RDATA_WIDTH); +localparam RADDR_WIDTH = depth2width(RD_DEPTH); +localparam MEM_DATA_WIDTH = (WDATA_WIDTH >= RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); + +reg a_rst_i; +reg wr_clk; +reg rd_clk; +reg wr_en_i; +reg rd_en_i; +reg [WDATA_WIDTH-1:0] wdata; +reg [WADDR_WIDTH-1:0] waddr; +reg [RADDR_WIDTH-1:0] raddr; +reg [MEM_DATA_WIDTH-1:0] dynamic_a[$]; +reg [MEM_DATA_WIDTH-1:0] dynamic_b[$]; +reg [RDATA_WIDTH-1:0] monitor, monitor_temp; +reg [RDATA_WIDTH-1:0] read_lastdata; +reg temp_empty_o; + +wire [RDATA_WIDTH-1:0] rdata; +wire rd_valid_o; +wire prog_full_o; +wire almost_full_o; +wire full_o; +wire overflow_o; +wire wr_ack_o; +wire prog_empty_o; +wire almost_empty_o; +wire empty_o; +wire underflow_o; +wire [WADDR_WIDTH:0] datacount_o; +wire [WADDR_WIDTH:0] wr_datacount_o; +wire [RADDR_WIDTH:0] rd_datacount_o; +wire clk_i; +wire wr_clk_i; +wire rd_clk_i; +wire rst_busy_0; + +integer write_period; +integer read_period; +integer count; +integer wr_count; +integer rd_count; + +initial begin + wr_clk = 0; + rd_clk = 0; + write_period = 7; + read_period = 9; +end + +always begin + #(write_period) wr_clk <= ~wr_clk; +end + +always begin + #(read_period) rd_clk <= ~rd_clk; +end + +assign clk_i = wr_clk; +assign wr_clk_i = wr_clk; +assign rd_clk_i = wr_clk; + +initial begin + a_rst_i = 1'b1; + #1080 + a_rst_i = 1'b0; +end + +initial begin + wr_en_i = 1'b0; + rd_en_i = 1'b0; + wdata = 'h0; + waddr = 'd0; + raddr = 'd0; + dynamic_a = {}; + dynamic_b = {}; +end + +assign wr_count = WR_DEPTH; +assign rd_count = ASYM_WIDTH_RATIO < 4 ? wr_count * RAM_MUX_RATIO : wr_count / RAM_MUX_RATIO; + +initial begin + wait (~a_rst_i & rst_busy_0); + repeat (10) @ (negedge wr_clk_i) ; + count = WR_DEPTH; + repeat (wr_count) @ (negedge wr_clk_i) begin + wr_en_i = 1'b1; + wdata = {WDATA_WIDTH{$random}}; + end + repeat (2) @ (negedge wr_clk_i) begin + wr_en_i = 1'b0; + end + repeat (rd_count) @ (negedge wr_clk_i) begin + rd_en_i = 1'b1; + end + repeat (2) @ (negedge wr_clk_i) begin + rd_en_i = 1'b0; + end + repeat (10) @ (negedge wr_clk_i) ; + $finish; +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + waddr <= waddr +1; + end + end + end +end + +initial begin + forever begin + @(posedge rd_clk_i) begin + if (rd_en_i && ~empty_o) begin + raddr <= raddr + 1; + end + end + end +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + if (ENDIANESS == 0) begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + else begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin //downsize + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if(rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 1) begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + if (SYNC_CLK) begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if (dynamic_b.size() == RAM_MUX_RATIO) begin + monitor <= dynamic_a.pop_front(); + end + else if (rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else begin + integer i; + if (dynamic_b.size() == RAM_MUX_RATIO) begin + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + #0.1 + if (rd_en_i && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if(RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "FWFT") begin + if (SYNC_CLK == 0) begin + @ (negedge empty_o) begin + if (~rd_en_i && dynamic_b.size() != 1) begin + //integer i + if (RDATA_WIDTH <= WDATA_WIDTH) begin + monitor <= dynamic_a.pop_front(); + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + @ (negedge empty_o); + end + end + else begin + @ (negedge empty_o); + end + end +end + +always @ (posedge rd_clk_i)begin + monitor_temp <= monitor; + temp_empty_o <= empty_o; +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(negedge rd_clk_i) begin + if (rd_valid_o == 1 && ~a_rst_i) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - FAIL! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (rd_en_i && rd_valid_o) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - ERROR! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + end +end + +generate + if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO == 4) begin + R0_FIFO u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO == 4) begin + R0_FIFO u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO != 4) begin + R0_FIFO u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO != 4) begin + R0_FIFO u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end +endgenerate + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/R0_FIFO.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/R0_FIFO.v new file mode 100644 index 0000000000000000000000000000000000000000..ecb17fa24c9e0a81407528867c313579c6bea4a4 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/R0_FIFO.v @@ -0,0 +1,1363 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _cc349a1fbef24271bac248be1963b8b9 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module R0_FIFO ( +output full_o, +output empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [127:0] wdata, +output [7:0] wr_datacount_o, +output rst_busy, +output [15:0] rdata, +output [10:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (128), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (256), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (1), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.full_o ( full_o ), +.empty_o ( empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/R0_FIFO_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/R0_FIFO_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..cfc864af5be50b4e8e8173b47ea14f858bd97eed --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/R0_FIFO_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 128; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 256; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 1; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2685d9086ccd14629af6c18e5954b91ceb43ed30 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TITANIUM", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/fifo_demo_Ti60.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/fifo_demo_Ti60.sdc new file mode 100644 index 0000000000000000000000000000000000000000..a8ce31b8c3c29445879145d95ade991677e74f90 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/fifo_demo_Ti60.sdc @@ -0,0 +1,3 @@ +create_clock -period 3.125 [get_ports pll_clkout_0] +create_clock -period 6.250 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..7a7d8f17da13b6a0390cdf1f4deff7bd53da72fa --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/Ti60F225_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +R0_FIFO xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/settings.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..cb5d3b1f7f1addaa1c0e135f426676e00c646bd4 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO/settings.json @@ -0,0 +1,72 @@ +{ + "args": [ + "-o", + "R0_FIFO", + "--base_path", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_fifo_top", + "version": "5.1" + } + ], + "conf": { + "SYNC_CLK": "0", + "SYNC_STAGE": "2", + "DEPTH_2": "8", + "DATA_WIDTH": "128", + "MODE": "\"FWFT\"", + "OUTPUT_REG": "0", + "PROG_FULL_ASSERT": "128", + "PROGRAMMABLE_FULL": "\"NONE\"", + "PFN_INTERNAL": "127", + "PEA_INTERNAL": "2", + "PEN_INTERNAL": "3", + "PROGRAMMABLE_EMPTY": "\"NONE\"", + "OPTIONAL_FLAGS": "0", + "PIPELINE_REG": "1", + "FAMILY": "\"TITANIUM\"", + "ASYM_WIDTH_RATIO": "1", + "BYPASS_RESET_SYNC": "0", + "ENDIANESS": "0" + }, + "output": { + "external_source_source": [ + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\R0_FIFO_tmpl.vhd", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\R0_FIFO_tmpl.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\R0_FIFO_define.vh", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\R0_FIFO.v" + ], + "external_example_example": [ + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\T20F256_devkit\\fifo_demo_top.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\T20F256_devkit\\fifo_demo_T20.sdc", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\T20F256_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\T20F256_devkit\\R0_FIFO.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\T20F256_devkit\\R0_FIFO_define.vh", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\T20F256_devkit\\fifo_demo.peri.xml", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\T20F256_devkit\\fifo_demo.xml" + ], + "external_example_2": [ + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\Ti60F225_devkit\\fifo_demo_top.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\Ti60F225_devkit\\fifo_demo_Ti60.sdc", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\Ti60F225_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\Ti60F225_devkit\\R0_FIFO.v", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\Ti60F225_devkit\\R0_FIFO_define.vh", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\Ti60F225_devkit\\fifo_demo.peri.xml", + "C:\\Users\\User\\AppData\\Local\\Temp\\tmp15hg3zje\\ip\\R0_FIFO\\Ti60F225_devkit\\fifo_demo.xml" + ], + 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100644 index 0000000000000000000000000000000000000000..e415a3e2aaaead62cd197ce4653b98959555b38f --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/R0_FIFO_32.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _ff3db65294a049509cbcec151351ef12 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module R0_FIFO_32 ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [127:0] wdata, +output [9:0] wr_datacount_o, +output rst_busy, +output [31:0] rdata, +output [11:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (128), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (512), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (512), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (4), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (1024), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (2), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/R0_FIFO_32_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/R0_FIFO_32_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..16051f382392053545e882f6c620526156179859 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/R0_FIFO_32_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 128; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 512; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 512; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 4; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 1024; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 2; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/R0_FIFO_32_tmpl.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/R0_FIFO_32_tmpl.v new file mode 100644 index 0000000000000000000000000000000000000000..abaddaca8e9d7f4b54006e635f510513c8d1948d --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/R0_FIFO_32_tmpl.v @@ -0,0 +1,60 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +R0_FIFO_32 u_R0_FIFO_32( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/R0_FIFO_32_tmpl.vhd b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/R0_FIFO_32_tmpl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..f9e6ebd380752d046f90594afcaa5ca93dbcccd1 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/R0_FIFO_32_tmpl.vhd @@ -0,0 +1,86 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +COMPONENT R0_FIFO_32 is +PORT ( +almost_full_o : out std_logic; +prog_full_o : out std_logic; +full_o : out std_logic; +overflow_o : out std_logic; +wr_ack_o : out std_logic; +empty_o : out std_logic; +almost_empty_o : out std_logic; +underflow_o : out std_logic; +rd_valid_o : out std_logic; +wr_clk_i : in std_logic; +rd_clk_i : in std_logic; +wr_en_i : in std_logic; +rd_en_i : in std_logic; +wdata : in std_logic_vector(127 downto 0); +wr_datacount_o : out std_logic_vector(9 downto 0); +rst_busy : out std_logic; +rdata : out std_logic_vector(31 downto 0); +rd_datacount_o : out std_logic_vector(11 downto 0); +a_rst_i : in std_logic); +END COMPONENT; +---------------------- End COMPONENT Declaration ------------ + +------------- Begin Cut here for INSTANTIATION Template ----- +u_R0_FIFO_32 : R0_FIFO_32 +PORT MAP ( +almost_full_o => almost_full_o, +prog_full_o => prog_full_o, +full_o => full_o, +overflow_o => overflow_o, +wr_ack_o => wr_ack_o, +empty_o => empty_o, +almost_empty_o => almost_empty_o, +underflow_o => underflow_o, +rd_valid_o => rd_valid_o, +wr_clk_i => wr_clk_i, +rd_clk_i => rd_clk_i, +wr_en_i => wr_en_i, +rd_en_i => rd_en_i, +wdata => wdata, +wr_datacount_o => wr_datacount_o, +rst_busy => rst_busy, +rdata => rdata, +rd_datacount_o => rd_datacount_o, +a_rst_i => a_rst_i); +------------------------ End INSTANTIATION Template --------- diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/R0_FIFO_32.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/R0_FIFO_32.v new file mode 100644 index 0000000000000000000000000000000000000000..e415a3e2aaaead62cd197ce4653b98959555b38f --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/R0_FIFO_32.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _ff3db65294a049509cbcec151351ef12 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module R0_FIFO_32 ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [127:0] wdata, +output [9:0] wr_datacount_o, +output rst_busy, +output [31:0] rdata, +output [11:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (128), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (512), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (512), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (4), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (1024), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (2), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/R0_FIFO_32_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/R0_FIFO_32_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..16051f382392053545e882f6c620526156179859 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/R0_FIFO_32_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 128; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 512; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 512; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 4; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 1024; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 2; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2be121c383281fb9a99ff17fdb3d2650a14d67ac --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TRION", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/fifo_demo_T20.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/fifo_demo_T20.sdc new file mode 100644 index 0000000000000000000000000000000000000000..10a4a373f691ff2166122d5276e52a56b5e9fc84 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/fifo_demo_T20.sdc @@ -0,0 +1,3 @@ +create_clock -period 8.6 [get_ports pll_clkout_0] +create_clock -period 8.6 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..fabecabe758dcd12249ad7fd64c88d66eb56bee8 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/T20F256_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +R0_FIFO_32 xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Testbench/R0_FIFO_32.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Testbench/R0_FIFO_32.v new file mode 100644 index 0000000000000000000000000000000000000000..e415a3e2aaaead62cd197ce4653b98959555b38f --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Testbench/R0_FIFO_32.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _ff3db65294a049509cbcec151351ef12 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module R0_FIFO_32 ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [127:0] wdata, +output [9:0] wr_datacount_o, +output rst_busy, +output [31:0] rdata, +output [11:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (128), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (512), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (512), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (4), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (1024), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (2), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Testbench/R0_FIFO_32_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Testbench/R0_FIFO_32_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..16051f382392053545e882f6c620526156179859 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Testbench/R0_FIFO_32_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 128; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 512; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 512; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 4; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 1024; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 2; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Testbench/fifo_tb.sv b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Testbench/fifo_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..53d55b623a8df2cdb913a698cd286c696d96e08a --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Testbench/fifo_tb.sv @@ -0,0 +1,473 @@ +`resetall +`timescale 1ns/1ps +`include "R0_FIFO_32_define.vh" + +module fifo_tb; + +`ifdef XRUN +initial begin + $shm_open("fifo_tb.shm"); + $shm_probe(fifo_tb,"ACMTF"); +end +`endif + +localparam WDATA_WIDTH_WGR = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 16 : + (ASYM_WIDTH_RATIO == 6)? 16 : + (ASYM_WIDTH_RATIO == 7)? 16 : + (ASYM_WIDTH_RATIO == 8)? 16 : 16; + +localparam WDATA_WIDTH_RGW = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 8 : + (ASYM_WIDTH_RATIO == 6)? 8 : + (ASYM_WIDTH_RATIO == 7)? 4 : + (ASYM_WIDTH_RATIO == 8)? 1 : 16; + +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,WDATA_WIDTH); +localparam RDATA_WIDTH_48 = (ASYM_WIDTH_RATIO >= 4) ? RDATA_WIDTH : 16; + +localparam WR_DEPTH = DEPTH; +localparam WADDR_WIDTH = depth2width(WR_DEPTH); +localparam RD_DEPTH = rddepthcompute(WR_DEPTH,WDATA_WIDTH,RDATA_WIDTH); +localparam RADDR_WIDTH = depth2width(RD_DEPTH); +localparam MEM_DATA_WIDTH = (WDATA_WIDTH >= RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); + +reg a_rst_i; +reg wr_clk; +reg rd_clk; +reg wr_en_i; +reg rd_en_i; +reg [WDATA_WIDTH-1:0] wdata; +reg [WADDR_WIDTH-1:0] waddr; +reg [RADDR_WIDTH-1:0] raddr; +reg [MEM_DATA_WIDTH-1:0] dynamic_a[$]; +reg [MEM_DATA_WIDTH-1:0] dynamic_b[$]; +reg [RDATA_WIDTH-1:0] monitor, monitor_temp; +reg [RDATA_WIDTH-1:0] read_lastdata; +reg temp_empty_o; + +wire [RDATA_WIDTH-1:0] rdata; +wire rd_valid_o; +wire prog_full_o; +wire almost_full_o; +wire full_o; +wire overflow_o; +wire wr_ack_o; +wire prog_empty_o; +wire almost_empty_o; +wire empty_o; +wire underflow_o; +wire [WADDR_WIDTH:0] datacount_o; +wire [WADDR_WIDTH:0] wr_datacount_o; +wire [RADDR_WIDTH:0] rd_datacount_o; +wire clk_i; +wire wr_clk_i; +wire rd_clk_i; +wire rst_busy_0; + +integer write_period; +integer read_period; +integer count; +integer wr_count; +integer rd_count; + +initial begin + wr_clk = 0; + rd_clk = 0; + write_period = 7; + read_period = 9; +end + +always begin + #(write_period) wr_clk <= ~wr_clk; +end + +always begin + #(read_period) rd_clk <= ~rd_clk; +end + +assign clk_i = wr_clk; +assign wr_clk_i = wr_clk; +assign rd_clk_i = wr_clk; + +initial begin + a_rst_i = 1'b1; + #1080 + a_rst_i = 1'b0; +end + +initial begin + wr_en_i = 1'b0; + rd_en_i = 1'b0; + wdata = 'h0; + waddr = 'd0; + raddr = 'd0; + dynamic_a = {}; + dynamic_b = {}; +end + +assign wr_count = WR_DEPTH; +assign rd_count = ASYM_WIDTH_RATIO < 4 ? wr_count * RAM_MUX_RATIO : wr_count / RAM_MUX_RATIO; + +initial begin + wait (~a_rst_i & rst_busy_0); + repeat (10) @ (negedge wr_clk_i) ; + count = WR_DEPTH; + repeat (wr_count) @ (negedge wr_clk_i) begin + wr_en_i = 1'b1; + wdata = {WDATA_WIDTH{$random}}; + end + repeat (2) @ (negedge wr_clk_i) begin + wr_en_i = 1'b0; + end + repeat (rd_count) @ (negedge wr_clk_i) begin + rd_en_i = 1'b1; + end + repeat (2) @ (negedge wr_clk_i) begin + rd_en_i = 1'b0; + end + repeat (10) @ (negedge wr_clk_i) ; + $finish; +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + waddr <= waddr +1; + end + end + end +end + +initial begin + forever begin + @(posedge rd_clk_i) begin + if (rd_en_i && ~empty_o) begin + raddr <= raddr + 1; + end + end + end +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + if (ENDIANESS == 0) begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + else begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin //downsize + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if(rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 1) begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + if (SYNC_CLK) begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if (dynamic_b.size() == RAM_MUX_RATIO) begin + monitor <= dynamic_a.pop_front(); + end + else if (rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else begin + integer i; + if (dynamic_b.size() == RAM_MUX_RATIO) begin + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + #0.1 + if (rd_en_i && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if(RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "FWFT") begin + if (SYNC_CLK == 0) begin + @ (negedge empty_o) begin + if (~rd_en_i && dynamic_b.size() != 1) begin + //integer i + if (RDATA_WIDTH <= WDATA_WIDTH) begin + monitor <= dynamic_a.pop_front(); + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + @ (negedge empty_o); + end + end + else begin + @ (negedge empty_o); + end + end +end + +always @ (posedge rd_clk_i)begin + monitor_temp <= monitor; + temp_empty_o <= empty_o; +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(negedge rd_clk_i) begin + if (rd_valid_o == 1 && ~a_rst_i) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - FAIL! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (rd_en_i && rd_valid_o) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - ERROR! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + end +end + +generate + if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO == 4) begin + R0_FIFO_32 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO == 4) begin + R0_FIFO_32 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO != 4) begin + R0_FIFO_32 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO != 4) begin + R0_FIFO_32 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end +endgenerate + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/R0_FIFO_32.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/R0_FIFO_32.v new file mode 100644 index 0000000000000000000000000000000000000000..e415a3e2aaaead62cd197ce4653b98959555b38f --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/R0_FIFO_32.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _ff3db65294a049509cbcec151351ef12 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module R0_FIFO_32 ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [127:0] wdata, +output [9:0] wr_datacount_o, +output rst_busy, +output [31:0] rdata, +output [11:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (128), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (512), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (512), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (4), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (1024), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (2), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/R0_FIFO_32_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/R0_FIFO_32_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..16051f382392053545e882f6c620526156179859 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/R0_FIFO_32_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 128; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 512; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 512; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 4; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 1024; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 2; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2685d9086ccd14629af6c18e5954b91ceb43ed30 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TITANIUM", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/fifo_demo_Ti60.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/fifo_demo_Ti60.sdc new file mode 100644 index 0000000000000000000000000000000000000000..a8ce31b8c3c29445879145d95ade991677e74f90 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/fifo_demo_Ti60.sdc @@ -0,0 +1,3 @@ +create_clock -period 3.125 [get_ports pll_clkout_0] +create_clock -period 6.250 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..fabecabe758dcd12249ad7fd64c88d66eb56bee8 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/Ti60F225_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +R0_FIFO_32 xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/settings.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..a300830efce7dd9e34b4f25b692989d18c6da14f --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/R0_FIFO_32/settings.json @@ -0,0 +1,72 @@ +{ + "args": [ + "-o", + "R0_FIFO_32", + "--base_path", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_fifo_top", + "version": "5.1" + } + ], + "conf": { + "SYNC_CLK": "0", + "SYNC_STAGE": "3", + "DEPTH_2": "10", + "DATA_WIDTH": "128", + "MODE": "\"FWFT\"", + "OUTPUT_REG": "0", + "PROG_FULL_ASSERT": "512", + "PROGRAMMABLE_FULL": "\"STATIC_SINGLE\"", + "PFN_INTERNAL": "511", + "PEA_INTERNAL": "4", + "PEN_INTERNAL": "5", + "PROGRAMMABLE_EMPTY": "\"NONE\"", + "OPTIONAL_FLAGS": "1", + "PIPELINE_REG": "1", + "FAMILY": "\"TITANIUM\"", + "ASYM_WIDTH_RATIO": "2", + "BYPASS_RESET_SYNC": "0", + "ENDIANESS": "0" + }, + "output": { + "external_source_source": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\R0_FIFO_32_tmpl.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\R0_FIFO_32_tmpl.vhd", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\R0_FIFO_32.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\R0_FIFO_32_define.vh" + ], + "external_example_example": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\T20F256_devkit\\fifo_demo.peri.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\T20F256_devkit\\fifo_demo.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\T20F256_devkit\\fifo_demo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\T20F256_devkit\\fifo_demo_T20.sdc", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\T20F256_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\T20F256_devkit\\R0_FIFO_32.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\T20F256_devkit\\R0_FIFO_32_define.vh" + ], + "external_example_2": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Ti60F225_devkit\\fifo_demo.peri.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Ti60F225_devkit\\fifo_demo.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Ti60F225_devkit\\fifo_demo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Ti60F225_devkit\\fifo_demo_Ti60.sdc", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Ti60F225_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Ti60F225_devkit\\R0_FIFO_32.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Ti60F225_devkit\\R0_FIFO_32_define.vh" + ], + "external_testbench_testbench": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Testbench\\fifo_tb.sv", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Testbench\\xrun.sh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Testbench\\msim.sh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Testbench\\flist", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Testbench\\modelsim.do", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Testbench\\R0_FIFO_32.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\R0_FIFO_32\\Testbench\\R0_FIFO_32_define.vh" + ] + }, + "sw_version": "2023.2.307", + "generated_date": "2024-10-10T09:59:01.061412" +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/W0_FIFO.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/W0_FIFO.v new file mode 100644 index 0000000000000000000000000000000000000000..d9b724a5e48d2846d52b84bdcec3b6f05122c53c --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/W0_FIFO.v @@ -0,0 +1,1375 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _7118a41ed8f84af5a8226ac9f890df83 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module W0_FIFO ( +output almost_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [63:0] wdata, +output [8:0] wr_datacount_o, +output rst_busy, +output [127:0] rdata, +output [7:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (64), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (512), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (5), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/W0_FIFO_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/W0_FIFO_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..528170b5fe7d83c81a66dbbd1a72311f4b0de725 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/W0_FIFO_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 64; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 512; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 5; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2be121c383281fb9a99ff17fdb3d2650a14d67ac --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TRION", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/fifo_demo_T20.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/fifo_demo_T20.sdc new file mode 100644 index 0000000000000000000000000000000000000000..10a4a373f691ff2166122d5276e52a56b5e9fc84 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/fifo_demo_T20.sdc @@ -0,0 +1,3 @@ +create_clock -period 8.6 [get_ports pll_clkout_0] +create_clock -period 8.6 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..621a16dd57c5433868cd85f984e50375c895db58 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/T20F256_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +W0_FIFO xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Testbench/W0_FIFO.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Testbench/W0_FIFO.v new file mode 100644 index 0000000000000000000000000000000000000000..d9b724a5e48d2846d52b84bdcec3b6f05122c53c --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Testbench/W0_FIFO.v @@ -0,0 +1,1375 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _7118a41ed8f84af5a8226ac9f890df83 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module W0_FIFO ( +output almost_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [63:0] wdata, +output [8:0] wr_datacount_o, +output rst_busy, +output [127:0] rdata, +output [7:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (64), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (512), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (5), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Testbench/W0_FIFO_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Testbench/W0_FIFO_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..528170b5fe7d83c81a66dbbd1a72311f4b0de725 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Testbench/W0_FIFO_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 64; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 512; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 5; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Testbench/fifo_tb.sv b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Testbench/fifo_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..244c9141257ed325bc1730ac50d9a7ba175d07ab --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Testbench/fifo_tb.sv @@ -0,0 +1,473 @@ +`resetall +`timescale 1ns/1ps +`include "W0_FIFO_define.vh" + +module fifo_tb; + +`ifdef XRUN +initial begin + $shm_open("fifo_tb.shm"); + $shm_probe(fifo_tb,"ACMTF"); +end +`endif + +localparam WDATA_WIDTH_WGR = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 16 : + (ASYM_WIDTH_RATIO == 6)? 16 : + (ASYM_WIDTH_RATIO == 7)? 16 : + (ASYM_WIDTH_RATIO == 8)? 16 : 16; + +localparam WDATA_WIDTH_RGW = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 8 : + (ASYM_WIDTH_RATIO == 6)? 8 : + (ASYM_WIDTH_RATIO == 7)? 4 : + (ASYM_WIDTH_RATIO == 8)? 1 : 16; + +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,WDATA_WIDTH); +localparam RDATA_WIDTH_48 = (ASYM_WIDTH_RATIO >= 4) ? RDATA_WIDTH : 16; + +localparam WR_DEPTH = DEPTH; +localparam WADDR_WIDTH = depth2width(WR_DEPTH); +localparam RD_DEPTH = rddepthcompute(WR_DEPTH,WDATA_WIDTH,RDATA_WIDTH); +localparam RADDR_WIDTH = depth2width(RD_DEPTH); +localparam MEM_DATA_WIDTH = (WDATA_WIDTH >= RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); + +reg a_rst_i; +reg wr_clk; +reg rd_clk; +reg wr_en_i; +reg rd_en_i; +reg [WDATA_WIDTH-1:0] wdata; +reg [WADDR_WIDTH-1:0] waddr; +reg [RADDR_WIDTH-1:0] raddr; +reg [MEM_DATA_WIDTH-1:0] dynamic_a[$]; +reg [MEM_DATA_WIDTH-1:0] dynamic_b[$]; +reg [RDATA_WIDTH-1:0] monitor, monitor_temp; +reg [RDATA_WIDTH-1:0] read_lastdata; +reg temp_empty_o; + +wire [RDATA_WIDTH-1:0] rdata; +wire rd_valid_o; +wire prog_full_o; +wire almost_full_o; +wire full_o; +wire overflow_o; +wire wr_ack_o; +wire prog_empty_o; +wire almost_empty_o; +wire empty_o; +wire underflow_o; +wire [WADDR_WIDTH:0] datacount_o; +wire [WADDR_WIDTH:0] wr_datacount_o; +wire [RADDR_WIDTH:0] rd_datacount_o; +wire clk_i; +wire wr_clk_i; +wire rd_clk_i; +wire rst_busy_0; + +integer write_period; +integer read_period; +integer count; +integer wr_count; +integer rd_count; + +initial begin + wr_clk = 0; + rd_clk = 0; + write_period = 7; + read_period = 9; +end + +always begin + #(write_period) wr_clk <= ~wr_clk; +end + +always begin + #(read_period) rd_clk <= ~rd_clk; +end + +assign clk_i = wr_clk; +assign wr_clk_i = wr_clk; +assign rd_clk_i = wr_clk; + +initial begin + a_rst_i = 1'b1; + #1080 + a_rst_i = 1'b0; +end + +initial begin + wr_en_i = 1'b0; + rd_en_i = 1'b0; + wdata = 'h0; + waddr = 'd0; + raddr = 'd0; + dynamic_a = {}; + dynamic_b = {}; +end + +assign wr_count = WR_DEPTH; +assign rd_count = ASYM_WIDTH_RATIO < 4 ? wr_count * RAM_MUX_RATIO : wr_count / RAM_MUX_RATIO; + +initial begin + wait (~a_rst_i & rst_busy_0); + repeat (10) @ (negedge wr_clk_i) ; + count = WR_DEPTH; + repeat (wr_count) @ (negedge wr_clk_i) begin + wr_en_i = 1'b1; + wdata = {WDATA_WIDTH{$random}}; + end + repeat (2) @ (negedge wr_clk_i) begin + wr_en_i = 1'b0; + end + repeat (rd_count) @ (negedge wr_clk_i) begin + rd_en_i = 1'b1; + end + repeat (2) @ (negedge wr_clk_i) begin + rd_en_i = 1'b0; + end + repeat (10) @ (negedge wr_clk_i) ; + $finish; +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + waddr <= waddr +1; + end + end + end +end + +initial begin + forever begin + @(posedge rd_clk_i) begin + if (rd_en_i && ~empty_o) begin + raddr <= raddr + 1; + end + end + end +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + if (ENDIANESS == 0) begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + else begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin //downsize + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if(rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 1) begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + if (SYNC_CLK) begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if (dynamic_b.size() == RAM_MUX_RATIO) begin + monitor <= dynamic_a.pop_front(); + end + else if (rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else begin + integer i; + if (dynamic_b.size() == RAM_MUX_RATIO) begin + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + #0.1 + if (rd_en_i && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if(RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "FWFT") begin + if (SYNC_CLK == 0) begin + @ (negedge empty_o) begin + if (~rd_en_i && dynamic_b.size() != 1) begin + //integer i + if (RDATA_WIDTH <= WDATA_WIDTH) begin + monitor <= dynamic_a.pop_front(); + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + @ (negedge empty_o); + end + end + else begin + @ (negedge empty_o); + end + end +end + +always @ (posedge rd_clk_i)begin + monitor_temp <= monitor; + temp_empty_o <= empty_o; +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(negedge rd_clk_i) begin + if (rd_valid_o == 1 && ~a_rst_i) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - FAIL! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (rd_en_i && rd_valid_o) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - ERROR! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + end +end + +generate + if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO == 4) begin + W0_FIFO u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO == 4) begin + W0_FIFO u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO != 4) begin + W0_FIFO u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO != 4) begin + W0_FIFO u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end +endgenerate + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/W0_FIFO.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/W0_FIFO.v new file mode 100644 index 0000000000000000000000000000000000000000..d9b724a5e48d2846d52b84bdcec3b6f05122c53c --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/W0_FIFO.v @@ -0,0 +1,1375 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _7118a41ed8f84af5a8226ac9f890df83 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module W0_FIFO ( +output almost_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [63:0] wdata, +output [8:0] wr_datacount_o, +output rst_busy, +output [127:0] rdata, +output [7:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (64), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (512), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (5), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/W0_FIFO_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/W0_FIFO_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..528170b5fe7d83c81a66dbbd1a72311f4b0de725 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/W0_FIFO_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 64; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 512; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 5; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2685d9086ccd14629af6c18e5954b91ceb43ed30 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TITANIUM", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/fifo_demo_Ti60.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/fifo_demo_Ti60.sdc new file mode 100644 index 0000000000000000000000000000000000000000..a8ce31b8c3c29445879145d95ade991677e74f90 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/fifo_demo_Ti60.sdc @@ -0,0 +1,3 @@ +create_clock -period 3.125 [get_ports pll_clkout_0] +create_clock -period 6.250 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..621a16dd57c5433868cd85f984e50375c895db58 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/Ti60F225_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +W0_FIFO xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO.v new file mode 100644 index 0000000000000000000000000000000000000000..d9b724a5e48d2846d52b84bdcec3b6f05122c53c --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO.v @@ -0,0 +1,1375 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _7118a41ed8f84af5a8226ac9f890df83 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module W0_FIFO ( +output almost_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [63:0] wdata, +output [8:0] wr_datacount_o, +output rst_busy, +output [127:0] rdata, +output [7:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (64), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("NONE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (512), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (5), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..528170b5fe7d83c81a66dbbd1a72311f4b0de725 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 64; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 512; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 5; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO_tmpl.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO_tmpl.v new file mode 100644 index 0000000000000000000000000000000000000000..8b43f6c14808384afcfec6d610ec4a5c11da9746 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO_tmpl.v @@ -0,0 +1,59 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +W0_FIFO u_W0_FIFO( +.almost_full_o ( almost_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO_tmpl.vhd b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO_tmpl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..c13e92e5a5a8b22fc6d06f907de15e2064f175a3 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/W0_FIFO_tmpl.vhd @@ -0,0 +1,84 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +COMPONENT W0_FIFO is +PORT ( +almost_full_o : out std_logic; +full_o : out std_logic; +overflow_o : out std_logic; +wr_ack_o : out std_logic; +empty_o : out std_logic; +almost_empty_o : out std_logic; +underflow_o : out std_logic; +rd_valid_o : out std_logic; +wr_clk_i : in std_logic; +rd_clk_i : in std_logic; +wr_en_i : in std_logic; +rd_en_i : in std_logic; +wdata : in std_logic_vector(63 downto 0); +wr_datacount_o : out std_logic_vector(8 downto 0); +rst_busy : out std_logic; +rdata : out std_logic_vector(127 downto 0); +rd_datacount_o : out std_logic_vector(7 downto 0); +a_rst_i : in std_logic); +END COMPONENT; +---------------------- End COMPONENT Declaration ------------ + +------------- Begin Cut here for INSTANTIATION Template ----- +u_W0_FIFO : W0_FIFO +PORT MAP ( +almost_full_o => almost_full_o, +full_o => full_o, +overflow_o => overflow_o, +wr_ack_o => wr_ack_o, +empty_o => empty_o, +almost_empty_o => almost_empty_o, +underflow_o => underflow_o, +rd_valid_o => rd_valid_o, +wr_clk_i => wr_clk_i, +rd_clk_i => rd_clk_i, +wr_en_i => wr_en_i, +rd_en_i => rd_en_i, +wdata => wdata, +wr_datacount_o => wr_datacount_o, +rst_busy => rst_busy, +rdata => rdata, +rd_datacount_o => rd_datacount_o, +a_rst_i => a_rst_i); +------------------------ End INSTANTIATION Template --------- diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/settings.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..f5bb0fabb1e0a9990706274c267b2e50d2a32942 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO/settings.json @@ -0,0 +1,72 @@ +{ + "args": [ + "-o", + "W0_FIFO", + "--base_path", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_fifo_top", + "version": "5.1" + } + ], + "conf": { + "SYNC_CLK": "0", + "SYNC_STAGE": "3", + "DEPTH_2": "9", + "DATA_WIDTH": "64", + "MODE": "\"FWFT\"", + "OUTPUT_REG": "0", + "PROG_FULL_ASSERT": "128", + "PROGRAMMABLE_FULL": "\"NONE\"", + "PFN_INTERNAL": "127", + "PEA_INTERNAL": "2", + "PEN_INTERNAL": "3", + "PROGRAMMABLE_EMPTY": "\"NONE\"", + "OPTIONAL_FLAGS": "1", + "PIPELINE_REG": "1", + "FAMILY": "\"TRION\"", + "ASYM_WIDTH_RATIO": "5", + "BYPASS_RESET_SYNC": "0", + "ENDIANESS": "0" + }, + "output": { + "external_source_source": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\W0_FIFO.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\W0_FIFO_define.vh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\W0_FIFO_tmpl.vhd", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\W0_FIFO_tmpl.v" + ], + "external_example_example": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\T20F256_devkit\\fifo_demo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\T20F256_devkit\\fifo_demo_T20.sdc", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\T20F256_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\T20F256_devkit\\W0_FIFO.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\T20F256_devkit\\W0_FIFO_define.vh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\T20F256_devkit\\fifo_demo.peri.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\T20F256_devkit\\fifo_demo.xml" + ], + "external_example_2": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Ti60F225_devkit\\fifo_demo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Ti60F225_devkit\\fifo_demo_Ti60.sdc", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Ti60F225_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Ti60F225_devkit\\W0_FIFO.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Ti60F225_devkit\\W0_FIFO_define.vh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Ti60F225_devkit\\fifo_demo.peri.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Ti60F225_devkit\\fifo_demo.xml" + ], + "external_testbench_testbench": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Testbench\\fifo_tb.sv", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Testbench\\xrun.sh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Testbench\\msim.sh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Testbench\\flist", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Testbench\\modelsim.do", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Testbench\\W0_FIFO.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO\\Testbench\\W0_FIFO_define.vh" + ] + }, + "sw_version": "2023.2.307", + "generated_date": "2024-10-09T14:27:53.011834" +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/W0_FIFO_32.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/W0_FIFO_32.v new file mode 100644 index 0000000000000000000000000000000000000000..68b38f9e0a80898fd171905a4216e1760da2a891 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/W0_FIFO_32.v @@ -0,0 +1,1367 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _86fdad8fd5cf42519e2204399d3b6af7 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module W0_FIFO_32 ( +output prog_full_o, +output full_o, +output empty_o, +output prog_empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [31:0] wdata, +output [11:0] wr_datacount_o, +output rst_busy, +output [127:0] rdata, +output [9:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (32), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (3072), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (3072), +.PROGRAMMABLE_EMPTY ("STATIC_SINGLE"), +.PROG_EMPTY_ASSERT (255), +.PROG_EMPTY_NEGATE (255), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (4096), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (6), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.empty_o ( empty_o ), +.prog_empty_o ( prog_empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/W0_FIFO_32_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/W0_FIFO_32_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..766836f109d68916cb60ebaab4ed52c14ae3afb0 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/W0_FIFO_32_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 32; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 3072; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 3072; +localparam PROGRAMMABLE_EMPTY = "STATIC_SINGLE"; +localparam PROG_EMPTY_ASSERT = 255; +localparam PROG_EMPTY_NEGATE = 255; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 4096; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 6; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2be121c383281fb9a99ff17fdb3d2650a14d67ac --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TRION", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/fifo_demo_T20.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/fifo_demo_T20.sdc new file mode 100644 index 0000000000000000000000000000000000000000..10a4a373f691ff2166122d5276e52a56b5e9fc84 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/fifo_demo_T20.sdc @@ -0,0 +1,3 @@ +create_clock -period 8.6 [get_ports pll_clkout_0] +create_clock -period 8.6 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..1c1cb1beaeab1bbbd68c94121f0df0d2cb635cfe --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/T20F256_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +W0_FIFO_32 xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Testbench/W0_FIFO_32.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Testbench/W0_FIFO_32.v new file mode 100644 index 0000000000000000000000000000000000000000..68b38f9e0a80898fd171905a4216e1760da2a891 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Testbench/W0_FIFO_32.v @@ -0,0 +1,1367 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _86fdad8fd5cf42519e2204399d3b6af7 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module W0_FIFO_32 ( +output prog_full_o, +output full_o, +output empty_o, +output prog_empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [31:0] wdata, +output [11:0] wr_datacount_o, +output rst_busy, +output [127:0] rdata, +output [9:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (32), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (3072), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (3072), +.PROGRAMMABLE_EMPTY ("STATIC_SINGLE"), +.PROG_EMPTY_ASSERT (255), +.PROG_EMPTY_NEGATE (255), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (4096), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (6), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.empty_o ( empty_o ), +.prog_empty_o ( prog_empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Testbench/W0_FIFO_32_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Testbench/W0_FIFO_32_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..766836f109d68916cb60ebaab4ed52c14ae3afb0 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Testbench/W0_FIFO_32_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 32; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 3072; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 3072; +localparam PROGRAMMABLE_EMPTY = "STATIC_SINGLE"; +localparam PROG_EMPTY_ASSERT = 255; +localparam PROG_EMPTY_NEGATE = 255; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 4096; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 6; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Testbench/fifo_tb.sv b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Testbench/fifo_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..225056f8bc97d5fd3246a5a1316a7471f4a939c5 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Testbench/fifo_tb.sv @@ -0,0 +1,473 @@ +`resetall +`timescale 1ns/1ps +`include "W0_FIFO_32_define.vh" + +module fifo_tb; + +`ifdef XRUN +initial begin + $shm_open("fifo_tb.shm"); + $shm_probe(fifo_tb,"ACMTF"); +end +`endif + +localparam WDATA_WIDTH_WGR = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 16 : + (ASYM_WIDTH_RATIO == 6)? 16 : + (ASYM_WIDTH_RATIO == 7)? 16 : + (ASYM_WIDTH_RATIO == 8)? 16 : 16; + +localparam WDATA_WIDTH_RGW = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 8 : + (ASYM_WIDTH_RATIO == 6)? 8 : + (ASYM_WIDTH_RATIO == 7)? 4 : + (ASYM_WIDTH_RATIO == 8)? 1 : 16; + +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,WDATA_WIDTH); +localparam RDATA_WIDTH_48 = (ASYM_WIDTH_RATIO >= 4) ? RDATA_WIDTH : 16; + +localparam WR_DEPTH = DEPTH; +localparam WADDR_WIDTH = depth2width(WR_DEPTH); +localparam RD_DEPTH = rddepthcompute(WR_DEPTH,WDATA_WIDTH,RDATA_WIDTH); +localparam RADDR_WIDTH = depth2width(RD_DEPTH); +localparam MEM_DATA_WIDTH = (WDATA_WIDTH >= RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); + +reg a_rst_i; +reg wr_clk; +reg rd_clk; +reg wr_en_i; +reg rd_en_i; +reg [WDATA_WIDTH-1:0] wdata; +reg [WADDR_WIDTH-1:0] waddr; +reg [RADDR_WIDTH-1:0] raddr; +reg [MEM_DATA_WIDTH-1:0] dynamic_a[$]; +reg [MEM_DATA_WIDTH-1:0] dynamic_b[$]; +reg [RDATA_WIDTH-1:0] monitor, monitor_temp; +reg [RDATA_WIDTH-1:0] read_lastdata; +reg temp_empty_o; + +wire [RDATA_WIDTH-1:0] rdata; +wire rd_valid_o; +wire prog_full_o; +wire almost_full_o; +wire full_o; +wire overflow_o; +wire wr_ack_o; +wire prog_empty_o; +wire almost_empty_o; +wire empty_o; +wire underflow_o; +wire [WADDR_WIDTH:0] datacount_o; +wire [WADDR_WIDTH:0] wr_datacount_o; +wire [RADDR_WIDTH:0] rd_datacount_o; +wire clk_i; +wire wr_clk_i; +wire rd_clk_i; +wire rst_busy_0; + +integer write_period; +integer read_period; +integer count; +integer wr_count; +integer rd_count; + +initial begin + wr_clk = 0; + rd_clk = 0; + write_period = 7; + read_period = 9; +end + +always begin + #(write_period) wr_clk <= ~wr_clk; +end + +always begin + #(read_period) rd_clk <= ~rd_clk; +end + +assign clk_i = wr_clk; +assign wr_clk_i = wr_clk; +assign rd_clk_i = wr_clk; + +initial begin + a_rst_i = 1'b1; + #1080 + a_rst_i = 1'b0; +end + +initial begin + wr_en_i = 1'b0; + rd_en_i = 1'b0; + wdata = 'h0; + waddr = 'd0; + raddr = 'd0; + dynamic_a = {}; + dynamic_b = {}; +end + +assign wr_count = WR_DEPTH; +assign rd_count = ASYM_WIDTH_RATIO < 4 ? wr_count * RAM_MUX_RATIO : wr_count / RAM_MUX_RATIO; + +initial begin + wait (~a_rst_i & rst_busy_0); + repeat (10) @ (negedge wr_clk_i) ; + count = WR_DEPTH; + repeat (wr_count) @ (negedge wr_clk_i) begin + wr_en_i = 1'b1; + wdata = {WDATA_WIDTH{$random}}; + end + repeat (2) @ (negedge wr_clk_i) begin + wr_en_i = 1'b0; + end + repeat (rd_count) @ (negedge wr_clk_i) begin + rd_en_i = 1'b1; + end + repeat (2) @ (negedge wr_clk_i) begin + rd_en_i = 1'b0; + end + repeat (10) @ (negedge wr_clk_i) ; + $finish; +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + waddr <= waddr +1; + end + end + end +end + +initial begin + forever begin + @(posedge rd_clk_i) begin + if (rd_en_i && ~empty_o) begin + raddr <= raddr + 1; + end + end + end +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + if (ENDIANESS == 0) begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + else begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin //downsize + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if(rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 1) begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + if (SYNC_CLK) begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if (dynamic_b.size() == RAM_MUX_RATIO) begin + monitor <= dynamic_a.pop_front(); + end + else if (rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else begin + integer i; + if (dynamic_b.size() == RAM_MUX_RATIO) begin + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + #0.1 + if (rd_en_i && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if(RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "FWFT") begin + if (SYNC_CLK == 0) begin + @ (negedge empty_o) begin + if (~rd_en_i && dynamic_b.size() != 1) begin + //integer i + if (RDATA_WIDTH <= WDATA_WIDTH) begin + monitor <= dynamic_a.pop_front(); + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + @ (negedge empty_o); + end + end + else begin + @ (negedge empty_o); + end + end +end + +always @ (posedge rd_clk_i)begin + monitor_temp <= monitor; + temp_empty_o <= empty_o; +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(negedge rd_clk_i) begin + if (rd_valid_o == 1 && ~a_rst_i) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - FAIL! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (rd_en_i && rd_valid_o) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - ERROR! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + end +end + +generate + if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO == 4) begin + W0_FIFO_32 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO == 4) begin + W0_FIFO_32 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO != 4) begin + W0_FIFO_32 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO != 4) begin + W0_FIFO_32 u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end +endgenerate + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/W0_FIFO_32.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/W0_FIFO_32.v new file mode 100644 index 0000000000000000000000000000000000000000..68b38f9e0a80898fd171905a4216e1760da2a891 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/W0_FIFO_32.v @@ -0,0 +1,1367 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _86fdad8fd5cf42519e2204399d3b6af7 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module W0_FIFO_32 ( +output prog_full_o, +output full_o, +output empty_o, +output prog_empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [31:0] wdata, +output [11:0] wr_datacount_o, +output rst_busy, +output [127:0] rdata, +output [9:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (32), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (3072), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (3072), +.PROGRAMMABLE_EMPTY ("STATIC_SINGLE"), +.PROG_EMPTY_ASSERT (255), +.PROG_EMPTY_NEGATE (255), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (4096), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (6), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.empty_o ( empty_o ), +.prog_empty_o ( prog_empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/W0_FIFO_32_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/W0_FIFO_32_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..766836f109d68916cb60ebaab4ed52c14ae3afb0 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/W0_FIFO_32_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 32; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 3072; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 3072; +localparam PROGRAMMABLE_EMPTY = "STATIC_SINGLE"; +localparam PROG_EMPTY_ASSERT = 255; +localparam PROG_EMPTY_NEGATE = 255; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 4096; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 6; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2685d9086ccd14629af6c18e5954b91ceb43ed30 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TITANIUM", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/fifo_demo_Ti60.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/fifo_demo_Ti60.sdc new file mode 100644 index 0000000000000000000000000000000000000000..a8ce31b8c3c29445879145d95ade991677e74f90 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/fifo_demo_Ti60.sdc @@ -0,0 +1,3 @@ +create_clock -period 3.125 [get_ports pll_clkout_0] +create_clock -period 6.250 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..1c1cb1beaeab1bbbd68c94121f0df0d2cb635cfe --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/Ti60F225_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +W0_FIFO_32 xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32.v new file mode 100644 index 0000000000000000000000000000000000000000..68b38f9e0a80898fd171905a4216e1760da2a891 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32.v @@ -0,0 +1,1367 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _86fdad8fd5cf42519e2204399d3b6af7 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module W0_FIFO_32 ( +output prog_full_o, +output full_o, +output empty_o, +output prog_empty_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [31:0] wdata, +output [11:0] wr_datacount_o, +output rst_busy, +output [127:0] rdata, +output [9:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (3), +.DATA_WIDTH (32), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (3072), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (3072), +.PROGRAMMABLE_EMPTY ("STATIC_SINGLE"), +.PROG_EMPTY_ASSERT (255), +.PROG_EMPTY_NEGATE (255), +.OPTIONAL_FLAGS (0), +.PIPELINE_REG (1), +.DEPTH (4096), +.FAMILY ("TRION"), +.ASYM_WIDTH_RATIO (6), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.empty_o ( empty_o ), +.prog_empty_o ( prog_empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..766836f109d68916cb60ebaab4ed52c14ae3afb0 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 3; +localparam DATA_WIDTH = 32; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 3072; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 3072; +localparam PROGRAMMABLE_EMPTY = "STATIC_SINGLE"; +localparam PROG_EMPTY_ASSERT = 255; +localparam PROG_EMPTY_NEGATE = 255; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 4096; +localparam FAMILY = "TRION"; +localparam ASYM_WIDTH_RATIO = 6; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32_tmpl.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32_tmpl.v new file mode 100644 index 0000000000000000000000000000000000000000..c7ac8e4d60b7a80f8258effcafb44a920e926b71 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32_tmpl.v @@ -0,0 +1,55 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +W0_FIFO_32 u_W0_FIFO_32( +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.empty_o ( empty_o ), +.prog_empty_o ( prog_empty_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32_tmpl.vhd b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32_tmpl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..0670f922b68b027f24a49cfc503cbfefbff945f0 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/W0_FIFO_32_tmpl.vhd @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +COMPONENT W0_FIFO_32 is +PORT ( +prog_full_o : out std_logic; +full_o : out std_logic; +empty_o : out std_logic; +prog_empty_o : out std_logic; +wr_clk_i : in std_logic; +rd_clk_i : in std_logic; +wr_en_i : in std_logic; +rd_en_i : in std_logic; +wdata : in std_logic_vector(31 downto 0); +wr_datacount_o : out std_logic_vector(11 downto 0); +rst_busy : out std_logic; +rdata : out std_logic_vector(127 downto 0); +rd_datacount_o : out std_logic_vector(9 downto 0); +a_rst_i : in std_logic); +END COMPONENT; +---------------------- End COMPONENT Declaration ------------ + +------------- Begin Cut here for INSTANTIATION Template ----- +u_W0_FIFO_32 : W0_FIFO_32 +PORT MAP ( +prog_full_o => prog_full_o, +full_o => full_o, +empty_o => empty_o, +prog_empty_o => prog_empty_o, +wr_clk_i => wr_clk_i, +rd_clk_i => rd_clk_i, +wr_en_i => wr_en_i, +rd_en_i => rd_en_i, +wdata => wdata, +wr_datacount_o => wr_datacount_o, +rst_busy => rst_busy, +rdata => rdata, +rd_datacount_o => rd_datacount_o, +a_rst_i => a_rst_i); +------------------------ End INSTANTIATION Template --------- diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/settings.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..2db613eea0f1075687f0c2d2711366984b34e984 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/W0_FIFO_32/settings.json @@ -0,0 +1,72 @@ +{ + "args": [ + "-o", + "W0_FIFO_32", + "--base_path", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_fifo_top", + "version": "5.1" + } + ], + "conf": { + "SYNC_CLK": "0", + "SYNC_STAGE": "3", + "DEPTH_2": "12", + "DATA_WIDTH": "32", + "MODE": "\"FWFT\"", + "OUTPUT_REG": "0", + "PROG_FULL_ASSERT": "3072", + "PROGRAMMABLE_FULL": "\"STATIC_SINGLE\"", + "PFN_INTERNAL": "3071", + "PEA_INTERNAL": "255", + "PEN_INTERNAL": "256", + "PROGRAMMABLE_EMPTY": "\"STATIC_SINGLE\"", + "OPTIONAL_FLAGS": "0", + "PIPELINE_REG": "1", + "FAMILY": "\"TRION\"", + "ASYM_WIDTH_RATIO": "6", + "BYPASS_RESET_SYNC": "0", + "ENDIANESS": "0" + }, + "output": { + "external_source_source": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\W0_FIFO_32_define.vh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\W0_FIFO_32_tmpl.vhd", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\W0_FIFO_32_tmpl.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\W0_FIFO_32.v" + ], + "external_example_example": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\T20F256_devkit\\fifo_demo.peri.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\T20F256_devkit\\fifo_demo.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\T20F256_devkit\\fifo_demo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\T20F256_devkit\\fifo_demo_T20.sdc", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\T20F256_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\T20F256_devkit\\W0_FIFO_32.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\T20F256_devkit\\W0_FIFO_32_define.vh" + ], + "external_example_2": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Ti60F225_devkit\\fifo_demo.peri.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Ti60F225_devkit\\fifo_demo.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Ti60F225_devkit\\fifo_demo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Ti60F225_devkit\\fifo_demo_Ti60.sdc", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Ti60F225_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Ti60F225_devkit\\W0_FIFO_32.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Ti60F225_devkit\\W0_FIFO_32_define.vh" + ], + "external_testbench_testbench": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Testbench\\fifo_tb.sv", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Testbench\\xrun.sh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Testbench\\msim.sh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Testbench\\flist", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Testbench\\modelsim.do", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Testbench\\W0_FIFO_32.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\W0_FIFO_32\\Testbench\\W0_FIFO_32_define.vh" + ] + }, + "sw_version": "2023.2.307", + "generated_date": "2024-10-10T09:32:38.731646" +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/asyn_fifo.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/asyn_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..be33e9115633d59e4b36886c0762c04dadec29b5 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/asyn_fifo.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _af32f278b05841e694433ae28c490f52 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module asyn_fifo ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [10:0] wdata, +output [12:0] wr_datacount_o, +output rst_busy, +output [10:0] rdata, +output [12:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (11), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (8192), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (4), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/asyn_fifo_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/asyn_fifo_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..ea2511f905089441ca3afac77f5769f1c0f0973d --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/asyn_fifo_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 11; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 8192; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2be121c383281fb9a99ff17fdb3d2650a14d67ac --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TRION", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/fifo_demo_T20.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/fifo_demo_T20.sdc new file mode 100644 index 0000000000000000000000000000000000000000..10a4a373f691ff2166122d5276e52a56b5e9fc84 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/fifo_demo_T20.sdc @@ -0,0 +1,3 @@ +create_clock -period 8.6 [get_ports pll_clkout_0] +create_clock -period 8.6 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..85c5a7e6d4ed1350f18382cb810420aa078a6fea --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/T20F256_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +asyn_fifo xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Testbench/asyn_fifo.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Testbench/asyn_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..be33e9115633d59e4b36886c0762c04dadec29b5 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Testbench/asyn_fifo.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _af32f278b05841e694433ae28c490f52 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module asyn_fifo ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [10:0] wdata, +output [12:0] wr_datacount_o, +output rst_busy, +output [10:0] rdata, +output [12:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (11), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (8192), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (4), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Testbench/asyn_fifo_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Testbench/asyn_fifo_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..ea2511f905089441ca3afac77f5769f1c0f0973d --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Testbench/asyn_fifo_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 11; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 8192; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Testbench/fifo_tb.sv b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Testbench/fifo_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..0827c0677be0b7f9b05353e96a40cf3803dd63f1 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Testbench/fifo_tb.sv @@ -0,0 +1,473 @@ +`resetall +`timescale 1ns/1ps +`include "asyn_fifo_define.vh" + +module fifo_tb; + +`ifdef XRUN +initial begin + $shm_open("fifo_tb.shm"); + $shm_probe(fifo_tb,"ACMTF"); +end +`endif + +localparam WDATA_WIDTH_WGR = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 16 : + (ASYM_WIDTH_RATIO == 6)? 16 : + (ASYM_WIDTH_RATIO == 7)? 16 : + (ASYM_WIDTH_RATIO == 8)? 16 : 16; + +localparam WDATA_WIDTH_RGW = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 8 : + (ASYM_WIDTH_RATIO == 6)? 8 : + (ASYM_WIDTH_RATIO == 7)? 4 : + (ASYM_WIDTH_RATIO == 8)? 1 : 16; + +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,WDATA_WIDTH); +localparam RDATA_WIDTH_48 = (ASYM_WIDTH_RATIO >= 4) ? RDATA_WIDTH : 16; + +localparam WR_DEPTH = DEPTH; +localparam WADDR_WIDTH = depth2width(WR_DEPTH); +localparam RD_DEPTH = rddepthcompute(WR_DEPTH,WDATA_WIDTH,RDATA_WIDTH); +localparam RADDR_WIDTH = depth2width(RD_DEPTH); +localparam MEM_DATA_WIDTH = (WDATA_WIDTH >= RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); + +reg a_rst_i; +reg wr_clk; +reg rd_clk; +reg wr_en_i; +reg rd_en_i; +reg [WDATA_WIDTH-1:0] wdata; +reg [WADDR_WIDTH-1:0] waddr; +reg [RADDR_WIDTH-1:0] raddr; +reg [MEM_DATA_WIDTH-1:0] dynamic_a[$]; +reg [MEM_DATA_WIDTH-1:0] dynamic_b[$]; +reg [RDATA_WIDTH-1:0] monitor, monitor_temp; +reg [RDATA_WIDTH-1:0] read_lastdata; +reg temp_empty_o; + +wire [RDATA_WIDTH-1:0] rdata; +wire rd_valid_o; +wire prog_full_o; +wire almost_full_o; +wire full_o; +wire overflow_o; +wire wr_ack_o; +wire prog_empty_o; +wire almost_empty_o; +wire empty_o; +wire underflow_o; +wire [WADDR_WIDTH:0] datacount_o; +wire [WADDR_WIDTH:0] wr_datacount_o; +wire [RADDR_WIDTH:0] rd_datacount_o; +wire clk_i; +wire wr_clk_i; +wire rd_clk_i; +wire rst_busy_0; + +integer write_period; +integer read_period; +integer count; +integer wr_count; +integer rd_count; + +initial begin + wr_clk = 0; + rd_clk = 0; + write_period = 7; + read_period = 9; +end + +always begin + #(write_period) wr_clk <= ~wr_clk; +end + +always begin + #(read_period) rd_clk <= ~rd_clk; +end + +assign clk_i = wr_clk; +assign wr_clk_i = wr_clk; +assign rd_clk_i = wr_clk; + +initial begin + a_rst_i = 1'b1; + #1080 + a_rst_i = 1'b0; +end + +initial begin + wr_en_i = 1'b0; + rd_en_i = 1'b0; + wdata = 'h0; + waddr = 'd0; + raddr = 'd0; + dynamic_a = {}; + dynamic_b = {}; +end + +assign wr_count = WR_DEPTH; +assign rd_count = ASYM_WIDTH_RATIO < 4 ? wr_count * RAM_MUX_RATIO : wr_count / RAM_MUX_RATIO; + +initial begin + wait (~a_rst_i & rst_busy_0); + repeat (10) @ (negedge wr_clk_i) ; + count = WR_DEPTH; + repeat (wr_count) @ (negedge wr_clk_i) begin + wr_en_i = 1'b1; + wdata = {WDATA_WIDTH{$random}}; + end + repeat (2) @ (negedge wr_clk_i) begin + wr_en_i = 1'b0; + end + repeat (rd_count) @ (negedge wr_clk_i) begin + rd_en_i = 1'b1; + end + repeat (2) @ (negedge wr_clk_i) begin + rd_en_i = 1'b0; + end + repeat (10) @ (negedge wr_clk_i) ; + $finish; +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + waddr <= waddr +1; + end + end + end +end + +initial begin + forever begin + @(posedge rd_clk_i) begin + if (rd_en_i && ~empty_o) begin + raddr <= raddr + 1; + end + end + end +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + if (ENDIANESS == 0) begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + else begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin //downsize + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if(rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 1) begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + if (SYNC_CLK) begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if (dynamic_b.size() == RAM_MUX_RATIO) begin + monitor <= dynamic_a.pop_front(); + end + else if (rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else begin + integer i; + if (dynamic_b.size() == RAM_MUX_RATIO) begin + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + #0.1 + if (rd_en_i && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if(RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "FWFT") begin + if (SYNC_CLK == 0) begin + @ (negedge empty_o) begin + if (~rd_en_i && dynamic_b.size() != 1) begin + //integer i + if (RDATA_WIDTH <= WDATA_WIDTH) begin + monitor <= dynamic_a.pop_front(); + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + @ (negedge empty_o); + end + end + else begin + @ (negedge empty_o); + end + end +end + +always @ (posedge rd_clk_i)begin + monitor_temp <= monitor; + temp_empty_o <= empty_o; +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(negedge rd_clk_i) begin + if (rd_valid_o == 1 && ~a_rst_i) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - FAIL! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (rd_en_i && rd_valid_o) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - ERROR! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + end +end + +generate + if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO == 4) begin + asyn_fifo u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO == 4) begin + asyn_fifo u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO != 4) begin + asyn_fifo u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO != 4) begin + asyn_fifo u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end +endgenerate + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/asyn_fifo.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/asyn_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..be33e9115633d59e4b36886c0762c04dadec29b5 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/asyn_fifo.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _af32f278b05841e694433ae28c490f52 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module asyn_fifo ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [10:0] wdata, +output [12:0] wr_datacount_o, +output rst_busy, +output [10:0] rdata, +output [12:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (11), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (8192), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (4), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/asyn_fifo_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/asyn_fifo_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..ea2511f905089441ca3afac77f5769f1c0f0973d --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/asyn_fifo_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 11; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 8192; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2685d9086ccd14629af6c18e5954b91ceb43ed30 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TITANIUM", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/fifo_demo_Ti60.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/fifo_demo_Ti60.sdc new file mode 100644 index 0000000000000000000000000000000000000000..a8ce31b8c3c29445879145d95ade991677e74f90 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/fifo_demo_Ti60.sdc @@ -0,0 +1,3 @@ +create_clock -period 3.125 [get_ports pll_clkout_0] +create_clock -period 6.250 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..85c5a7e6d4ed1350f18382cb810420aa078a6fea --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/Ti60F225_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +asyn_fifo xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..be33e9115633d59e4b36886c0762c04dadec29b5 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _af32f278b05841e694433ae28c490f52 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module asyn_fifo ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [10:0] wdata, +output [12:0] wr_datacount_o, +output rst_busy, +output [10:0] rdata, +output [12:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (11), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (128), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (128), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (8192), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (4), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..ea2511f905089441ca3afac77f5769f1c0f0973d --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 11; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 8192; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo_tmpl.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo_tmpl.v new file mode 100644 index 0000000000000000000000000000000000000000..5113920b3fe4e42312388e7635f92b84dc824c0a --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo_tmpl.v @@ -0,0 +1,60 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +asyn_fifo u_asyn_fifo( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo_tmpl.vhd b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo_tmpl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..d512d6b8284223c2a49b24bb50e18040f92796fb --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/asyn_fifo_tmpl.vhd @@ -0,0 +1,86 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +COMPONENT asyn_fifo is +PORT ( +almost_full_o : out std_logic; +prog_full_o : out std_logic; +full_o : out std_logic; +overflow_o : out std_logic; +wr_ack_o : out std_logic; +empty_o : out std_logic; +almost_empty_o : out std_logic; +underflow_o : out std_logic; +rd_valid_o : out std_logic; +wr_clk_i : in std_logic; +rd_clk_i : in std_logic; +wr_en_i : in std_logic; +rd_en_i : in std_logic; +wdata : in std_logic_vector(10 downto 0); +wr_datacount_o : out std_logic_vector(12 downto 0); +rst_busy : out std_logic; +rdata : out std_logic_vector(10 downto 0); +rd_datacount_o : out std_logic_vector(12 downto 0); +a_rst_i : in std_logic); +END COMPONENT; +---------------------- End COMPONENT Declaration ------------ + +------------- Begin Cut here for INSTANTIATION Template ----- +u_asyn_fifo : asyn_fifo +PORT MAP ( +almost_full_o => almost_full_o, +prog_full_o => prog_full_o, +full_o => full_o, +overflow_o => overflow_o, +wr_ack_o => wr_ack_o, +empty_o => empty_o, +almost_empty_o => almost_empty_o, +underflow_o => underflow_o, +rd_valid_o => rd_valid_o, +wr_clk_i => wr_clk_i, +rd_clk_i => rd_clk_i, +wr_en_i => wr_en_i, +rd_en_i => rd_en_i, +wdata => wdata, +wr_datacount_o => wr_datacount_o, +rst_busy => rst_busy, +rdata => rdata, +rd_datacount_o => rd_datacount_o, +a_rst_i => a_rst_i); +------------------------ End INSTANTIATION Template --------- diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/settings.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..8208389837e077288b43c443ffeb06eaa5265586 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/asyn_fifo/settings.json @@ -0,0 +1,72 @@ +{ + "args": [ + "-o", + "asyn_fifo", + "--base_path", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_fifo_top", + "version": "5.1" + } + ], + "conf": { + "SYNC_CLK": "0", + "SYNC_STAGE": "2", + "DEPTH_2": "13", + "DATA_WIDTH": "11", + "MODE": "\"FWFT\"", + "OUTPUT_REG": "0", + "PROG_FULL_ASSERT": "128", + "PROGRAMMABLE_FULL": "\"STATIC_SINGLE\"", + "PFN_INTERNAL": "127", + "PEA_INTERNAL": "2", + "PEN_INTERNAL": "3", + "PROGRAMMABLE_EMPTY": "\"NONE\"", + "OPTIONAL_FLAGS": "1", + "PIPELINE_REG": "1", + "FAMILY": "\"TITANIUM\"", + "ASYM_WIDTH_RATIO": "4", + "BYPASS_RESET_SYNC": "0", + "ENDIANESS": "0" + }, + "output": { + "external_source_source": [ + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\asyn_fifo_tmpl.v", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\asyn_fifo_define.vh", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\asyn_fifo_tmpl.vhd", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\asyn_fifo.v" + ], + "external_example_example": [ + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\T20F256_devkit\\fifo_demo_top.v", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\T20F256_devkit\\fifo_demo_T20.sdc", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\T20F256_devkit\\efx_symmetric_width_fifo_top.v", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\T20F256_devkit\\asyn_fifo.v", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\T20F256_devkit\\asyn_fifo_define.vh", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\T20F256_devkit\\fifo_demo.peri.xml", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\T20F256_devkit\\fifo_demo.xml" + ], + "external_example_2": [ + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Ti60F225_devkit\\fifo_demo_top.v", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Ti60F225_devkit\\fifo_demo_Ti60.sdc", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Ti60F225_devkit\\efx_symmetric_width_fifo_top.v", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Ti60F225_devkit\\asyn_fifo.v", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Ti60F225_devkit\\asyn_fifo_define.vh", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Ti60F225_devkit\\fifo_demo.peri.xml", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Ti60F225_devkit\\fifo_demo.xml" + ], + "external_testbench_testbench": [ + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Testbench\\fifo_tb.sv", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Testbench\\xrun.sh", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Testbench\\msim.sh", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Testbench\\flist", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Testbench\\modelsim.do", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Testbench\\asyn_fifo.v", + "D:\\FPGA_Competition\\FPGAprojects\\data_in_uart_control\\Bilinear_interpolation_prj\\ip\\asyn_fifo\\Testbench\\asyn_fifo_define.vh" + ] + }, + "sw_version": "2023.2.307", + "generated_date": "2024-10-05T03:22:08.860606" +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/data_in_fifo.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/data_in_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..c72a60bee01c274dac0dbe73b1e5e0aecba85e31 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/data_in_fifo.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _4fc7e6a339594633b0381370215e196c +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module data_in_fifo ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [23:0] wdata, +output [13:0] wr_datacount_o, +output rst_busy, +output [23:0] rdata, +output [13:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (24), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (11), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (11), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (16384), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (4), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/data_in_fifo_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/data_in_fifo_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..38f09a55a3ff5ddec7f6556629abd81e102bfb3b --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/data_in_fifo_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 24; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 11; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 11; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 16384; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2be121c383281fb9a99ff17fdb3d2650a14d67ac --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TRION", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/fifo_demo_T20.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/fifo_demo_T20.sdc new file mode 100644 index 0000000000000000000000000000000000000000..10a4a373f691ff2166122d5276e52a56b5e9fc84 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/fifo_demo_T20.sdc @@ -0,0 +1,3 @@ +create_clock -period 8.6 [get_ports pll_clkout_0] +create_clock -period 8.6 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..cbae5ec49a0e648184cf6055d5556c6576861d13 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/T20F256_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +data_in_fifo xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Testbench/data_in_fifo.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Testbench/data_in_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..c72a60bee01c274dac0dbe73b1e5e0aecba85e31 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Testbench/data_in_fifo.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _4fc7e6a339594633b0381370215e196c +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module data_in_fifo ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [23:0] wdata, +output [13:0] wr_datacount_o, +output rst_busy, +output [23:0] rdata, +output [13:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (24), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (11), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (11), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (16384), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (4), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Testbench/data_in_fifo_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Testbench/data_in_fifo_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..38f09a55a3ff5ddec7f6556629abd81e102bfb3b --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Testbench/data_in_fifo_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 24; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 11; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 11; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 16384; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Testbench/fifo_tb.sv b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Testbench/fifo_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..487a0c2b5661188d144edc140e1d5c30dc5079bf --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Testbench/fifo_tb.sv @@ -0,0 +1,473 @@ +`resetall +`timescale 1ns/1ps +`include "data_in_fifo_define.vh" + +module fifo_tb; + +`ifdef XRUN +initial begin + $shm_open("fifo_tb.shm"); + $shm_probe(fifo_tb,"ACMTF"); +end +`endif + +localparam WDATA_WIDTH_WGR = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 16 : + (ASYM_WIDTH_RATIO == 6)? 16 : + (ASYM_WIDTH_RATIO == 7)? 16 : + (ASYM_WIDTH_RATIO == 8)? 16 : 16; + +localparam WDATA_WIDTH_RGW = (ASYM_WIDTH_RATIO == 0)? 16 : + (ASYM_WIDTH_RATIO == 1)? 16 : + (ASYM_WIDTH_RATIO == 2)? 16 : + (ASYM_WIDTH_RATIO == 3)? 16 : + (ASYM_WIDTH_RATIO == 4)? 16 : + (ASYM_WIDTH_RATIO == 5)? 8 : + (ASYM_WIDTH_RATIO == 6)? 8 : + (ASYM_WIDTH_RATIO == 7)? 4 : + (ASYM_WIDTH_RATIO == 8)? 1 : 16; + +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,WDATA_WIDTH); +localparam RDATA_WIDTH_48 = (ASYM_WIDTH_RATIO >= 4) ? RDATA_WIDTH : 16; + +localparam WR_DEPTH = DEPTH; +localparam WADDR_WIDTH = depth2width(WR_DEPTH); +localparam RD_DEPTH = rddepthcompute(WR_DEPTH,WDATA_WIDTH,RDATA_WIDTH); +localparam RADDR_WIDTH = depth2width(RD_DEPTH); +localparam MEM_DATA_WIDTH = (WDATA_WIDTH >= RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); + +reg a_rst_i; +reg wr_clk; +reg rd_clk; +reg wr_en_i; +reg rd_en_i; +reg [WDATA_WIDTH-1:0] wdata; +reg [WADDR_WIDTH-1:0] waddr; +reg [RADDR_WIDTH-1:0] raddr; +reg [MEM_DATA_WIDTH-1:0] dynamic_a[$]; +reg [MEM_DATA_WIDTH-1:0] dynamic_b[$]; +reg [RDATA_WIDTH-1:0] monitor, monitor_temp; +reg [RDATA_WIDTH-1:0] read_lastdata; +reg temp_empty_o; + +wire [RDATA_WIDTH-1:0] rdata; +wire rd_valid_o; +wire prog_full_o; +wire almost_full_o; +wire full_o; +wire overflow_o; +wire wr_ack_o; +wire prog_empty_o; +wire almost_empty_o; +wire empty_o; +wire underflow_o; +wire [WADDR_WIDTH:0] datacount_o; +wire [WADDR_WIDTH:0] wr_datacount_o; +wire [RADDR_WIDTH:0] rd_datacount_o; +wire clk_i; +wire wr_clk_i; +wire rd_clk_i; +wire rst_busy_0; + +integer write_period; +integer read_period; +integer count; +integer wr_count; +integer rd_count; + +initial begin + wr_clk = 0; + rd_clk = 0; + write_period = 7; + read_period = 9; +end + +always begin + #(write_period) wr_clk <= ~wr_clk; +end + +always begin + #(read_period) rd_clk <= ~rd_clk; +end + +assign clk_i = wr_clk; +assign wr_clk_i = wr_clk; +assign rd_clk_i = wr_clk; + +initial begin + a_rst_i = 1'b1; + #1080 + a_rst_i = 1'b0; +end + +initial begin + wr_en_i = 1'b0; + rd_en_i = 1'b0; + wdata = 'h0; + waddr = 'd0; + raddr = 'd0; + dynamic_a = {}; + dynamic_b = {}; +end + +assign wr_count = WR_DEPTH; +assign rd_count = ASYM_WIDTH_RATIO < 4 ? wr_count * RAM_MUX_RATIO : wr_count / RAM_MUX_RATIO; + +initial begin + wait (~a_rst_i & rst_busy_0); + repeat (10) @ (negedge wr_clk_i) ; + count = WR_DEPTH; + repeat (wr_count) @ (negedge wr_clk_i) begin + wr_en_i = 1'b1; + wdata = {WDATA_WIDTH{$random}}; + end + repeat (2) @ (negedge wr_clk_i) begin + wr_en_i = 1'b0; + end + repeat (rd_count) @ (negedge wr_clk_i) begin + rd_en_i = 1'b1; + end + repeat (2) @ (negedge wr_clk_i) begin + rd_en_i = 1'b0; + end + repeat (10) @ (negedge wr_clk_i) ; + $finish; +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + waddr <= waddr +1; + end + end + end +end + +initial begin + forever begin + @(posedge rd_clk_i) begin + if (rd_en_i && ~empty_o) begin + raddr <= raddr + 1; + end + end + end +end + +initial begin + forever begin + @(posedge wr_clk_i) begin + if (wr_en_i && ~full_o) begin + if (ENDIANESS == 0) begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + else begin + if (WDATA_WIDTH <= RDATA_WIDTH) begin + dynamic_a.push_back(wdata); + dynamic_b.push_back(wdata); + $display("%t - write data %h to address: %d ", $time(), wdata, waddr ); + end + else begin //downsize + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + lsbaddr = i; + dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]); + end + $display("%t - write data %h to address: %d", $time(), wdata, waddr); + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if(rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 1) begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + if (SYNC_CLK) begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + if (dynamic_b.size() == RAM_MUX_RATIO) begin + monitor <= dynamic_a.pop_front(); + end + else if (rd_en_i == 1 && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else begin + integer i; + if (dynamic_b.size() == RAM_MUX_RATIO) begin + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (RDATA_WIDTH <= WDATA_WIDTH) begin + #0.1 + if (rd_en_i && ~empty_o) begin + monitor <= dynamic_a.pop_front(); + end + end + else if(RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + if (rd_en_i && ~almost_empty_o) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + end + end +end + +initial begin + forever begin + if (MODE == "FWFT") begin + if (SYNC_CLK == 0) begin + @ (negedge empty_o) begin + if (~rd_en_i && dynamic_b.size() != 1) begin + //integer i + if (RDATA_WIDTH <= WDATA_WIDTH) begin + monitor <= dynamic_a.pop_front(); + end + else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin + integer i; + for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + else begin + integer i; + for (i=0; i < RAM_MUX_RATIO; i=i+1) begin + monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front(); + end + end + end + end + end + else begin + @ (negedge empty_o); + end + end + else begin + @ (negedge empty_o); + end + end +end + +always @ (posedge rd_clk_i)begin + monitor_temp <= monitor; + temp_empty_o <= empty_o; +end + +initial begin + forever begin + if (MODE == "STANDARD") begin + @(negedge rd_clk_i) begin + if (rd_valid_o == 1 && ~a_rst_i) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - FAIL! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + else begin + @(posedge rd_clk_i) begin + if (rd_en_i && rd_valid_o) begin + if (monitor === rdata) begin + $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor); + end + else begin + $error("%t - ERROR! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor); + end + end + end + end + end +end + +generate + if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO == 4) begin + data_in_fifo u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO == 4) begin + data_in_fifo u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end + else if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO != 4) begin + data_in_fifo u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .clk_i (clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO != 4) begin + data_in_fifo u_efx_fifo_top ( + .a_rst_i (a_rst_i), + .rst_busy (rst_busy_0), + .wr_clk_i (wr_clk_i), + .wr_en_i (wr_en_i), + .wdata (wdata), + .rd_clk_i (rd_clk_i), + .rd_en_i (rd_en_i), + .rdata (rdata), + .rd_valid_o (rd_valid_o), + .full_o (full_o), + .almost_empty_o (almost_empty_o), + .empty_o (empty_o) + ); + end +endgenerate + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/data_in_fifo.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/data_in_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..c72a60bee01c274dac0dbe73b1e5e0aecba85e31 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/data_in_fifo.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _4fc7e6a339594633b0381370215e196c +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module data_in_fifo ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [23:0] wdata, +output [13:0] wr_datacount_o, +output rst_busy, +output [23:0] rdata, +output [13:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (24), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (11), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (11), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (16384), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (4), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/data_in_fifo_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/data_in_fifo_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..38f09a55a3ff5ddec7f6556629abd81e102bfb3b --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/data_in_fifo_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 24; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 11; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 11; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 16384; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/efx_symmetric_width_fifo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/efx_symmetric_width_fifo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..2685d9086ccd14629af6c18e5954b91ceb43ed30 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/efx_symmetric_width_fifo_top.v @@ -0,0 +1,1291 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2021.M.200 +// IP Version: 1.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +module efx_symmetric_width_fifo_top # ( +parameter FAMILY = "TITANIUM", +parameter SYNC_CLK = 1, +parameter OUTPUT_REG = 0, +parameter MODE = "STANDARD", +parameter PIPELINE_REG = 1, +parameter OPTIONAL_FLAGS = 0, +parameter PROGRAMMABLE_FULL = "NONE", +parameter PROGRAMMABLE_EMPTY = "NONE", +parameter ASYM_WIDTH_RATIO = 4, +parameter DATA_WIDTH = 32, +parameter DEPTH = 512 +) ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output prog_empty_o, +output underflow_o, +output rd_valid_o, +output [32:0] rdata, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [32:0] wdata, +output [8:0] wr_datacount_o, +output [8:0] rd_datacount_o, +input a_rst_i, +output rst_busy +); +efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #( +.OPTIONAL_FLAGS (OPTIONAL_FLAGS), +.SYNC_CLK (SYNC_CLK), +.DEPTH (DEPTH), +.DATA_WIDTH (DATA_WIDTH), +.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), +.MODE (MODE), +.OUTPUT_REG (OUTPUT_REG), +.BYPASS_RESET_SYNC (0), +.PROG_FULL_ASSERT (7), +.PIPELINE_REG (PIPELINE_REG), +.PROG_FULL_NEGATE (3), +.SYNC_STAGE (2), +.PROG_EMPTY_ASSERT (2), +.PROG_EMPTY_NEGATE (3), +.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), +.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), +.FAMILY (FAMILY) +) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.prog_empty_o ( prog_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.rdata ( rdata ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rd_datacount_o ( rd_datacount_o ), +.rst_busy ( rst_busy ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4 +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/fifo_demo_Ti60.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/fifo_demo_Ti60.sdc new file mode 100644 index 0000000000000000000000000000000000000000..a8ce31b8c3c29445879145d95ade991677e74f90 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/fifo_demo_Ti60.sdc @@ -0,0 +1,3 @@ +create_clock -period 3.125 [get_ports pll_clkout_0] +create_clock -period 6.250 [get_ports pll_clkout_1] +create_clock -period 200 [get_ports led_clk] \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/fifo_demo_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/fifo_demo_top.v new file mode 100644 index 0000000000000000000000000000000000000000..cbae5ec49a0e648184cf6055d5556c6576861d13 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/Ti60F225_devkit/fifo_demo_top.v @@ -0,0 +1,198 @@ +module fifo_demo_top #( + parameter SYNC_CLK = 0, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter DEPTH = 512, + parameter DATA_WIDTH = 16, + parameter PIPELINE_REG = 1, + parameter OPTIONAL_FLAGS = 1, + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", + parameter PROG_FULL_ASSERT = 128, + parameter PROG_FULL_NEGATE = 196, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", + parameter PROG_EMPTY_ASSERT = 8, + parameter PROG_EMPTY_NEGATE = 16, + parameter ASYM_WIDTH_RATIO = 5 +) ( + input wire pll_clkout_0, + input wire pll_clkout_1, + input wire led_clk, + input wire pll_lock, + input wire sys_rst_n, + input wire stop_fifo_wr, + input wire stop_fifo_rd, + output wire pll_reset, + output reg led_blink, + output wire led_rdata_error, + output wire led_fifo_full, + output wire led_fifo_empty +); + +wire wr_clk; +wire rd_clk; +wire [31:0] dut_rdata; +wire [31:0] golden_rdata; +wire dut_rd_valid; +wire golden_rd_valid; +wire dut_trigger_rd; +wire dut_rst_busy; +wire golden_rst_busy; +wire compare_error; +wire dut_wr_en; +wire dut_full_o; +wire dut_empty_o; +wire sys_rst; +wire rst_busy_all; + +reg rd_en; +reg rdata_error; +reg dut_wren; +reg dut_wr_en_r; +reg [15:0] dut_wr_data; +reg [31:0] golden_wr_data; +reg golden_wr_en; + +`ifdef SIMULATION +reg [1:0] led_counter; +`else +reg [19:0] led_counter; +`endif + +assign pll_reset = 1'b1; +assign led_rdata_error = rdata_error; +assign led_fifo_full = dut_full_o; +assign led_fifo_empty = dut_empty_o; + +// =========================================================== +// ========== LED will blink if the design is alive ========== +// =========================================================== + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_counter <= 'd0; + end + else begin + led_counter <= led_counter + 1'b1; + end +end + +always @ (posedge led_clk) begin + if (sys_rst) begin + led_blink <= 1'b0; + end + else if (&led_counter) begin + led_blink <= ~led_blink; + end +end + +// =========================================================== +// ========== Asymmetric Width FIFO 1:2 DUT ================== +// =========================================================== + +assign wr_clk = pll_clkout_0; +assign rd_clk = pll_clkout_1; +assign sys_rst = ~sys_rst_n; // push button is active low +assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low +assign dut_rd_en = rd_en & stop_fifo_rd; // push button is active low + +assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + dut_wren <= 1'b0; + dut_wr_data <= 16'h0; + end + else if (pll_lock && rst_busy_all) begin + dut_wren <= 1'b1; + dut_wr_data <= dut_wr_data + 1'b1; + end +end + +data_in_fifo xdut_1_to_2_fifo ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (dut_wr_en), + .wdata (dut_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (dut_rd_en), + .rdata (dut_rdata), + .rd_valid_o (dut_rd_valid), + .prog_full_o (dut_trigger_rd), + .rst_busy (dut_rst_busy), + .full_o (dut_full_o), + .empty_o (dut_empty_o) +); + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_data <= 'h0; + dut_wr_en_r <= 'h0; + end + else if (~golden_rst_busy) begin + golden_wr_data <= {golden_wr_data[15:0],dut_wr_data}; + dut_wr_en_r <= dut_wren; + end +end + +always @ (posedge wr_clk or posedge sys_rst) begin + if (sys_rst) begin + golden_wr_en <= 'h0; + end + else if (dut_wr_en_r)begin + golden_wr_en <= ~golden_wr_en; + end +end + +// =========================================================== +// ========== Symmetric Width FIFO 1:1 Storage =============== +// =========================================================== + +efx_symmetric_width_fifo_top #( + .SYNC_CLK (0), + .OUTPUT_REG (0), + .MODE ("STANDARD"), + .PIPELINE_REG (PIPELINE_REG), + .OPTIONAL_FLAGS (1'b0), + .PROGRAMMABLE_FULL ("NONE"), + .PROGRAMMABLE_EMPTY ("NONE"), + .ASYM_WIDTH_RATIO (4), + .DATA_WIDTH (32), + .DEPTH (DEPTH) +) xdut_1_to_1_golden ( + .a_rst_i (sys_rst), + .wr_clk_i (wr_clk), + .wr_en_i (golden_wr_en), + .wdata (golden_wr_data), + .rd_clk_i (rd_clk), + .rd_en_i (rd_en), + .rdata (golden_rdata), + .rd_valid_o (golden_rd_valid), + .rst_busy (golden_rst_busy) +); + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rd_en <= 1'b0; + end + else if (dut_trigger_rd) begin + rd_en <= 1'b1; + end +end + +// =========================================================== +// ========== Read Data Comparison Logic ===================== +// =========================================================== + +assign compare_error = dut_rd_valid|golden_rd_valid ? dut_rdata != golden_rdata : 0; + +always @ (posedge rd_clk or posedge sys_rst) begin + if (sys_rst) begin + rdata_error <= 1'b0; + end + else if (compare_error) begin + rdata_error <= 1'b1; + end +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..c72a60bee01c274dac0dbe73b1e5e0aecba85e31 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo.v @@ -0,0 +1,1377 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _4fc7e6a339594633b0381370215e196c +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module data_in_fifo ( +output almost_full_o, +output prog_full_o, +output full_o, +output overflow_o, +output wr_ack_o, +output empty_o, +output almost_empty_o, +output underflow_o, +output rd_valid_o, +input wr_clk_i, +input rd_clk_i, +input wr_en_i, +input rd_en_i, +input [23:0] wdata, +output [13:0] wr_datacount_o, +output rst_busy, +output [23:0] rdata, +output [13:0] rd_datacount_o, +input a_rst_i +); +`IP_MODULE_NAME(efx_fifo_top) #( +.SYNC_CLK (0), +.SYNC_STAGE (2), +.DATA_WIDTH (24), +.MODE ("FWFT"), +.OUTPUT_REG (0), +.PROG_FULL_ASSERT (11), +.PROGRAMMABLE_FULL ("STATIC_SINGLE"), +.PROG_FULL_NEGATE (11), +.PROGRAMMABLE_EMPTY ("NONE"), +.PROG_EMPTY_ASSERT (0), +.PROG_EMPTY_NEGATE (2), +.OPTIONAL_FLAGS (1), +.PIPELINE_REG (1), +.DEPTH (16384), +.FAMILY ("TITANIUM"), +.ASYM_WIDTH_RATIO (4), +.BYPASS_RESET_SYNC (0), +.ENDIANESS (0) +) u_efx_fifo_top( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0 //0: Big endian (default) 1: Little endian +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + reg [LSB_WIDTH-1 :0 ] lsbaddr; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + wr_ack <= wr_en_int & ~wr_overflow; + end + end + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + raddr_cntr_r <= 'h0; + end + else if (rd_en_int) begin + raddr_cntr <= raddr_cntr + 1'b1; + raddr_cntr_r <= raddr_cntr; + end +end + +generate + if (SYNC_CLK) begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr_w; + end + else begin + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..38f09a55a3ff5ddec7f6556629abd81e102bfb3b --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo_define.vh @@ -0,0 +1,63 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 24; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 11; +localparam PROGRAMMABLE_FULL = "STATIC_SINGLE"; +localparam PROG_FULL_NEGATE = 11; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 0; +localparam PROG_EMPTY_NEGATE = 2; +localparam OPTIONAL_FLAGS = 1; +localparam PIPELINE_REG = 1; +localparam DEPTH = 16384; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo_tmpl.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo_tmpl.v new file mode 100644 index 0000000000000000000000000000000000000000..07d7215614aaf4ed355c22d0f91c7c0ae012c589 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo_tmpl.v @@ -0,0 +1,60 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +data_in_fifo u_data_in_fifo( +.almost_full_o ( almost_full_o ), +.prog_full_o ( prog_full_o ), +.full_o ( full_o ), +.overflow_o ( overflow_o ), +.wr_ack_o ( wr_ack_o ), +.empty_o ( empty_o ), +.almost_empty_o ( almost_empty_o ), +.underflow_o ( underflow_o ), +.rd_valid_o ( rd_valid_o ), +.wr_clk_i ( wr_clk_i ), +.rd_clk_i ( rd_clk_i ), +.wr_en_i ( wr_en_i ), +.rd_en_i ( rd_en_i ), +.wdata ( wdata ), +.wr_datacount_o ( wr_datacount_o ), +.rst_busy ( rst_busy ), +.rdata ( rdata ), +.rd_datacount_o ( rd_datacount_o ), +.a_rst_i ( a_rst_i ) +); diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo_tmpl.vhd b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo_tmpl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..2ecfc9f831895bef8f5e5be22540e5b10a068d27 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/data_in_fifo_tmpl.vhd @@ -0,0 +1,86 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +COMPONENT data_in_fifo is +PORT ( +almost_full_o : out std_logic; +prog_full_o : out std_logic; +full_o : out std_logic; +overflow_o : out std_logic; +wr_ack_o : out std_logic; +empty_o : out std_logic; +almost_empty_o : out std_logic; +underflow_o : out std_logic; +rd_valid_o : out std_logic; +wr_clk_i : in std_logic; +rd_clk_i : in std_logic; +wr_en_i : in std_logic; +rd_en_i : in std_logic; +wdata : in std_logic_vector(23 downto 0); +wr_datacount_o : out std_logic_vector(13 downto 0); +rst_busy : out std_logic; +rdata : out std_logic_vector(23 downto 0); +rd_datacount_o : out std_logic_vector(13 downto 0); +a_rst_i : in std_logic); +END COMPONENT; +---------------------- End COMPONENT Declaration ------------ + +------------- Begin Cut here for INSTANTIATION Template ----- +u_data_in_fifo : data_in_fifo +PORT MAP ( +almost_full_o => almost_full_o, +prog_full_o => prog_full_o, +full_o => full_o, +overflow_o => overflow_o, +wr_ack_o => wr_ack_o, +empty_o => empty_o, +almost_empty_o => almost_empty_o, +underflow_o => underflow_o, +rd_valid_o => rd_valid_o, +wr_clk_i => wr_clk_i, +rd_clk_i => rd_clk_i, +wr_en_i => wr_en_i, +rd_en_i => rd_en_i, +wdata => wdata, +wr_datacount_o => wr_datacount_o, +rst_busy => rst_busy, +rdata => rdata, +rd_datacount_o => rd_datacount_o, +a_rst_i => a_rst_i); +------------------------ End INSTANTIATION Template --------- diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/settings.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..0a842672d673ef5d17b792232a51d694e12790b1 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/data_in_fifo/settings.json @@ -0,0 +1,72 @@ +{ + "args": [ + "-o", + "data_in_fifo", + "--base_path", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_fifo_top", + "version": "5.1" + } + ], + "conf": { + "SYNC_CLK": "0", + "SYNC_STAGE": "2", + "DEPTH_2": "14", + "DATA_WIDTH": "24", + "MODE": "\"FWFT\"", + "OUTPUT_REG": "0", + "PROG_FULL_ASSERT": "11", + "PROGRAMMABLE_FULL": "\"STATIC_SINGLE\"", + "PFN_INTERNAL": "10", + "PEA_INTERNAL": "2", + "PEN_INTERNAL": "3", + "PROGRAMMABLE_EMPTY": "\"NONE\"", + "OPTIONAL_FLAGS": "1", + "PIPELINE_REG": "1", + "FAMILY": "\"TITANIUM\"", + "ASYM_WIDTH_RATIO": "4", + "BYPASS_RESET_SYNC": "0", + "ENDIANESS": "0" + }, + "output": { + "external_source_source": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\data_in_fifo_define.vh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\data_in_fifo_tmpl.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\data_in_fifo_tmpl.vhd", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\data_in_fifo.v" + ], + "external_example_example": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\T20F256_devkit\\fifo_demo.peri.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\T20F256_devkit\\fifo_demo.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\T20F256_devkit\\fifo_demo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\T20F256_devkit\\fifo_demo_T20.sdc", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\T20F256_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\T20F256_devkit\\data_in_fifo.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\T20F256_devkit\\data_in_fifo_define.vh" + ], + "external_example_2": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Ti60F225_devkit\\fifo_demo.peri.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Ti60F225_devkit\\fifo_demo.xml", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Ti60F225_devkit\\fifo_demo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Ti60F225_devkit\\fifo_demo_Ti60.sdc", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Ti60F225_devkit\\efx_symmetric_width_fifo_top.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Ti60F225_devkit\\data_in_fifo.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Ti60F225_devkit\\data_in_fifo_define.vh" + ], + "external_testbench_testbench": [ + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Testbench\\fifo_tb.sv", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Testbench\\xrun.sh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Testbench\\msim.sh", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Testbench\\flist", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Testbench\\modelsim.do", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Testbench\\data_in_fifo.v", + "C:\\Users\\32954\\Desktop\\107liantiao\\1051\\ip\\data_in_fifo\\Testbench\\data_in_fifo_define.vh" + ] + }, + "sw_version": "2023.2.307", + "generated_date": "2024-10-08T14:16:45.332098" +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/divider_ip/T20F256_devkit/demo_divider.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/divider_ip/T20F256_devkit/demo_divider.v new file mode 100644 index 0000000000000000000000000000000000000000..5fc3db26c72582ac68deda733f4cfffd664a5a31 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/divider_ip/T20F256_devkit/demo_divider.v @@ -0,0 +1,373 @@ + +`timescale 1ns / 1ps + +module demo_divider ( + output wire pll_rst_n_o, + output wire pass_led, + output wire fail_led, + + input clk, + input clken, + input reset +); + +`include "divider_ip_define.vh" + +genvar i; +reg [3:0] count; +reg [LATENCY:0] clken_reg; +reg pass, fail; + +assign pass_led = pass; +assign fail_led = fail; + +always @(posedge clk or posedge reset) begin + if (reset) begin + clken_reg[0] <= 1'b0; + end + else begin + clken_reg[0] <= clken; + end +end + +generate +for (i=0; i 0) begin + reg [LATENCY-1:0] ready; + + assign sub = (ready[0] || ~clken_IP) ? ({{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]} - denom_sub) : ({remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]} - denom_reg); + + always @(posedge clk,posedge reset) begin + if(reset) begin + ready <= {LATENCY{1'b0}}; + end + else if(clken) begin + if(ready[0] || ~clken_IP) begin + ready <= {1'b1, {LATENCY-1{1'b0}}}; + end + else begin + ready <= {1'b0, ready[LATENCY-1:1]}; + end + end + else begin + ready <= {LATENCY{1'b0}}; + end + end + + always @(posedge clk,posedge reset) begin + if(reset) begin + remain_reg <= {WIDTHN{1'b0}}; + quotient_reg <= {WIDTHN{1'b0}}; + denom_reg <= {WIDTHN{1'b0}}; + end + else if(clken) begin + if(ready[0] || ~clken_IP) begin + denom_reg <= denom_temp; + if (sub[(WIDTHN)] == 0) begin + remain_reg <= sub[(WIDTHN-1):0]; + quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b1}; + end + else begin + remain_reg <= {{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]}; + quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b0}; + end + end + else begin + if (sub[(WIDTHN)] == 0) begin + remain_reg <= sub[(WIDTHN-1):0]; + quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b1}; + end + else begin + remain_reg <= {remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]}; + quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b0}; + end + end + end + end + + if (ENABLE_OUTREG) begin + always @(posedge clk,posedge reset) begin + if (reset) begin + rfd <= 1'b0; + end + else begin + rfd <= ready[0]; + end + end + end + else begin + always @* begin + rfd = ready[0]; + end + end + + always @* begin + quotient_combi[0] = quotient_reg; + remain_combi[0] = remain_reg; + end + + for (i=0; i 0) begin + reg [LATENCY-1:0] ready; + + assign sub = (ready[0] || ~clken_IP) ? ({{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]} - denom_sub) : ({remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]} - denom_reg); + + always @(posedge clk,posedge reset) begin + if(reset) begin + ready <= {LATENCY{1'b0}}; + end + else if(clken) begin + if(ready[0] || ~clken_IP) begin + ready <= {1'b1, {LATENCY-1{1'b0}}}; + end + else begin + ready <= {1'b0, ready[LATENCY-1:1]}; + end + end + else begin + ready <= {LATENCY{1'b0}}; + end + end + + always @(posedge clk,posedge reset) begin + if(reset) begin + remain_reg <= {WIDTHN{1'b0}}; + quotient_reg <= {WIDTHN{1'b0}}; + denom_reg <= {WIDTHN{1'b0}}; + end + else if(clken) begin + if(ready[0] || ~clken_IP) begin + denom_reg <= denom_temp; + if (sub[(WIDTHN)] == 0) begin + remain_reg <= sub[(WIDTHN-1):0]; + quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b1}; + end + else begin + remain_reg <= {{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]}; + quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b0}; + end + end + else begin + if (sub[(WIDTHN)] == 0) begin + remain_reg <= sub[(WIDTHN-1):0]; + quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b1}; + end + else begin + remain_reg <= {remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]}; + quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b0}; + end + end + end + end + + if (ENABLE_OUTREG) begin + always @(posedge clk,posedge reset) begin + if (reset) begin + rfd <= 1'b0; + end + else begin + rfd <= ready[0]; + end + end + end + else begin + always @* begin + rfd = ready[0]; + end + end + + always @* begin + quotient_combi[0] = quotient_reg; + remain_combi[0] = remain_reg; + end + + for (i=0; i 0) begin + reg [LATENCY-1:0] ready; + + assign sub = (ready[0] || ~clken_IP) ? ({{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]} - denom_sub) : ({remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]} - denom_reg); + + always @(posedge clk,posedge reset) begin + if(reset) begin + ready <= {LATENCY{1'b0}}; + end + else if(clken) begin + if(ready[0] || ~clken_IP) begin + ready <= {1'b1, {LATENCY-1{1'b0}}}; + end + else begin + ready <= {1'b0, ready[LATENCY-1:1]}; + end + end + else begin + ready <= {LATENCY{1'b0}}; + end + end + + always @(posedge clk,posedge reset) begin + if(reset) begin + remain_reg <= {WIDTHN{1'b0}}; + quotient_reg <= {WIDTHN{1'b0}}; + denom_reg <= {WIDTHN{1'b0}}; + end + else if(clken) begin + if(ready[0] || ~clken_IP) begin + denom_reg <= denom_temp; + if (sub[(WIDTHN)] == 0) begin + remain_reg <= sub[(WIDTHN-1):0]; + quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b1}; + end + else begin + remain_reg <= {{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]}; + quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b0}; + end + end + else begin + if (sub[(WIDTHN)] == 0) begin + remain_reg <= sub[(WIDTHN-1):0]; + quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b1}; + end + else begin + remain_reg <= {remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]}; + quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b0}; + end + end + end + end + + if (ENABLE_OUTREG) begin + always @(posedge clk,posedge reset) begin + if (reset) begin + rfd <= 1'b0; + end + else begin + rfd <= ready[0]; + end + end + end + else begin + always @* begin + rfd = ready[0]; + end + end + + always @* begin + quotient_combi[0] = quotient_reg; + remain_combi[0] = remain_reg; + end + + for (i=0; i -max [get_ports {clken}] +# set_input_delay -clock -min [get_ports {clken}] +# set_input_delay -clock -max [get_ports {ext_clk}] +# set_input_delay -clock -min [get_ports {ext_clk}] +# set_input_delay -clock -max [get_ports {reset}] +# set_input_delay -clock -min [get_ports {reset}] +# set_input_delay -clock -max [get_ports {swit}] +# set_input_delay -clock -min [get_ports {swit}] +# set_output_delay -clock -max [get_ports {led_o[0]}] +# set_output_delay -clock -min [get_ports {led_o[0]}] +# set_output_delay -clock -max [get_ports {led_o[1]}] +# set_output_delay -clock -min [get_ports {led_o[1]}] +# set_output_delay -clock -max [get_ports {led_o[2]}] +# set_output_delay -clock -min [get_ports {led_o[2]}] +# set_output_delay -clock -max [get_ports {led_o[3]}] +# set_output_delay -clock -min [get_ports {led_o[3]}] +# set_output_delay -clock -max [get_ports {led_o[4]}] +# set_output_delay -clock -min [get_ports {led_o[4]}] +# set_output_delay -clock -max [get_ports {led_o[5]}] +# set_output_delay -clock -min [get_ports {led_o[5]}] +# set_output_delay -clock -max [get_ports {led_o[6]}] +# set_output_delay -clock -min [get_ports {led_o[6]}] +# set_output_delay -clock -max [get_ports {led_o[7]}] +# set_output_delay -clock -min [get_ports {led_o[7]}] + + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/divider_ip/divider_ip.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/divider_ip/divider_ip.v new file mode 100644 index 0000000000000000000000000000000000000000..01c1b3b7580bb360185d270e409509f81f7ba83a --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/divider_ip/divider_ip.v @@ -0,0 +1,390 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _570d993e5fb64d11900c366fe0e2a2eb +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module divider_ip ( +input [26:0] numer, +input [11:0] denom, +input clken, +input clk, +input reset, +output [26:0] quotient, +output [11:0] remain, +output rfd +); +`IP_MODULE_NAME(divider) #( +.NREPRESENTATION ("UNSIGNED"), +.WIDTHN (27), +.WIDTHD (12), +.DREPRESENTATION ("UNSIGNED"), +.PIPELINE (1'b0), +.LATENCY (27) +) u_divider( +.numer ( numer ), +.denom ( denom ), +.clken ( clken ), +.clk ( clk ), +.reset ( reset ), +.quotient ( quotient ), +.remain ( remain ), +.rfd ( rfd ) +); + +endmodule + +`timescale 1ns / 1ps + +module `IP_MODULE_NAME(divider) ( + clk, + reset, + numer, + denom, + quotient, + remain, + rfd, + clken +); + +parameter WIDTHN = 8; +parameter WIDTHD = 8; +parameter LATENCY = 8; +parameter PIPELINE = 1; +parameter NREPRESENTATION = "UNSIGNED"; +parameter DREPRESENTATION = "UNSIGNED"; +parameter ENABLE_OUTREG = 0; + +input clk; +input reset; +input clken; +input [(WIDTHN-1):0] numer; +input [(WIDTHD-1):0] denom; +//output +output reg rfd; +output reg [(WIDTHN-1):0] quotient; +output reg [(WIDTHD-1):0] remain; + +wire [WIDTHN-1:0] numer_temp; +wire [WIDTHD-1:0] denom_temp; +wire sign_numer; +wire sign_denom; + +wire [(WIDTHN-1):0] quotient_copy; +wire [(WIDTHD-1):0] remain_copy; +reg sign_quotient[LATENCY:0]; + +genvar i, j; +// Main operation +generate begin + if(NREPRESENTATION == "SIGNED") begin + assign numer_temp = (numer[(WIDTHN-1)] == 1'b1) ? (~numer + 1) : numer; + assign sign_numer = (numer[(WIDTHN-1)] == 1'b1) ? 1'b1 : 1'b0; + end + else begin + assign numer_temp = numer; + assign sign_numer = 1'b0; + end + + if(DREPRESENTATION == "SIGNED") begin + assign denom_temp = (denom[(WIDTHD-1)] == 1'b1) ? (~denom + 1) : denom; + assign sign_denom = (denom[(WIDTHD-1)] == 1'b1) ? 1'b1 : 1'b0; + end + else begin + assign denom_temp = denom; + assign sign_denom = 1'b0; + end + + always @* begin + sign_quotient[0] = sign_numer ^ sign_denom; + end + + for (i=0; i 0) begin + reg [LATENCY-1:0] ready; + + assign sub = (ready[0] || ~clken_IP) ? ({{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]} - denom_sub) : ({remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]} - denom_reg); + + always @(posedge clk,posedge reset) begin + if(reset) begin + ready <= {LATENCY{1'b0}}; + end + else if(clken) begin + if(ready[0] || ~clken_IP) begin + ready <= {1'b1, {LATENCY-1{1'b0}}}; + end + else begin + ready <= {1'b0, ready[LATENCY-1:1]}; + end + end + else begin + ready <= {LATENCY{1'b0}}; + end + end + + always @(posedge clk,posedge reset) begin + if(reset) begin + remain_reg <= {WIDTHN{1'b0}}; + quotient_reg <= {WIDTHN{1'b0}}; + denom_reg <= {WIDTHN{1'b0}}; + end + else if(clken) begin + if(ready[0] || ~clken_IP) begin + denom_reg <= denom_temp; + if (sub[(WIDTHN)] == 0) begin + remain_reg <= sub[(WIDTHN-1):0]; + quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b1}; + end + else begin + remain_reg <= {{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]}; + quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b0}; + end + end + else begin + if (sub[(WIDTHN)] == 0) begin + remain_reg <= sub[(WIDTHN-1):0]; + quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b1}; + end + else begin + remain_reg <= {remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]}; + quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b0}; + end + end + end + end + + if (ENABLE_OUTREG) begin + always @(posedge clk,posedge reset) begin + if (reset) begin + rfd <= 1'b0; + end + else begin + rfd <= ready[0]; + end + end + end + else begin + always @* begin + rfd = ready[0]; + end + end + + always @* begin + quotient_combi[0] = quotient_reg; + remain_combi[0] = remain_reg; + end + + for (i=0; i numer, +denom => denom, +clken => clken, +clk => clk, +reset => reset, +quotient => quotient, +remain => remain, +rfd => rfd); +------------------------ End INSTANTIATION Template --------- diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/divider_ip/settings.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/divider_ip/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..ddbf7388fb7b1a8750732a8ca9694805df278a96 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/divider_ip/settings.json @@ -0,0 +1,56 @@ +{ + "args": [ + "-o", + "divider_ip", + "--base_path", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "arithmetic", + "name": "efx_divider", + "version": "5.1" + } + ], + "conf": { + "NREPRESENTATION": "\"UNSIGNED\"", + "WIDTHN": "27", + "WIDTHD": "12", + "DREPRESENTATION": "\"UNSIGNED\"", + "PIPELINE": "1'b0", + "LATENCY": "27" + }, + "output": { + "external_source_source": [ + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\divider_ip_tmpl.v", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\divider_ip_define.vh", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\divider_ip_tmpl.vhd", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\divider_ip.v" + ], + "external_example_example": [ + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\T20F256_devkit\\divider.peri.xml", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\T20F256_devkit\\divider.xml", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\T20F256_devkit\\demo_divider.v", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\T20F256_devkit\\example_divider_T20.sdc", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\T20F256_devkit\\divider_ip.v", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\T20F256_devkit\\divider_ip_define.vh" + ], + "external_example_2": [ + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\Ti60F225_devkit\\divider.peri.xml", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\Ti60F225_devkit\\divider.xml", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\Ti60F225_devkit\\demo_divider.v", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\Ti60F225_devkit\\example_divider_Ti60.sdc", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\Ti60F225_devkit\\divider_ip.v", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\Ti60F225_devkit\\divider_ip_define.vh" + ], + "external_testbench_testbench": [ + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\Testbench\\tb_divider.v", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\Testbench\\demo_divider.v", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\Testbench\\modelsim.do", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\Testbench\\divider_ip.v", + "C:\\Users\\ADMINI~1\\AppData\\Local\\Temp\\tmpufldeq4z\\ip\\divider_ip\\Testbench\\divider_ip_define.vh" + ] + }, + "sw_version": "2023.2.307", + "generated_date": "2024-10-07T07:54:04.580772" +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_decompose.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_decompose.vh new file mode 100644 index 0000000000000000000000000000000000000000..b2920525560f301c7a67451f9b6f6033e5bde356 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_decompose.vh @@ -0,0 +1,101 @@ +localparam TOTAL_SIZE_A = 8; +localparam TOTAL_SIZE_B = 8; +localparam GROUP_COLUMNS = 1; +parameter DECOMPOSE_WRITE_MODE = "READ_FIRST"; +localparam bram_table_size = 1; +localparam bram_table_loop_mode = 1; +localparam bram_mapping_size = 1; +localparam rMux_mapping_A_size = 0; +localparam rMux_mapping_B_size = 0; +localparam wen_sel_mapping_A_size = 0; +localparam wen_sel_mapping_B_size = 0; +localparam data_mapping_table_A_size = 0; +localparam data_mapping_table_B_size = 0; +localparam address_mapping_table_A_size = 0; +localparam address_mapping_table_B_size = 0; + + +function integer bram_feature_table; +input integer index;//Mode type +input integer val_; //Address_width, data_width, en_width, reserved +case (index) +0: bram_feature_table=(val_==0)?9:(val_==1)?20:(val_==2)?2:(val_==3)?2:(val_==4)?0:0; +1: bram_feature_table=(val_==0)?9:(val_==1)?16:(val_==2)?2:(val_==3)?2:(val_==4)?1:0; +2: bram_feature_table=(val_==0)?10:(val_==1)?10:(val_==2)?1:(val_==3)?2:(val_==4)?0:0; +3: bram_feature_table=(val_==0)?10:(val_==1)?8:(val_==2)?1:(val_==3)?2:(val_==4)?1:0; +4: bram_feature_table=(val_==0)?11:(val_==1)?5:(val_==2)?1:(val_==3)?2:(val_==4)?0:0; +5: bram_feature_table=(val_==0)?11:(val_==1)?4:(val_==2)?1:(val_==3)?2:(val_==4)?1:0; +6: bram_feature_table=(val_==0)?12:(val_==1)?2:(val_==2)?1:(val_==3)?2:(val_==4)?1:0; +7: bram_feature_table=(val_==0)?13:(val_==1)?1:(val_==2)?1:(val_==3)?2:(val_==4)?1:0; + endcase +endfunction + + +function integer bram_decompose_table; +input integer index;//Mode type +input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved +case (index) + 0: bram_decompose_table=(val_==0)? 0:(val_==1)? 0:(val_==2)? 1:(val_==3)? 0:(val_==4)? 0:0; + endcase +endfunction + + +function integer bram_mapping_table; +input integer index;//Mode type +input integer val_;// Y, X, DataA [MSB], DataA [LSB], DataA Repeat, Read MuxA, Wen0 SelA, Wen1 SelA, Byteen A, DataB [MSB], DataB [LSB], DataB Repeat, Read MuxB, Wen0 SelB, Wen1 SelB, Byteen B, Addr Width A Data Width A Addr Width B Data Width B +case (index) + 0: bram_mapping_table=(val_== 0)? 0:(val_== 1)? 0:(val_== 2)? 15:(val_== 3)? 0:(val_== 4)? 0:(val_== 5)? 0:(val_== 6)? 0:(val_== 7)? 0:(val_== 8)? 0:(val_== 9)? 15:(val_==10)? 0:(val_==11)? 0:(val_==12)? 0:(val_==13)? 0:(val_==14)? 0:(val_==15)? 0:(val_==16)? 9:(val_==17)? 20:(val_==18)? 9:(val_==19)? 20:0; + endcase +endfunction + + +function integer rMux_mapping_table_A; +input integer index;//Mode type +input integer val_;// PortA Addr MSB, PortA Addr LSB, DataA[MSB], DataA[LSB], MuxSelA[MSB], MuxSelA[LSB], Bypass, +rMux_mapping_table_A = 0; +endfunction + + +function integer rMux_mapping_table_B; +input integer index;//Mode type +input integer val_;// PortB Addr MSB, PortB Addr LSB, DataB[MSB], DataB[LSB], MuxSelB[MSB], MuxSelB[LSB], Bypass, +rMux_mapping_table_B = 0; +endfunction + + +function integer wen_sel_mapping_table_A; +input integer index;//Mode type +input integer val_;// PortA Addr MSB, PortA Addr LSB, WenSelA[MSB], WenSelA[LSB], Bypass, +wen_sel_mapping_table_A = 0; +endfunction + + +function integer wen_sel_mapping_table_B; +input integer index;//Mode type +input integer val_;// PortB Addr MSB, PortB Addr LSB, WenSelB[MSB], WenSelB[LSB], Bypass, +wen_sel_mapping_table_B = 0; +endfunction + + +function integer data_mapping_table_A; +input integer index;// +data_mapping_table_A = 0; +endfunction + + +function integer data_mapping_table_B; +input integer index;// +data_mapping_table_B = 0; +endfunction + + +function integer address_mapping_table_A; +input integer index;// +address_mapping_table_A = 0; +endfunction + + +function integer address_mapping_table_B; +input integer index;// +address_mapping_table_B = 0; +endfunction diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_ini.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_ini.vh new file mode 100644 index 0000000000000000000000000000000000000000..4d8a31dc2d99327fa9991db109c0927e45e1e816 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_ini.vh @@ -0,0 +1,49 @@ + +function [255:0] bram_ini_table; +input integer index;//Mode type +input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved +case (index) + 0: bram_ini_table= +(val_== 0)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_== 1)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_== 2)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_== 5)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_== 6)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_== 7)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_== 8)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_== 9)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==10)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==11)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==12)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==13)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==14)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==15)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==16)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==17)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==18)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==19)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==20)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==21)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==22)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==23)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==24)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==25)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==26)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==27)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==28)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==29)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==30)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==31)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==32)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==33)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==34)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==35)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==36)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==37)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==38)?256'h0000000000000000000000000000000000000000000000000000000000000000: +(val_==39)?256'h0000000000000000000000000000000000000000000000000000000000000000: +0; + endcase +endfunction diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_primitive.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_primitive.v new file mode 100644 index 0000000000000000000000000000000000000000..94e92b0f38664cc9184c56ff67a1a625bc5dbf2f --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_primitive.v @@ -0,0 +1,281 @@ +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bram_primitive.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// +// ******************************* + +module bram_primitive #( + parameter FAMILY = "TITANIUM", + + //Trion and Titanium parameters + parameter WRITE_WIDTH = 16, // write width + parameter WCLK_POLARITY = 1'b1, //wclk polarity, 0:falling edge, 1:rising edge + parameter WCLKE_POLARITY = 1'b1, //wclke polarity, 0:active low, 1:active high + parameter WE_POLARITY = 1'b1, //we polarity, 0:active low, 1:active high + parameter WRITE_MODE = "READ_FIRST",//write mode, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter READ_WIDTH = 16, // read width + parameter RCLK_POLARITY = 1'b1, // rclk polarity, 0:falling edge, 1:rising edge + parameter RE_POLARITY = 1'b1, // re polarity, 0:active low , 1:active high + parameter OUTPUT_REG = 1'b0, // Output register enable, 1:add pipe-line read register + + //Titanium extra paramters + parameter RST_POLARITY = 1'b1, // rst polarity + parameter RESET_RAM = "ASYNC", // reset mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG = "ASYNC", // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter WADDREN_POLARITY = 1'b1, // waddren polarity + parameter RADDREN_POLARITY = 1'b1, // raddren polarity + + //Titanium Option for byte enable in WEN width = 2 when it is Mode 512x16 or 512x20 + parameter WEN_WIDTH = 1, + + parameter ini_index = 0 + +) +( + //Trion and Titanium ports + WCLK, // Write clock input + WCLKE, // Write clock-enable input + WE, // Write-enable input + WADDR, // Write address input + WDATA, // Write data input + + RCLK, // Read clock input + RE, // Read-enable input + RADDR, // Read address input + RDATA, // Read data output + + //Titanium extra ports + RST, // reset + WADDREN, // write address enable + RADDREN // read address enable + + ); +function integer address_map; +input integer index;//Input data width parameter +input integer type_; //Mapped data width, Mapped Address Width for Ram 5K(Trion), Mapped Address Width for Ram 10K(Titanium), WEN width for Ram 5K(Trion), WEN width for Ram 10K(Titanium) +case (index) +0 : address_map= (type_==0)? 1 :(type_==1)? 12 :(type_==2)? 13 :1; +1 : address_map= (type_==0)? 1 :(type_==1)? 12 :(type_==2)? 13 :1; +2 : address_map= (type_==0)? 2 :(type_==1)? 11 :(type_==2)? 12 :1; +3 : address_map= (type_==0)? 4 :(type_==1)? 10 :(type_==2)? 11 :1; +4 : address_map= (type_==0)? 4 :(type_==1)? 10 :(type_==2)? 11 :1; +5 : address_map= (type_==0)? 5 :(type_==1)? 10 :(type_==2)? 11 :1; +6 : address_map= (type_==0)? 8 :(type_==1)? 9 :(type_==2)? 10 :1; +7 : address_map= (type_==0)? 8 :(type_==1)? 9 :(type_==2)? 10 :1; +8 : address_map= (type_==0)? 8 :(type_==1)? 9 :(type_==2)? 10 :1; +9 : address_map= (type_==0)? 10 :(type_==1)? 9 :(type_==2)? 10 :1; +10 : address_map= (type_==0)? 10 :(type_==1)? 9 :(type_==2)? 10 :1; +11 : address_map= (type_==0)? 16 :(type_==1)? 8 :(type_==2)? 9 :1; +12 : address_map= (type_==0)? 16 :(type_==1)? 8 :(type_==2)? 9 :1; +13 : address_map= (type_==0)? 16 :(type_==1)? 8 :(type_==2)? 9 :1; +14 : address_map= (type_==0)? 16 :(type_==1)? 8 :(type_==2)? 9 :1; +15 : address_map= (type_==0)? 16 :(type_==1)? 8 :(type_==2)? 9 :1; +16 : address_map= (type_==0)? 16 :(type_==1)? 8 :(type_==2)? 9 :1; +17 : address_map= (type_==0)? 20 :(type_==1)? 8 :(type_==2)? 9 :1; +18 : address_map= (type_==0)? 20 :(type_==1)? 8 :(type_==2)? 9 :1; +19 : address_map= (type_==0)? 20 :(type_==1)? 8 :(type_==2)? 9 :1; +20 : address_map= (type_==0)? 20 :(type_==1)? 8 :(type_==2)? 9 :1; + endcase +endfunction + +localparam WRITE_DATA_WIDTH = address_map(WRITE_WIDTH,0); +localparam WRITE_ADDRESS_WIDTH = address_map(WRITE_WIDTH,(FAMILY=="TRION")?1:2); + +localparam READ_DATA_WIDTH = address_map(READ_WIDTH,0); +localparam READ_ADDRESS_WIDTH = address_map(READ_WIDTH,(FAMILY=="TRION")?1:2); + + +//Trion and Titanium ports +input WCLK; // Write clock input +input WCLKE; // Write clock-enable input +input [WEN_WIDTH-1:0] WE; // Write-enable input +input [WRITE_ADDRESS_WIDTH-1:0] WADDR; // Write address input +input [WRITE_DATA_WIDTH-1:0] WDATA; // Write data input + +input RCLK; // Read clock input +input RE; // Read-enable input +input [READ_ADDRESS_WIDTH-1:0] RADDR; // Read address input +output[READ_DATA_WIDTH-1:0]RDATA; // Read data output + +//Titanium extra ports +input RST; // reset +input WADDREN; // write address enable +input RADDREN; // read address enable + + +`include "bram_ini.vh" +parameter filePath = "bram_ini.vh"; +integer fd; + + generate + initial begin + fd = $fopen(filePath, "r"); + $fclose(fd); + end + + + if (FAMILY=="TRION") + begin + EFX_RAM_5K # ( + .WRITE_WIDTH (WRITE_WIDTH), + .WCLK_POLARITY (WCLK_POLARITY), + .WCLKE_POLARITY (WCLKE_POLARITY), + .WE_POLARITY (WE_POLARITY), + .WRITE_MODE (WRITE_MODE), + + .READ_WIDTH (READ_WIDTH), + .RCLK_POLARITY (RCLK_POLARITY), + .RE_POLARITY (RE_POLARITY), + .OUTPUT_REG (OUTPUT_REG), + + + .INIT_0 (bram_ini_table(ini_index,16'h0 )), + .INIT_1 (bram_ini_table(ini_index,16'h1 )), + .INIT_2 (bram_ini_table(ini_index,16'h2 )), + .INIT_3 (bram_ini_table(ini_index,16'h3 )), + .INIT_4 (bram_ini_table(ini_index,16'h4 )), + .INIT_5 (bram_ini_table(ini_index,16'h5 )), + .INIT_6 (bram_ini_table(ini_index,16'h6 )), + .INIT_7 (bram_ini_table(ini_index,16'h7 )), + .INIT_8 (bram_ini_table(ini_index,16'h8 )), + .INIT_9 (bram_ini_table(ini_index,16'h9 )), + .INIT_A (bram_ini_table(ini_index,16'hA )), + .INIT_B (bram_ini_table(ini_index,16'hB )), + .INIT_C (bram_ini_table(ini_index,16'hC )), + .INIT_D (bram_ini_table(ini_index,16'hD )), + .INIT_E (bram_ini_table(ini_index,16'hE )), + .INIT_F (bram_ini_table(ini_index,16'hF )), + .INIT_10 (bram_ini_table(ini_index,16'h10)), + .INIT_11 (bram_ini_table(ini_index,16'h11)), + .INIT_12 (bram_ini_table(ini_index,16'h12)), + .INIT_13 (bram_ini_table(ini_index,16'h13)) + ) + ram5k ( + .WCLK(WCLK), // Write clock input + .WE(WE[0]), // Write-enable input + .WCLKE(WCLKE), // Write clock-enable input + .WADDR(WADDR), // Write address input + .WDATA(WDATA), // Write data input + + .RCLK(RCLK), // Read clock input + .RE(RE), // Read-enable input + .RADDR(RADDR), // Read address input + .RDATA(RDATA) // Read data output + ); + end + else + begin + + wire [1:0]w_wen_ram10; + assign w_wen_ram10[0] = WE[0]; + + if (WEN_WIDTH>1) + assign w_wen_ram10[1] = WE[1]; + else if (WRITE_DATA_WIDTH >= 16 ) + assign w_wen_ram10[1] = WE[0]; + else + assign w_wen_ram10[1] = 1'b0; + + EFX_RAM10 # ( + + .WRITE_WIDTH (WRITE_WIDTH), + .WCLK_POLARITY (WCLK_POLARITY), + .WCLKE_POLARITY (WCLKE_POLARITY), + .WE_POLARITY ({2{WE_POLARITY}}), + .WRITE_MODE (WRITE_MODE), + + .READ_WIDTH (READ_WIDTH), + .RCLK_POLARITY (RCLK_POLARITY), + .RE_POLARITY (RE_POLARITY), + .OUTPUT_REG (OUTPUT_REG), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY), // rst polarity + .RESET_RAM (RESET_RAM), // reset mode on ram + .RESET_OUTREG (RESET_OUTREG), // reset mode on output register + .WADDREN_POLARITY (WADDREN_POLARITY), // waddren polarity + .RADDREN_POLARITY (RADDREN_POLARITY), // raddren polarity + + + .INIT_0 (bram_ini_table(ini_index, 16'h0 )), + .INIT_1 (bram_ini_table(ini_index, 16'h1 )), + .INIT_2 (bram_ini_table(ini_index, 16'h2 )), + .INIT_3 (bram_ini_table(ini_index, 16'h3 )), + .INIT_4 (bram_ini_table(ini_index, 16'h4 )), + .INIT_5 (bram_ini_table(ini_index, 16'h5 )), + .INIT_6 (bram_ini_table(ini_index, 16'h6 )), + .INIT_7 (bram_ini_table(ini_index, 16'h7 )), + .INIT_8 (bram_ini_table(ini_index, 16'h8 )), + .INIT_9 (bram_ini_table(ini_index, 16'h9 )), + .INIT_A (bram_ini_table(ini_index, 16'hA )), + .INIT_B (bram_ini_table(ini_index, 16'hB )), + .INIT_C (bram_ini_table(ini_index, 16'hC )), + .INIT_D (bram_ini_table(ini_index, 16'hD )), + .INIT_E (bram_ini_table(ini_index, 16'hE )), + .INIT_F (bram_ini_table(ini_index, 16'hF )), + .INIT_10 (bram_ini_table(ini_index, 16'h10)), + .INIT_11 (bram_ini_table(ini_index, 16'h11)), + .INIT_12 (bram_ini_table(ini_index, 16'h12)), + .INIT_13 (bram_ini_table(ini_index, 16'h13)), + .INIT_14 (bram_ini_table(ini_index, 16'h14)), + .INIT_15 (bram_ini_table(ini_index, 16'h15)), + .INIT_16 (bram_ini_table(ini_index, 16'h16)), + .INIT_17 (bram_ini_table(ini_index, 16'h17)), + .INIT_18 (bram_ini_table(ini_index, 16'h18)), + .INIT_19 (bram_ini_table(ini_index, 16'h19)), + .INIT_1A (bram_ini_table(ini_index, 16'h1A)), + .INIT_1B (bram_ini_table(ini_index, 16'h1B)), + .INIT_1C (bram_ini_table(ini_index, 16'h1C)), + .INIT_1D (bram_ini_table(ini_index, 16'h1D)), + .INIT_1E (bram_ini_table(ini_index, 16'h1E)), + .INIT_1F (bram_ini_table(ini_index, 16'h1F)), + .INIT_20 (bram_ini_table(ini_index, 16'h20)), + .INIT_21 (bram_ini_table(ini_index, 16'h21)), + .INIT_22 (bram_ini_table(ini_index, 16'h22)), + .INIT_23 (bram_ini_table(ini_index, 16'h23)), + .INIT_24 (bram_ini_table(ini_index, 16'h24)), + .INIT_25 (bram_ini_table(ini_index, 16'h25)), + .INIT_26 (bram_ini_table(ini_index, 16'h26)), + .INIT_27 (bram_ini_table(ini_index, 16'h27)) + + ) + ram10k( + + .WCLK(WCLK), // Write clock input + .WE(w_wen_ram10), // Write-enable input + .WCLKE(WCLKE), // Write clock-enable input + .WADDR(WADDR), // Write address input + .WDATA(WDATA), // Write data input + + .RCLK(RCLK), // Read clock input + .RE(RE), // Read-enable input + .RADDR(RADDR), // Read address input + .RDATA(RDATA), // Read data output + + //Titanium extra ports + .RST (RST), // reset + .WADDREN (WADDREN), // write address enable + .RADDREN (RADDREN) // read address enable + + ); + end + endgenerate + +endmodule \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_top.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_top.sdc new file mode 100644 index 0000000000000000000000000000000000000000..661aa4e945f0d6c0419b505a9c9b009c8d747a45 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_top.sdc @@ -0,0 +1,3 @@ +create_clock -period 40.00 i_fb_clk +create_clock -period 10.00 i_wclk +create_clock -waveform {2.500 7.500} -period 10.00 i_rclk \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_wrapper_mwm.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_wrapper_mwm.v new file mode 100644 index 0000000000000000000000000000000000000000..d34f673a25aa290e64cf1168c1eac0ab676bfc25 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/bram_wrapper_mwm.v @@ -0,0 +1,779 @@ +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// Modified on 23 September 2022 +// ******************************* + +module bram_wrapper_mwm #( + parameter FAMILY = "TITANIUM", + + //Trion and Titanium parameters + parameter WCLK_POLARITY = 1'b1, //wclk polarity, 0:falling edge, 1:rising edge + parameter WCLKE_POLARITY = 1'b1, //wclke polarity, 0:active low, 1:active high + parameter WE_POLARITY = 1'b1, //we polarity, 0:active low, 1:active high + parameter WRITE_MODE = "READ_FIRST",//write mode, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter RCLK_POLARITY = 1'b1, // rclk polarity, 0:falling edge, 1:rising edge + parameter RE_POLARITY = 1'b1, // re polarity, 0:active low , 1:active high + parameter OUTPUT_REG = 1'b0, // Output register enable, 1:add pipe-line read register + + parameter BYTEEN_POLARITY = 1'b1, // byteen polarity 0:active low, 1:active high + + //Titanium extra paramters + parameter RST_POLARITY = 1'b1, // rst polarity + parameter RESET_RAM = "ASYNC", // reset mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG = "ASYNC", // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter WADDREN_POLARITY = 1'b1, // waddren polarity + parameter RADDREN_POLARITY = 1'b1, // raddren polarity + + parameter DATA_WIDTH_A = 16, + parameter DATA_WIDTH_B = 16, + parameter ADDR_WIDTH_A = 4, + parameter ADDR_WIDTH_B = 4, + parameter BYTEEN_WIDTH = 2 + +) +( + //Trion and Titanium ports + wclk, // Write clock input + wclke, // Write clock-enable input + byteen, // Byteen input + we, // Write-enable input + waddr, // Write address input + wdata, // Write data input + + rclk, // Read clock input + re, // Read-enable input + raddr, // Read address input + rdata, // Read data output + + //Titanium extra ports + reset, // reset + waddren, // write address enable + raddren // read address enable + + ); + + +`include "bram_decompose.vh" +//`include "bram_feature.vh" + +input wclk; +input wclke; +input we; +input [BYTEEN_WIDTH-1:0] byteen; +input [ADDR_WIDTH_A-1:0 ] waddr; +input [DATA_WIDTH_A-1:0 ] wdata; + +input rclk; +input re; +input [ADDR_WIDTH_B-1:0 ] raddr; +output [DATA_WIDTH_B-1:0 ]rdata; + +input reset; +input waddren; +input raddren; + +localparam MAP_ADDR_WIDTH_A = (address_mapping_table_A_size!=0)?address_mapping_table_A_size:ADDR_WIDTH_A; +localparam MAP_ADDR_WIDTH_B = (address_mapping_table_B_size!=0)?address_mapping_table_B_size:ADDR_WIDTH_B; +initial begin + $display("MAP_ADDR_WIDTH_A: %d", MAP_ADDR_WIDTH_A); + $display("MAP_ADDR_WIDTH_B: %d", MAP_ADDR_WIDTH_B); +end + +wire [MAP_ADDR_WIDTH_A-1:0 ] w_waddr_map; +wire [DATA_WIDTH_A-1:0 ] w_wdata_map; + +wire [MAP_ADDR_WIDTH_B-1:0 ] w_raddr_map; +wire [DATA_WIDTH_B-1:0 ] w_rdata_map; + +wire rclk_i; +wire wclk_i; +assign rclk_i = rclk ~^ RCLK_POLARITY; +assign wclk_i = wclk ~^ WCLK_POLARITY; + +function integer get_current_row_index; +input integer row;//Mode type +integer x; + begin + get_current_row_index = 0; + for (x=0; x1) + begin + assign w_we[1] = ((we == WE_POLARITY) & wen_decode[WRSEL_INDEX] & (byteen[BYTEEN_INDEX] == BYTEEN_POLARITY) ) ? WE_POLARITY: !WE_POLARITY; + end + + bram_primitive #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH(WDATA_WIDTH_ROW), + .WCLK_POLARITY(WCLK_POLARITY), + .WCLKE_POLARITY(WCLKE_POLARITY), + .WE_POLARITY(WE_POLARITY), + .WRITE_MODE(WRITE_MODE), + + .READ_WIDTH(RDATA_WIDTH_ROW), + .RCLK_POLARITY(RCLK_POLARITY), + .RE_POLARITY(RE_POLARITY), + .OUTPUT_REG(OUTPUT_REG), + + //Titanium extra paramters + .RST_POLARITY(RST_POLARITY), + .RESET_RAM(RESET_RAM), + .RESET_OUTREG(RESET_OUTREG), + .WADDREN_POLARITY(WADDREN_POLARITY), + .RADDREN_POLARITY(RADDREN_POLARITY), + + .WEN_WIDTH(WEN_WIDTH_ROW), + + .ini_index(DATA_MAP_INDEX) + + ) bram ( + //Trion and Titanium ports + .WCLK(wclk), // Write clock input + .WCLKE(wclke), // Write clock-enable input + .WE(w_we), // Write-enable input + .WADDR(w_waddr), // Write address input + .WDATA(w_wdata), // Write data input + + .RCLK(rclk), // Read clock input + .RE(re), // Read-enable input + .RADDR(w_raddr), // Read address input + .RDATA(w_rdata), // Read data output + + //Titanium extra ports + .RST(reset), // reset + .WADDREN(waddren), // write address enable + .RADDREN(raddren) // read address enable + ); + end + end + + end + else if (bram_table_loop_mode == 1 ) + begin:scan_row + initial begin + $display("Scan Row Loop:(Speed)"); + end + + for (gen_y=0; gen_y1) + begin + assign w_we[1] = ((we == WE_POLARITY) & wen_decode[WRSEL_INDEX] & (byteen[BYTEEN_INDEX] == BYTEEN_POLARITY)) ? WE_POLARITY: !WE_POLARITY; + end + + bram_primitive #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH(WDATA_WIDTH_ROW), + .WCLK_POLARITY(WCLK_POLARITY), + .WCLKE_POLARITY(WCLKE_POLARITY), + .WE_POLARITY(WE_POLARITY), + .WRITE_MODE(WRITE_MODE), + + .READ_WIDTH(RDATA_WIDTH_ROW), + .RCLK_POLARITY(RCLK_POLARITY), + .RE_POLARITY(RE_POLARITY), + .OUTPUT_REG(OUTPUT_REG), + + //Titanium extra paramters + .RST_POLARITY(RST_POLARITY), + .RESET_RAM(RESET_RAM), + .RESET_OUTREG(RESET_OUTREG), + .WADDREN_POLARITY(WADDREN_POLARITY), + .RADDREN_POLARITY(RADDREN_POLARITY), + + .WEN_WIDTH(WEN_WIDTH_ROW), + + .ini_index(DATA_MAP_INDEX) + + ) bram ( + //Trion and Titanium ports + .WCLK(wclk), // Write clock input + .WCLKE(wclke), // Write clock-enable input + .WE(w_we), // Write-enable input + .WADDR(w_waddr), // Write address input + .WDATA(w_wdata), // Write data input + + .RCLK(rclk), // Read clock input + .RE(re), // Read-enable input + .RADDR(w_raddr), // Read address input + .RDATA(w_rdata), // Read data output + + //Titanium extra ports + .RST(reset), // reset + .WADDREN(waddren), // write address enable + .RADDREN(raddren) // read address enable + ); + end + end + + end + endgenerate + + +endmodule \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/debug_profile.wizard.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/debug_profile.wizard.json new file mode 100644 index 0000000000000000000000000000000000000000..8678020a5c941cb17f95d5bd49b8b5ae02a45e2a --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/debug_profile.wizard.json @@ -0,0 +1,188 @@ +{ + "debug_cores": [ + { + "name": "la0", + "type": "la", + "uuid": "067907bc791d4c609da8200a70631e9d", + "trigin_en": false, + "trigout_en": false, + "auto_inserted": true, + "capture_control": false, + "data_depth": 1024, + "input_pipeline": 1, + "probes": [ + { + "name": "inst_test_pattern/re", + "width": 1, + "probe_type": 1 + } + ] + } + ], + "connections": [ + { + "command": "add_ports", + "id": 1, + "args": { + "netlist": "dpram_top_trion", + "ports": [ + { + "name": "jtag_inst1_CAPTURE", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_DRCK", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_RESET", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_RUNTEST", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_SEL", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_SHIFT", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_TCK", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_TDI", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_TMS", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_UPDATE", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_TDO", + "dir": "out", + "width": 1 + } + ] + } + }, + { + "command": "instantiate", + "netlist": "edb_top", + "id": 2, + "instance": "edb_top_inst" + }, + { + "command": "connect", + "id": 3, + "args": { + "instance": "edb_top_inst", + "ports": [ + { + "name": "bscan_CAPTURE", + "net": "jtag_inst1_CAPTURE" + }, + { + "name": "bscan_DRCK", + "net": "jtag_inst1_DRCK" + }, + { + "name": "bscan_RESET", + "net": "jtag_inst1_RESET" + }, + { + "name": "bscan_RUNTEST", + "net": "jtag_inst1_RUNTEST" + }, + { + "name": "bscan_SEL", + "net": "jtag_inst1_SEL" + }, + { + "name": "bscan_SHIFT", + "net": "jtag_inst1_SHIFT" + }, + { + "name": "bscan_TCK", + "net": "jtag_inst1_TCK" + }, + { + "name": "bscan_TDI", + "net": "jtag_inst1_TDI" + }, + { + "name": "bscan_TMS", + "net": "jtag_inst1_TMS" + }, + { + "name": "bscan_UPDATE", + "net": "jtag_inst1_UPDATE" + }, + { + "name": "bscan_TDO", + "net": "jtag_inst1_TDO" + }, + { + "name": "la0_clk", + "net": "i_wclk", + "path": [] + }, + { + "name": "la0_probe0", + "net": "re", + "path": [ + "inst_test_pattern" + ] + } + ] + } + } + ], + "vdbs": [ + { + "file": "debug_top.post.vdb", + "instance": "edb_top_inst" + } + ], + "session": { + "wizard": { + "data_depth": 1024, + "capture_control": false, + "selected_nets": [ + { + "name": "re", + "width": 1, + "clk_domain": "i_wclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "inst_test_pattern" + ] + } + ], + "top_module": "dpram_top_trion", + "db_checksum": "ba5fce12098a2c03e7bae2e9a172d1842464edfca8e284870b3519e987537970", + "src": "elaborate", + "jtag_user": "USER1", + "input_pipeline": 1 + } + } +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/dpram_top_trion.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/dpram_top_trion.v new file mode 100644 index 0000000000000000000000000000000000000000..3b2a04dfa9036de61bee23b535f3b4a115ef642f --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/dpram_top_trion.v @@ -0,0 +1,916 @@ + +//`define TEST_SP_RAM +`define TEST_SDP_RAM +//`define TEST_TDP_RAM +//`define TEST_SP_ROM +//`define TEST_TDP_ROM + + + +module dpram_top_trion #( +) +( + i_arstn, + + o_pll_bram_RSTN, + i_pll_bram_LOCKED, + i_wclk, + i_rclk, + + + o_led0_r, + o_led0_g, + o_led0_b, + + o_led1_r, + o_led1_g, + o_led1_b, + + i_sw0, + i_sw1, + i_sw2, + + ); + +`ifdef TEST_SP_RAM +`define SINGLE_TEST + +//Trion and Titanium parameters + parameter CLK_POLARITY = 1'b1; //clk polarity, 0:falling edge, 1:rising edge + + parameter WCLKE_POLARITY = 1'b1; //wclke polarity, 0:active low, 1:active high + parameter WE_POLARITY = 1'b1; //we polarity, 0:active low, 1:active high + parameter WRITE_MODE = "WRITE_FIRST";//write mode, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter RE_POLARITY = 1'b1; // re polarity, 0:active low , 1:active high + parameter OUTPUT_REG = 1'b1; // Output register enable, 1:add pipe-line read register + + parameter BYTEEN_POLARITY = 1'b1; //byteen polarity, 0:active low, 1:active high + + //Port Enable + parameter WCLKE_ENABLE = 1'b1; //1: Enalbe the port for waddren pin , 0: dislable + + parameter WE_ENABLE = 1'b1; //1: Enalbe the port for WE pin , 0: dislable + parameter RE_ENABLE = 1'b1; //1: Enalbe the port for RE pin , 0: dislable + parameter BYTEEN_ENABLE = 1'b1; //1: Enalbe the port for Byteen pins , 0: dislable + + //Titanium extra paramters + parameter RST_POLARITY = 1'b1; // rst polarity + parameter RESET_RAM = "ASYNC"; // reset mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG = "ASYNC"; // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDREN_POLARITY = 1'b1; // addren polarity + + + //Port Enable + parameter RESET_ENABLE = 1'b1; //1: Enalbe the port for reset pin , 0: dislable + + parameter ADDREN_ENABLE = 1'b1; //1: Enalbe the port for addren pin , 0: dislable + +`endif + +`ifdef TEST_SDP_RAM +`define SINGLE_TEST + +//Trion and Titanium parameters + parameter CLK_POLARITY = 1'b1; //clk polarity, 0:falling edge, 1:rising edge + + parameter WCLK_POLARITY = 1'b1; //wclk polarity, 0:falling edge, 1:rising edge + + parameter WCLKE_POLARITY = 1'b1; //wclke polarity, 0:active low, 1:active high + parameter WE_POLARITY = 1'b1; //we polarity, 0:active low, 1:active high + parameter WRITE_MODE = "READ_FIRST";//write mode, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + parameter RCLK_POLARITY = 1'b1; // rclk polarity, 0:falling edge, 1:rising edge + parameter RE_POLARITY = 1'b1; // re polarity, 0:active low , 1:active high + parameter OUTPUT_REG = 1'b0; // Output register enable, 1:add pipe-line read register + + parameter BYTEEN_POLARITY = 1'b1; //byteen polarity, 0:active low, 1:active high + + //Port Enable + parameter CLK_MODE = 2; //1: ONE CLK Mode, CLK pin will provide the clock source to the memory + //2: TWO CLK Mode, wclk pin will provide the clock source for write operation , rclk pin will provide the clock source for read operation + + parameter WCLKE_ENABLE = 1'b1; //1: Enalbe the port for waddren pin , 0: dislable + + parameter WE_ENABLE = 1'b1; //1: Enalbe the port for WE pin , 0: dislable + parameter RE_ENABLE = 1'b1; //1: Enalbe the port for RE pin , 0: dislable + parameter BYTEEN_ENABLE = 1'b1; //1: Enalbe the port for Byteen pins , 0: dislable + + //Titanium extra paramters + parameter RST_POLARITY = 1'b1; // rst polarity + parameter RESET_RAM = "ASYNC"; // reset mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG = "ASYNC"; // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter WADDREN_POLARITY = 1'b1; // waddren polarity + parameter RADDREN_POLARITY = 1'b1; // raddren polarity + + + //Port Enable + parameter RESET_ENABLE = 1'b1; //1: Enalbe the port for reset pin , 0: dislable + + parameter WADDREN_ENABLE = 1'b1; //1: Enalbe the port for waddren pin , 0: dislable + parameter RADDREN_ENABLE = 1'b1; //1: Enalbe the port for raddren pin , 0: dislable + parameter DATA_WIDTH_A = 16; + parameter DATA_WIDTH_B = 16; + parameter ADDR_WIDTH_A = 3; + parameter ADDR_WIDTH_B = 3; + parameter BYTEEN_WIDTH = 1; + parameter GROUP_DATA_WIDTH = 16; + parameter FAMILY = "TRION"; + +`endif + +`ifdef TEST_TDP_RAM +`define DUAL_TEST + + //Trion and Titanium parameters + parameter CLK_POLARITY = 1'b1; //clk polarity for one clk mode, 0:falling edge, 1:rising edge + parameter CLKE_POLARITY = 1'b1; //clke polarity for one clk mode, 0:active low, 1:active high + + parameter CLKA_POLARITY = 1'b1; //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEA_POLARITY = 1'b1; //clke A polarity, 0:active low, 1:active high + parameter WEA_POLARITY = 1'b0; //we A polarity, 0:active low, 1:active high + parameter WRITE_MODE_A = "WRITE_FIRST";//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter OUTPUT_REG_A = 1'b1; // Output register enable, 1:add pipe-line read register + parameter BYTEENA_POLARITY = 1'b1; // byteen polarity 0:active low, 1:active high + + parameter CLKB_POLARITY = 1'b1; //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEB_POLARITY = 1'b1; //clke A polarity, 0:active low, 1:active high + parameter WEB_POLARITY = 1'b0; //we B polarity, 0:active low, 1:active high + parameter WRITE_MODE_B = "WRITE_FIRST";//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter OUTPUT_REG_B = 1'b1; // Output register enable, 1:add pipe-line read register + parameter BYTEENB_POLARITY = 1'b1; // byteen polarity 0:active low, 1:active high + + + //Port Enable + parameter CLK_MODE = 1; //1: ONE CLK Mode, CLK pin will provide the clock source to the memory + //2: TWO CLK Mode, clk_a and clk_b + parameter CLKEA_ENABLE = 1'b1; //1: Enalbe the port for clke_a pin , 0: dislable + parameter WEA_ENABLE = 1'b1; //1: Enable the port for we_a pin , 0: disable + parameter BYTEENA_ENABLE = 1'b1; //1: Enable the port for Byteen_a pins , 0: disable + + parameter CLKEB_ENABLE = 1'b1; //1: Enalbe the port for clke_b pin , 0: dislable + parameter WEB_ENABLE = 1'b1; //1: Enable the port for we_b pin , 0: disable + parameter BYTEENB_ENABLE = 1'b1; //1: Enable the port for Byteen_b pins , 0: disable + + + //Titanium extra paramters + parameter RSTA_POLARITY = 1'b1; // rst A polarity + parameter RESET_RAM_A = "ASYNC"; // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_A = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENA_POLARITY = 1'b1; // addrena polarity + + parameter RSTB_POLARITY = 1'b1; // rst A polarity + parameter RESET_RAM_B = "ASYNC"; // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_B = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENB_POLARITY = 1'b1; // addrenb polarity + + //Port Enable + parameter RESET_A_ENABLE = 1'b1; //1: Enable the port for reset_a pin , 0: disable + parameter ADDREN_A_ENABLE = 1'b1; //1: Enable the port for addren_a pin , 0: disable + + parameter RESET_B_ENABLE = 1'b1; //1: Enable the port for reset_b pin , 0: disable + parameter ADDREN_B_ENABLE = 1'b1; //1: Enable the port for addren_b pin , 0: disable + +`endif + + +`ifdef TEST_SP_ROM + `define SINGLE_TEST + parameter WE_POLARITY = 1'b1; // re polarity, 0:active low , 1:active high + + +//Trion and Titanium parameters + parameter CLK_POLARITY = 1'b1; //clk polarity, 0:falling edge, 1:rising edge + + parameter RE_POLARITY = 1'b1; // re polarity, 0:active low , 1:active high + parameter OUTPUT_REG = 1'b0; // Output register enable, 1:add pipe-line read register + + parameter RE_ENABLE = 1'b1; //1: Enable the port for RE pin , 0: disable + parameter BYTEEN_ENABLE = 1'b1; //1: Enable the port for Byteen pins , 0: disable + + //Titanium extra paramters + parameter RST_POLARITY = 1'b1; // rst polarity + parameter RESET_RAM = "ASYNC"; // reset mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG = "ASYNC"; // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDREN_POLARITY = 1'b1; // addren polarity + + + //Port Enable + parameter RESET_ENABLE = 1'b1; //1: Enable the port for reset pin , 0: disable + + parameter ADDREN_ENABLE = 1'b1; //1: Enable the port for addren pin , 0: disable + + +`endif + +`ifdef TEST_TDP_ROM + `define DUAL_TEST + parameter WEA_POLARITY = 1'b1; //we A polarity, 0:active low, 1:active high + parameter WEB_POLARITY = 1'b1; //we A polarity, 0:active low, 1:active high + + + + //Trion and Titanium parameters + parameter CLK_POLARITY = 1'b1; //clk polarity for one clk mode, 0:falling edge, 1:rising edge + parameter CLKE_POLARITY = 1'b1; //clke polarity for one clk mode, 0:active low, 1:active high + + parameter CLKA_POLARITY = 1'b1; //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEA_POLARITY = 1'b1; //clke A polarity, 0:active low, 1:active high + + parameter OUTPUT_REG_A = 1'b0; // Output register enable, 1:add pipe-line read register + parameter BYTEENA_POLARITY = 1'b1; // byteen polarity 0:active low, 1:active high + + parameter CLKB_POLARITY = 1'b1; //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEB_POLARITY = 1'b1; //clke A polarity, 0:active low, 1:active high + + parameter OUTPUT_REG_B = 1'b0; // Output register enable, 1:add pipe-line read register + parameter BYTEENB_POLARITY = 1'b1; // byteen polarity 0:active low, 1:active high + + + //Port Enable + parameter CLK_MODE = 2; //1: ONE CLK Mode, CLK pin will provide the clock source to the memory + //2: TWO CLK Mode, clk_a and clk_b + parameter CLKEA_ENABLE = 1'b1; //1: Enalbe the port for clke_a pin , 0: dislable + + parameter CLKEB_ENABLE = 1'b1; //1: Enalbe the port for clke_b pin , 0: dislable + + + //Titanium extra paramters + parameter RSTA_POLARITY = 1'b1; // rst A polarity + parameter RESET_RAM_A = "ASYNC"; // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_A = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENA_POLARITY = 1'b1; // addrena polarity + + parameter RSTB_POLARITY = 1'b1; // rst A polarity + parameter RESET_RAM_B = "ASYNC"; // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_B = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENB_POLARITY = 1'b1; // addrenb polarity + + //Port Enable + parameter RESET_A_ENABLE = 1'b1; //1: Enable the port for reset_a pin , 0: disable + parameter ADDREN_A_ENABLE = 1'b1; //1: Enable the port for addren_a pin , 0: disable + + parameter RESET_B_ENABLE = 1'b1; //1: Enable the port for reset_b pin , 0: disable + parameter ADDREN_B_ENABLE = 1'b1; //1: Enable the port for addren_b pin , 0: disable +`endif + + + +`include "bram_decompose.vh" + + + input i_arstn; + + output o_pll_bram_RSTN; + input i_pll_bram_LOCKED; + input i_wclk; + input i_rclk; + + + output o_led0_r; + output o_led0_g; + output o_led0_b; + + output o_led1_r; + output o_led1_g; + output o_led1_b; + + input i_sw0; + input i_sw1; + input i_sw2; + + // output [DATA_WIDTH_B-1:0] rdata; + + + + + + + +assign o_pll_bram_RSTN = 1'b1;//i_arstn; + +//assign w_re = RE_POLARITY; + +reg [2:0] r_led0_rgb; +reg [2:0] r_led1_rgb; + +wire w_pattern_rst; +wire w_bram_rst; +wire [2:0] w_state; + +assign {o_led0_r,o_led0_g,o_led0_b} = r_led0_rgb; +assign {o_led1_r,o_led1_g,o_led1_b} = r_led1_rgb; + + + + +`ifdef DUAL_TEST + +reset_ctrl +#( + .NUM_RST (2), + .CYCLE (10), + .IN_RST_ACTIVE (2'b00), + .OUT_RST_ACTIVE ({2{ RSTA_POLARITY }}) +) +inst_reset_mcu_ctrl +( + .i_arst ({2{i_pll_bram_LOCKED}}), + .i_clk ({2{i_wclk}}), + .o_srst ({w_pattern_rst,w_bram_rst}) +); + +wire w_wclke; +wire [BYTEEN_WIDTH_A-1:0] w_byteen_A; + +//Titanium extra ports +wire w_addren_A; +wire [ADDR_WIDTH_A-1:0] w_addr_A; +wire w_we_A; +wire [DATA_WIDTH_A-1:0] w_wdata_A; + +wire w_raddren_A; +wire w_re_A; +wire [DATA_WIDTH_A-1:0] w_rdata_A; + +wire [2:0] w_state_A; + + +wire [BYTEEN_WIDTH_B-1:0] w_byteen_B; +wire w_addren_B; +wire [ADDR_WIDTH_B-1:0] w_addr_B; +wire w_we_B; +wire [DATA_WIDTH_B-1:0] w_wdata_B; + +wire w_raddren_B; +wire w_re_B; +wire [DATA_WIDTH_B-1:0] w_rdata_B; + +wire [2:0] w_state_B; + + +localparam TEST_PORT_WRITE = 1; //0: write port A, 1: write port B +localparam TEST_BYTEEN_A = 0; //1: Shifting the Byten Enable in test. +localparam TEST_BYTEEN_B = 0; //1: Shifting the Byten Enable in test. + + +localparam TEST_PATTERN_A = (TEST_PORT_WRITE ==0)? "WriteRead": "READ"; +localparam TEST_PATTERN_B = (TEST_PORT_WRITE ==0)? "READ": "WriteRead"; + + + + wire w_compare_A; + test_pattern #( + //Trion and Titanium parameters + .WADDR_WIDTH (ADDR_WIDTH_A), + .WDATA_WIDTH (DATA_WIDTH_A), + .WRITE_COUNT (TOTAL_SIZE_A), + .BYTEEN_WIDTH(BYTEEN_WIDTH_A), + + .TEST_PATTERN(TEST_PATTERN_A), + .TEST_BYTEEN(TEST_BYTEEN_A), + + .WE_POLARITY (WEA_POLARITY), + + + .RADDR_WIDTH (ADDR_WIDTH_A), + .RDATA_WIDTH (DATA_WIDTH_A), + .READ_COUNT (TOTAL_SIZE_A), + .RE_POLARITY (WEA_POLARITY), + .OUTPUT_REG (OUTPUT_REG_A), + + .GROUP_DATA (GROUP_DATA_WIDTH) + ) + inst_test_pattern_A + ( + //Trion and Titanium ports + .clk(i_wclk), // clock input for one clock mode + + .reset(w_pattern_rst), + + .start_in(i_sw0), + .rd_start_in(i_sw2), + + .we(w_we_A), // write enale output + .waddr(w_addr_A), // Write address output + .wdata(w_wdata_A), // Write data output + .byteen(w_byteen_A), + + + .re(w_re_A), // read enale output + .raddr(), // read address output + .rdata(w_rdata_A), // read data output + + .state(w_state), + .compare(w_compare_A) + ); + + + wire w_compare_B; + test_pattern #( + //Trion and Titanium parameters + .WADDR_WIDTH (ADDR_WIDTH_B), + .WDATA_WIDTH (DATA_WIDTH_B), + .WRITE_COUNT (TOTAL_SIZE_B), + .BYTEEN_WIDTH(BYTEEN_WIDTH_B), + + .TEST_PATTERN(TEST_PATTERN_B), + .TEST_BYTEEN(TEST_BYTEEN_B), + + .WE_POLARITY (WEB_POLARITY), + + + .RADDR_WIDTH (ADDR_WIDTH_B), + .RDATA_WIDTH (DATA_WIDTH_B), + .READ_COUNT (TOTAL_SIZE_B), + .RE_POLARITY (WEB_POLARITY), + .OUTPUT_REG (OUTPUT_REG_B), + + .GROUP_DATA (GROUP_DATA_WIDTH) + ) + inst_test_pattern_B + ( + //Trion and Titanium ports + .clk(i_wclk), // clock input for one clock mode + + .reset(w_pattern_rst), + + .start_in(i_sw1), + .rd_start_in(i_sw2), + + .we(w_we_B), // write enale output + .waddr(w_addr_B), // Write address output + .wdata(w_wdata_B), // Write data output + .byteen(w_byteen_B), + + + .re(w_re_B), // read enale output + .raddr(), // read address output + .rdata(w_rdata_B), // read data output + + .state(w_state_B), + .compare(w_compare_B) + ); + + always@(*) + begin + + if (w_compare_A) + r_led1_rgb <= 3'b100; + else + r_led1_rgb <= 3'b001; + + // r_led0_rgb = w_state; + end + + always@(*) + begin + + if (w_compare_B) + r_led0_rgb <= 3'b100; + else + r_led0_rgb <= 3'b001; + + //r_led0_rgb = w_state; + end + +`else + + +reset_ctrl +#( + .NUM_RST (2), + .CYCLE (10), + .IN_RST_ACTIVE (2'b00), + .OUT_RST_ACTIVE ({2{ RST_POLARITY }}) +) +inst_reset_mcu_ctrl +( + .i_arst ({2{i_pll_bram_LOCKED}}), + .i_clk ({2{i_wclk}}), + .o_srst ({w_pattern_rst,w_bram_rst}) +); + +wire w_wclke; +wire [BYTEEN_WIDTH-1:0] w_byteen; + +//Titanium extra ports +wire w_waddren; +wire [ADDR_WIDTH_A-1:0] w_waddr; +wire w_we; +wire [DATA_WIDTH_A-1:0] w_wdata; + +wire w_raddren; +wire [ADDR_WIDTH_B-1:0] w_raddr; +wire [DATA_WIDTH_B-1:0] w_rdata; +wire w_wr_start; +wire w_wr_end; + + + +wire w_re; + +localparam TEST_PATTERN = "WriteRead"; + wire w_compare; +test_pattern #( + .TEST_PATTERN(TEST_PATTERN), + +//Trion and Titanium parameters + .WADDR_WIDTH (ADDR_WIDTH_A), + .WDATA_WIDTH (DATA_WIDTH_A), + .WRITE_COUNT (TOTAL_SIZE_A), + .WE_POLARITY (WE_POLARITY), + + + .RADDR_WIDTH (ADDR_WIDTH_B), + .RDATA_WIDTH (DATA_WIDTH_B), + .READ_COUNT (TOTAL_SIZE_B), + .RE_POLARITY (RE_POLARITY), + .OUTPUT_REG (OUTPUT_REG) +) +inst_test_pattern +( + //Trion and Titanium ports + .clk(i_wclk), // clock input for one clock mode + + .reset(w_pattern_rst), + + .start_in(i_sw0), + + .we(w_we), // write enale output + .waddr(w_waddr), // Write address output + .wdata(w_wdata), // Write data output + + + .re(w_re), // read enale output + .raddr(w_raddr), // read address output + .rdata(w_rdata), // read data output + + .state(w_state), + .compare(w_compare) + ); + +always@(*) +begin + + if (w_compare) + r_led1_rgb <= 3'b100; //FAIL : 6th LED will ON + else + r_led1_rgb <= 3'b001; //PASS : 4th LED will ON + + r_led0_rgb = w_state; +end + + + `endif + + + + + +`ifdef TEST_SP_RAM + +assign w_waddren = ADDREN_POLARITY; + +assign w_wclke = WCLKE_POLARITY; +assign w_byteen ={BYTEEN_WIDTH {BYTEEN_POLARITY} }; + + + efx_single_port_ram #( + .CLK_POLARITY (CLK_POLARITY ), + .WCLKE_POLARITY (WCLKE_POLARITY ), + .WE_POLARITY (WE_POLARITY ), + .WRITE_MODE (WRITE_MODE ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .BYTEEN_POLARITY (BYTEEN_POLARITY), + .WCLKE_ENABLE (WCLKE_ENABLE ), + .WE_ENABLE (WE_ENABLE ), + .RE_ENABLE (RE_ENABLE ), + .BYTEEN_ENABLE (BYTEEN_ENABLE ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .ADDREN_POLARITY (ADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .ADDREN_ENABLE (ADDREN_ENABLE ) + +) +inst_memory +( + .clk (i_wclk ), + .wclke (w_wclke ), + .byteen (w_byteen ), + .we (w_we ), + .addr (w_waddr), + .wdata (w_wdata), + .re (w_re ), + .rdata (w_rdata), + .reset (w_bram_rst), + .addren (w_waddren ) + ); + + `endif + + + `ifdef TEST_SP_ROM + +assign w_waddren = ADDREN_POLARITY; + + + + efx_single_port_rom #( + .CLK_POLARITY (CLK_POLARITY ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .RE_ENABLE (RE_ENABLE ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .ADDREN_POLARITY (ADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .ADDREN_ENABLE (ADDREN_ENABLE ) + +) +inst_memory +( + .clk (i_wclk ), + .addr (w_waddr), + .re (w_re ), + .rdata (w_rdata), + .reset (w_bram_rst), + .addren (w_waddren ) + ); + + `endif + +`ifdef TEST_SDP_RAM + + +assign w_waddren = WADDREN_POLARITY; +assign w_raddren = RADDREN_POLARITY; +assign w_wclke = WCLKE_POLARITY; +assign w_byteen = {BYTEEN_WIDTH {BYTEEN_POLARITY} }; + + efx_simple_dual_port_ram #( + .CLK_POLARITY (CLK_POLARITY ), + + .WCLK_POLARITY (WCLK_POLARITY ), + .WCLKE_POLARITY (WCLKE_POLARITY ), + .WE_POLARITY (WE_POLARITY ), + .WRITE_MODE (WRITE_MODE ), + + .RCLK_POLARITY (RCLK_POLARITY ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .BYTEEN_POLARITY (BYTEEN_POLARITY), + .CLK_MODE (CLK_MODE), + .WCLKE_ENABLE (WCLKE_ENABLE ), + .WE_ENABLE (WE_ENABLE ), + .RE_ENABLE (RE_ENABLE ), + .BYTEEN_ENABLE (BYTEEN_ENABLE ), + + .DATA_WIDTH_A (DATA_WIDTH_A ), + .DATA_WIDTH_B (DATA_WIDTH_B ), + .ADDR_WIDTH_A (ADDR_WIDTH_A ), + .ADDR_WIDTH_B (ADDR_WIDTH_B ), + .BYTEEN_WIDTH (BYTEEN_WIDTH ), + .FAMILY (FAMILY ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .RADDREN_POLARITY (RADDREN_POLARITY), + .WADDREN_POLARITY (WADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .RADDREN_ENABLE (RADDREN_ENABLE ), + .WADDREN_ENABLE (WADDREN_ENABLE ) + +) +inst_memory +( + .clk (i_wclk ), //for 1 clock mode + + .wclk (i_wclk ), //for 2 clock mode + .wclke (w_wclke ), + .byteen (w_byteen ), + .we (w_we ), + .waddr (w_waddr), + .wdata ({~w_wdata[7:0],w_wdata[7:0]}), + + .rclk (i_wclk ), //i_rclk for 2 clock mode + .re (w_re ), + .raddr (w_raddr), + .rdata (w_rdata), + + .reset (w_bram_rst), + .waddren (w_waddren ), + .raddren (w_raddren ) + ); + + `endif + + `ifdef TEST_TDP_RAM + + +assign w_addren_A = ADDRENA_POLARITY; +assign w_clke_A = CLKEA_POLARITY; +assign w_byteen_A ={BYTEEN_WIDTH {BYTEENA_POLARITY} }; + +assign w_addren_B = ADDRENB_POLARITY; +assign w_clke_B = CLKEB_POLARITY; +assign w_byteen_B ={BYTEEN_WIDTH {BYTEENB_POLARITY} }; + + + efx_true_dual_port_ram #( + + //Trion and Titanium parameters + .CLK_POLARITY ( CLK_POLARITY ), + .CLKE_POLARITY ( CLKE_POLARITY ), + .CLKA_POLARITY ( CLKA_POLARITY ), + .CLKEA_POLARITY ( CLKEA_POLARITY ), + .WEA_POLARITY ( WEA_POLARITY ), + .WRITE_MODE_A ( WRITE_MODE_A ), + .OUTPUT_REG_A ( OUTPUT_REG_A ), + .BYTEENA_POLARITY( BYTEENA_POLARITY), + .CLKB_POLARITY ( CLKB_POLARITY ), + .CLKEB_POLARITY ( CLKEB_POLARITY ), + .WEB_POLARITY ( WEB_POLARITY ), + .WRITE_MODE_B ( WRITE_MODE_B ), + .OUTPUT_REG_B ( OUTPUT_REG_B ), + .BYTEENB_POLARITY(BYTEENB_POLARITY), + + + //Port Enable + .CLK_MODE (CLK_MODE ), + .CLKEA_ENABLE (CLKEA_ENABLE ), + .WEA_ENABLE (WEA_ENABLE ), + .BYTEENA_ENABLE (BYTEENA_ENABLE ), + .CLKEB_ENABLE (CLKEB_ENABLE ), + .WEB_ENABLE (WEB_ENABLE ), + .BYTEENB_ENABLE (BYTEENB_ENABLE ), + + + //Titanium extra paramters + .RSTA_POLARITY (RSTA_POLARITY ), + .RESET_RAM_A (RESET_RAM_A ), + .RESET_OUTREG_A (RESET_OUTREG_A ), + .ADDRENA_POLARITY (ADDRENA_POLARITY ), + .RSTB_POLARITY (RSTB_POLARITY ), + .RESET_RAM_B (RESET_RAM_B ), + .RESET_OUTREG_B (RESET_OUTREG_B ), + .ADDRENB_POLARITY (ADDRENB_POLARITY ), + + //Port Enable + .RESET_A_ENABLE (RESET_A_ENABLE ), + .ADDREN_A_ENABLE (ADDREN_A_ENABLE), + .RESET_B_ENABLE (RESET_B_ENABLE ), + .ADDREN_B_ENABLE (ADDREN_B_ENABLE) +) +inst_memory +( + //Trion and Titanium ports + .clk(i_wclk), // for 1 clock mode + .clke(w_clke_A), // for 1 clock mode + + .clk_a(i_wclk), //for 2 clock mode + .clke_a(w_clke_A), + .byteen_a(w_byteen_A), + .we_a(w_we_A), + .addr_a(w_addr_A), + .wdata_a(w_wdata_A), + .rdata_a(w_rdata_A), + + .clk_b(i_rclk), //for 2 clock mode + .clke_b(w_clke_B), + .byteen_b(w_byteen_B), + .we_b(w_we_B), + .addr_b(w_addr_B), + .wdata_b(w_wdata_B), + .rdata_b(w_rdata_B), + + //Titanium extra ports + .reset_a(w_bram_rst), + .addren_a(w_addren_A), + .reset_b(w_bram_rst), + .addren_b(w_addren_B) + + ); + + `endif + + + +`ifdef TEST_TDP_ROM + + +assign w_addren_A = ADDRENA_POLARITY; +assign w_clke_A = CLKEA_POLARITY; +assign w_byteen_A ={BYTEEN_WIDTH {BYTEENA_POLARITY} }; + +assign w_addren_B = ADDRENB_POLARITY; +assign w_clke_B = CLKEB_POLARITY; +assign w_byteen_B ={BYTEEN_WIDTH {BYTEENB_POLARITY} }; + + + efx_true_dual_port_rom #( + + //Trion and Titanium parameters + .CLK_POLARITY ( CLK_POLARITY ), + .CLKE_POLARITY ( CLKE_POLARITY ), + .CLKA_POLARITY ( CLKA_POLARITY ), + .CLKEA_POLARITY ( CLKEA_POLARITY ), + + .OUTPUT_REG_A ( OUTPUT_REG_A ), + .CLKB_POLARITY ( CLKB_POLARITY ), + .CLKEB_POLARITY ( CLKEB_POLARITY ), + .OUTPUT_REG_B ( OUTPUT_REG_B ), + + + //Port Enable + .CLK_MODE (CLK_MODE ), + .CLKEA_ENABLE (CLKEA_ENABLE ), + .CLKEB_ENABLE (CLKEB_ENABLE ), + + + //Titanium extra paramters + .RSTA_POLARITY (RSTA_POLARITY ), + .RESET_RAM_A (RESET_RAM_A ), + .RESET_OUTREG_A (RESET_OUTREG_A ), + .ADDRENA_POLARITY (ADDRENA_POLARITY ), + .RSTB_POLARITY (RSTB_POLARITY ), + .RESET_RAM_B (RESET_RAM_B ), + .RESET_OUTREG_B (RESET_OUTREG_B ), + .ADDRENB_POLARITY (ADDRENB_POLARITY ), + + //Port Enable + .RESET_A_ENABLE (RESET_A_ENABLE ), + .ADDREN_A_ENABLE (ADDREN_A_ENABLE), + .RESET_B_ENABLE (RESET_B_ENABLE ), + .ADDREN_B_ENABLE (ADDREN_B_ENABLE) +) +inst_memory +( + //Trion and Titanium ports + .clk(i_wclk), // for 1 clock mode + .clke(w_clke_A), // for 1 clock mode + + .clk_a(i_wclk), //for 2 clock mode + .clke_a(w_clke_A), + .addr_a(w_addr_A), + .rdata_a(w_rdata_A), + + .clk_b(i_rclk), //for 2 clock mode + .clke_b(w_clke_B), + .addr_b(w_addr_B), + .rdata_b(w_rdata_B), + + //Titanium extra ports + .reset_a(w_bram_rst), + .addren_a(w_addren_A), + .reset_b(w_bram_rst), + .addren_b(w_addren_B) + + ); + + `endif + +endmodule \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/efx_simple_dual_port_ram.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/efx_simple_dual_port_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..0fd0d6e3f814aa2f14c0a5f0827740923356fd25 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/efx_simple_dual_port_ram.v @@ -0,0 +1,194 @@ +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// +// ******************************* + +module efx_simple_dual_port_ram ( + //Trion and Titanium ports + clk, // clock input for one clock mode + + + wclk, // Write clock input for two clock mode + wclke, // Write clock-enable input + byteen, // Byteen input + we, // Write-enable input + waddr, // Write address input + wdata, // Write data input + + rclk, // Read clock input for two clock mode + re, // Read-enable input + raddr, // Read address input + rdata, // Read data output + + //Titanium extra ports + reset, // reset + waddren, // write address enable + raddren // read address enable +); + +//`include "bram_decompose.vh" + +//Trion and Titanium parameters +parameter CLK_POLARITY = 1'b1; //clk polarity; 0:falling edge; 1:rising edge + +parameter WCLK_POLARITY = 1'b1; //wclk polarity; 0:falling edge; 1:rising edge +parameter WCLKE_POLARITY = 1'b1; //wclke polarity; 0:active low; 1:active high +parameter WE_POLARITY = 1'b1; //we polarity; 0:active low; 1:active high + +parameter RCLK_POLARITY = 1'b1; // rclk polarity; 0:falling edge; 1:rising edge +parameter RE_POLARITY = 1'b1; // re polarity; 0:active low ; 1:active high +parameter OUTPUT_REG = 1'b0; // Output register enable; 1:add pipe-line read register + +parameter BYTEEN_POLARITY = 1'b1; //byteen polarity; 0:active low; 1:active high + +//Port Enable +parameter CLK_MODE = 2; //1: ONE CLK Mode; CLK pin will provide the clock source to the memory + //2: TWO CLK Mode; wclk pin will provide the clock source for write operation ; rclk pin will provide the clock source for read operation +parameter WCLKE_ENABLE = 1'b1; //1: Enalbe the port for waddren pin ; 0: dislable + +parameter WE_ENABLE = 1'b1; //1: Enable the port for WE pin ; 0: disable +parameter RE_ENABLE = 1'b1; //1: Enable the port for RE pin ; 0: disable +parameter BYTEEN_ENABLE = 1'b1; //1: Enable the port for Byteen pins ; 0: disable + +//Titanium extra paramters +parameter RST_POLARITY = 1'b1; // rst polarity +parameter RESET_RAM = "ASYNC"; // reset mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG = "ASYNC"; // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter WADDREN_POLARITY = 1'b1; // waddren polarity +parameter RADDREN_POLARITY = 1'b1; // raddren polarity + + +//Port Enable +parameter RESET_ENABLE = 1'b1; //1: Enable the port for reset pin ; 0: disable + +parameter WADDREN_ENABLE = 1'b1; //1: Enable the port for waddren pin ; 0: disable +parameter RADDREN_ENABLE = 1; //1: Enable the port for raddren pin ; 0: disable + +parameter WRITE_MODE = "READ_FIRST"; + +parameter DATA_WIDTH_A = 16; +parameter DATA_WIDTH_B = 16; +parameter ADDR_WIDTH_A = 3; +parameter ADDR_WIDTH_B = 3; +parameter BYTEEN_WIDTH = 2; +parameter FAMILY = "TITANIUM"; + +//Trion and Titanium ports +input clk; + +input wclk; +input wclke; +input [BYTEEN_WIDTH-1:0] byteen; +input we; +input [ADDR_WIDTH_A-1:0] waddr; +input [DATA_WIDTH_A-1:0] wdata; + +input rclk; +input re; +input [ADDR_WIDTH_B-1:0] raddr; +output [DATA_WIDTH_B-1:0] rdata; + +//Titanium extra ports +input reset; +input waddren; +input raddren; + +//localparam WRITE_MODE = DECOMPOSE_WRITE_MODE; // "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + + +wire w_wclk; +wire w_rclk; +wire w_wclke; +wire [BYTEEN_WIDTH-1:0] w_byteen; +wire w_we; +wire w_re; +wire w_reset; +wire w_waddren; +wire w_raddren; + +assign w_wclk = (CLK_MODE==2) ? wclk : clk; +assign w_rclk = (CLK_MODE==2) ? rclk : clk; +assign w_wclke = (WCLKE_ENABLE==1) ? wclke : WCLKE_POLARITY; +assign w_byteen= (BYTEEN_ENABLE==1) ? byteen : {BYTEEN_WIDTH{BYTEEN_POLARITY}}; +assign w_we = (WE_ENABLE==1) ? we : WE_POLARITY; +assign w_re = (RE_ENABLE==1) ? re : RE_POLARITY; + +//Titanium extra ports +assign w_reset = (RESET_ENABLE==1) ? reset : (RST_POLARITY==1'b1) ? 1'b0: 1'b1; +assign w_waddren = (WADDREN_ENABLE==1)? waddren : WADDREN_POLARITY; +assign w_raddren = (RADDREN_ENABLE==1)? raddren : RADDREN_POLARITY; + + +localparam WCLK_POLARITY_LC = (CLK_MODE==2) ? WCLK_POLARITY : CLK_POLARITY; +localparam RCLK_POLARITY_LC = (CLK_MODE==2) ? RCLK_POLARITY : CLK_POLARITY; + + + + bram_wrapper_mwm #( + //Trion and Titanium parameters + .WCLK_POLARITY(WCLK_POLARITY_LC), + .WCLKE_POLARITY(WCLKE_POLARITY), + .WE_POLARITY(WE_POLARITY), + .WRITE_MODE(WRITE_MODE), + + .RCLK_POLARITY(RCLK_POLARITY_LC), + .RE_POLARITY(RE_POLARITY), + .OUTPUT_REG(OUTPUT_REG), + + .BYTEEN_POLARITY(BYTEEN_POLARITY), + + .DATA_WIDTH_A(DATA_WIDTH_A), + .DATA_WIDTH_B(DATA_WIDTH_B), + .ADDR_WIDTH_A(ADDR_WIDTH_A), + .ADDR_WIDTH_B(ADDR_WIDTH_B), + .BYTEEN_WIDTH(BYTEEN_WIDTH), + .FAMILY(FAMILY), + + //Titanium extra paramters + .RST_POLARITY(RST_POLARITY), + .RESET_RAM(RESET_RAM), + .RESET_OUTREG(RESET_OUTREG), + .WADDREN_POLARITY(WADDREN_POLARITY), + .RADDREN_POLARITY(RADDREN_POLARITY) + + ) brams ( + .wclk(w_wclk), + .wclke(w_wclke), + .we(w_we), + .byteen(w_byteen), + + .waddr(waddr), + .wdata(wdata), + + .rclk(w_rclk), + .re(w_re), + .raddr(raddr), + .rdata(rdata), + + + //Titanium extra ports + .reset(w_reset), // reset + .waddren(w_waddren), // write address enable + .raddren(w_raddren) // read address enable + ); + + +endmodule \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/my_bram_ip.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/my_bram_ip.v new file mode 100644 index 0000000000000000000000000000000000000000..79d9b4df6c85e2e89787a5132ab876cb32cfc6bd --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/my_bram_ip.v @@ -0,0 +1,2110 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _f3a990bbbff84057a1e36dad7040b59c +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module my_bram_ip ( +input we_a, +input we_b, +input [10:0] addr_a, +input [7:0] wdata_a, +output [7:0] rdata_a, +output [7:0] rdata_b, +input [10:0] addr_b, +input [7:0] wdata_b, +input clk_a, +input clk_b +); +`IP_MODULE_NAME(efx_bram) #( +.ADDR_WIDTH_A (11), +.ADDR_WIDTH_B (11), +.RESET_A_ENABLE (0), +.RESET_B_ENABLE (0), +.RSTA_POLARITY (1), +.RSTB_POLARITY (1), +.FAMILY ("TITANIUM"), +.MEMORY_MODE ("SPEED"), +.WRITE_MODE_A ("READ_FIRST"), +.WRITE_MODE_B ("READ_FIRST"), +.OUTPUT_REG_A (0), +.OUTPUT_REG_B (0), +.MEMORY_TYPE ("TDP_RAM"), +.GROUP_DATA_WIDTH_B (8), +.BYTEENA_ENABLE (0), +.BYTEENB_ENABLE (0), +.BYTEENA_POLARITY (1), +.BYTEENB_POLARITY (1), +.BYTEEN_WIDTH_A (1), +.BYTEEN_WIDTH_B (1), +.BYTEEN_ENABLE (0), +.BYTEEN_POLARITY (1), +.GROUP_DATA_WIDTH (8), +.BYTEEN_WIDTH (1), +.WIDTH_RATIO (4), +.GROUP_DATA_WIDTH_A (8), +.DATA_WIDTH_A (8), +.DATA_WIDTH_B (8), +.ADDREN_ENABLE (1), +.ADDREN_POLARITY (1), +.CLK_MODE (2), +.CLKA_POLARITY (1), +.CLKB_POLARITY (1), +.CLKE_POLARITY (1), +.CLKEA_POLARITY (1), +.CLKEA_ENABLE (0), +.RESET_OUTREG_A ("ASYNC"), +.RESET_OUTREG_B ("ASYNC"), +.RESET_RAM_B ("ASYNC"), +.WEA_ENABLE (1), +.WEA_POLARITY (1), +.WEB_ENABLE (1), +.WEB_POLARITY (1), +.RADDREN_ENABLE (1), +.RADDREN_POLARITY (1), +.WADDREN_ENABLE (1), +.WADDREN_POLARITY (1), +.RCLK_POLARITY (1), +.ADDREN_A_ENABLE (0), +.ADDREN_B_ENABLE (0), +.ADDRENA_POLARITY (1), +.ADDRENB_POLARITY (1), +.WE_ENABLE (1), +.WE_POLARITY (1), +.WCLKE_ENABLE (1), +.WCLKE_POLARITY (1), +.WCLK_POLARITY (1), +.RESET_RAM_A ("ASYNC"), +.RESET_RAM ("ASYNC"), +.CLK_POLARITY (1), +.OUTPUT_REG (0), +.RE_POLARITY (1), +.RE_ENABLE (1), +.WRITE_MODE ("READ_FIRST"), +.RESET_OUTREG ("ASYNC"), +.RESET_ENABLE (1), +.RST_POLARITY (1), +.CLKEB_POLARITY (1), +.CLKEB_ENABLE (0) +) u_efx_bram( +.we_a ( we_a ), +.we_b ( we_b ), +.addr_a ( addr_a ), +.wdata_a ( wdata_a ), +.rdata_a ( rdata_a ), +.rdata_b ( rdata_b ), +.addr_b ( addr_b ), +.wdata_b ( wdata_b ), +.clk_a ( clk_a ), +.clk_b ( clk_b ) +); + +endmodule + +module `IP_MODULE_NAME(efx_bram) #( + +parameter CLK_POLARITY = 1'b1, //clk polarity; 0:falling edge; 1:rising edge +parameter CLKE_POLARITY = 1'b1, //clke polarity for one clk mode; 0:active low; 1:active high +parameter CLKA_POLARITY = 1'b1, //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEA_POLARITY = 1'b1, //clke A polarity; 0:active low; 1:active high +parameter WEA_POLARITY = 1'b1, //we A polarity; 0:active low; 1:active high +parameter OUTPUT_REG_A = 1'b0, // Output register enable; 1:add pipe-line read register +parameter BYTEENA_POLARITY = 1'b1, // byteen polarity 0:active low; 1:active high +parameter CLKB_POLARITY = 1'b1, //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEB_POLARITY = 1'b1, //clke A polarity; 0:active low; 1:active high +parameter WEB_POLARITY = 1'b1, //we B polarity; 0:active low; 1:active high +parameter OUTPUT_REG_B = 1'b0, // Output register enable; 1:add pipe-line read register +parameter BYTEENB_POLARITY = 1'b1, // byteen polarity 0:active low; 1:active high +parameter WCLKE_POLARITY = 1'b1, //wclke polarity; 0:active low; 1:active high +parameter WCLK_POLARITY = 1'b1, //wclk polarity; 0:falling edge; 1:rising edge +parameter RCLK_POLARITY = 1'b1, // rclk polarity; 0:falling edge; 1:rising edge +parameter WE_POLARITY = 1'b1, //we polarity; 0:active low; 1:active high +parameter RE_POLARITY = 1'b1, // re polarity; 0:active low ; 1:active high +parameter OUTPUT_REG = 1'b0, // Output register enable; 1:add pipe-line read register +parameter BYTEEN_POLARITY = 1'b1, //byteen polarity; 0:active low; 1:active high +parameter WCLKE_ENABLE = 1'b1, //1: Enable the port for waddren pin ; 0: disable +parameter WE_ENABLE = 1'b1, //1: Enable the port for WE pin ; 0: disable +parameter RE_ENABLE = 1'b1, //1: Enable the port for RE pin ; 0: disable +parameter BYTEEN_ENABLE = 1'b1, //1: Enable the port for Byteen pins ; 0: disable +parameter RST_POLARITY = 1'b1, // rst polarity +parameter RESET_RAM = "ASYNC", // reset mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG = "ASYNC", // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDREN_POLARITY = 1'b1, // addren polarity +parameter RESET_ENABLE = 1'b1, //1: Enable the port for reset pin ; 0: disable +parameter ADDREN_ENABLE = 1'b1, //1: Enable the port for addren pin ; 0: disable +parameter CLK_MODE = 2, //1: ONE CLK Mode; CLK pin will provide the clock source to the memory + //2: TWO CLK Mode; wclk pin will provide the clock source for write operation ; rclk pin will provide the clock source for read operation +parameter WADDREN_POLARITY = 1'b1, // waddren polarity +parameter RADDREN_POLARITY = 1'b1, // raddren polarity +parameter CLKEA_ENABLE = 1'b1, //1: Enalbe the port for clke_a pin ; 0: dislable +parameter WEA_ENABLE = 1'b1, //1: Enable the port for we_a pin ; 0: disable +parameter BYTEENA_ENABLE = 1'b1, //1: Enable the port for Byteen_a pins ; 0: disable + // +parameter CLKEB_ENABLE = 1'b1, //1: Enalbe the port for clke_b pin ; 0: dislable +parameter WEB_ENABLE = 1'b1, //1: Enable the port for we_b pin ; 0: disable +parameter BYTEENB_ENABLE = 1'b1, //1: Enable the port for Byteen_b pins ; 0: disable +parameter RSTA_POLARITY = 1'b1, // rst A polarity +parameter RESET_RAM_A = "ASYNC", // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_A = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENA_POLARITY = 1'b1, // addrena polarity +parameter RSTB_POLARITY = 1'b1, // rst A polarity +parameter RESET_RAM_B = "ASYNC", // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_B = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENB_POLARITY = 1'b1, // addrenb polarity +parameter RESET_A_ENABLE = 1'b1, //1: Enable the port for reset_a pin ; 0: disable +parameter ADDREN_A_ENABLE = 1'b1, //1: Enable the port for addren_a pin ; 0: disable +parameter RESET_B_ENABLE = 1'b1, //1: Enable the port for reset_b pin ; 0: disable +parameter ADDREN_B_ENABLE = 1'b1, //1: Enable the port for addren_b pin ; 0: disable +parameter WADDREN_ENABLE = 1'b1, //1: Enable the port for waddren pin ; 0: disable +parameter RADDREN_ENABLE = 1'b1, //1: Enable the port for raddren pin ; 0: disable + +parameter ADDR_WIDTH_A = 3, +parameter DATA_WIDTH_A = 16, +parameter ADDR_WIDTH_B = 3, +parameter DATA_WIDTH_B = 16, +parameter BYTEEN_WIDTH = 2, +parameter BYTEEN_WIDTH_A = 2, +parameter BYTEEN_WIDTH_B = 2, +parameter MEMORY_TYPE = "SP_RAM", //1:sp_ram, 2:sdp_ram, 3:tdp_ram +parameter WRITE_MODE = "READ_FIRST", +parameter WRITE_MODE_A = "READ_FIRST", +parameter WRITE_MODE_B = "READ_FIRST", +parameter FAMILY = "TITANIUM", //1:Titanium, 0:Trion +parameter GROUP_DATA_WIDTH = 8, +parameter GROUP_DATA_WIDTH_A= 8, +parameter GROUP_DATA_WIDTH_B= 8, +parameter MEMORY_MODE = "SPEED", //1:speed, 2:area +parameter WIDTH_RATIO = 4 +) + + +( +//////////// data input/output /////////////////// +input wire [DATA_WIDTH_A-1:0] wdata_a, +input wire [DATA_WIDTH_B-1:0] wdata_b, +output wire [DATA_WIDTH_A-1:0] rdata_a, +output wire [DATA_WIDTH_B-1:0] rdata_b, + +///////// Single Port RAM/ROM ports //////////// +input wire clk, +input wire [ADDR_WIDTH_A-1:0] addr, +input wire wclke, +input wire [BYTEEN_WIDTH-1:0] byteen, +input wire we, +input wire re, +//Titanium extra ports +input wire reset, +input wire addren, + +//////////// Simple Dual Port RAM ports /////////// +input wire wclk, +input wire [ADDR_WIDTH_A-1:0] waddr, +input wire rclk, +input wire [ADDR_WIDTH_B-1:0] raddr, +//Titanium extra ports +input wire waddren, +input wire raddren, + +//////////True Dual Port RAM/ROM ports //////////////// +input wire clke, +input wire clk_a, +input wire clke_a, +input wire we_a, +input wire [BYTEEN_WIDTH_A-1:0] byteen_a, +input wire [ADDR_WIDTH_A-1:0 ] addr_a, +input wire clk_b, +input wire clke_b, +input wire we_b, +input wire [BYTEEN_WIDTH_B-1:0] byteen_b, +input wire [ADDR_WIDTH_B-1:0 ] addr_b, +//Titanium extra ports +input wire reset_a, +input wire addren_a, +input wire reset_b, +input wire addren_b +); + +generate + if (MEMORY_TYPE == "SP_RAM") //Single Port RAM + begin + //if (BYTEEN_ENABLE == 1) + //begin + + `IP_MODULE_NAME(efx_single_port_ram) #( + .CLK_POLARITY (CLK_POLARITY ), + .WCLKE_POLARITY (WCLKE_POLARITY ), + .WE_POLARITY (WE_POLARITY ), + .WRITE_MODE (WRITE_MODE ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .BYTEEN_POLARITY (BYTEEN_POLARITY), + .WCLKE_ENABLE (WCLKE_ENABLE ), + .WE_ENABLE (WE_ENABLE ), + .RE_ENABLE (RE_ENABLE ), + .BYTEEN_ENABLE (BYTEEN_ENABLE ), + + .BYTEEN_WIDTH (BYTEEN_WIDTH ), + .ADDR_WIDTH_A (ADDR_WIDTH_A ), + .DATA_WIDTH_A (DATA_WIDTH_A ), + + .FAMILY (FAMILY ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .ADDREN_POLARITY (ADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .ADDREN_ENABLE (ADDREN_ENABLE ) + ) + spram_inst + ( + .clk (clk ), + .addr (addr ), + .wclke (wclke ), + .byteen (byteen ), + .we (we ), + .wdata_a (wdata_a), + .re (re ), + .rdata_a (rdata_a), + .reset (reset ), + .addren (addren ) + ); + //end + //else if (BYTEEN_ENABLE == 0) + //begin + // + // `IP_MODULE_NAME(efx_single_port_ram) #( + // .CLK_POLARITY (CLK_POLARITY ), + // .WCLKE_POLARITY (WCLKE_POLARITY ), + // .WE_POLARITY (WE_POLARITY ), + // .WRITE_MODE (WRITE_MODE ), + // .RE_POLARITY (RE_POLARITY ), + // .OUTPUT_REG (OUTPUT_REG ), + // .BYTEEN_POLARITY (BYTEEN_POLARITY), + // .WCLKE_ENABLE (WCLKE_ENABLE ), + // .WE_ENABLE (WE_ENABLE ), + // .RE_ENABLE (RE_ENABLE ), + // .BYTEEN_ENABLE (BYTEEN_ENABLE ), + // + // .BYTEEN_WIDTH (BYTEEN_WIDTH ), + // .ADDR_WIDTH_A (ADDR_WIDTH_A ), + // .DATA_WIDTH_A (DATA_WIDTH_A ), + // .DATA_WIDTH_B (DATA_WIDTH_B ), + // + // .FAMILY (FAMILY ), + // + // //Titanium extra paramters + // .RST_POLARITY (RST_POLARITY ), + // .RESET_RAM (RESET_RAM ), + // .RESET_OUTREG (RESET_OUTREG ), + // .ADDREN_POLARITY (ADDREN_POLARITY), + // .RESET_ENABLE (RESET_ENABLE ), + // .ADDREN_ENABLE (ADDREN_ENABLE ) + // ) + // spram_inst + // ( + // .clk (clk ), + // .addr (addr ), + // .wclke (wclke ), + // .we (we ), + // .wdata_a(wdata_a), + // .re (re ), + // .rdata_a(rdata_a), + // .reset (reset ), + // .addren (addren ) + // ); + //end + end + else if (MEMORY_TYPE == "SDP_RAM") //Simple Dual Port RAM + begin + + `IP_MODULE_NAME(efx_simple_dual_port_ram) #( + .CLK_POLARITY (CLK_POLARITY ), + .WCLK_POLARITY (WCLK_POLARITY ), + .WCLKE_POLARITY (WCLKE_POLARITY ), + .WE_POLARITY (WE_POLARITY ), + .WRITE_MODE (WRITE_MODE ), + + .RCLK_POLARITY (RCLK_POLARITY ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .BYTEEN_POLARITY (BYTEEN_POLARITY), + .CLK_MODE (CLK_MODE), + .WCLKE_ENABLE (WCLKE_ENABLE ), + .WE_ENABLE (WE_ENABLE ), + .RE_ENABLE (RE_ENABLE ), + .BYTEEN_ENABLE (BYTEEN_ENABLE ), + + .BYTEEN_WIDTH (BYTEEN_WIDTH ), + .ADDR_WIDTH_A (ADDR_WIDTH_A ), + .DATA_WIDTH_A (DATA_WIDTH_A ), + .ADDR_WIDTH_B (ADDR_WIDTH_B ), + .DATA_WIDTH_B (DATA_WIDTH_B ), + + .FAMILY (FAMILY ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .RADDREN_POLARITY (RADDREN_POLARITY), + .WADDREN_POLARITY (WADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .RADDREN_ENABLE (RADDREN_ENABLE ), + .WADDREN_ENABLE (WADDREN_ENABLE) + ) + sdpram_inst + ( + .clk (clk ), + .wclk (wclk ), + .wclke (wclke ), + .byteen (byteen ), + .we (we ), + .waddr (waddr ), + .wdata_a (wdata_a ), + .rclk (rclk ), + .re (re ), + .raddr (raddr ), + .rdata_b (rdata_b ), + .reset (reset ), + .waddren (waddren ), + .raddren (raddren ) + + ); + + end + else if (MEMORY_TYPE == "TDP_RAM") //True Dual Port RAM + begin + + `IP_MODULE_NAME(efx_true_dual_port_ram) #( + + //Trion and Titanium parameters + .CLK_POLARITY (CLK_POLARITY ), + .CLKE_POLARITY (CLKE_POLARITY ), + .CLKA_POLARITY (CLKA_POLARITY ), + .CLKEA_POLARITY (CLKEA_POLARITY ), + .WEA_POLARITY (WEA_POLARITY ), + .WRITE_MODE_A (WRITE_MODE_A ), + .OUTPUT_REG_A (OUTPUT_REG_A ), + .BYTEENA_POLARITY(BYTEENA_POLARITY), + .CLKB_POLARITY (CLKB_POLARITY ), + .CLKEB_POLARITY (CLKEB_POLARITY ), + .WEB_POLARITY (WEB_POLARITY ), + .WRITE_MODE_B (WRITE_MODE_B ), + .OUTPUT_REG_B (OUTPUT_REG_B ), + .BYTEENB_POLARITY(BYTEENB_POLARITY), + + .BYTEEN_WIDTH_A (BYTEEN_WIDTH_A ), + .BYTEEN_WIDTH_B (BYTEEN_WIDTH_B ), + .ADDR_WIDTH_A (ADDR_WIDTH_A ), + .DATA_WIDTH_A (DATA_WIDTH_A ), + .ADDR_WIDTH_B (ADDR_WIDTH_B ), + .DATA_WIDTH_B (DATA_WIDTH_B ), + + .FAMILY (FAMILY ), + + + //Port Enable + .CLK_MODE (CLK_MODE ), + .CLKEA_ENABLE (CLKEA_ENABLE ), + .WEA_ENABLE (WEA_ENABLE ), + .BYTEENA_ENABLE (BYTEENA_ENABLE ), + .CLKEB_ENABLE (CLKEB_ENABLE ), + .WEB_ENABLE (WEB_ENABLE ), + .BYTEENB_ENABLE (BYTEENB_ENABLE ), + + + //Titanium extra paramters + .RSTA_POLARITY (RSTA_POLARITY ), + .RESET_RAM_A (RESET_RAM_A ), + .RESET_OUTREG_A (RESET_OUTREG_A ), + .ADDRENA_POLARITY (ADDRENA_POLARITY ), + .RSTB_POLARITY (RSTB_POLARITY ), + .RESET_RAM_B (RESET_RAM_B ), + .RESET_OUTREG_B (RESET_OUTREG_B ), + .ADDRENB_POLARITY (ADDRENB_POLARITY ), + + //Port Enable + .RESET_A_ENABLE (RESET_A_ENABLE ), + .ADDREN_A_ENABLE (ADDREN_A_ENABLE), + .RESET_B_ENABLE (RESET_B_ENABLE ), + .ADDREN_B_ENABLE (ADDREN_B_ENABLE) + ) + tdpram_inst + ( + .clk (clk ), + .clke (clke ), + .clk_a (clk_a ), + .clke_a (clke_a ), + .we_a (we_a ), + .byteen_a (byteen_a), + .addr_a (addr_a ), + .wdata_a (wdata_a), + .rdata_a (rdata_a), + .clk_b (clk_b ), + .clke_b (clke_b ), + .we_b (we_b ), + .byteen_b (byteen_b), + .addr_b (addr_b ), + .wdata_b (wdata_b), + .rdata_b (rdata_b), + .reset_a (reset_a), + .addren_a (addren_a), + .reset_b (reset_b), + .addren_b (addren_b) + + ); + end + else if (MEMORY_TYPE == "SP_ROM") //Single Port ROM + begin + + `IP_MODULE_NAME(efx_single_port_rom) #( + + .CLK_POLARITY (CLK_POLARITY ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .RE_ENABLE (RE_ENABLE ), + + .BYTEEN_WIDTH (BYTEEN_WIDTH ), + .ADDR_WIDTH_A (ADDR_WIDTH_A ), + .DATA_WIDTH_A (DATA_WIDTH_A ), + .FAMILY (FAMILY ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .ADDREN_POLARITY (ADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .ADDREN_ENABLE (ADDREN_ENABLE ) + + ) + sprom_inst + ( + .clk (clk ), + .addr (addr ), + .re (re ), + .rdata_a (rdata_a), + .reset (reset ), + .addren (addren) + + ); + end + else if (MEMORY_TYPE == "DP_ROM") //Dual Port ROM + begin + + `IP_MODULE_NAME(efx_dual_port_rom) #( + + //Trion and Titanium parameters + .CLK_POLARITY ( CLK_POLARITY ), + .CLKE_POLARITY ( CLKE_POLARITY ), + .CLKA_POLARITY ( CLKA_POLARITY ), + .CLKEA_POLARITY ( CLKEA_POLARITY ), + + .OUTPUT_REG_A ( OUTPUT_REG_A ), + .CLKB_POLARITY ( CLKB_POLARITY ), + .CLKEB_POLARITY ( CLKEB_POLARITY ), + .OUTPUT_REG_B ( OUTPUT_REG_B ), + + + //Port Enable + .CLK_MODE (CLK_MODE ), + .CLKEA_ENABLE (CLKEA_ENABLE ), + .CLKEB_ENABLE (CLKEB_ENABLE ), + + + //Titanium extra paramters + .RSTA_POLARITY (RSTA_POLARITY ), + .RESET_RAM_A (RESET_RAM_A ), + .RESET_OUTREG_A (RESET_OUTREG_A ), + .ADDRENA_POLARITY (ADDRENA_POLARITY ), + .RSTB_POLARITY (RSTB_POLARITY ), + .RESET_RAM_B (RESET_RAM_B ), + .RESET_OUTREG_B (RESET_OUTREG_B ), + .ADDRENB_POLARITY (ADDRENB_POLARITY ), + + //Port Enable + .RESET_A_ENABLE (RESET_A_ENABLE ), + .ADDREN_A_ENABLE (ADDREN_A_ENABLE), + .RESET_B_ENABLE (RESET_B_ENABLE ), + .ADDREN_B_ENABLE (ADDREN_B_ENABLE), + + //DATA and ADDR + .DATA_WIDTH_A (DATA_WIDTH_A), + .DATA_WIDTH_B (DATA_WIDTH_B), + .ADDR_WIDTH_A (ADDR_WIDTH_A), + .ADDR_WIDTH_B (ADDR_WIDTH_B), + .FAMILY (FAMILY) + ) + dprom_inst + ( + .clk (clk ), + .clke (clke ), + .clk_a (clk_a ), + .clke_a (clke_a ), + .addr_a (addr_a ), + .rdata_a (rdata_a), + .clk_b (clk_b ), + .clke_b (clke_b ), + .addr_b (addr_b ), + .rdata_b (rdata_b), + .reset_a (reset_a), + .addren_a (addren_a), + .reset_b (reset_b), + .addren_b (addren_b) + + ); + end +endgenerate + +endmodule + + + + + + + + + + + + + + + + + + + + + + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(dpbram_primitive) #( + parameter FAMILY = "TITANIUM", //0:Trion, 1:Titanium + + //Trion and Titanium parameters + parameter WRITE_WIDTH_A = 8, // write width + parameter CLKA_POLARITY = 1'b1, //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEA_POLARITY = 1'b1, //clke A polarity, 0:active low, 1:active high + parameter WEA_POLARITY = 1'b1, //we A polarity, 0:active low, 1:active high + parameter WRITE_MODE_A = "READ_FIRST",//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter READ_WIDTH_A = 8, // read width A + parameter OUTPUT_REG_A = 1'b1, // Output register enable, 1:add pipe-line read register + + parameter WRITE_WIDTH_B = 8, // write width + parameter CLKB_POLARITY = 1'b1, //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEB_POLARITY = 1'b1, //clke A polarity, 0:active low, 1:active high + parameter WEB_POLARITY = 1'b1, //we A polarity, 0:active low, 1:active high + parameter WRITE_MODE_B = "READ_FIRST",//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter READ_WIDTH_B = 8, // read width A + parameter OUTPUT_REG_B = 1'b0, // Output register enable, 1:add pipe-line read register + + //Titanium extra paramters + parameter RSTA_POLARITY = 1'b1, // rst A polarity + parameter RESET_RAM_A = "ASYNC", // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_A = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENA_POLARITY = 1'b1, // addrena polarity + + parameter RSTB_POLARITY = 1'b1, // rst A polarity + parameter RESET_RAM_B = "ASYNC", // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_B = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENB_POLARITY = 1'b1, // addrenb polarity + + //Titanium Option for byte enable in WEN width = 2 when it is Mode 512x16 or 512x20 + + parameter ini_index = 0 + +) +( +//Trion and Titanium ports + CLKA, // A-port clk + CLKEA, // A-port clk enable + WEA, // A-port write enable + ADDRA, // A-port address input + WDATAA, // A-port write data input + RDATAA, // A-port read address output + + CLKB, // B-port clk + CLKEB, // B-port clk enable + WEB, // B-port write enable + ADDRB, // B-port address input + WDATAB, // B-port write data input + RDATAB, // B-port read address output + + //Titanium extra ports + + RSTA, // A-port reset + ADDRENA, // A-port address enable + + RSTB, // B-port reset + ADDRENB // B-port address enable + + ); +function integer address_map; +input integer index;//Input data width parameter +input integer type_; //Mapped data width, Mapped Address Width for Ram 5K(Trion), Mapped Address Width for Ram 10K(Titanium), WEN width for Ram 5K(Trion), WEN width for Ram 10K(Titanium) +case (index) +0 : address_map= (type_==0)? 1 :(type_==1)? 12 :(type_==2)? 13 :1; +1 : address_map= (type_==0)? 1 :(type_==1)? 12 :(type_==2)? 13 :1; +2 : address_map= (type_==0)? 2 :(type_==1)? 11 :(type_==2)? 12 :1; +3 : address_map= (type_==0)? 4 :(type_==1)? 10 :(type_==2)? 11 :1; +4 : address_map= (type_==0)? 4 :(type_==1)? 10 :(type_==2)? 11 :1; +5 : address_map= (type_==0)? 5 :(type_==1)? 10 :(type_==2)? 11 :1; +6 : address_map= (type_==0)? 8 :(type_==1)? 9 :(type_==2)? 10 :1; +7 : address_map= (type_==0)? 8 :(type_==1)? 9 :(type_==2)? 10 :1; +8 : address_map= (type_==0)? 8 :(type_==1)? 9 :(type_==2)? 10 :1; +9 : address_map= (type_==0)? 10 :(type_==1)? 9 :(type_==2)? 10 :1; +10 : address_map= (type_==0)? 10 :(type_==1)? 9 :(type_==2)? 10 :1; + endcase +endfunction + +localparam WRITE_DATA_WIDTH_A = address_map(WRITE_WIDTH_A,0); +localparam WRITE_ADDRESS_WIDTH_A = address_map(WRITE_WIDTH_A,(FAMILY=="TRION")?1:2); + +localparam WRITE_DATA_WIDTH_B = address_map(WRITE_WIDTH_B,0); +localparam WRITE_ADDRESS_WIDTH_B = address_map(WRITE_WIDTH_B,(FAMILY=="TRION")?1:2); + +//Trion and Titanium ports +input CLKA; // A-port clk +input CLKEA; // A-port clk enable +input [0:0] WEA; // A-port write enable +input [WRITE_ADDRESS_WIDTH_A-1:0] ADDRA; // A-port address input +input [WRITE_DATA_WIDTH_A-1:0] WDATAA; // A-port write data input +output [WRITE_DATA_WIDTH_A-1:0] RDATAA; // A-port read address output + +input CLKB; // B-port clk +input CLKEB; // B-port clk enable +input [0:0] WEB; // B-port write enable +input [WRITE_ADDRESS_WIDTH_B-1:0] ADDRB; // B-port address input +input [WRITE_DATA_WIDTH_B-1:0] WDATAB; // B-port write data input +output [WRITE_DATA_WIDTH_B-1:0] RDATAB; // B-port read address output + + //Titanium extra ports + +input RSTA; // A-port reset +input ADDRENA; // A-port address enable + +input RSTB; // B-port reset +input ADDRENB; // B-port address enable + + +`include "bram_ini.vh" + + generate + if (FAMILY=="TRION") + begin + EFX_DPRAM_5K # ( + .WRITE_WIDTH_A (WRITE_WIDTH_A), + .CLKA_POLARITY (CLKA_POLARITY), // clka polarity + .CLKEA_POLARITY (CLKEA_POLARITY), // clkea polarity + .WEA_POLARITY (WEA_POLARITY), // wea polarity + .WRITE_MODE_A (WRITE_MODE_A), // A-port write mode + + .READ_WIDTH_A (READ_WIDTH_A), // A-port read width + .OUTPUT_REG_A (OUTPUT_REG_A), // A-port output register enable + + + .WRITE_WIDTH_B (WRITE_WIDTH_B), // B-port write width + .CLKB_POLARITY (CLKB_POLARITY), // clkb polarity + .CLKEB_POLARITY(CLKEB_POLARITY), // clkeb polarity + .WEB_POLARITY (WEB_POLARITY), // web polarity + .WRITE_MODE_B (WRITE_MODE_B), // B-port write mode + + .READ_WIDTH_B (READ_WIDTH_B), // B-port read width + .OUTPUT_REG_B (OUTPUT_REG_B), // B-port output register enable + + + .INIT_0 (bram_ini_table(ini_index,16'h0 )), + .INIT_1 (bram_ini_table(ini_index,16'h1 )), + .INIT_2 (bram_ini_table(ini_index,16'h2 )), + .INIT_3 (bram_ini_table(ini_index,16'h3 )), + .INIT_4 (bram_ini_table(ini_index,16'h4 )), + .INIT_5 (bram_ini_table(ini_index,16'h5 )), + .INIT_6 (bram_ini_table(ini_index,16'h6 )), + .INIT_7 (bram_ini_table(ini_index,16'h7 )), + .INIT_8 (bram_ini_table(ini_index,16'h8 )), + .INIT_9 (bram_ini_table(ini_index,16'h9 )), + .INIT_A (bram_ini_table(ini_index,16'hA )), + .INIT_B (bram_ini_table(ini_index,16'hB )), + .INIT_C (bram_ini_table(ini_index,16'hC )), + .INIT_D (bram_ini_table(ini_index,16'hD )), + .INIT_E (bram_ini_table(ini_index,16'hE )), + .INIT_F (bram_ini_table(ini_index,16'hF )), + .INIT_10 (bram_ini_table(ini_index,16'h10)), + .INIT_11 (bram_ini_table(ini_index,16'h11)), + .INIT_12 (bram_ini_table(ini_index,16'h12)), + .INIT_13 (bram_ini_table(ini_index,16'h13)) + ) + dpram5k ( + //Trion and Titanium ports + .CLKA (CLKA), // A-port clk + .CLKEA (CLKEA), // A-port clk enable + .WEA (WEA), // A-port write enable + .ADDRA (ADDRA), // A-port address input + .WDATAA (WDATAA), // A-port write data input + .RDATAA (RDATAA), // A-port read address output + + .CLKB (CLKB), // B-port clk + .CLKEB (CLKEB), // B-port clk enable + .WEB (WEB), // B-port write enable + .ADDRB (ADDRB), // B-port address input + .WDATAB (WDATAB), // B-port write data input + .RDATAB (RDATAB) // B-port read address output + + ); + end + else + begin + + EFX_DPRAM10 # ( + + .WRITE_WIDTH_A (WRITE_WIDTH_A), + .CLKA_POLARITY (CLKA_POLARITY), // clka polarity + .CLKEA_POLARITY (CLKEA_POLARITY), // clkea polarity + .WEA_POLARITY (WEA_POLARITY), // wea polarity + .WRITE_MODE_A (WRITE_MODE_A), // A-port write mode + + .READ_WIDTH_A (READ_WIDTH_A), // A-port read width + .OUTPUT_REG_A (OUTPUT_REG_A), // A-port output register enable + + + .WRITE_WIDTH_B (WRITE_WIDTH_B), // B-port write width + .CLKB_POLARITY (CLKB_POLARITY), // clkb polarity + .CLKEB_POLARITY(CLKEB_POLARITY), // clkeb polarity + .WEB_POLARITY (WEB_POLARITY), // web polarity + .WRITE_MODE_B (WRITE_MODE_B), // B-port write mode + + .READ_WIDTH_B (READ_WIDTH_B), // B-port read width + .OUTPUT_REG_B (OUTPUT_REG_B), // B-port output register enable + + + //Titanium extra paramters + .RSTA_POLARITY (RSTA_POLARITY), // rsta polarity + .RESET_RAM_A (RESET_RAM_A), // A-port reset mode on ram + .RESET_OUTREG_A (RESET_OUTREG_A), // A-port reset mode on output register + .ADDRENA_POLARITY (ADDRENA_POLARITY), // addrena polarity + + .RSTB_POLARITY (RSTB_POLARITY), // rstb polarity + .RESET_RAM_B (RESET_RAM_B), // B-port reset mode on ram + .RESET_OUTREG_B (RESET_OUTREG_B), // B-port reset mode on output register + .ADDRENB_POLARITY (ADDRENB_POLARITY), // addrenb polarity + + + .INIT_0 (bram_ini_table(ini_index, 16'h0 )), + .INIT_1 (bram_ini_table(ini_index, 16'h1 )), + .INIT_2 (bram_ini_table(ini_index, 16'h2 )), + .INIT_3 (bram_ini_table(ini_index, 16'h3 )), + .INIT_4 (bram_ini_table(ini_index, 16'h4 )), + .INIT_5 (bram_ini_table(ini_index, 16'h5 )), + .INIT_6 (bram_ini_table(ini_index, 16'h6 )), + .INIT_7 (bram_ini_table(ini_index, 16'h7 )), + .INIT_8 (bram_ini_table(ini_index, 16'h8 )), + .INIT_9 (bram_ini_table(ini_index, 16'h9 )), + .INIT_A (bram_ini_table(ini_index, 16'hA )), + .INIT_B (bram_ini_table(ini_index, 16'hB )), + .INIT_C (bram_ini_table(ini_index, 16'hC )), + .INIT_D (bram_ini_table(ini_index, 16'hD )), + .INIT_E (bram_ini_table(ini_index, 16'hE )), + .INIT_F (bram_ini_table(ini_index, 16'hF )), + .INIT_10 (bram_ini_table(ini_index, 16'h10)), + .INIT_11 (bram_ini_table(ini_index, 16'h11)), + .INIT_12 (bram_ini_table(ini_index, 16'h12)), + .INIT_13 (bram_ini_table(ini_index, 16'h13)), + .INIT_14 (bram_ini_table(ini_index, 16'h14)), + .INIT_15 (bram_ini_table(ini_index, 16'h15)), + .INIT_16 (bram_ini_table(ini_index, 16'h16)), + .INIT_17 (bram_ini_table(ini_index, 16'h17)), + .INIT_18 (bram_ini_table(ini_index, 16'h18)), + .INIT_19 (bram_ini_table(ini_index, 16'h19)), + .INIT_1A (bram_ini_table(ini_index, 16'h1A)), + .INIT_1B (bram_ini_table(ini_index, 16'h1B)), + .INIT_1C (bram_ini_table(ini_index, 16'h1C)), + .INIT_1D (bram_ini_table(ini_index, 16'h1D)), + .INIT_1E (bram_ini_table(ini_index, 16'h1E)), + .INIT_1F (bram_ini_table(ini_index, 16'h1F)), + .INIT_20 (bram_ini_table(ini_index, 16'h20)), + .INIT_21 (bram_ini_table(ini_index, 16'h21)), + .INIT_22 (bram_ini_table(ini_index, 16'h22)), + .INIT_23 (bram_ini_table(ini_index, 16'h23)), + .INIT_24 (bram_ini_table(ini_index, 16'h24)), + .INIT_25 (bram_ini_table(ini_index, 16'h25)), + .INIT_26 (bram_ini_table(ini_index, 16'h26)), + .INIT_27 (bram_ini_table(ini_index, 16'h27)) + + ) + dpram10k( + //Trion and Titanium ports + .CLKA (CLKA), // A-port clk + .CLKEA (CLKEA), // A-port clk enable + .WEA (WEA), // A-port write enable + .ADDRA (ADDRA), // A-port address input + .WDATAA (WDATAA), // A-port write data input + .RDATAA (RDATAA), // A-port read address output + + .CLKB (CLKB), // B-port clk + .CLKEB (CLKEB), // B-port clk enable + .WEB (WEB), // B-port write enable + .ADDRB (ADDRB), // B-port address input + .WDATAB (WDATAB), // B-port write data input + .RDATAB (RDATAB), // B-port read address output + + + //Titanium extra ports + + .RSTA (RSTA), // A-port reset + .ADDRENA (ADDRENA), // A-port address enable + + .RSTB (RSTB), // B-port reset + .ADDRENB (ADDRENB) // B-port address enable + + + ); + end + endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// Modified on 23 September 2022 +// ******************************* + +module `IP_MODULE_NAME(dpram_wrapper_mwm) #( + //Trion and Titanium parameters + parameter CLKA_POLARITY = 1'b1, //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEA_POLARITY = 1'b1, //clke A polarity, 0:active low, 1:active high + parameter WEA_POLARITY = 1'b1, //we A polarity, 0:active low, 1:active high + parameter WRITE_MODE_A = "READ_FIRST",//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "NO_CHANGE": Previously read data is held. + + parameter OUTPUT_REG_A = 1'b0, // Output register enable, 1:add pipe-line read register + parameter BYTEENA_POLARITY = 1'b1, // byteen polarity 0:active low, 1:active high + + parameter CLKB_POLARITY = 1'b1, //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEB_POLARITY = 1'b1, //clke A polarity, 0:active low, 1:active high + parameter WEB_POLARITY = 1'b1, //we B polarity, 0:active low, 1:active high + parameter WRITE_MODE_B = "READ_FIRST",//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "NO_CHANGE": Previously read data is held. + + parameter OUTPUT_REG_B = 1'b0, // Output register enable, 1:add pipe-line read register + parameter BYTEENB_POLARITY = 1'b1, // byteen polarity 0:active low, 1:active high + + //Titanium extra paramters + parameter RSTA_POLARITY = 1'b1, // rst A polarity + parameter RESET_RAM_A = "ASYNC", // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_A = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENA_POLARITY = 1'b1, // addrena polarity + + parameter RSTB_POLARITY = 1'b1, // rst A polarity + parameter RESET_RAM_B = "ASYNC", // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_B = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENB_POLARITY = 1'b1, // addrenb polarity + + parameter DATA_WIDTH_A = 16, + parameter DATA_WIDTH_B = 16, + parameter ADDR_WIDTH_A = 4, + parameter ADDR_WIDTH_B = 4, + parameter BYTEEN_WIDTH_A = 2, + parameter BYTEEN_WIDTH_B = 2, + parameter FAMILY = "TITANIUM" + + + //Titanium Option for byte enable in WEN width = 2 when it is Mode 512x16 or 512x20 +) +( + //Trion and Titanium ports + clk_a, // A-port clk + clke_a, // A-port clk enable + byteen_a, // A-port Byteen input + we_a, // A-port write enable + addr_a, // A-port address input + wdata_a, // A-port write data input + rdata_a, // A-port read address output + + clk_b, // B-port clk + clke_b, // B-port clk enable + byteen_b, // B-port Byteen input + we_b, // B-port write enable + addr_b, // B-port address input + wdata_b, // B-port write data input + rdata_b, // B-port read address output + + //Titanium extra ports + reset_a, // A-port reset + addren_a, // A-port address enable + + reset_b, // B-port reset + addren_b // B-port address enable + + ); + +`include "bram_decompose.vh" +//`include "bram_feature.vh" + +input clk_a; +input clke_a; +input we_a; +input [BYTEEN_WIDTH_A-1:0] byteen_a; +input [ADDR_WIDTH_A-1:0 ] addr_a; +input [DATA_WIDTH_A-1:0 ] wdata_a; +output [DATA_WIDTH_A-1:0 ]rdata_a; + +input clk_b; +input clke_b; +input we_b; +input [BYTEEN_WIDTH_B-1:0] byteen_b; +input [ADDR_WIDTH_B-1:0 ] addr_b; +input [DATA_WIDTH_B-1:0 ] wdata_b; +output [DATA_WIDTH_B-1:0 ]rdata_b; + +input reset_a; +input addren_a; + +input reset_b; +input addren_b; + + +localparam MAP_ADDR_WIDTH_A = (address_mapping_table_A_size!=0)?address_mapping_table_A_size:ADDR_WIDTH_A; +localparam MAP_ADDR_WIDTH_B = (address_mapping_table_B_size!=0)?address_mapping_table_B_size:ADDR_WIDTH_B; + + + +wire [MAP_ADDR_WIDTH_A-1:0 ] w_addr_map_a; +wire [DATA_WIDTH_A-1:0 ] w_wdata_map_a; +wire [DATA_WIDTH_A-1:0 ] w_rdata_map_a; + +wire [MAP_ADDR_WIDTH_B-1:0 ] w_addr_map_b; +wire [DATA_WIDTH_B-1:0 ] w_wdata_map_b; +wire [DATA_WIDTH_B-1:0 ] w_rdata_map_b; + +wire clk_a_i; +wire clk_b_i; +assign clk_a_i = clk_a ~^ CLKA_POLARITY; +assign clk_b_i = clk_b ~^ CLKB_POLARITY; + +function integer get_current_row_index; +input integer row;//Mode type +integer x; + begin + get_current_row_index = 0; + for (x=0; x1) + begin + assign w_we_a[1] = ( (we_a == WEA_POLARITY) & wen_decode_a[WRSEL_INDEX_A] & (byteen_a[BYTEEN_INDEX_A] == BYTEENA_POLARITY) ) ? WEA_POLARITY: !WEA_POLARITY; + end + + assign w_we_b[0] = ( (we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY) ) ? WEB_POLARITY: !WEB_POLARITY; + if ( WEN_WIDTH_ROW_B >1) + begin + assign w_we_b[1] =((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY) )? WEB_POLARITY: !WEB_POLARITY ; + end + + `IP_MODULE_NAME(dpbram_primitive) #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH_A(DATA_WIDTH_ROW_A), + .READ_WIDTH_A(DATA_WIDTH_ROW_A), + + .CLKA_POLARITY(CLKA_POLARITY), + .CLKEA_POLARITY(CLKEA_POLARITY), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + .OUTPUT_REG_A(OUTPUT_REG_A), + + .WRITE_WIDTH_B(DATA_WIDTH_ROW_B), + .READ_WIDTH_B(DATA_WIDTH_ROW_B), + + .CLKB_POLARITY(CLKB_POLARITY), + .CLKEB_POLARITY(CLKEB_POLARITY), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + .OUTPUT_REG_B(OUTPUT_REG_B), + + .ini_index(DATA_MAP_INDEX), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY) + + + + ) bram ( + //Trion and Titanium ports + .CLKA (clk_a), // A-port clk + .CLKEA (clke_a), // A-port clk enable + .WEA (w_we_a), // A-port write enable + .ADDRA (w_addr_a), // A-port address input + .WDATAA(w_wdata_a), // A-port write data input + .RDATAA(w_rdata_a), // A-port read address output + + .CLKB (clk_b), // B-port clk + .CLKEB (clke_b), // B-port clk enable + .WEB (w_we_b), // B-port write enable + .ADDRB (w_addr_b), // B-port address input + .WDATAB(w_wdata_b), // B-port write data input + .RDATAB(w_rdata_b), // B-port read address output + + //Titanium extra ports + + .RSTA (reset_a), // A-port reset + .ADDRENA(addren_a), // A-port address enable + + .RSTB(reset_b), // B-port reset + .ADDRENB(addren_b) // B-port address enable + ); + end + end + + end + else if (bram_table_loop_mode == 1 ) + begin:scan_row + for (gen_y=0; gen_y ADDR_WIDTH_A )? ADDR_WIDTH_A:ADDR_WIDTH_ROW_A; + + + localparam ADDR_WIDTH_ROW_B = bram_feature_table(bram_mode_b,0); + localparam DATA_WIDTH_ROW_B = bram_feature_table(bram_mode_b,1); + localparam WEN_WIDTH_ROW_B = bram_feature_table(bram_mode_b,2); + localparam ADDR_WIDTH_ROW_MAP_B = (ADDR_WIDTH_ROW_B > ADDR_WIDTH_B )? ADDR_WIDTH_B:ADDR_WIDTH_ROW_B; + + + + localparam START_ROW_INDEX = get_current_row_index(gen_y); + + + for (gen_x=0; gen_x1) + begin + assign w_we_a[1] = ((we_a == WEA_POLARITY) & wen_decode_a[WRSEL_INDEX_A] & (byteen_a[BYTEEN_INDEX_A] == BYTEENA_POLARITY) ) ? WEA_POLARITY: !WEA_POLARITY; + end + + assign w_we_b[0] = ((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY)) ? WEB_POLARITY: !WEB_POLARITY; + if ( WEN_WIDTH_ROW_B >1) + begin + assign w_we_b[1] = ((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY)) ? WEB_POLARITY : !WEB_POLARITY; + end + + `IP_MODULE_NAME(dpbram_primitive) #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH_A(DATA_WIDTH_ROW_A), + .READ_WIDTH_A(DATA_WIDTH_ROW_A), + + .CLKA_POLARITY(CLKA_POLARITY), + .CLKEA_POLARITY(CLKEA_POLARITY), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + .OUTPUT_REG_A(OUTPUT_REG_A), + + .WRITE_WIDTH_B(DATA_WIDTH_ROW_B), + .READ_WIDTH_B(DATA_WIDTH_ROW_B), + + .CLKB_POLARITY(CLKB_POLARITY), + .CLKEB_POLARITY(CLKEB_POLARITY), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + .OUTPUT_REG_B(OUTPUT_REG_B), + + .ini_index(DATA_MAP_INDEX), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY) + + + ) bram ( + //Trion and Titanium ports + .CLKA (clk_a), // A-port clk + .CLKEA (clke_a), // A-port clk enable + .WEA (w_we_a), // A-port write enable + .ADDRA (w_addr_a), // A-port address input + .WDATAA(w_wdata_a), // A-port write data input + .RDATAA(w_rdata_a), // A-port read address output + + .CLKB (clk_b), // B-port clk + .CLKEB (clke_b), // B-port clk enable + .WEB (w_we_b), // B-port write enable + .ADDRB (w_addr_b), // B-port address input + .WDATAB(w_wdata_b), // B-port write data input + .RDATAB(w_rdata_b), // B-port read address output + + //Titanium extra ports + + .RSTA (reset_a), // A-port reset + .ADDRENA(addren_a), // A-port address enable + + .RSTB(reset_b), // B-port reset + .ADDRENB(addren_b) // B-port address enable + ); + + + + end + end + + end + endgenerate + + +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_true_dual_port_ram) ( + //Trion and Titanium ports + clk, // clock input for one clock mode + clke, // clk enable + + clk_a, // A-port clk + clke_a, // A-port clk enable + byteen_a, // A-port Byteen input + we_a, // A-port write enable + addr_a, // A-port address input + wdata_a, // A-port write data input + rdata_a, // A-port read address output + + clk_b, // B-port clk + clke_b, // B-port clk enable + byteen_b, // B-port Byteen input + we_b, // B-port write enable + addr_b, // B-port address input + wdata_b, // B-port write data input + rdata_b, // B-port read address output + + //Titanium extra ports + reset_a, // A-port reset + addren_a, // A-port address enable + + reset_b, // B-port reset + addren_b // B-port address enable + + ); + +//`include "bram_decompose.vh" + +//Trion and Titanium parameters +parameter CLK_POLARITY = 1'b1; //clk polarity for one clk mode; 0:falling edge; 1:rising edge +parameter CLKE_POLARITY = 1'b1; //clke polarity for one clk mode; 0:active low; 1:active high + +parameter CLKA_POLARITY = 1'b1; //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEA_POLARITY = 1'b1; //clke A polarity; 0:active low; 1:active high +parameter WEA_POLARITY = 1'b1; //we A polarity; 0:active low; 1:active high + +parameter OUTPUT_REG_A = 1'b0; // Output register enable; 1:add pipe-line read register +parameter BYTEENA_POLARITY = 1'b1; // byteen polarity 0:active low; 1:active high + +parameter CLKB_POLARITY = 1'b1; //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEB_POLARITY = 1'b1; //clke A polarity; 0:active low; 1:active high +parameter WEB_POLARITY = 1'b1; //we B polarity; 0:active low; 1:active high + +parameter OUTPUT_REG_B = 1'b0; // Output register enable; 1:add pipe-line read register +parameter BYTEENB_POLARITY = 1'b1; // byteen polarity 0:active low; 1:active high + + +//Port Enable +parameter CLK_MODE = 2; //1: ONE CLK Mode; CLK pin will provide the clock source to the memory + //2: TWO CLK Mode; clk_a and clk_b +parameter CLKEA_ENABLE = 1'b1; //1: Enalbe the port for clke_a pin ; 0: dislable +parameter WEA_ENABLE = 1'b1; //1: Enable the port for we_a pin ; 0: disable +parameter BYTEENA_ENABLE = 1'b1; //1: Enable the port for Byteen_a pins ; 0: disable + +parameter CLKEB_ENABLE = 1'b1; //1: Enalbe the port for clke_b pin ; 0: dislable +parameter WEB_ENABLE = 1'b1; //1: Enable the port for we_b pin ; 0: disable +parameter BYTEENB_ENABLE = 1'b1; //1: Enable the port for Byteen_b pins ; 0: disable + + +//Titanium extra paramters +parameter RSTA_POLARITY = 1'b1; // rst A polarity +parameter RESET_RAM_A = "ASYNC"; // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_A = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENA_POLARITY = 1'b1; // addrena polarity + +parameter RSTB_POLARITY = 1'b1; // rst A polarity +parameter RESET_RAM_B = "ASYNC"; // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_B = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENB_POLARITY = 1'b1; // addrenb polarity + +//Port Enable +parameter RESET_A_ENABLE = 1'b1; //1: Enable the port for reset_a pin ; 0: disable +parameter ADDREN_A_ENABLE = 1'b1; //1: Enable the port for addren_a pin ; 0: disable + +parameter RESET_B_ENABLE = 1'b1; //1: Enable the port for reset_b pin ; 0: disable +parameter ADDREN_B_ENABLE = 1'b1; //1: Enable the port for addren_b pin ; 0: disable + +parameter WRITE_MODE_A = "READ_FIRST"; +parameter WRITE_MODE_B = "READ_FIRST"; +parameter DATA_WIDTH_A = 16; +parameter DATA_WIDTH_B = 16; +parameter ADDR_WIDTH_A = 4; +parameter ADDR_WIDTH_B = 4; +parameter BYTEEN_WIDTH_A = 2; +parameter BYTEEN_WIDTH_B = 2; +parameter FAMILY = "TITANIUM"; + +//Trion and Titanium ports +input clk; +input clke; + +input clk_a; +input clke_a; +input we_a; +input [BYTEEN_WIDTH_A-1:0] byteen_a; +input [ADDR_WIDTH_A-1:0 ] addr_a; +input [DATA_WIDTH_A-1:0 ] wdata_a; +output [DATA_WIDTH_A-1:0 ]rdata_a; + +input clk_b; +input clke_b; +input we_b; +input [BYTEEN_WIDTH_B-1:0] byteen_b; +input [ADDR_WIDTH_B-1:0 ] addr_b; +input [DATA_WIDTH_B-1:0 ] wdata_b; +output [DATA_WIDTH_B-1:0 ]rdata_b; + +//Titanium extra ports +input reset_a; +input addren_a; + +input reset_b; +input addren_b; + +////////////////// wires ////////////////// +wire w_clk_a; +wire w_clke_a; +wire [BYTEEN_WIDTH_A-1:0] w_byteen_a; +wire w_we_a; + +wire w_clk_b; +wire w_clke_b; +wire [BYTEEN_WIDTH_B-1:0] w_byteen_b; +wire w_we_b; + +wire w_reset_a; +wire w_addren_a; + +wire w_reset_b; +wire w_addren_b; + + +assign w_clk_a = (CLK_MODE==2) ? clk_a : clk; +assign w_clke_a = (CLKEA_ENABLE==1) ? ((CLK_MODE==2) ? clke_a : clke) : CLKEA_POLARITY; +assign w_byteen_a = (BYTEENA_ENABLE==1)? byteen_a : {BYTEEN_WIDTH_A{BYTEENA_POLARITY}}; +assign w_we_a = (WEA_ENABLE==1) ? we_a : WEA_POLARITY; + +assign w_clk_b = (CLK_MODE==2) ? clk_b : clk; +assign w_clke_b = (CLKEB_ENABLE==1) ? ((CLK_MODE==2) ? clke_b : clke) : CLKEB_POLARITY; +assign w_byteen_b = (BYTEENB_ENABLE==1)? byteen_b : {BYTEEN_WIDTH_B{BYTEENB_POLARITY}}; +assign w_we_b = (WEB_ENABLE==1) ? we_b : WEB_POLARITY; + + +//Titanium extra ports +assign w_reset_a = (RESET_A_ENABLE==1) ? reset_a : (RSTA_POLARITY==1'b1) ? 1'b0: 1'b1; +assign w_addren_a = (ADDREN_A_ENABLE==1) ? addren_a : ADDRENA_POLARITY; + +assign w_reset_b = (RESET_B_ENABLE==1) ? reset_b : (RSTB_POLARITY==1'b1) ? 1'b0: 1'b1; +assign w_addren_b = (ADDREN_B_ENABLE==1) ? addren_b : ADDRENB_POLARITY; + + +localparam CLKA_POLARITY_LC = (CLK_MODE==2) ? CLKA_POLARITY : CLK_POLARITY; +localparam CLKB_POLARITY_LC = (CLK_MODE==2) ? CLKB_POLARITY : CLK_POLARITY; + +localparam CLKEA_POLARITY_LC = (CLK_MODE==2) ? CLKEA_POLARITY : CLKE_POLARITY; +localparam CLKEB_POLARITY_LC = (CLK_MODE==2) ? CLKEB_POLARITY : CLKE_POLARITY; + + `IP_MODULE_NAME(dpram_wrapper_mwm) #( + //Trion and Titanium parameters + .CLKA_POLARITY(CLKA_POLARITY_LC), + .CLKEA_POLARITY(CLKEA_POLARITY_LC), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + + .OUTPUT_REG_A(OUTPUT_REG_A), + .BYTEENA_POLARITY(BYTEENA_POLARITY), + + .CLKB_POLARITY(CLKB_POLARITY_LC), + .CLKEB_POLARITY(CLKEB_POLARITY_LC), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + + .OUTPUT_REG_B(OUTPUT_REG_B), + .BYTEENB_POLARITY(BYTEENB_POLARITY), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY), + + .DATA_WIDTH_A(DATA_WIDTH_A), + .DATA_WIDTH_B(DATA_WIDTH_B), + .ADDR_WIDTH_A(ADDR_WIDTH_A), + .ADDR_WIDTH_B(ADDR_WIDTH_B), + .BYTEEN_WIDTH_A(BYTEEN_WIDTH_A), + .BYTEEN_WIDTH_B(BYTEEN_WIDTH_B), + + .FAMILY(FAMILY) + + + ) brams ( + //Trion and Titanium ports + .clk_a(w_clk_a), + .clke_a(w_clke_a), + .byteen_a(w_byteen_a), + .we_a(w_we_a), + .addr_a(addr_a), + .wdata_a(wdata_a), + .rdata_a(rdata_a), + + .clk_b(w_clk_b), + .clke_b(w_clke_b), + .byteen_b(w_byteen_b), + .we_b(w_we_b), + .addr_b(addr_b), + .wdata_b(wdata_b), + .rdata_b(rdata_b), + + //Titanium extra ports + .reset_a(w_reset_a), + .addren_a(w_addren_a), + .reset_b(w_reset_b), + .addren_b(w_addren_b) + + ); + + + +endmodule +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/my_bram_ip_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/my_bram_ip_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..f7e5ae0550c31f2dda23480dde3443f9bd41c78c --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/my_bram_ip_define.vh @@ -0,0 +1,114 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam ADDR_WIDTH_A = 11; +localparam ADDR_WIDTH_B = 11; +localparam RESET_A_ENABLE = 0; +localparam RESET_B_ENABLE = 0; +localparam RSTA_POLARITY = 1; +localparam RSTB_POLARITY = 1; +localparam FAMILY = "TITANIUM"; +localparam MEMORY_MODE = "SPEED"; +localparam WRITE_MODE_A = "READ_FIRST"; +localparam WRITE_MODE_B = "READ_FIRST"; +localparam OUTPUT_REG_A = 0; +localparam OUTPUT_REG_B = 0; +localparam MEMORY_TYPE = "TDP_RAM"; +localparam GROUP_DATA_WIDTH_B = 8; +localparam BYTEENA_ENABLE = 0; +localparam BYTEENB_ENABLE = 0; +localparam BYTEENA_POLARITY = 1; +localparam BYTEENB_POLARITY = 1; +localparam BYTEEN_WIDTH_A = 1; +localparam BYTEEN_WIDTH_B = 1; +localparam BYTEEN_ENABLE = 0; +localparam BYTEEN_POLARITY = 1; +localparam GROUP_DATA_WIDTH = 8; +localparam BYTEEN_WIDTH = 1; +localparam WIDTH_RATIO = 4; +localparam GROUP_DATA_WIDTH_A = 8; +localparam DATA_WIDTH_A = 8; +localparam DATA_WIDTH_B = 8; +localparam ADDREN_ENABLE = 1; +localparam ADDREN_POLARITY = 1; +localparam CLK_MODE = 2; +localparam CLKA_POLARITY = 1; +localparam CLKB_POLARITY = 1; +localparam CLKE_POLARITY = 1; +localparam CLKEA_POLARITY = 1; +localparam CLKEA_ENABLE = 0; +localparam RESET_OUTREG_A = "ASYNC"; +localparam RESET_OUTREG_B = "ASYNC"; +localparam RESET_RAM_B = "ASYNC"; +localparam WEA_ENABLE = 1; +localparam WEA_POLARITY = 1; +localparam WEB_ENABLE = 1; +localparam WEB_POLARITY = 1; +localparam RADDREN_ENABLE = 1; +localparam RADDREN_POLARITY = 1; +localparam WADDREN_ENABLE = 1; +localparam WADDREN_POLARITY = 1; +localparam RCLK_POLARITY = 1; +localparam ADDREN_A_ENABLE = 0; +localparam ADDREN_B_ENABLE = 0; +localparam ADDRENA_POLARITY = 1; +localparam ADDRENB_POLARITY = 1; +localparam WE_ENABLE = 1; +localparam WE_POLARITY = 1; +localparam WCLKE_ENABLE = 1; +localparam WCLKE_POLARITY = 1; +localparam WCLK_POLARITY = 1; +localparam RESET_RAM_A = "ASYNC"; +localparam RESET_RAM = "ASYNC"; +localparam CLK_POLARITY = 1; +localparam OUTPUT_REG = 0; +localparam RE_POLARITY = 1; +localparam RE_ENABLE = 1; +localparam WRITE_MODE = "READ_FIRST"; +localparam RESET_OUTREG = "ASYNC"; +localparam RESET_ENABLE = 1; +localparam RST_POLARITY = 1; +localparam CLKEB_POLARITY = 1; +localparam CLKEB_ENABLE = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/reset.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/reset.v new file mode 100644 index 0000000000000000000000000000000000000000..db7ee8d9308129b57e029d1364626aaedfb7b316 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/reset.v @@ -0,0 +1,213 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// Description: +// System Reset Control +// +// Language: Verilog 2001 +// +// ------------------------------------------------------------------------------ +///////////////////////////////////////////////////////////////////////////////// + +module reset_ctrl +#( + parameter NUM_RST = 1, + parameter CYCLE = 1, + parameter IN_RST_ACTIVE = 1'b1, + parameter OUT_RST_ACTIVE = 1'b1 +) +( + input [NUM_RST-1:0] i_arst, + input [NUM_RST-1:0] i_clk, + output [NUM_RST-1:0] o_srst +); + +genvar i; +generate + for (i=0; i1) ? BYTEEN_WIDTH: 2; + +localparam TEST_PATTERN_WD_WIDTH = ((WDATA_WIDTH/BYTEEN_WIDTH)1) ? (WDATA_WIDTH/BYTEEN_WIDTH): WADDR_WIDTH : WADDR_WIDTH; +localparam TEST_PATTERN_RD_WIDTH = ((RDATA_WIDTH/BYTEEN_WIDTH)1) ? (RDATA_WIDTH/BYTEEN_WIDTH): RADDR_WIDTH : RADDR_WIDTH; + +input clk; + +input reset; +input start_in; +input rd_start_in; +output reg we; +output reg [WADDR_WIDTH-1:0] waddr; +output reg [WDATA_WIDTH-1:0] wdata; +output [BYTEEN_WIDTH_-1:0]byteen; + +output reg re; +output reg [RADDR_WIDTH-1:0] raddr; +input wire [RDATA_WIDTH-1:0] rdata; + +output [3:0] state; +output reg compare; + +reg [WADDR_WIDTH-1:0] r_wcount; +reg [RADDR_WIDTH-1:0] r_rcount; + +reg [BYTEEN_WIDTH_-1:0] r_shiftbyte; + + +reg [RADDR_WIDTH-1:0] r_rcount_1P; +reg [RADDR_WIDTH-1:0] r_rcount_2P; +reg [RADDR_WIDTH-1:0] r_rcount_3P; + + + +reg r_start_in_1P; +reg r_start_in_2P; + +reg r_rd_start_in_1P; +reg r_rd_start_in_2P; + +reg r_re_1p; +reg r_re_2p; + + +reg [3:0] test_state; + +reg [BYTEEN_WIDTH_-1:0] r_byteen; + +reg [RDATA_WIDTH-1:0] r_rdata_1P; + +assign state = test_state; + +localparam STATE_IDLE = 4'd0; +localparam STATE_START = 4'd1; +localparam STATE_WE_START = 4'd2; +localparam STATE_WE = 4'd3; +localparam STATE_WE_END = 4'd4; +localparam STATE_RE_START = 4'd5; +localparam STATE_RE = 4'd6; +localparam STATE_RE_EXTRA = 4'd7; + +localparam STATE_RE_END = 4'd8; + + + +localparam FIRST_ACCESS = (TEST_PATTERN=="READ")?STATE_RE_START:(TEST_PATTERN=="WriteRead")?STATE_WE_START:STATE_WE_START; + +assign byteen = (TEST_BYTEEN==0)? {BYTEEN_WIDTH_{1'b1}} : (BYTEEN_WIDTH >1)?r_byteen:2'b11; + +localparam COMPARE_WIDTH = (RADDR_WIDTH>=RDATA_WIDTH)?RDATA_WIDTH: RADDR_WIDTH; + +localparam DATA_MULTI_W = (WDATA_WIDTH<=TEST_PATTERN_WD_WIDTH) ?1: (WDATA_WIDTH/TEST_PATTERN_WD_WIDTH)+1; +localparam DATA_MULTI_R = (RDATA_WIDTH<=TEST_PATTERN_RD_WIDTH) ?1: (RDATA_WIDTH/TEST_PATTERN_RD_WIDTH)+1; + +always@(posedge clk or posedge reset) +begin + if(reset) + begin + + test_state <= STATE_IDLE; + + r_start_in_1P <= 1'b0; + r_start_in_2P <= 1'b0; + + r_rd_start_in_1P <= 1'b0; + r_rd_start_in_2P <= 1'b0; + + + r_wcount <= {WADDR_WIDTH{1'b0}}; + r_rcount <= {RADDR_WIDTH{1'b0}}; + r_shiftbyte <= {BYTEEN_WIDTH_{1'b0}}; + + r_rdata_1P <= {RDATA_WIDTH{1'b0}}; + + + end + else + begin + + r_start_in_1P <= start_in; + r_start_in_2P <= r_start_in_1P; + + r_rd_start_in_1P <= rd_start_in; + r_rd_start_in_2P <= r_rd_start_in_1P; + + r_rdata_1P <= rdata; + + case (test_state) + STATE_IDLE : + begin + if (r_start_in_1P & ~r_start_in_2P) + begin + test_state <= STATE_START; + end + else if (r_rd_start_in_1P & ~r_rd_start_in_2P) + begin + test_state <= STATE_RE_START; + end + end + STATE_START : + begin + test_state <= FIRST_ACCESS; //STATE_RE_START;//STATE_WE_START; + end + STATE_WE_START: + begin + r_wcount <= {WADDR_WIDTH{1'b0}}; + r_shiftbyte <= 1'b1; + test_state <= STATE_WE; + end + STATE_WE: + begin + if (r_wcount == (TEST_WRITE_COUNT-1)) + begin + test_state <= STATE_WE_END; + end + else + begin + r_wcount <= r_wcount+1'b1; + test_state <= STATE_WE; + end + + r_shiftbyte <= {r_shiftbyte[BYTEEN_WIDTH_-2:0], r_shiftbyte[BYTEEN_WIDTH_-1]}; + + end + STATE_WE_END : + begin + test_state <= STATE_RE_START; + end + STATE_RE_START : + begin + r_rcount <= {WADDR_WIDTH{1'b0}}; + test_state <= STATE_RE; + end + STATE_RE: + begin + if (r_rcount == (TEST_READ_COUNT-1)) + begin + if (OUTPUT_REG == 1'b0) + begin + test_state <= STATE_RE_END; + end + else + begin + test_state <= STATE_RE_EXTRA; + end + end + else + begin + r_rcount <= r_rcount+1'b1; + test_state <= STATE_RE; + end + end + STATE_RE_EXTRA: + begin + test_state <= STATE_RE_END; + end + STATE_RE_END : + begin + test_state <= STATE_IDLE; + end + + endcase + + end + +end + + +always@(posedge clk or posedge reset) +begin + if(reset) + begin + + we <= ~WE_POLARITY; + waddr <= {WADDR_WIDTH{1'b0}}; + wdata <= {WDATA_WIDTH{1'b0}}; + r_byteen<= {BYTEEN_WIDTH_{1'b0}}; + + re <= ~RE_POLARITY; + raddr <= {RADDR_WIDTH{1'b0}}; + compare <= 1'b0; + + r_rcount_1P <= {RADDR_WIDTH{1'b0}}; + r_rcount_2P <= {RADDR_WIDTH{1'b0}}; + r_rcount_3P <= {RADDR_WIDTH{1'b0}}; + + r_re_1p <= 1'b0; + r_re_2p <= 1'b0; + + end + else + begin + + r_rcount_1P <= r_rcount; + r_rcount_2P <= r_rcount_1P; + r_rcount_3P <= r_rcount_2P; + + r_re_1p <= re; + r_re_2p <= r_re_1p; + + if(test_state == STATE_WE) + begin + we <= WE_POLARITY; + waddr <= r_wcount; + // wdata <= {DATA_MULTI_W{r_wcount[TEST_PATTERN_WD_WIDTH-1:0]}}; + wdata <= (GROUP_DATA==0)? r_wcount : ({(WDATA_WIDTH/WADDR_WIDTH){r_wcount[WADDR_WIDTH-1:0]}}); + r_byteen <= r_shiftbyte; + re <= ~RE_POLARITY; + raddr <= r_rcount; + + compare <= 1'b0; + + + end + else if((test_state == STATE_RE)||(test_state == STATE_RE_EXTRA)) + begin + we <= ~WE_POLARITY; + waddr <= r_rcount; + wdata <= {WDATA_WIDTH{1'b0}}; + r_byteen<= {BYTEEN_WIDTH_{1'b0}}; + + re <= RE_POLARITY; + raddr <= r_rcount; + end + else + begin + we <= ~WE_POLARITY; + waddr <= {WADDR_WIDTH{1'b0}}; + wdata <= {WDATA_WIDTH{1'b0}}; + r_byteen<= {BYTEEN_WIDTH_{1'b0}}; + + + re <= ~RE_POLARITY; + raddr <= {RADDR_WIDTH{1'b0}}; + + compare <= 1'b0; + end + + + + if (OUTPUT_REG == 1'b0) + begin + if (r_re_1p== RE_POLARITY) + begin + + //if( rdata == {DATA_MULTI_R{r_rcount_2P[TEST_PATTERN_RD_WIDTH-1:0]}} ) + if(r_rcount_2P[COMPARE_WIDTH-1:0] == rdata[COMPARE_WIDTH-1:0]) + begin + compare <= 1'b0; + end + else + begin + compare <= 1'b1; + + end + end + end + else + begin + if (r_re_2p== RE_POLARITY) + begin + + //if( rdata == {DATA_MULTI_R{r_rcount_2P[TEST_PATTERN_RD_WIDTH-1:0]}} ) + if(r_rcount_3P[COMPARE_WIDTH-1:0] == rdata[COMPARE_WIDTH-1:0]) + begin + compare <= 1'b0; + end + else + begin + compare <= 1'b1; + + end + end + + end + end + +end + + + +endmodule \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/write_pattern.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/write_pattern.v new file mode 100644 index 0000000000000000000000000000000000000000..8f42734cd28d405ad8150840207a8d785d542ab9 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/T120F576_devkit/write_pattern.v @@ -0,0 +1,132 @@ +module write_pattern #( +//Trion and Titanium parameters + parameter ADDR_WIDTH = 14, + parameter DATA_WIDTH = 32, + parameter PATTERN_COUNT = 100, + parameter WE_POLARITY = 1'b1 +) +( + //Trion and Titanium ports + clk, // clock input for one clock mode + + reset, + + start_in, + + we, // write enale output + addr, // Write address output + data, // Write data output + + start_out, + end_out + + ); + +function integer log2; + input integer val; + integer i; + begin + log2 = 0; + for (i=0; 2**i> 1; + end + get_rand_en = temp[0]; + end +endfunction + +function [BYTEEN_WIDTH-1:0] get_rand_byteen(input integer dummy); + reg [BYTEEN_WIDTH-1:0] temp; + integer i; + begin + temp = {BYTEEN_WIDTH{1'b0}}; + for(i=0 ; i 5) begin + sim_end <= 1; + end else begin + read_cnt <= read_cnt + 1; + end + end + + TEST_READOUT: begin + clke <= 0; + + if (read_cnt == (1< 1024x8 +// 4 --> 2048x4 +// 2 --> 4096x2 +// 1 --> 8192x1 +// 10 --> 1024x10 +// 5 --> 2048x5 +// Reading and Writing can be in different WIDTHs +// +// Writing can be done in one of three WRITE MODEs +// READ_FIRST +// WRITE_FIRST +// NO_CHANGE +// +// Behavior is undefined when +// reading / writing the same address +// TODO: Need to add address collision checking! +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// ******************************* +///////////////////////////////////////////////////////////////////////////// + +module EFX_DPRAM10 +( + CLKA, WEA, CLKEA, RSTA, ADDRENA, WDATAA, ADDRA, RDATAA, + CLKB, WEB, CLKEB, RSTB, ADDRENB, WDATAB, ADDRB, RDATAB +); + + + parameter [0:0] CLKA_POLARITY = 1'b1; + parameter [0:0] CLKEA_POLARITY = 1'b1; + parameter [0:0] WEA_POLARITY = 1'b1; + parameter [0:0] ADDRENA_POLARITY = 1'b1; + parameter [0:0] RSTA_POLARITY = 1'b1; + parameter [0:0] CLKB_POLARITY = 1'b1; + parameter [0:0] CLKEB_POLARITY = 1'b1; + parameter [0:0] WEB_POLARITY = 1'b1; + parameter [0:0] ADDRENB_POLARITY = 1'b1; + parameter [0:0] RSTB_POLARITY = 1'b1; + // Need to add all the data & address input polarity inversion parameters + parameter READ_WIDTH_A = 8; + parameter WRITE_WIDTH_A = 8; + parameter READ_WIDTH_B = 8; + parameter WRITE_WIDTH_B = 8; + parameter OUTPUT_REG_A = 1'b0; + parameter OUTPUT_REG_B = 1'b0; + parameter WRITE_MODE_A = "READ_FIRST"; + parameter WRITE_MODE_B = "READ_FIRST"; + parameter RESET_RAM_A = "ASYNC"; + parameter RESET_OUTREG_A = "ASYNC"; + parameter RESET_RAM_B = "ASYNC"; + parameter RESET_OUTREG_B = "ASYNC"; + parameter [255:0] INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + localparam READ_AWIDTH_A = + (READ_WIDTH_A == 1) ? 13 : + (READ_WIDTH_A == 2) ? 12 : + (READ_WIDTH_A == 4) ? 11 : + (READ_WIDTH_A == 5) ? 11 : + (READ_WIDTH_A == 8) ? 10 : + (READ_WIDTH_A == 10) ? 10 :-1; + + localparam WRITE_AWIDTH_A = + (WRITE_WIDTH_A == 1) ? 13 : + (WRITE_WIDTH_A == 2) ? 12 : + (WRITE_WIDTH_A == 4) ? 11 : + (WRITE_WIDTH_A == 5) ? 11 : + (WRITE_WIDTH_A == 8) ? 10 : + (WRITE_WIDTH_A == 10) ? 10 :-1; + + // Greater of Read and Write widths defines input size + localparam AWIDTH_A = (READ_AWIDTH_A > WRITE_AWIDTH_A) ? READ_AWIDTH_A : WRITE_AWIDTH_A; + localparam DWIDTH_A = (READ_WIDTH_A > WRITE_WIDTH_A) ? WRITE_WIDTH_A : READ_WIDTH_A; + + localparam READ_AWIDTH_B = + (READ_WIDTH_B == 1) ? 13 : + (READ_WIDTH_B == 2) ? 12 : + (READ_WIDTH_B == 4) ? 11 : + (READ_WIDTH_B == 5) ? 11 : + (READ_WIDTH_B == 8) ? 10 : + (READ_WIDTH_B == 10) ? 10 :-1; + + localparam WRITE_AWIDTH_B = + (WRITE_WIDTH_B == 1) ? 13 : + (WRITE_WIDTH_B == 2) ? 12 : + (WRITE_WIDTH_B == 4) ? 11 : + (WRITE_WIDTH_B == 5) ? 11 : + (WRITE_WIDTH_B == 8) ? 10 : + (WRITE_WIDTH_B == 10) ? 10 :-1; + + // Greater of Read and Write widths defines input size + localparam AWIDTH_B = (READ_AWIDTH_B > WRITE_AWIDTH_B) ? READ_AWIDTH_B : WRITE_AWIDTH_B; + localparam DWIDTH_B = (READ_WIDTH_B > WRITE_WIDTH_B) ? WRITE_WIDTH_B : READ_WIDTH_B; + + + localparam MEMORY_SIZE = 512*20; + + localparam READ_FIRST = 0; + localparam WRITE_FIRST = 1; + localparam WRITE_NOT_READ = 2; + + input CLKA, WEA, CLKEA, RSTA, ADDRENA; + input CLKB, WEB, CLKEB, RSTB, ADDRENB; + input [WRITE_WIDTH_A-1:0] WDATAA; + input [AWIDTH_A-1:0] ADDRA; + reg [READ_WIDTH_A-1:0] RDATAA_early, RDATAA_late; + reg [READ_WIDTH_A-1:0] RDATAA_out = 0; + reg [READ_WIDTH_A-1:0] RDATAA_reg = 0; + output [READ_WIDTH_A-1:0] RDATAA; + input [WRITE_WIDTH_B-1:0] WDATAB; + input [AWIDTH_B-1:0] ADDRB; + reg [READ_WIDTH_B-1:0] RDATAB_early, RDATAB_late; + reg [READ_WIDTH_B-1:0] RDATAB_out = 0; + reg [READ_WIDTH_B-1:0] RDATAB_reg = 0; + output [READ_WIDTH_B-1:0] RDATAB; + + // Local variables + reg mem [MEMORY_SIZE-1:0]; + integer i; + + // Create nets for optional control inputs + // allows us to assign to them without getting warning + // for coercing input to inout + wire WEA_net; + wire CLKEA_net; + wire RSTA_net; + wire ADDRENA_net; + wire WEB_net; + wire CLKEB_net; + wire RSTB_net; + wire ADDRENB_net; + + // Pull unused address lines low, to mirror EFX synthesis behavior. + wire [AWIDTH_A-1:0] ADDRA_net; + wire [AWIDTH_B-1:0] ADDRB_net; + reg [AWIDTH_A-1:0] ADDRA_r; + reg [AWIDTH_B-1:0] ADDRB_r; + + // Default values for optional control signals + assign (weak0, weak1) WEA_net = ~WEA_POLARITY; + assign (weak0, weak1) CLKEA_net = CLKEA_POLARITY; + assign (weak0, weak1) RSTA_net = ~RSTA_POLARITY; + assign (weak0, weak1) ADDRENA_net = ADDRENA_POLARITY; + assign (weak0, weak1) WEB_net = ~WEB_POLARITY; + assign (weak0, weak1) CLKEB_net = CLKEB_POLARITY; + assign (weak0, weak1) RSTB_net = ~RSTB_POLARITY; + assign (weak0, weak1) ADDRENB_net = ADDRENB_POLARITY; + + assign (weak0, weak1) ADDRA_net = {AWIDTH_A{1'b0}}; + assign (weak0, weak1) ADDRB_net = {AWIDTH_B{1'b0}}; + + // Now assign the input + assign WEA_net = WEA; + assign CLKEA_net = CLKEA; + assign RSTA_net = RSTA; + assign ADDRENA_net = ADDRENA; + assign WEB_net = WEB; + assign CLKEB_net = CLKEB; + assign RSTB_net = RSTB; + assign ADDRENB_net = ADDRENB; + + assign ADDRA_net = ADDRA; + assign ADDRB_net = ADDRB; + + function COMPATIBLE_WIDTH; + input integer w1, w2; + COMPATIBLE_WIDTH = ((((w1==1)||(w1==2)||(w1==4)||(w1==8))&&((w2==1)||(w2==2)||(w2==4)||(w2==8))) || + (((w1==5)||(w1==10))&&((w2==5)||(w2==10)))); + endfunction + + + reg finish_error = 0; + initial begin + // Check for illegal modes, address width will be -1 + if (READ_AWIDTH_A == -1) begin + $display("ERROR:Illegal READ WIDTH Port A %d", READ_WIDTH_A); + finish_error = 1; + end + if (WRITE_AWIDTH_A == -1) begin + $display("ERROR:Illegal WRITE WIDTH Port A %d", WRITE_WIDTH_A); + finish_error = 1; + end + if (READ_AWIDTH_B == -1) begin + $display("ERROR:Illegal READ WIDTH Port B %d", READ_WIDTH_B); + finish_error = 1; + end + if (WRITE_AWIDTH_B == -1) begin + $display("ERROR:Illegal WRITE WIDTH Port B %d", WRITE_WIDTH_B); + finish_error = 1; + end + if (~COMPATIBLE_WIDTH(READ_WIDTH_A,WRITE_WIDTH_A)) begin + $display("ERROR: Port A READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH_A, WRITE_WIDTH_A); + finish_error = 1; + end + if (~COMPATIBLE_WIDTH(READ_WIDTH_B,WRITE_WIDTH_B)) begin + $display("ERROR: Port B READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH_B, WRITE_WIDTH_B); + finish_error = 1; + end + if (~COMPATIBLE_WIDTH(READ_WIDTH_A,READ_WIDTH_B)||~COMPATIBLE_WIDTH(WRITE_WIDTH_A,WRITE_WIDTH_B)) begin + $display("ERROR: Port A READ/WRITE WIDTHS %d/%d cannot be used with Port B READ/WRITE WIDTHs %d/%d", + READ_WIDTH_A, WRITE_WIDTH_A, READ_WIDTH_B, WRITE_WIDTH_B); + finish_error = 1; + end + // Check for illegal write modes + if (WRITE_MODE_A != "READ_FIRST" && WRITE_MODE_A != "WRITE_FIRST" && WRITE_MODE_A != "NO_CHANGE") begin + $display("ERROR:Illegal WRITE_MODE A %s", WRITE_MODE_A); + finish_error = 1; + end + if (WRITE_MODE_B != "READ_FIRST" && WRITE_MODE_B != "WRITE_FIRST" && WRITE_MODE_B != "NO_CHANGE") begin + $display("ERROR:Illegal WRITE_MODE B %s", WRITE_MODE_B); + finish_error = 1; + end + if (RESET_RAM_A != "ASYNC" && RESET_RAM_A != "SYNC" && RESET_RAM_A != "NONE") begin + $display("ERROR: Illegal RESET_RAM_A setting %s", RESET_RAM_A); + finish_error = 1; + end + if (RESET_RAM_B != "ASYNC" && RESET_RAM_B != "SYNC" && RESET_RAM_B != "NONE") begin + $display("ERROR: Illegal RESET_RAM_B setting %s", RESET_RAM_B); + finish_error = 1; + end + if (RESET_OUTREG_A != "ASYNC" && RESET_OUTREG_A != "NONE") begin + $display("ERROR: Illegal RESET_OUTREG_A setting %s", RESET_OUTREG_A); + finish_error = 1; + end + if (RESET_OUTREG_B != "ASYNC" && RESET_OUTREG_B != "NONE") begin + $display("ERROR: Illegal RESET_OUTREG_B setting %s", RESET_OUTREG_B); + finish_error = 1; + end + + if (finish_error == 1) + #1 $finish(); + + // Initialize memory + for (i=0; i < 256; i=i+1) begin + mem[256*0+i] = INIT_0[i]; + mem[256*1+i] = INIT_1[i]; + mem[256*2+i] = INIT_2[i]; + mem[256*3+i] = INIT_3[i]; + mem[256*4+i] = INIT_4[i]; + mem[256*5+i] = INIT_5[i]; + mem[256*6+i] = INIT_6[i]; + mem[256*7+i] = INIT_7[i]; + mem[256*8+i] = INIT_8[i]; + mem[256*9+i] = INIT_9[i]; + mem[256*10+i] = INIT_A[i]; + mem[256*11+i] = INIT_B[i]; + mem[256*12+i] = INIT_C[i]; + mem[256*13+i] = INIT_D[i]; + mem[256*14+i] = INIT_E[i]; + mem[256*15+i] = INIT_F[i]; + mem[256*16+i] = INIT_10[i]; + mem[256*17+i] = INIT_11[i]; + mem[256*18+i] = INIT_12[i]; + mem[256*19+i] = INIT_13[i]; + mem[256*20+i] = INIT_14[i]; + mem[256*21+i] = INIT_15[i]; + mem[256*22+i] = INIT_16[i]; + mem[256*23+i] = INIT_17[i]; + mem[256*24+i] = INIT_18[i]; + mem[256*25+i] = INIT_19[i]; + mem[256*26+i] = INIT_1A[i]; + mem[256*27+i] = INIT_1B[i]; + mem[256*28+i] = INIT_1C[i]; + mem[256*29+i] = INIT_1D[i]; + mem[256*30+i] = INIT_1E[i]; + mem[256*31+i] = INIT_1F[i]; + mem[256*32+i] = INIT_20[i]; + mem[256*33+i] = INIT_21[i]; + mem[256*34+i] = INIT_22[i]; + mem[256*35+i] = INIT_23[i]; + mem[256*36+i] = INIT_24[i]; + mem[256*37+i] = INIT_25[i]; + mem[256*38+i] = INIT_26[i]; + mem[256*39+i] = INIT_27[i]; + end + end + + // Wires for the polarity control. + // Only supporting clocks and enable for now + wire CLKA_i, WEA_i, CLKEA_i, RSTA_i, ADDRENA_i; + wire CLKB_i, WEB_i, CLKEB_i, RSTB_i, ADDRENB_i; + + assign CLKA_i = CLKA_POLARITY ~^ CLKA; + assign CLKEA_i = CLKEA_POLARITY ~^ CLKEA_net; + assign RSTA_i = RSTA_POLARITY ~^ RSTA_net; + assign ADDRENA_i = ADDRENA_POLARITY ~^ ADDRENA_net; + assign WEA_i = WEA_POLARITY ~^ WEA_net; + assign CLKB_i = CLKB_POLARITY ~^ CLKB; + assign CLKEB_i = CLKEB_POLARITY ~^ CLKEB_net; + assign RSTB_i = RSTB_POLARITY ~^ RSTB_net; + assign ADDRENB_i = ADDRENB_POLARITY ~^ ADDRENB_net; + assign WEB_i = WEB_POLARITY ~^ WEB_net; + + ////////////////////////////////////////////////////////////// + // Port A + ////////////////////////////////////////////////////////////// + // Wires for the configurable reset controls + wire ram_async_rsta, ram_sync_rsta, outreg_async_rsta; + assign ram_async_rsta = (RESET_RAM_A == "ASYNC") ? RSTA_i : 1'b0; + assign ram_sync_rsta = (RESET_RAM_A == "SYNC") ? RSTA_i : 1'b0; + assign outreg_async_rsta = (RESET_OUTREG_A == "ASYNC") ? RSTA_i : 1'b0; + + task read_rama; + input [READ_AWIDTH_A-1:0] addr; + output [READ_WIDTH_A-1:0] rdata; + + begin + + for (i=0; i < READ_WIDTH_A; i=i+1) + rdata[i] = mem[addr*READ_WIDTH_A+i]; + end + endtask + + task write_rama; + input [WRITE_AWIDTH_A-1:0] addr; + input [WRITE_WIDTH_A-1:0] wdata; + input we; + + begin + if (we) + for (i=0; i < WRITE_WIDTH_A; i=i+1) + mem[addr*WRITE_WIDTH_A+i] = wdata[i]; + end + endtask + + always@(posedge CLKA_i) begin + if (CLKEA_i) begin + // Only update the address latch if not stalled + ADDRA_r = ADDRENA_i ? ADDRA_net : ADDRA_r; + + // Do an early read, write and late read + // Then decide what do do with the read data + read_rama(ADDRA_r[AWIDTH_A-1:AWIDTH_A - READ_AWIDTH_A], RDATAA_early); + #0; // Use #0 delay blocking assignments to allow cross port read/write + write_rama(ADDRA_r[AWIDTH_A-1:AWIDTH_A - WRITE_AWIDTH_A], WDATAA, WEA_i); + #0; // Use #0 delay blocking assignments to allow cross port read/write + read_rama(ADDRA_r[AWIDTH_A-1:AWIDTH_A - READ_AWIDTH_A], RDATAA_late); + #0; + end + end + + // Decide which data to output + always@(posedge CLKA_i or posedge ram_async_rsta) begin + if (ram_async_rsta) begin + RDATAA_out <= {READ_WIDTH_A{1'b0}}; + end + else begin + // Delay for the read/write/read to happen + #0; #0; #0; + if (CLKEA_i) begin + // Check for sync reset + if (ram_sync_rsta) begin + RDATAA_out <= {READ_WIDTH_A{1'b0}}; + end + else begin + // Based on the write mode decide which read data to use + if (WRITE_MODE_A == "READ_FIRST") begin + RDATAA_out <= RDATAA_early; + end + else if (WRITE_MODE_A == "WRITE_FIRST") begin + if (WEA_i) RDATAA_out <= WDATAA; + else RDATAA_out <= RDATAA_late; + end + else /* (WRITE_MODE_A == "NO_CHANGE") */ begin + RDATAA_out <= WEA_i ? RDATAA_out : RDATAA_early; + end + end + end + end + end + + // Optional output register + generate if (OUTPUT_REG_A) + begin + always@(posedge CLKA_i or posedge outreg_async_rsta) begin + if (outreg_async_rsta) RDATAA_reg <= {READ_WIDTH_A{1'b0}}; + else if (CLKEA_i) RDATAA_reg <= RDATAA_out; + end + + assign RDATAA = RDATAA_reg; + end + else + begin + assign RDATAA = RDATAA_out; + end + endgenerate + + ////////////////////////////////////////////////////////////// + // Port B + ////////////////////////////////////////////////////////////// + // Wires for the configurable reset controls + wire ram_async_rstb, ram_sync_rstb, outreg_async_rstb; + assign ram_async_rstb = (RESET_RAM_B == "ASYNC") ? RSTB_i : 1'b0; + assign ram_sync_rstb = (RESET_RAM_B == "SYNC") ? RSTB_i : 1'b0; + assign outreg_async_rstb = (RESET_OUTREG_B == "ASYNC") ? RSTB_i : 1'b0; + + task read_ramb; + input [READ_AWIDTH_B-1:0] addr; + output [READ_WIDTH_B-1:0] rdata; + + begin + for (i=0; i < READ_WIDTH_B; i=i+1) + rdata[i] = mem[addr*READ_WIDTH_B+i]; + end + endtask + + task write_ramb; + input [WRITE_AWIDTH_B-1:0] addr; + input [WRITE_WIDTH_B-1:0] wdata; + input we; + + begin + if (we) + for (i=0; i < WRITE_WIDTH_B; i=i+1) + mem[addr*WRITE_WIDTH_B+i] = wdata[i]; + end + endtask + + always@(posedge CLKB_i) begin + if (CLKEB_i) begin + // Only update the address latch if not stalled + ADDRB_r = ADDRENB_i ? ADDRB_net : ADDRB_r; + + // Do an early read, write and late read + // Then decide what do do with the read data + read_ramb(ADDRB_r[AWIDTH_B-1:AWIDTH_B - READ_AWIDTH_B], RDATAB_early); + #0; // Use #0 delay blocking assignments to allow cross port read/write + write_ramb(ADDRB_r[AWIDTH_B-1:AWIDTH_B - WRITE_AWIDTH_B], WDATAB, WEB_i); + #0; // Use #0 delay blocking assignments to allow cross port read/write + read_ramb(ADDRB_r[AWIDTH_B-1:AWIDTH_B - READ_AWIDTH_B], RDATAB_late); + #0; + + end + end + + // Choose the Read value to output + always@(posedge CLKB_i or posedge ram_async_rstb) begin + if (ram_async_rstb) begin + RDATAB_out <= {READ_WIDTH_B{1'b0}}; + end + else begin + // Delay for the read/write/read to happen + #0; #0; #0; + if (CLKEB_i) begin + if (ram_sync_rstb) begin + RDATAB_out <= {READ_WIDTH_B{1'b0}}; + end + else begin + // Based on the write mode decide which read data to use + if (WRITE_MODE_B == "READ_FIRST") begin + RDATAB_out <= RDATAB_early; + end + else if (WRITE_MODE_B == "WRITE_FIRST") begin + if (WEB_i) RDATAB_out <= WDATAB; + else RDATAB_out <= RDATAB_late; + end + else /* (WRITE_MODE_B == "NO_CHANGE") */ begin + RDATAB_out <= WEB_i ? RDATAB_out : RDATAB_early; + end + end + end + end + end + + // Optional output register + generate if (OUTPUT_REG_B) + begin + always@(posedge CLKB_i or posedge outreg_async_rstb) begin + if (outreg_async_rstb) RDATAB_reg <= {READ_WIDTH_B{1'b0}}; + else if (CLKEB_i)RDATAB_reg <= RDATAB_out; + end + + assign RDATAB = RDATAB_reg; + end + else + begin + assign RDATAB = RDATAB_out; + end + endgenerate + +endmodule // EFX_DPRAM10 + +////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +///////////////////////////////////////////////////////////////////////////// diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/efx_dpram_5k.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/efx_dpram_5k.v new file mode 100644 index 0000000000000000000000000000000000000000..c9f73411e25cfcd22fd9c19e6238fe53e816d642 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/efx_dpram_5k.v @@ -0,0 +1,420 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2013-2016 Efinix Inc. All rights reserved. +// +// Efinix Dual-Port Block RAM (BRAM): +// +// This is a 5K true dual-port RAM +// +// The A & B ports can +// Be in any of the following WIDTHs: +// 8 --> 512x8 +// 4 --> 1024x4 +// 2 --> 2048x2 +// 1 --> 4096x1 +// 10 --> 512x10 +// 5 --> 1024x5 +// Reading and Writing can be in different WIDTHs +// +// Writing can be done in one of three WRITE MODEs +// READ_FIRST +// WRITE_FIRST +// NO_CHANGE +// +// Behavior is undefined when +// reading / writing the same address +// TODO: Need to add address collision checking! +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// ******************************* +///////////////////////////////////////////////////////////////////////////// + +module EFX_DPRAM_5K +( + CLKA, WEA, CLKEA, WDATAA, ADDRA, RDATAA, + CLKB, WEB, CLKEB, WDATAB, ADDRB, RDATAB +); + + + parameter CLKA_POLARITY = 1'b1; + parameter CLKEA_POLARITY = 1'b1; + parameter WEA_POLARITY = 1'b1; + parameter CLKB_POLARITY = 1'b1; + parameter CLKEB_POLARITY = 1'b1; + parameter WEB_POLARITY = 1'b1; + // Need to add all the data & address input polarity inversion parameters + parameter READ_WIDTH_A = 8; + parameter WRITE_WIDTH_A = 8; + parameter READ_WIDTH_B = 8; + parameter WRITE_WIDTH_B = 8; + parameter OUTPUT_REG_A = 1'b0; + parameter OUTPUT_REG_B = 1'b0; + parameter WRITE_MODE_A = "READ_FIRST"; + parameter WRITE_MODE_B = "READ_FIRST"; + parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + localparam READ_AWIDTH_A = + (READ_WIDTH_A == 1) ? 12 : + (READ_WIDTH_A == 2) ? 11 : + (READ_WIDTH_A == 4) ? 10 : + (READ_WIDTH_A == 5) ? 10 : + (READ_WIDTH_A == 8) ? 9 : + (READ_WIDTH_A == 10) ? 9 :-1; + + localparam WRITE_AWIDTH_A = + (WRITE_WIDTH_A == 1) ? 12 : + (WRITE_WIDTH_A == 2) ? 11 : + (WRITE_WIDTH_A == 4) ? 10 : + (WRITE_WIDTH_A == 5) ? 10 : + (WRITE_WIDTH_A == 8) ? 9 : + (WRITE_WIDTH_A == 10) ? 9 :-1; + + // Greater of Read and Write widths defines input size + localparam AWIDTH_A = (READ_AWIDTH_A > WRITE_AWIDTH_A) ? READ_AWIDTH_A : WRITE_AWIDTH_A; + localparam DWIDTH_A = (READ_WIDTH_A > WRITE_WIDTH_A) ? WRITE_WIDTH_A : READ_WIDTH_A; + + localparam READ_AWIDTH_B = + (READ_WIDTH_B == 1) ? 12 : + (READ_WIDTH_B == 2) ? 11 : + (READ_WIDTH_B == 4) ? 10 : + (READ_WIDTH_B == 5) ? 10 : + (READ_WIDTH_B == 8) ? 9 : + (READ_WIDTH_B == 10) ? 9 :-1; + + localparam WRITE_AWIDTH_B = + (WRITE_WIDTH_B == 1) ? 12 : + (WRITE_WIDTH_B == 2) ? 11 : + (WRITE_WIDTH_B == 4) ? 10 : + (WRITE_WIDTH_B == 5) ? 10 : + (WRITE_WIDTH_B == 8) ? 9 : + (WRITE_WIDTH_B == 10) ? 9 :-1; + + // Greater of Read and Write widths defines input size + localparam AWIDTH_B = (READ_AWIDTH_B > WRITE_AWIDTH_B) ? READ_AWIDTH_B : WRITE_AWIDTH_B; + localparam DWIDTH_B = (READ_WIDTH_B > WRITE_WIDTH_B) ? WRITE_WIDTH_B : READ_WIDTH_B; + + + localparam MEMORY_SIZE = 256*20; + + localparam READ_FIRST = 0; + localparam WRITE_FIRST = 1; + localparam WRITE_NOT_READ = 2; + + input CLKA, WEA, CLKEA; + input CLKB, WEB, CLKEB; + input [WRITE_WIDTH_A-1:0] WDATAA; + input [AWIDTH_A-1:0] ADDRA; + reg [READ_WIDTH_A-1:0] RDATAA_early, RDATAA_late; + reg [READ_WIDTH_A-1:0] RDATAA_out = 0; + reg [READ_WIDTH_A-1:0] RDATAA_reg = 0; + output [READ_WIDTH_A-1:0] RDATAA; + input [WRITE_WIDTH_B-1:0] WDATAB; + input [AWIDTH_B-1:0] ADDRB; + reg [READ_WIDTH_B-1:0] RDATAB_early, RDATAB_late; + reg [READ_WIDTH_B-1:0] RDATAB_out = 0; + reg [READ_WIDTH_B-1:0] RDATAB_reg = 0; + output [READ_WIDTH_B-1:0] RDATAB; + + // Local variables + reg mem [MEMORY_SIZE-1:0]; + integer i; + + // Create nets for optional control inputs + // allows us to assign to them without getting warning + // for coercing input to inout + wire WEA_net; + wire CLKEA_net; + wire WEB_net; + wire CLKEB_net; + + // Pull unused address lines low, to mirror EFX synthesis behavior. + wire [AWIDTH_A-1:0] ADDRA_net; + wire [AWIDTH_B-1:0] ADDRB_net; + + // Default values for optional control signals + assign (weak0, weak1) WEA_net = WEA_POLARITY ? 1'b0 : 1'b1; + assign (weak0, weak1) CLKEA_net = CLKEA_POLARITY ? 1'b1 : 1'b0; + assign (weak0, weak1) WEB_net = WEB_POLARITY ? 1'b0 : 1'b1; + assign (weak0, weak1) CLKEB_net = CLKEB_POLARITY ? 1'b1 : 1'b0; + + assign (weak0, weak1) ADDRA_net = {AWIDTH_A{1'b0}}; + assign (weak0, weak1) ADDRB_net = {AWIDTH_B{1'b0}}; + + // Now assign the input + assign WEA_net = WEA; + assign CLKEA_net = CLKEA; + assign WEB_net = WEB; + assign CLKEB_net = CLKEB; + + assign ADDRA_net = ADDRA; + assign ADDRB_net = ADDRB; + + function COMPATIBLE_WIDTH; + input integer w1, w2; + COMPATIBLE_WIDTH = ((((w1==1)||(w1==2)||(w1==4)||(w1==8))&&((w2==1)||(w2==2)||(w2==4)||(w2==8))) || + (((w1==5)||(w1==10))&&((w2==5)||(w2==10)))); + endfunction + + + initial begin + // Check for illegal modes, address width will be -1 + if (READ_AWIDTH_A == -1) begin + $display("ERROR:Illegal READ WIDTH Port A %d", READ_WIDTH_A); + $finish(); + end + if (WRITE_AWIDTH_A == -1) begin + $display("ERROR:Illegal WRITE WIDTH Port A %d", WRITE_WIDTH_A); + $finish(); + end + if (READ_AWIDTH_B == -1) begin + $display("ERROR:Illegal READ WIDTH Port B %d", READ_WIDTH_B); + $finish(); + end + if (WRITE_AWIDTH_B == -1) begin + $display("ERROR:Illegal WRITE WIDTH Port B %d", WRITE_WIDTH_B); + $finish(); + end + if (~COMPATIBLE_WIDTH(READ_WIDTH_A,WRITE_WIDTH_A)) begin + $display("ERROR: Port A READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH_A, WRITE_WIDTH_A); + $finish(); + end + if (~COMPATIBLE_WIDTH(READ_WIDTH_B,WRITE_WIDTH_B)) begin + $display("ERROR: Port B READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH_B, WRITE_WIDTH_B); + $finish(); + end + if (~COMPATIBLE_WIDTH(READ_WIDTH_A,READ_WIDTH_B)||~COMPATIBLE_WIDTH(WRITE_WIDTH_A,WRITE_WIDTH_B)) begin + $display("ERROR: Port A READ/WRITE WIDTHS %d/%d cannot be used with Port B READ/WRITE WIDTHs %d/%d", + READ_WIDTH_A, WRITE_WIDTH_A, READ_WIDTH_B, WRITE_WIDTH_B); + $finish(); + end + // Check for illegal write modes + if (WRITE_MODE_A != "READ_FIRST" && WRITE_MODE_A != "WRITE_FIRST" && WRITE_MODE_A != "NO_CHANGE") begin + $display("ERROR:Illegal WRITE_MODE A %s", WRITE_MODE_A); + $finish(); + end + if (WRITE_MODE_B != "READ_FIRST" && WRITE_MODE_B != "WRITE_FIRST" && WRITE_MODE_B != "NO_CHANGE") begin + $display("ERROR:Illegal WRITE_MODE B %s", WRITE_MODE_B); + $finish(); + end + // Initialize memory + for (i=0; i < 256; i=i+1) begin + mem[256*0+i] = INIT_0[i]; + mem[256*1+i] = INIT_1[i]; + mem[256*2+i] = INIT_2[i]; + mem[256*3+i] = INIT_3[i]; + mem[256*4+i] = INIT_4[i]; + mem[256*5+i] = INIT_5[i]; + mem[256*6+i] = INIT_6[i]; + mem[256*7+i] = INIT_7[i]; + mem[256*8+i] = INIT_8[i]; + mem[256*9+i] = INIT_9[i]; + mem[256*10+i] = INIT_A[i]; + mem[256*11+i] = INIT_B[i]; + mem[256*12+i] = INIT_C[i]; + mem[256*13+i] = INIT_D[i]; + mem[256*14+i] = INIT_E[i]; + mem[256*15+i] = INIT_F[i]; + mem[256*16+i] = INIT_10[i]; + mem[256*17+i] = INIT_11[i]; + mem[256*18+i] = INIT_12[i]; + mem[256*19+i] = INIT_13[i]; + end + end + + // Wires for the polarity control. + // Only supporting clocks and enable for now + wire CLKA_i, WEA_i, CLKEA_i; + wire CLKB_i, WEB_i, CLKEB_i; + + assign CLKA_i = CLKA_POLARITY ? CLKA : ~CLKA; + assign CLKEA_i = CLKEA_POLARITY ? CLKEA_net : ~CLKEA_net; + assign WEA_i = WEA_POLARITY ? WEA_net : ~WEA_net; + assign CLKB_i = CLKB_POLARITY ? CLKB : ~CLKB; + assign CLKEB_i = CLKEB_POLARITY ? CLKEB_net : ~CLKEB_net; + assign WEB_i = WEB_POLARITY ? WEB_net : ~WEB_net; + + ////////////////////////////////////////////////////////////// + // Port A + ////////////////////////////////////////////////////////////// + task read_rama; + input [READ_AWIDTH_A-1:0] addr; + output [READ_WIDTH_A-1:0] rdata; + + + begin + + for (i=0; i < READ_WIDTH_A; i=i+1) + rdata[i] = mem[addr*READ_WIDTH_A+i]; + end + endtask + + task write_rama; + input [WRITE_AWIDTH_A-1:0] addr; + input [WRITE_WIDTH_A-1:0] wdata; + input we; + + begin + if (we) + for (i=0; i < WRITE_WIDTH_A; i=i+1) + mem[addr*WRITE_WIDTH_A+i] = wdata[i]; + end + endtask + + always@(posedge CLKA_i) + if (CLKEA_i) begin + // Do an early read, write and late read + // Then decide what do do with the read data + read_rama(ADDRA_net[AWIDTH_A-1:AWIDTH_A - READ_AWIDTH_A], RDATAA_early); + #0; // Use #0 delay blocking assignments to allow cross port read/write + write_rama(ADDRA_net[AWIDTH_A-1:AWIDTH_A - WRITE_AWIDTH_A], WDATAA, WEA_i); + #0; // Use #0 delay blocking assignments to allow cross port read/write + read_rama(ADDRA_net[AWIDTH_A-1:AWIDTH_A - READ_AWIDTH_A], RDATAA_late); + + // Based on the write mode decide which read data to use + if (WRITE_MODE_A == "READ_FIRST") begin + RDATAA_out = RDATAA_early; + end + else if (WRITE_MODE_A == "WRITE_FIRST") begin + RDATAA_out = RDATAA_late; + end + else /* (WRITE_MODE_A == "NO_CHANGE") */ begin + RDATAA_out = WEA_i ? RDATAA_out : RDATAA_early; + end + end + + // Optional output register + generate if (OUTPUT_REG_A) + begin + always@(posedge CLKA_i) + RDATAA_reg <= RDATAA_out; + + assign RDATAA = RDATAA_reg; + end + else + begin + assign RDATAA = RDATAA_out; + end + endgenerate + + ////////////////////////////////////////////////////////////// + // Port B + ////////////////////////////////////////////////////////////// + task read_ramb; + input [READ_AWIDTH_B-1:0] addr; + output [READ_WIDTH_B-1:0] rdata; + + begin + for (i=0; i < READ_WIDTH_B; i=i+1) + rdata[i] = mem[addr*READ_WIDTH_B+i]; + end + endtask + + task write_ramb; + input [WRITE_AWIDTH_B-1:0] addr; + input [WRITE_WIDTH_B-1:0] wdata; + input we; + + begin + if (we) + for (i=0; i < WRITE_WIDTH_B; i=i+1) + mem[addr*WRITE_WIDTH_B+i] = wdata[i]; + end + endtask + + always@(posedge CLKB_i) + if (CLKEB_i) begin + // Do an early read, write and late read + // Then decide what do do with the read data + read_ramb(ADDRB_net[AWIDTH_B-1:AWIDTH_B - READ_AWIDTH_B], RDATAB_early); + #0; // Use #0 delay blocking assignments to allow cross port read/write + write_ramb(ADDRB_net[AWIDTH_B-1:AWIDTH_B - WRITE_AWIDTH_B], WDATAB, WEB_i); + #0; // Use #0 delay blocking assignments to allow cross port read/write + read_ramb(ADDRB_net[AWIDTH_B-1:AWIDTH_B - READ_AWIDTH_B], RDATAB_late); + + // Based on the write mode decide which read data to use + if (WRITE_MODE_B == "READ_FIRST") begin + RDATAB_out = RDATAB_early; + end + else if (WRITE_MODE_B == "WRITE_FIRST") begin + RDATAB_out = RDATAB_late; + end + else /* (WRITE_MODE_B == "NO_CHANGE") */ begin + RDATAB_out = WEB_i ? RDATAB_out : RDATAB_early; + end + end + + // Optional output register + generate if (OUTPUT_REG_B) + begin + always@(posedge CLKB_i) + RDATAB_reg <= RDATAB_out; + + assign RDATAB = RDATAB_reg; + end + else + begin + assign RDATAB = RDATAB_out; + end + endgenerate + +endmodule // EFX_DPRAM_5K + +////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2016 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +///////////////////////////////////////////////////////////////////////////// diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/efx_ram10.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/efx_ram10.v new file mode 100644 index 0000000000000000000000000000000000000000..7ba87f91972fb6258b9f4fe12b0060f473de712d --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/efx_ram10.v @@ -0,0 +1,457 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2018 Efinix Inc. All rights reserved. +// +// Efinix Block RAM (BRAM): +// +// This is a 10K simple dual-port RAM +// (one read & one write port) +// +// The read and write ports can +// Be in any of the following WIDTHS +// 16 --> 512x16 +// 8 --> 1024x8 +// 4 --> 2048x4 +// 2 --> 4096x2 +// 1 --> 8192x1 +// 20 --> 512x20 +// 10 --> 1024x10 +// 5 --> 2048x5 +// +// Writing can be done in one of three WRITE MODEs +// READ_FIRST +// WRITE_FIRST +// READ_UNKNOWN +// +// Behavior is undefined when +// reading / writing the same address +// TODO: Need to add address collision checking! +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// ******************************* +///////////////////////////////////////////////////////////////////////////// + +module EFX_RAM10 +( + WCLK, WE, WCLKE, WADDREN, WDATA, WADDR, + RCLK, RE, RST, RADDREN, RDATA, RADDR +); + + + parameter [0:0] WCLK_POLARITY = 1'b1; + parameter [0:0] WCLKE_POLARITY = 1'b1; + parameter [0:0] WADDREN_POLARITY = 1'b1; + parameter [1:0] WE_POLARITY = 2'b11; + parameter [0:0] RCLK_POLARITY = 1'b1; + parameter [0:0] RE_POLARITY = 1'b1; + parameter [0:0] RST_POLARITY = 1'b1; + parameter [0:0] RADDREN_POLARITY = 1'b1; + // Need to add all the data & address input polarity inversion parameters + parameter READ_WIDTH = 16; + parameter WRITE_WIDTH = 16; + parameter [0:0] OUTPUT_REG = 1'b0; + parameter WRITE_MODE = "READ_FIRST"; + parameter RESET_RAM = "ASYNC"; + parameter RESET_OUTREG = "ASYNC"; + + parameter [255:0] INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + localparam READ_AWIDTH = + (READ_WIDTH == 1) ? 13 : + (READ_WIDTH == 2) ? 12 : + (READ_WIDTH == 4) ? 11 : + (READ_WIDTH == 5) ? 11 : + (READ_WIDTH == 8) ? 10 : + (READ_WIDTH == 10) ? 10 : + (READ_WIDTH == 16) ? 9 : + (READ_WIDTH == 20) ? 9 :-1; + + localparam WRITE_AWIDTH = + (WRITE_WIDTH == 1) ? 13 : + (WRITE_WIDTH == 2) ? 12 : + (WRITE_WIDTH == 4) ? 11 : + (WRITE_WIDTH == 5) ? 11 : + (WRITE_WIDTH == 8) ? 10 : + (WRITE_WIDTH == 10) ? 10 : + (WRITE_WIDTH == 16) ? 9 : + (WRITE_WIDTH == 20) ? 9 :-1; + + localparam WRITE_BYTES = (WRITE_WIDTH == 16) || (WRITE_WIDTH == 20); + + localparam MEMORY_SIZE = 512*20; + + input WCLK, WCLKE, WADDREN; + input RCLK, RE, RST, RADDREN; + input [1:0] WE; + input [WRITE_WIDTH-1:0] WDATA; + input [WRITE_AWIDTH-1:0] WADDR; + input [READ_AWIDTH-1:0] RADDR; + reg [READ_WIDTH-1:0] RDATA_early, RDATA_late; + reg [READ_WIDTH-1:0] RDATA_out = 0; + reg [READ_WIDTH-1:0] RDATA_reg = 0; + output [READ_WIDTH-1:0] RDATA; + + // Local variables + reg mem [MEMORY_SIZE-1:0]; + integer i; + + // Create nets for optional control inputs + // allows us to assign to them without getting warning + // for coercing input to inout + wire [1:0] WE_net; + wire WCLKE_net; + wire WADDREN_net; + wire RE_net; + wire RST_net; + wire RADDREN_net; + + // Pull unused address lines low, to mirror EFX synthesis behavior. + wire [WRITE_AWIDTH-1:0] WADDR_net; + wire [READ_AWIDTH-1:0] RADDR_net; + reg [WRITE_AWIDTH-1:0] WADDR_r = 0; + reg [READ_AWIDTH-1:0] RADDR_r = 0; + + // Default values for optional control signals + assign (weak0, weak1) WE_net = ~WE_POLARITY; + assign (weak0, weak1) WCLKE_net = WCLKE_POLARITY; + assign (weak0, weak1) WADDREN_net = WADDREN_POLARITY; + assign (weak0, weak1) RE_net = RE_POLARITY; + assign (weak0, weak1) RST_net = ~RST_POLARITY; + assign (weak0, weak1) RADDREN_net = RADDREN_POLARITY; + + assign (weak0, weak1) WADDR_net = {WRITE_AWIDTH{1'b0}}; + assign (weak0, weak1) RADDR_net = {READ_AWIDTH{1'b0}}; + + // Now assign the input + assign WE_net = WE; + assign WCLKE_net = WCLKE; + assign WADDREN_net = WADDREN; + assign RE_net = RE; + assign RST_net = RST; + assign RADDREN_net = RADDREN; + + assign WADDR_net = WADDR; + assign RADDR_net = RADDR; + + function COMPATIBLE_WIDTH; + input integer w1, w2; + COMPATIBLE_WIDTH = ((((w1==1)||(w1==2)||(w1==4)||(w1==8)||(w1==16))&&((w2==1)||(w2==2)||(w2==4)||(w2==8)||(w2==16))) || + (((w1==5)||(w1==10)||(w1==20))&&((w2==5)||(w2==10)||(w2==20)))); + endfunction + + reg finish_error = 0; + initial begin + // Check for illegal modes, address width will be -1 + if (READ_AWIDTH == -1) begin + $display("ERROR: Illegal READ WIDTH %d", READ_WIDTH); + finish_error = 1; + end + if (WRITE_AWIDTH == -1) begin + $display("ERROR: Illegal WRITE WIDTH %d", WRITE_WIDTH); + finish_error = 1; + end + if (~COMPATIBLE_WIDTH(READ_WIDTH,WRITE_WIDTH)) begin + $display("ERROR: READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH, WRITE_WIDTH); + finish_error = 1; + end + // Check for illegal write modes + if (WRITE_MODE != "READ_FIRST" && WRITE_MODE != "WRITE_FIRST" && WRITE_MODE != "READ_UNKNOWN") begin + $display("ERROR: Illegal WRITE_MODE %s", WRITE_MODE); + finish_error = 1; + end + if (RESET_RAM != "ASYNC" && RESET_RAM != "SYNC" && RESET_RAM != "NONE") begin + $display("ERROR: Illegal RESET_RAM setting %s", RESET_RAM); + finish_error = 1; + end + if (RESET_OUTREG != "ASYNC" && RESET_OUTREG != "NONE") begin + $display("ERROR: Illegal RESET_OUTREG setting %s", RESET_OUTREG); + finish_error = 1; + end + if ((WRITE_MODE === "WRITE_FIRST") && (WRITE_WIDTH != READ_WIDTH)) begin + $display("ERROR: WRITE_WIDTH %d must match READ_WIDTH %d in WRITE_FIRST WRITE_MODE", WRITE_WIDTH, READ_WIDTH); + finish_error = 1; + end + + if (finish_error == 1) + #1 $finish(); + + // Initialize memory + for (i=0; i < 256; i=i+1) begin + mem[256*0+i] = INIT_0[i]; + mem[256*1+i] = INIT_1[i]; + mem[256*2+i] = INIT_2[i]; + mem[256*3+i] = INIT_3[i]; + mem[256*4+i] = INIT_4[i]; + mem[256*5+i] = INIT_5[i]; + mem[256*6+i] = INIT_6[i]; + mem[256*7+i] = INIT_7[i]; + mem[256*8+i] = INIT_8[i]; + mem[256*9+i] = INIT_9[i]; + mem[256*10+i] = INIT_A[i]; + mem[256*11+i] = INIT_B[i]; + mem[256*12+i] = INIT_C[i]; + mem[256*13+i] = INIT_D[i]; + mem[256*14+i] = INIT_E[i]; + mem[256*15+i] = INIT_F[i]; + mem[256*16+i] = INIT_10[i]; + mem[256*17+i] = INIT_11[i]; + mem[256*18+i] = INIT_12[i]; + mem[256*19+i] = INIT_13[i]; + mem[256*20+i] = INIT_14[i]; + mem[256*21+i] = INIT_15[i]; + mem[256*22+i] = INIT_16[i]; + mem[256*23+i] = INIT_17[i]; + mem[256*24+i] = INIT_18[i]; + mem[256*25+i] = INIT_19[i]; + mem[256*26+i] = INIT_1A[i]; + mem[256*27+i] = INIT_1B[i]; + mem[256*28+i] = INIT_1C[i]; + mem[256*29+i] = INIT_1D[i]; + mem[256*30+i] = INIT_1E[i]; + mem[256*31+i] = INIT_1F[i]; + mem[256*32+i] = INIT_20[i]; + mem[256*33+i] = INIT_21[i]; + mem[256*34+i] = INIT_22[i]; + mem[256*35+i] = INIT_23[i]; + mem[256*36+i] = INIT_24[i]; + mem[256*37+i] = INIT_25[i]; + mem[256*38+i] = INIT_26[i]; + mem[256*39+i] = INIT_27[i]; + + end + end + + // Wires for the polarity control. + // Only supporting clocks and enable for now + wire WCLK_i, WCLKE_i, WADDREN_i; + wire RCLK_i, RE_i, RCLKE_i, RST_i, RADDREN_i; + wire [1:0] WE_i; + + assign WCLK_i = WCLK_POLARITY ~^ WCLK; + assign WCLKE_i = WCLKE_POLARITY ~^ WCLKE_net; + assign WE_i = WE_POLARITY ~^ WE_net; + assign WADDREN_i = WADDREN_POLARITY ~^ WADDREN_net; + assign RCLK_i = RCLK_POLARITY ~^ RCLK; + assign RE_i = RE_POLARITY ~^ RE_net; + assign RST_i = RST_POLARITY ~^ RST_net; + assign RADDREN_i = RADDREN_POLARITY ~^ RADDREN_net; + + // Wires for the configurable reset controls + wire ram_async_rst, ram_sync_rst, outreg_async_rst; + assign ram_async_rst = (RESET_RAM == "ASYNC") ? RST_i : 1'b0; + assign ram_sync_rst = (RESET_RAM == "SYNC") ? RST_i : 1'b0; + assign outreg_async_rst = (RESET_OUTREG == "ASYNC") ? RST_i : 1'b0; + + ////////////////////////////////////////////////////////////// + // Tasks for actual RAM reading & writing + ////////////////////////////////////////////////////////////// + task read_ram; + input [READ_AWIDTH-1:0] addr; + output [READ_WIDTH-1:0] rdata; + + begin + for (i=0; i < READ_WIDTH; i=i+1) + rdata[i] = mem[addr*READ_WIDTH+i]; + end + endtask + + task write_ram; + input [WRITE_AWIDTH-1:0] addr; + input [WRITE_WIDTH-1:0] wdata; + + begin + for (i=0; i < WRITE_WIDTH; i=i+1) + mem[addr*WRITE_WIDTH+i] = wdata[i]; + end + endtask + + task write_ram_lo; + input [WRITE_AWIDTH-1:0] addr; + input [WRITE_WIDTH-1:0] wdata; + + begin + for (i=0; i < (WRITE_WIDTH/2); i=i+1) + mem[addr*WRITE_WIDTH+i] = wdata[i]; + end + endtask + + task write_ram_hi; + input [WRITE_AWIDTH-1:0] addr; + input [WRITE_WIDTH-1:0] wdata; + + begin + for (i=(WRITE_WIDTH/2); i < WRITE_WIDTH; i=i+1) + mem[addr*WRITE_WIDTH+i] = wdata[i]; + end + endtask + + + always@(posedge WCLK_i) begin + if (WCLKE_i) begin + // Only update the address latch if not stalled + WADDR_r = WADDREN_i ? WADDR_net : WADDR_r; + // #0 delay blocking assignments for coordinating cross port read/write + #0; // Early read + // Write + // Decide if we are writing bytes or the whole data width + if (WRITE_BYTES) begin + if (WE_i[0]) begin + // Write low byte + write_ram_lo(WADDR_r, WDATA); + end + if (WE_i[1]) begin + // Write high byte + write_ram_hi(WADDR_r, WDATA); + end + end + else begin + if (WE_i[0]) begin + // Write full width + write_ram(WADDR_r, WDATA); + end + end + #0; // Late read + end + end + + always@(posedge RCLK_i) begin + if (RE_i) begin + // Update the address latch if reading & not stalled + RADDR_r = RADDREN_i ? RADDR_net : RADDR_r; + + // early read, write and late read + read_ram(RADDR_r, RDATA_early); + #0; // Use #0 delay blocking assignments to allow cross port read/write + #0; // Use #0 delay blocking assignments to allow cross port read/write + read_ram(RADDR_r, RDATA_late); + #0; + end + end + + // Decide which data to output + always@(posedge RCLK_i or posedge ram_async_rst) begin + // Check for async reset + if (ram_async_rst) begin + RDATA_out <= {READ_WIDTH{1'b0}}; + end + else begin + // Delay for the read/write/read to happen + #0; #0; #0; + if (RE_i) begin + // Check for sync reset + if (ram_sync_rst) begin + RDATA_out <= {READ_WIDTH{1'b0}}; + end + else begin + // Based on the write mode decide which read data to use + if (WRITE_MODE == "READ_FIRST") begin + RDATA_out <= RDATA_early; + end + else if (WRITE_MODE == "WRITE_FIRST") begin + RDATA_out <= RDATA_late; + end + else /* (WRITE_MODE == "READ_UNKNOWN") */ begin + RDATA_out <= (RDATA_early === RDATA_late) ? RDATA_early : {READ_WIDTH{1'bx}}; + end + end + end + end + end + + // Optional output register + generate if (OUTPUT_REG) + begin + always@(posedge RCLK_i or posedge outreg_async_rst) begin + if (outreg_async_rst) RDATA_reg <= {READ_WIDTH{1'b0}}; + else if (RE_i) RDATA_reg <= RDATA_out; + end + + assign RDATA = RDATA_reg; + end + else + begin + assign RDATA = RDATA_out; + end // else: !if(OUTPUT_REG) + endgenerate + +endmodule + +////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2017 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +///////////////////////////////////////////////////////////////////////////// diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/efx_ram_5k.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/efx_ram_5k.v new file mode 100644 index 0000000000000000000000000000000000000000..97f1eb60fbe85994433f1eb0c22ec6c3898fb7b3 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/efx_ram_5k.v @@ -0,0 +1,304 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2013-2016 Efinix Inc. All rights reserved. +// +// Efinix Block RAM (BRAM): +// +// This is a 5K simple dual-port RAM +// (one read & one write port) +// +// The read and write ports can +// Be in any of the following WIDTHS +// 16 --> 256x16 +// 8 --> 512x8 +// 4 --> 1024x4 +// 2 --> 2048x2 +// 1 --> 4096x1 +// 20 --> 256x20 +// 10 --> 512x10 +// 5 --> 1024x5 +// +// Writing can be done in one of two READ DURING WRITE MODEs +// READ_FIRST +// WRITE_FIRST +// READ_UNKNOWN +// +// Behavior is undefined when +// reading / writing the same address +// TODO: Need to add address collision checking! +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// ******************************* +///////////////////////////////////////////////////////////////////////////// + +module EFX_RAM_5K +( + WCLK, WE, WCLKE, WDATA, WADDR, + RCLK, RE, RDATA, RADDR +); + + + parameter WCLK_POLARITY = 1'b1; + parameter WCLKE_POLARITY = 1'b1; + parameter WE_POLARITY = 1'b1; + parameter RCLK_POLARITY = 1'b1; + parameter RE_POLARITY = 1'b1; + // Need to add all the data & address input polarity inversion parameters + parameter READ_WIDTH = 16; + parameter WRITE_WIDTH = 16; + parameter OUTPUT_REG = 1'b0; + parameter WRITE_MODE = "READ_FIRST"; + parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + localparam READ_AWIDTH = + (READ_WIDTH == 1) ? 12 : + (READ_WIDTH == 2) ? 11 : + (READ_WIDTH == 4) ? 10 : + (READ_WIDTH == 5) ? 10 : + (READ_WIDTH == 8) ? 9 : + (READ_WIDTH == 10) ? 9 : + (READ_WIDTH == 16) ? 8 : + (READ_WIDTH == 20) ? 8 :-1; + + localparam WRITE_AWIDTH = + (WRITE_WIDTH == 1) ? 12 : + (WRITE_WIDTH == 2) ? 11 : + (WRITE_WIDTH == 4) ? 10 : + (WRITE_WIDTH == 5) ? 10 : + (WRITE_WIDTH == 8) ? 9 : + (WRITE_WIDTH == 10) ? 9 : + (WRITE_WIDTH == 16) ? 8 : + (WRITE_WIDTH == 20) ? 8 :-1; + + localparam MEMORY_SIZE = 256*20; + + input WCLK, WE, WCLKE; + input RCLK, RE; + input [WRITE_WIDTH-1:0] WDATA; + input [WRITE_AWIDTH-1:0] WADDR; + input [READ_AWIDTH-1:0] RADDR; + reg [READ_WIDTH-1:0] RDATA_early, RDATA_late; + reg [READ_WIDTH-1:0] RDATA_out = 0; + reg [READ_WIDTH-1:0] RDATA_reg = 0; + output [READ_WIDTH-1:0] RDATA; + + // Local variables + reg mem [MEMORY_SIZE-1:0]; + integer i; + + // Create nets for optional control inputs + // allows us to assign to them without getting warning + // for coercing input to inout + wire WE_net; + wire WCLKE_net; + wire RE_net; + + // Pull unused address lines low, to mirror EFX synthesis behavior. + wire [WRITE_AWIDTH-1:0] WADDR_net; + wire [READ_AWIDTH-1:0] RADDR_net; + + // Default values for optional control signals + assign (weak0, weak1) WE_net = WE_POLARITY ? 1'b0 : 1'b1; + assign (weak0, weak1) WCLKE_net = WCLKE_POLARITY ? 1'b1 : 1'b0; + assign (weak0, weak1) RE_net = RE_POLARITY ? 1'b1 : 1'b0; + + assign (weak0, weak1) WADDR_net = {WRITE_AWIDTH{1'b0}}; + assign (weak0, weak1) RADDR_net = {READ_AWIDTH{1'b0}}; + + // Now assign the input + assign WE_net = WE; + assign WCLKE_net = WCLKE; + assign RE_net = RE; + + assign WADDR_net = WADDR; + assign RADDR_net = RADDR; + + function COMPATIBLE_WIDTH; + input integer w1, w2; + COMPATIBLE_WIDTH = ((((w1==1)||(w1==2)||(w1==4)||(w1==8)||(w1==16))&&((w2==1)||(w2==2)||(w2==4)||(w2==8)||(w2==16))) || + (((w1==5)||(w1==10)||(w1==20))&&((w2==5)||(w2==10)||(w2==20)))); + endfunction + + initial begin + // Check for illegal modes, address width will be -1 + if (READ_AWIDTH == -1) begin + $display("ERROR:Illegal READ WIDTH %d", READ_WIDTH); + $finish(); + end + if (WRITE_AWIDTH == -1) begin + $display("ERROR:Illegal WRITE WIDTH %d", WRITE_WIDTH); + $finish(); + end + if (~COMPATIBLE_WIDTH(READ_WIDTH,WRITE_WIDTH)) begin + $display("ERROR: READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH, WRITE_WIDTH); + $finish(); + end + // Check for illegal write modes + if (WRITE_MODE != "READ_FIRST" && WRITE_MODE != "WRITE_FIRST" && WRITE_MODE != "READ_UNKNOWN") begin + $display("ERROR:Illegal WRITE_MODE %s", WRITE_MODE); + $finish(); + end + // Initialize memory + for (i=0; i < 256; i=i+1) begin + mem[256*0+i] = INIT_0[i]; + mem[256*1+i] = INIT_1[i]; + mem[256*2+i] = INIT_2[i]; + mem[256*3+i] = INIT_3[i]; + mem[256*4+i] = INIT_4[i]; + mem[256*5+i] = INIT_5[i]; + mem[256*6+i] = INIT_6[i]; + mem[256*7+i] = INIT_7[i]; + mem[256*8+i] = INIT_8[i]; + mem[256*9+i] = INIT_9[i]; + mem[256*10+i] = INIT_A[i]; + mem[256*11+i] = INIT_B[i]; + mem[256*12+i] = INIT_C[i]; + mem[256*13+i] = INIT_D[i]; + mem[256*14+i] = INIT_E[i]; + mem[256*15+i] = INIT_F[i]; + mem[256*16+i] = INIT_10[i]; + mem[256*17+i] = INIT_11[i]; + mem[256*18+i] = INIT_12[i]; + mem[256*19+i] = INIT_13[i]; + end + end + + // Wires for the polarity control. + // Only supporting clocks and enable for now + wire WCLK_i, WE_i, WCLKE_i; + wire RCLK_i, RE_i, RCLKE_i; + + assign WCLK_i = WCLK_POLARITY ? WCLK : ~WCLK; + assign WCLKE_i = WCLKE_POLARITY ? WCLKE_net : ~WCLKE_net; + assign WE_i = WE_POLARITY ? WE_net : ~WE_net; + assign RCLK_i = RCLK_POLARITY ? RCLK : ~RCLK; + assign RE_i = RE_POLARITY ? RE_net : ~RE_net; + + ////////////////////////////////////////////////////////////// + // Tasks for actual RAM reading & writing + ////////////////////////////////////////////////////////////// + task read_ram; + input [READ_AWIDTH-1:0] addr; + output [READ_WIDTH-1:0] rdata; + + begin + for (i=0; i < READ_WIDTH; i=i+1) + rdata[i] = mem[addr*READ_WIDTH+i]; + end + endtask + + task write_ram; + input [WRITE_AWIDTH-1:0] addr; + input [WRITE_WIDTH-1:0] wdata; + + begin + for (i=0; i < WRITE_WIDTH; i=i+1) + mem[addr*WRITE_WIDTH+i] = wdata[i]; + end + endtask + + always@(posedge WCLK_i) + if (WE_i & WCLKE_i) begin + // Do an early read, write and late read + // Then decide what do do with the read data + #0; // Use #0 delay blocking assignments to allow cross port read/write + write_ram(WADDR_net, WDATA); + #0; // Use #0 delay blocking assignments to allow cross port read/write + end + + always@(posedge RCLK_i) + if (RE_i) begin + // Do an early read, write and late read + // Then decide what do do with the read data + read_ram(RADDR_net, RDATA_early); + #0; // Use #0 delay blocking assignments to allow cross port read/write + #0; // Use #0 delay blocking assignments to allow cross port read/write + read_ram(RADDR_net, RDATA_late); + + // Based on the write mode decide which read data to use + if (WRITE_MODE == "READ_FIRST") begin + RDATA_out = RDATA_early; + end + else if (WRITE_MODE == "WRITE_FIRST") begin + RDATA_out = RDATA_late; + end + else /* (WRITE_MODE == "READ_UNKNOWN") */ begin + RDATA_out = (RDATA_early === RDATA_late) ? RDATA_early : {READ_WIDTH{1'bx}}; + end + end + + // Optional output register + generate if (OUTPUT_REG) + begin + always@(posedge RCLK_i) + RDATA_reg <= RDATA_out; + + assign RDATA = RDATA_reg; + end + else + begin + assign RDATA = RDATA_out; + end // else: !if(OUTPUT_REG) + endgenerate + +endmodule // EFX_RAM_5K + +////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2017 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +///////////////////////////////////////////////////////////////////////////// diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/monitor_sdp.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/monitor_sdp.v new file mode 100644 index 0000000000000000000000000000000000000000..f2a67c5517b3fb7b3019dd67ff4fd7685461b727 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/monitor_sdp.v @@ -0,0 +1,311 @@ + +module monitor_sdp ( + rclk, + wclk, + bram_rst, + rdata_b, + wclke, + we, + re, + waddr, + raddr, + byteen, + wdata_a, + waddren, + raddren +); +//`include "bram_decompose.vh" +parameter CLK_MODE = 2; +parameter MEMORY_TYPE = "SP_RAM"; // 1:SP_RAM, 2:SDP_RAM, 3:TDP_RAM +parameter RESET_RAM = "ASYNC"; +parameter RESET_OUTREG = "ASYNC"; +parameter [0:0] WCLK_POLARITY = 1'b1; +parameter [0:0] RCLK_POLARITY = 1'b1; +parameter [0:0] WCLKE_POLARITY = 1'b1; +parameter [0:0] WE_POLARITY = 1'b1; +parameter [0:0] RE_POLARITY = 1'b1; +parameter [0:0] OUTPUT_REG = 1'b1; +parameter [0:0] BYTEEN_POLARITY = 1'b1; +parameter [0:0] WADDREN_POLARITY = 1'b1; +parameter [0:0] RADDREN_POLARITY = 1'b1; +parameter [0:0] WCLKE_ENABLE = 1'b1; +parameter [0:0] WE_ENABLE = 1'b1; +parameter [0:0] RE_ENABLE = 1'b1; +parameter [0:0] BYTEEN_ENABLE = 1'b1; +parameter [0:0] RST_POLARITY = 1'b1; +parameter [0:0] RESET_ENABLE = 1'b1; +parameter [0:0] WADDREN_ENABLE = 1'b1; +parameter [0:0] RADDREN_ENABLE = 1'b1; + +parameter DATA_WIDTH_A = 16; +parameter DATA_WIDTH_B = 16; +parameter ADDR_WIDTH_A = 4; +parameter ADDR_WIDTH_B = 4; +parameter BYTEEN_WIDTH = 2; +parameter GROUP_DATA_WIDTH = 8; +parameter FAMILY = "TITANIUM"; // 0:TRION, 1:TITANIUM +parameter WRITE_MODE = "READ_FIRST"; + +input wclk; +input rclk; +input bram_rst; +input [DATA_WIDTH_B-1:0] rdata_b; +input wclke; +input we; +input re; +input [ADDR_WIDTH_A-1:0] waddr; +input [ADDR_WIDTH_B-1:0] raddr; +input [BYTEEN_WIDTH-1:0] byteen; +input [DATA_WIDTH_A-1:0] wdata_a; +//Titanium extra ports +input waddren; +input raddren; + + + +wire rclk_i; +wire wclk_i; +assign rclk_i = RCLK_POLARITY ^~ rclk; +assign wclk_i = WCLK_POLARITY ^~ wclk; + +localparam DEPTH = 2**ADDR_WIDTH_A; +reg [DATA_WIDTH_A-1:0] mem[0:DEPTH-1]; +reg [ADDR_WIDTH_B-1:0] raddr_r = 0; +reg [ADDR_WIDTH_A-1:0] waddr_r = 0; +wire w_waddren; +wire w_raddren; +assign w_waddren = FAMILY == "TRION" ? WADDREN_POLARITY : waddren; +assign w_raddren = FAMILY == "TRION" ? RADDREN_POLARITY : raddren; + +reg [DATA_WIDTH_A-1:0] mask_wdata; +reg [ADDR_WIDTH_A-1:0] waddr_i; +reg [ADDR_WIDTH_B-1:0] raddr_i; +reg [DATA_WIDTH_B-1:0] exp_rdata_r1 = 0; +reg [DATA_WIDTH_B-1:0] exp_rdata_r2 = 0; +reg dont_care_r1 = 0; +reg dont_care_r2 = 0; +reg re_r1 = ~RE_POLARITY; +reg re_r2 = ~RE_POLARITY; +reg we_r1 = ~WE_POLARITY; +reg we_r2 = ~WE_POLARITY; +reg wclke_r1 = ~WCLKE_POLARITY; +reg wclke_r2 = ~WCLKE_POLARITY; +reg [DATA_WIDTH_A-1:0] wdata_r1 = 0; +reg [DATA_WIDTH_A-1:0] wdata_r2 = 0; + +wire [DATA_WIDTH_B-1:0] final_exp_rdata; +wire final_re; +wire final_we; +wire final_wclke; +wire final_dont_care; +integer i = 0; +integer success_cnt = 0; +integer failure_cnt = 0; +reg error_occur = 0; +integer stop_cnt = 0; + +localparam WR_RATIO = (DATA_WIDTH_A / DATA_WIDTH_B); +localparam RW_RATIO = (DATA_WIDTH_B / DATA_WIDTH_A); +localparam WR_RATIO_WID = $clog2(WR_RATIO); +localparam RW_RATIO_WID = $clog2(RW_RATIO); +localparam DATA_WIDTH_MAX = DATA_WIDTH_A > DATA_WIDTH_B ? DATA_WIDTH_A : DATA_WIDTH_B; +localparam RATIO_WID = WR_RATIO_WID > RW_RATIO_WID ? WR_RATIO_WID : RW_RATIO_WID == 0 ? 1 : RW_RATIO_WID; +localparam BYTE_LAST = (BYTEEN_WIDTH-1)*GROUP_DATA_WIDTH >= 0 ? (BYTEEN_WIDTH-1)*GROUP_DATA_WIDTH : 0; + +wire [RATIO_WID-1:0] data_sel; +generate + if (WR_RATIO == 1) begin + assign data_sel = 0; + end else if (WR_RATIO > 1) begin + assign data_sel = raddr_i[WR_RATIO_WID-1:0]; + end else begin + assign data_sel = waddr_i[RW_RATIO_WID-1:0]; + end +endgenerate + + +function [DATA_WIDTH_B-1:0] get_rdata(input [ADDR_WIDTH_B-1:0] addr); + integer i; + integer mem_addr; + reg [DATA_WIDTH_MAX-1:0] temp; + begin + if (WR_RATIO >= 1) begin //write data width >= read data width + mem_addr = addr >> WR_RATIO_WID; + temp = mem[mem_addr]; + get_rdata = temp[data_sel*DATA_WIDTH_B +: DATA_WIDTH_B]; + end else begin + mem_addr = addr << RW_RATIO_WID; + for (i=0 ; i 0 && RW_RATIO_WID != 0) || (RW_RATIO_WID > 0 && WR_RATIO_WID != 0)) begin + $error("Unexpected Write Read Ratio. WR_RATIO: %d, RW_RATIO: %d, WR_RATIO_WID: %d, RW_RATIO_WID: %d", + WR_RATIO, RW_RATIO, WR_RATIO_WID, RW_RATIO_WID); + #10 $stop; + end +end + +always @(*) begin + if (w_waddren == WADDREN_POLARITY && wclke == WCLKE_POLARITY) + waddr_i = waddr; + else + waddr_i = waddr_r; + + if (w_raddren == RADDREN_POLARITY && re == RE_POLARITY) + raddr_i = raddr; + else + raddr_i = raddr_r; + + mask_wdata = mem[waddr_i]; + + for(i=0 ; i> WR_RATIO_WID) == (waddr_i >> RW_RATIO_WID) && wclke == WCLKE_POLARITY && we == WE_POLARITY && !(MEMORY_TYPE == "SP_ROM")) begin +// verilator lint_off SELRANGE + if (WR_RATIO >= 1) begin //data width of write port >= read port + exp_rdata_r1 <= mask_wdata[data_sel*DATA_WIDTH_B +: DATA_WIDTH_B]; + end else begin + exp_rdata_r1 <= get_rdata(raddr_i); + exp_rdata_r1[data_sel*DATA_WIDTH_A +: DATA_WIDTH_A] <= mask_wdata; +// verilator lint_on SELRANGE + end + end else begin + exp_rdata_r1 <= get_rdata(raddr_i); + end + end + + "READ_FIRST": begin + exp_rdata_r1 <= get_rdata(raddr_i); + end + + "READ_UNKNOWN": begin + if ((raddr_i >> WR_RATIO_WID) == (waddr_i >> RW_RATIO_WID) && wclke == WCLKE_POLARITY && we == WE_POLARITY && !(MEMORY_TYPE == "SP_ROM")) begin + exp_rdata_r1 <= {DATA_WIDTH_B{1'bx}}; + dont_care_r1 <= 1; + end else begin + exp_rdata_r1 <= get_rdata(raddr_i); + end + end + endcase + end + end +end + +always @(*) begin + if (FAMILY == "TITANIUM" && bram_rst == RST_POLARITY) begin + exp_rdata_r1 <= {DATA_WIDTH_B{1'b0}}; + end +end + +always @(posedge rclk_i) begin //verify WRITE_MODE + if (final_dont_care) begin + //pass + end else begin + if (final_exp_rdata === rdata_b) begin + $display("%t ps - PASS! BRAM read data %h is match expected data %h ", $time(), rdata_b, final_exp_rdata); + success_cnt <= success_cnt + 1; + + end else if (final_exp_rdata === {DATA_WIDTH_B{1'bx}} && rdata_b === {DATA_WIDTH_B{1'b0}}) //expected condition when initiated memory is less than BRAM depth + begin + $display("Warning check: user .mem file content less than BRAM depth"); + $display("Testbench proceed\n"); + success_cnt <= success_cnt + 1; + + end else begin + $error("%t ps - FAIL! BRAM read data %h doesn't match expected data %h ", $time(), rdata_b, final_exp_rdata); + $display("INFO: FAMILY: %s, MEMORY_TYPE: %s, WRITE_MODE: %s, ADDR_WIDTH_A: %d, DATA_WIDTH_B: %d, ADDR_WIDTH_B: %d, DATA_WIDTH_A: %d, GROUP_DATA_WIDTH: %d, ", FAMILY, MEMORY_TYPE, WRITE_MODE, ADDR_WIDTH_A, DATA_WIDTH_B, ADDR_WIDTH_B, DATA_WIDTH_A, GROUP_DATA_WIDTH); + error_occur <= 1; + end + end +end + +always @(posedge rclk_i) begin + if (error_occur) begin + stop_cnt <= stop_cnt + 1; + if (stop_cnt >= 10) + $stop; + end +end +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/monitor_sp.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/monitor_sp.v new file mode 100644 index 0000000000000000000000000000000000000000..966a2527cd14618661a9100af01474ce7f2e8a77 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/monitor_sp.v @@ -0,0 +1,246 @@ + +module monitor_sp ( + clk, + bram_rst, + rdata_a, + wclke, + we, + re, + addr, + byteen, + wdata_a, + addren +); +//`include "bram_decompose.vh" +parameter MEMORY_TYPE = "SP_RAM"; +parameter RESET_RAM = "ASYNC"; +parameter RESET_OUTREG = "ASYNC"; +parameter [0:0] CLK_POLARITY = 1'b1; +parameter [0:0] WCLKE_POLARITY = 1'b1; +parameter [0:0] WE_POLARITY = 1'b1; +parameter [0:0] RE_POLARITY = 1'b1; +parameter [0:0] OUTPUT_REG = 1'b1; +parameter [0:0] BYTEEN_POLARITY = 1'b1; +parameter [0:0] WCLKE_ENABLE = 1'b1; +parameter [0:0] WE_ENABLE = 1'b1; +parameter [0:0] RE_ENABLE = 1'b1; +parameter [0:0] BYTEEN_ENABLE = 1'b1; +parameter [0:0] RST_POLARITY = 1'b1; +parameter [0:0] ADDREN_POLARITY = 1'b1; +parameter [0:0] RESET_ENABLE = 1'b1; +parameter [0:0] ADDREN_ENABLE = 1'b1; + +parameter DATA_WIDTH_A = 16; +parameter DATA_WIDTH_B = 16; +parameter ADDR_WIDTH_A = 4; +parameter BYTEEN_WIDTH = 2; +parameter GROUP_DATA_WIDTH = 8; +parameter FAMILY = "TITANIUM"; // 0:TRION, 1:TITANIUM +parameter WRITE_MODE = "READ_FIRST"; + + +input clk; +input bram_rst; +input [DATA_WIDTH_A-1:0] rdata_a; +input wclke; +input we; +input re; +input [ADDR_WIDTH_A-1:0] addr; +input [BYTEEN_WIDTH-1:0] byteen; +input [DATA_WIDTH_A-1:0] wdata_a; +//Titanium extra ports +input addren; + + + +wire clk_i; +assign clk_i = CLK_POLARITY ~^ clk; + +localparam DEPTH = 2**ADDR_WIDTH_A; +reg [DATA_WIDTH_A-1:0] mem[0:DEPTH-1]; +reg [ADDR_WIDTH_A-1:0] raddr_r = 0; +reg [ADDR_WIDTH_A-1:0] waddr_r = 0; +wire w_addren; +assign w_addren = FAMILY == "TRION" ? ADDREN_POLARITY : addren; + +reg [DATA_WIDTH_A-1:0] mask_wdata; +reg [ADDR_WIDTH_A-1:0] waddr_i; +reg [ADDR_WIDTH_A-1:0] raddr_i; +reg [DATA_WIDTH_A-1:0] exp_rdata_r1 = 0; +reg [DATA_WIDTH_A-1:0] exp_rdata_r2 = 0; +reg dont_care_r1 = 0; +reg dont_care_r2 = 0; +reg re_r1 = ~RE_POLARITY; +reg re_r2 = ~RE_POLARITY; +reg we_r1 = ~WE_POLARITY; +reg we_r2 = ~WE_POLARITY; +reg wclke_r1 = ~WCLKE_POLARITY; +reg wclke_r2 = ~WCLKE_POLARITY; +reg [DATA_WIDTH_A-1:0] wdata_r1 = 0; +reg [DATA_WIDTH_A-1:0] wdata_r2 = 0; + +wire [DATA_WIDTH_A-1:0] final_exp_rdata; +wire final_re; +wire final_we; +wire final_wclke; +wire final_dont_care; +integer i = 0; +integer success_cnt = 0; +integer failure_cnt = 0; +reg error_occur = 0; +integer stop_cnt = 0; + +initial begin + $readmemh("init_hex.mem", mem); +end + +always @(*) begin + if (w_addren == ADDREN_POLARITY && wclke == WCLKE_POLARITY) + waddr_i = addr; + else + waddr_i = waddr_r; + + if (w_addren == ADDREN_POLARITY && re == RE_POLARITY) + raddr_i = addr; + else + raddr_i = raddr_r; + + mask_wdata = mem[waddr_i]; + + for(i=0 ; i= 10) + $stop; + end +end +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/monitor_tdp.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/monitor_tdp.v new file mode 100644 index 0000000000000000000000000000000000000000..8d252971bd7a4111155542f4fb0f2b0b4ab1bee2 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/monitor_tdp.v @@ -0,0 +1,510 @@ + +//TODO: separate RAM models and checking logic +module monitor_tdp ( + //Trion and Titanium ports + clk_a, // A-port clk + rdata_a, // A-port read address output + clke_a, // A-port clk enable + byteen_a, // A-port Byteen input + we_a, // A-port write enable + addr_a, // A-port address input + wdata_a, // A-port write data input + state_a, + + clk_b, // B-port clk + rdata_b, // B-port read address output + clke_b, // B-port clk enable + byteen_b, // B-port Byteen input + we_b, // B-port write enable + addr_b, // B-port address input + wdata_b, // B-port write data input + state_b, + + //Titanium extra ports + bram_rst_a, // A-port reset + addren_a, // A-port address enable + + bram_rst_b, // B-port reset + addren_b // B-port address enable +); +//`include "bram_decompose.vh" +parameter MEMORY_TYPE = "SP_RAM"; // 1:SP_RAM, 2:SDP_RAM, 3:TDP_RAM +parameter CLK_MODE = 2; +//Trion and Titanium parameters +parameter CLKA_POLARITY = 1'b1; +parameter CLKEA_POLARITY = 1'b1; +parameter WEA_POLARITY = 1'b1; +parameter OUTPUT_REG_A = 1'b1; +parameter [0:0] BYTEENA_POLARITY = 1'b1; +parameter CLKB_POLARITY = 1'b1; +parameter CLKEB_POLARITY = 1'b1; +parameter WEB_POLARITY = 1'b1; +parameter OUTPUT_REG_B = 1'b1; +parameter [0:0] BYTEENB_POLARITY = 1'b1; +//Port Enable +parameter CLKEA_ENABLE = 1'b1; +parameter WEA_ENABLE = 1'b1; +parameter BYTEENA_ENABLE = 1'b1; +parameter CLKEB_ENABLE = 1'b1; +parameter WEB_ENABLE = 1'b1; +parameter BYTEENB_ENABLE = 1'b1; +//Titanium extra paramters +parameter RSTA_POLARITY = 1'b1; +parameter RESET_RAM_A = "SYNC"; +parameter RESET_OUTREG_A = "NONE"; +parameter ADDRENA_POLARITY = 1'b1; +parameter RSTB_POLARITY = 1'b1; +parameter RESET_RAM_B = "SYNC"; +parameter RESET_OUTREG_B = "NONE"; +parameter ADDRENB_POLARITY = 1'b1; +//Port Enable +parameter RESET_A_ENABLE = 1'b1; +parameter ADDREN_A_ENABLE = 1'b1; +parameter RESET_B_ENABLE = 1'b1; +parameter ADDREN_B_ENABLE = 1'b1; + +parameter DATA_WIDTH_A = 16; +parameter DATA_WIDTH_B = 16; +parameter ADDR_WIDTH_A = 4; +parameter ADDR_WIDTH_B = 4; +parameter BYTEEN_WIDTH_A = 2; +parameter BYTEEN_WIDTH_B = 2; +parameter GROUP_DATA_WIDTH_A = 8; +parameter GROUP_DATA_WIDTH_B = 8; +parameter WRITE_MODE_A = "READ_FIRST"; +parameter WRITE_MODE_B = "READ_FIRST"; +parameter FAMILY = "TITANIUM"; + +input clk_a; +input [DATA_WIDTH_A-1:0 ] rdata_a; +input clke_a; +input we_a; +input [BYTEEN_WIDTH_A-1:0] byteen_a; +input [ADDR_WIDTH_A-1:0 ] addr_a; +input [DATA_WIDTH_A-1:0 ] wdata_a; +input bram_rst_a; +input addren_a; +input signed [31:0] state_a; + +input clk_b; +input [DATA_WIDTH_B-1:0 ] rdata_b; +input clke_b; +input we_b; +input [BYTEEN_WIDTH_B-1:0] byteen_b; +input [ADDR_WIDTH_B-1:0 ] addr_b; +input [DATA_WIDTH_B-1:0 ] wdata_b; +input bram_rst_b; +input addren_b; +input signed [31:0] state_b; + +//localparam WRITE_MODE_B = DECOMPOSE_WRITE_MODE; +//localparam WRITE_MODE_A = DECOMPOSE_WRITE_MODE; + +wire clk_a_i; +wire clk_b_i; +wire we_a_i; +wire we_b_i; +wire addren_a_i; +wire addren_b_i; +wire bram_rst_a_i; +wire bram_rst_b_i; +wire clke_a_i; +wire clke_b_i; +wire [BYTEEN_WIDTH_A-1:0] byteen_a_i; +wire [BYTEEN_WIDTH_B-1:0] byteen_b_i; +assign clk_a_i = CLKA_POLARITY ~^ clk_a; +assign clk_b_i = CLKB_POLARITY ~^ clk_b; +assign we_a_i = WEA_POLARITY ~^ we_a; +assign we_b_i = WEB_POLARITY ~^ we_b; +assign addren_a_i = FAMILY == "TRION" ? 1'b1 : ADDRENA_POLARITY ~^ addren_a; +assign addren_b_i = FAMILY == "TRION" ? 1'b1 : ADDRENB_POLARITY ~^ addren_b; +assign bram_rst_a_i = RSTA_POLARITY ~^ bram_rst_a; +assign bram_rst_b_i = RSTB_POLARITY ~^ bram_rst_b; +assign clke_a_i = (MEMORY_TYPE == "TDP_RAM")? CLKEA_POLARITY ~^ clke_a: CLKEA_POLARITY; +assign clke_b_i = (MEMORY_TYPE == "TDP_RAM")? CLKEB_POLARITY ~^ clke_b: CLKEB_POLARITY; +assign byteen_a_i = {BYTEEN_WIDTH_A{BYTEENA_POLARITY}} ~^ byteen_a; +assign byteen_b_i = {BYTEEN_WIDTH_B{BYTEENB_POLARITY}} ~^ byteen_b; + +localparam DEPTH_A = 2**ADDR_WIDTH_A; +localparam DEPTH_B = 2**ADDR_WIDTH_B; +localparam DWA = DATA_WIDTH_A; +localparam DWB = DATA_WIDTH_B; +localparam AB_RATIO = (DATA_WIDTH_A / DATA_WIDTH_B); +localparam BA_RATIO = (DATA_WIDTH_B / DATA_WIDTH_A); +localparam AB_RATIO_WID = $clog2(AB_RATIO); +localparam BA_RATIO_WID = $clog2(BA_RATIO); +localparam DATA_WIDTH_MAX = DATA_WIDTH_A > DATA_WIDTH_B ? DATA_WIDTH_A : DATA_WIDTH_B; +localparam RATIO_WID = AB_RATIO_WID > BA_RATIO_WID ? AB_RATIO_WID : BA_RATIO_WID == 0 ? 1 : BA_RATIO_WID; +reg [DATA_WIDTH_A-1:0] mem_reg[DEPTH_A-1:0]; +reg [DATA_WIDTH_A*DEPTH_A-1:0] mem; +reg [ADDR_WIDTH_A-1:0] r_addr_a = 0; +reg [ADDR_WIDTH_B-1:0] r_addr_b = 0; + +reg [DATA_WIDTH_A-1:0] mask_wdata_a; +reg [DATA_WIDTH_B-1:0] mask_wdata_b; +reg [DATA_WIDTH_A-1:0] mask_wdata_temp_a; +reg [DATA_WIDTH_B-1:0] mask_wdata_temp_b; +reg [ADDR_WIDTH_A-1:0] addr_a_i; +reg [ADDR_WIDTH_B-1:0] addr_b_i; +reg [ADDR_WIDTH_A-1:0] addr_a_r1 = 0; +reg [ADDR_WIDTH_B-1:0] addr_b_r1 = 0; +reg [ADDR_WIDTH_A-1:0] addr_a_r2 = 0; +reg [ADDR_WIDTH_B-1:0] addr_b_r2 = 0; +reg [DATA_WIDTH_A-1:0] exp_rdata_a_r1 = 0; +reg [DATA_WIDTH_A-1:0] exp_rdata_a_r2 = 0; +reg we_a_r1 = 0; +reg we_a_r2 = 0; +reg wclke_a_r1 = 0; +reg wclke_a_r2 = 0; +reg [DATA_WIDTH_A-1:0] wdata_a_r1 = 0; +reg [DATA_WIDTH_A-1:0] wdata_a_r2 = 0; +reg [DATA_WIDTH_B-1:0] exp_rdata_b_r1 = 0; +reg [DATA_WIDTH_B-1:0] exp_rdata_b_r2 = 0; +reg we_b_r1 = 0; +reg we_b_r2 = 0; +reg wclke_b_r1 = 0; +reg wclke_b_r2 = 0; +reg [DATA_WIDTH_B-1:0] wdata_b_r1 = 0; +reg [DATA_WIDTH_B-1:0] wdata_b_r2 = 0; + +wire [DATA_WIDTH_A-1:0] final_exp_rdata_a; +wire [DATA_WIDTH_B-1:0] final_exp_rdata_b; +wire final_we_a; +wire final_we_b; +wire final_clke_a; +wire final_clke_b; +wire wr_same_addr; +wire [RATIO_WID-1:0] data_sel; +assign wr_same_addr = addr_a_i >> BA_RATIO_WID == addr_b_i >> AB_RATIO_WID; +integer i = 0; +integer success_cnt = 0; +integer failure_cnt = 0; +integer collision_cnt = 0; + +generate + if (AB_RATIO == 1) begin + assign data_sel = 0; + end else if (AB_RATIO > 1) begin + assign data_sel = addr_b_i[AB_RATIO_WID-1:0]; + end else begin + assign data_sel = addr_a_i[BA_RATIO_WID-1:0]; + end +endgenerate + + +initial begin + $readmemh("init_hex.mem", mem_reg); + + for (i=0; i 0 && BA_RATIO_WID != 0) || + (BA_RATIO_WID > 0 && AB_RATIO_WID != 0)) begin + $error("Unexpected Write Read Ratio. AB_RATIO: %0d, BA_RATIO: %0d, AB_RATIO_WID: %0d, BA_RATIO_WID: %0d", + AB_RATIO, BA_RATIO, AB_RATIO_WID, BA_RATIO_WID); + #10 $stop; + end + + if (DATA_WIDTH_A*DEPTH_A != DATA_WIDTH_B*DEPTH_B) begin + $error("Size of Port A and Port B mismatch. DATA_WIDTH_A: %0d, DEPTH_A: %0d, DATA_WIDTH_B: %0d, DEPTH_B: %0d", DATA_WIDTH_A, DEPTH_A, DATA_WIDTH_B, DEPTH_B); + #10 $stop; + end + + if ($rtoi($ceil($itor(DATA_WIDTH_A)/GROUP_DATA_WIDTH_A)) != BYTEEN_WIDTH_A) begin + $error("byte enable width of Port A mismatch. DATA_WIDTH_A: %0d, GROUP_DATA_WIDTH_A: %0d, BYTEEN_WIDTH_A: %0d", DATA_WIDTH_A, GROUP_DATA_WIDTH_A, BYTEEN_WIDTH_A); + #10 $stop; + end + + if ($rtoi($ceil($itor(DATA_WIDTH_B)/GROUP_DATA_WIDTH_B)) != BYTEEN_WIDTH_B) begin + $error("byte enable width of Port B mismatch. DATA_WIDTH_B: %0d, GROUP_DATA_WIDTH_B: %0d, BYTEEN_WIDTH_B: %0d", DATA_WIDTH_B, GROUP_DATA_WIDTH_B, BYTEEN_WIDTH_B); + #10 $stop; + end +end + +generate + //port a + if (OUTPUT_REG_A) begin + assign final_exp_rdata_a = exp_rdata_a_r2; + assign final_we_a = we_a_r2; + assign final_clke_a = wclke_a_r2; + end else begin + assign final_exp_rdata_a = exp_rdata_a_r1; + assign final_we_a = we_a_r1; + assign final_clke_a = wclke_a_r1; + end + + //port b + if (OUTPUT_REG_B) begin + assign final_exp_rdata_b = exp_rdata_b_r2; + assign final_we_b = we_b_r2; + assign final_clke_b = wclke_b_r2; + end else begin + assign final_exp_rdata_b = exp_rdata_b_r1; + assign final_we_b = we_b_r1; + assign final_clke_b = wclke_b_r1; + end +endgenerate + + +always @(*) begin //port a b + if (addren_a_i && clke_a_i) + addr_a_i = addr_a; + else + addr_a_i = r_addr_a; + + if (addren_b_i && clke_b_i) + addr_b_i = addr_b; + else + addr_b_i = r_addr_b; + + mask_wdata_temp_a = mem[addr_a_i*DWA +: DWA]; + mask_wdata_temp_b = mem[addr_b_i*DWB +: DWB]; + + for(i=0 ; i= 1) begin //data width of port a >= port b + if (mask_wdata_temp_a[data_sel*DWB +: DWB] == mask_wdata_temp_b) + mask_wdata_b = mask_wdata_temp_b; + else + mask_wdata_b = {DWB{1'bx}}; + end else begin + if (mask_wdata_b[data_sel*DWA +: DWA] == mask_wdata_temp_a) + mask_wdata_b[data_sel*DWA +: DWA] = mask_wdata_temp_b[data_sel*DWA +: DWA]; + else + mask_wdata_b[data_sel*DWA +: DWA] = {DWA{1'bx}}; + end + end + + if (wr_same_addr && clke_a_i && we_a_i && clke_b_i && we_b_i) begin //addra & b may have different width + if (AB_RATIO >= 1) begin //data width of port a >= port b + if (mask_wdata_a[data_sel*DWB +: DWB] == mask_wdata_temp_b) + mask_wdata_a[data_sel*DWB +: DWB] = mask_wdata_temp_a[data_sel*DWB +: DWB]; + else + mask_wdata_a[data_sel*DWB +: DWB] = {DWB{1'bx}}; + end else begin + if (mask_wdata_b[data_sel*DWA +: DWA] == mask_wdata_temp_a) + mask_wdata_a = mask_wdata_temp_a; + else + mask_wdata_a = {DWA{1'bx}}; + end + end +end + +always @(posedge clk_a_i) begin + if (clke_a_i && we_a_i && !(MEMORY_TYPE == "DP_ROM")) begin + mem[addr_a_i*DWA +: DWA] <= mask_wdata_a; + + if (wr_same_addr) + collision_cnt <= collision_cnt + 1; + end +end + +always @(posedge clk_b_i) begin + if (clke_b_i && we_b_i && !(MEMORY_TYPE == "DP_ROM")) begin + mem[addr_b_i*DWB +: DWB] <= mask_wdata_b; + end +end + +always @(posedge clk_a_i) begin + addr_a_r1 <= addr_a_i; + wdata_a_r1 <= wdata_a; + we_a_r1 <= we_a_i; + wclke_a_r1 <= clke_a_i; + addr_a_r2 <= addr_a_r1; + wdata_a_r2 <= wdata_a_r1; + we_a_r2 <= we_a_r1; + wclke_a_r2 <= wclke_a_r1; + + if (addren_a_i && clke_a_i) begin + r_addr_a <= addr_a; + end + + if (FAMILY == "TITANIUM") begin + if (clke_a_i) begin + exp_rdata_a_r2 <= exp_rdata_a_r1; + end + end else begin //clock enable doesn't affect output registers in Trion + exp_rdata_a_r2 <= exp_rdata_a_r1; + end + + if (clke_a_i) begin + if (FAMILY == "TITANIUM" && bram_rst_a_i) begin + exp_rdata_a_r1 <= {DWA{1'b0}}; + end else begin + case (WRITE_MODE_A) + "WRITE_FIRST": begin + if (!we_a_i) begin + if (clke_b_i && we_b_i && wr_same_addr) begin + if (AB_RATIO >= 1) begin + exp_rdata_a_r1 <= mem[addr_a_i*DWA +: DWA]; + exp_rdata_a_r1[data_sel*DWB +: DWB] <= mask_wdata_b; + end else begin + exp_rdata_a_r1 <= mask_wdata_b[data_sel*DWA +: DWA]; + end + end else begin + exp_rdata_a_r1 <= mem[addr_a_i*DWA +: DWA]; + end + end else if (we_a_i && !(MEMORY_TYPE == "DP_ROM")) begin + exp_rdata_a_r1 <= mask_wdata_a; + end + end + + "READ_FIRST": begin + exp_rdata_a_r1 <= mem[addr_a_i*DWA +: DWA]; + end + + "NO_CHANGE": begin + if (!we_a_i) begin + exp_rdata_a_r1 <= mem[addr_a_i*DWA +: DWA]; + end else if (!(MEMORY_TYPE == "DP_ROM")) begin + exp_rdata_a_r1 <= exp_rdata_a_r1; + end + end + endcase + end + end +end + +always @(posedge clk_b_i) begin + addr_b_r1 <= addr_b_i; + wdata_b_r1 <= wdata_b; + we_b_r1 <= we_b_i; + wclke_b_r1 <= clke_b_i; + addr_b_r2 <= addr_b_r1; + wdata_b_r2 <= wdata_b_r1; + we_b_r2 <= we_b_r1; + wclke_b_r2 <= wclke_b_r1; + + if (addren_b_i && clke_b_i) begin + r_addr_b <= addr_b; + end + + if (FAMILY == "TITANIUM") begin + if (clke_b_i) begin + exp_rdata_b_r2 <= exp_rdata_b_r1; + end + end else begin //clock enable doesn't affect output registers in Trion + exp_rdata_b_r2 <= exp_rdata_b_r1; + end + + if (clke_b_i) begin + if (FAMILY == "TITANIUM" && bram_rst_b_i) begin + exp_rdata_b_r1 <= {DWB{1'b0}}; + end else begin + case (WRITE_MODE_B) + "WRITE_FIRST": begin + if (!we_b_i) begin + if (clke_a_i && we_a_i && wr_same_addr) begin + if (AB_RATIO >= 1) begin + exp_rdata_b_r1 <= mask_wdata_a[data_sel*DWB +: DWB]; + end else begin + exp_rdata_b_r1 <= mem[addr_b_i*DWB +: DWB]; + exp_rdata_b_r1[data_sel*DWA +: DWA] <= mask_wdata_a; + end + end else begin + exp_rdata_b_r1 <= mem[addr_b_i*DWB +: DWB]; + end + end else if (we_b_i && !(MEMORY_TYPE == "DP_ROM")) begin + exp_rdata_b_r1 <= mask_wdata_b; + end + end + + "READ_FIRST": begin + exp_rdata_b_r1 <= mem[addr_b_i*DWB +: DWB]; + end + + "NO_CHANGE": begin + if (!we_b_i) begin + exp_rdata_b_r1 <= mem[addr_b_i*DWB +: DWB]; + end else if (!(MEMORY_TYPE == "DP_ROM")) begin + exp_rdata_b_r1 <= exp_rdata_b_r1; + end + end + endcase + end + end +end + +always @(*) begin + if (FAMILY == "TITANIUM" && bram_rst_a_i) begin + exp_rdata_a_r1 <= {DWA{1'b0}}; + end + + if (FAMILY == "TITANIUM" && bram_rst_b_i) begin + exp_rdata_b_r1 <= {DWB{1'b0}}; + end +end + + +integer acnt = 0; +always @(posedge clk_a_i) begin //verify WRITE_MODE + if (state_a != 0) begin + for(acnt=0 ; acnt1) + begin + assign w_we_a[1] = ( (we_a == WEA_POLARITY) & wen_decode_a[WRSEL_INDEX_A] & (byteen_a[BYTEEN_INDEX_A] == BYTEENA_POLARITY) ) ? WEA_POLARITY: !WEA_POLARITY; + end + + assign w_we_b[0] = ( (we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY) ) ? WEB_POLARITY: !WEB_POLARITY; + if ( WEN_WIDTH_ROW_B >1) + begin + assign w_we_b[1] =((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY) )? WEB_POLARITY: !WEB_POLARITY ; + end + + `IP_MODULE_NAME(dpbram_primitive) #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH_A(DATA_WIDTH_ROW_A), + .READ_WIDTH_A(DATA_WIDTH_ROW_A), + + .CLKA_POLARITY(CLKA_POLARITY), + .CLKEA_POLARITY(CLKEA_POLARITY), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + .OUTPUT_REG_A(OUTPUT_REG_A), + + .WRITE_WIDTH_B(DATA_WIDTH_ROW_B), + .READ_WIDTH_B(DATA_WIDTH_ROW_B), + + .CLKB_POLARITY(CLKB_POLARITY), + .CLKEB_POLARITY(CLKEB_POLARITY), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + .OUTPUT_REG_B(OUTPUT_REG_B), + + .ini_index(DATA_MAP_INDEX), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY) + + + + ) bram ( + //Trion and Titanium ports + .CLKA (clk_a), // A-port clk + .CLKEA (clke_a), // A-port clk enable + .WEA (w_we_a), // A-port write enable + .ADDRA (w_addr_a), // A-port address input + .WDATAA(w_wdata_a), // A-port write data input + .RDATAA(w_rdata_a), // A-port read address output + + .CLKB (clk_b), // B-port clk + .CLKEB (clke_b), // B-port clk enable + .WEB (w_we_b), // B-port write enable + .ADDRB (w_addr_b), // B-port address input + .WDATAB(w_wdata_b), // B-port write data input + .RDATAB(w_rdata_b), // B-port read address output + + //Titanium extra ports + + .RSTA (reset_a), // A-port reset + .ADDRENA(addren_a), // A-port address enable + + .RSTB(reset_b), // B-port reset + .ADDRENB(addren_b) // B-port address enable + ); + end + end + + end + else if (bram_table_loop_mode == 1 ) + begin:scan_row + for (gen_y=0; gen_y ADDR_WIDTH_A )? ADDR_WIDTH_A:ADDR_WIDTH_ROW_A; + + + localparam ADDR_WIDTH_ROW_B = bram_feature_table(bram_mode_b,0); + localparam DATA_WIDTH_ROW_B = bram_feature_table(bram_mode_b,1); + localparam WEN_WIDTH_ROW_B = bram_feature_table(bram_mode_b,2); + localparam ADDR_WIDTH_ROW_MAP_B = (ADDR_WIDTH_ROW_B > ADDR_WIDTH_B )? ADDR_WIDTH_B:ADDR_WIDTH_ROW_B; + + + + localparam START_ROW_INDEX = get_current_row_index(gen_y); + + + for (gen_x=0; gen_x1) + begin + assign w_we_a[1] = ((we_a == WEA_POLARITY) & wen_decode_a[WRSEL_INDEX_A] & (byteen_a[BYTEEN_INDEX_A] == BYTEENA_POLARITY) ) ? WEA_POLARITY: !WEA_POLARITY; + end + + assign w_we_b[0] = ((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY)) ? WEB_POLARITY: !WEB_POLARITY; + if ( WEN_WIDTH_ROW_B >1) + begin + assign w_we_b[1] = ((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY)) ? WEB_POLARITY : !WEB_POLARITY; + end + + `IP_MODULE_NAME(dpbram_primitive) #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH_A(DATA_WIDTH_ROW_A), + .READ_WIDTH_A(DATA_WIDTH_ROW_A), + + .CLKA_POLARITY(CLKA_POLARITY), + .CLKEA_POLARITY(CLKEA_POLARITY), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + .OUTPUT_REG_A(OUTPUT_REG_A), + + .WRITE_WIDTH_B(DATA_WIDTH_ROW_B), + .READ_WIDTH_B(DATA_WIDTH_ROW_B), + + .CLKB_POLARITY(CLKB_POLARITY), + .CLKEB_POLARITY(CLKEB_POLARITY), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + .OUTPUT_REG_B(OUTPUT_REG_B), + + .ini_index(DATA_MAP_INDEX), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY) + + + ) bram ( + //Trion and Titanium ports + .CLKA (clk_a), // A-port clk + .CLKEA (clke_a), // A-port clk enable + .WEA (w_we_a), // A-port write enable + .ADDRA (w_addr_a), // A-port address input + .WDATAA(w_wdata_a), // A-port write data input + .RDATAA(w_rdata_a), // A-port read address output + + .CLKB (clk_b), // B-port clk + .CLKEB (clke_b), // B-port clk enable + .WEB (w_we_b), // B-port write enable + .ADDRB (w_addr_b), // B-port address input + .WDATAB(w_wdata_b), // B-port write data input + .RDATAB(w_rdata_b), // B-port read address output + + //Titanium extra ports + + .RSTA (reset_a), // A-port reset + .ADDRENA(addren_a), // A-port address enable + + .RSTB(reset_b), // B-port reset + .ADDRENB(addren_b) // B-port address enable + ); + + + + end + end + + end + endgenerate + + +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_true_dual_port_ram) ( + //Trion and Titanium ports + clk, // clock input for one clock mode + clke, // clk enable + + clk_a, // A-port clk + clke_a, // A-port clk enable + byteen_a, // A-port Byteen input + we_a, // A-port write enable + addr_a, // A-port address input + wdata_a, // A-port write data input + rdata_a, // A-port read address output + + clk_b, // B-port clk + clke_b, // B-port clk enable + byteen_b, // B-port Byteen input + we_b, // B-port write enable + addr_b, // B-port address input + wdata_b, // B-port write data input + rdata_b, // B-port read address output + + //Titanium extra ports + reset_a, // A-port reset + addren_a, // A-port address enable + + reset_b, // B-port reset + addren_b // B-port address enable + + ); + +//`include "bram_decompose.vh" + +//Trion and Titanium parameters +parameter CLK_POLARITY = 1'b1; //clk polarity for one clk mode; 0:falling edge; 1:rising edge +parameter CLKE_POLARITY = 1'b1; //clke polarity for one clk mode; 0:active low; 1:active high + +parameter CLKA_POLARITY = 1'b1; //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEA_POLARITY = 1'b1; //clke A polarity; 0:active low; 1:active high +parameter WEA_POLARITY = 1'b1; //we A polarity; 0:active low; 1:active high + +parameter OUTPUT_REG_A = 1'b0; // Output register enable; 1:add pipe-line read register +parameter BYTEENA_POLARITY = 1'b1; // byteen polarity 0:active low; 1:active high + +parameter CLKB_POLARITY = 1'b1; //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEB_POLARITY = 1'b1; //clke A polarity; 0:active low; 1:active high +parameter WEB_POLARITY = 1'b1; //we B polarity; 0:active low; 1:active high + +parameter OUTPUT_REG_B = 1'b0; // Output register enable; 1:add pipe-line read register +parameter BYTEENB_POLARITY = 1'b1; // byteen polarity 0:active low; 1:active high + + +//Port Enable +parameter CLK_MODE = 2; //1: ONE CLK Mode; CLK pin will provide the clock source to the memory + //2: TWO CLK Mode; clk_a and clk_b +parameter CLKEA_ENABLE = 1'b1; //1: Enalbe the port for clke_a pin ; 0: dislable +parameter WEA_ENABLE = 1'b1; //1: Enable the port for we_a pin ; 0: disable +parameter BYTEENA_ENABLE = 1'b1; //1: Enable the port for Byteen_a pins ; 0: disable + +parameter CLKEB_ENABLE = 1'b1; //1: Enalbe the port for clke_b pin ; 0: dislable +parameter WEB_ENABLE = 1'b1; //1: Enable the port for we_b pin ; 0: disable +parameter BYTEENB_ENABLE = 1'b1; //1: Enable the port for Byteen_b pins ; 0: disable + + +//Titanium extra paramters +parameter RSTA_POLARITY = 1'b1; // rst A polarity +parameter RESET_RAM_A = "ASYNC"; // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_A = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENA_POLARITY = 1'b1; // addrena polarity + +parameter RSTB_POLARITY = 1'b1; // rst A polarity +parameter RESET_RAM_B = "ASYNC"; // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_B = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENB_POLARITY = 1'b1; // addrenb polarity + +//Port Enable +parameter RESET_A_ENABLE = 1'b1; //1: Enable the port for reset_a pin ; 0: disable +parameter ADDREN_A_ENABLE = 1'b1; //1: Enable the port for addren_a pin ; 0: disable + +parameter RESET_B_ENABLE = 1'b1; //1: Enable the port for reset_b pin ; 0: disable +parameter ADDREN_B_ENABLE = 1'b1; //1: Enable the port for addren_b pin ; 0: disable + +parameter WRITE_MODE_A = "READ_FIRST"; +parameter WRITE_MODE_B = "READ_FIRST"; +parameter DATA_WIDTH_A = 16; +parameter DATA_WIDTH_B = 16; +parameter ADDR_WIDTH_A = 4; +parameter ADDR_WIDTH_B = 4; +parameter BYTEEN_WIDTH_A = 2; +parameter BYTEEN_WIDTH_B = 2; +parameter FAMILY = "TITANIUM"; + +//Trion and Titanium ports +input clk; +input clke; + +input clk_a; +input clke_a; +input we_a; +input [BYTEEN_WIDTH_A-1:0] byteen_a; +input [ADDR_WIDTH_A-1:0 ] addr_a; +input [DATA_WIDTH_A-1:0 ] wdata_a; +output [DATA_WIDTH_A-1:0 ]rdata_a; + +input clk_b; +input clke_b; +input we_b; +input [BYTEEN_WIDTH_B-1:0] byteen_b; +input [ADDR_WIDTH_B-1:0 ] addr_b; +input [DATA_WIDTH_B-1:0 ] wdata_b; +output [DATA_WIDTH_B-1:0 ]rdata_b; + +//Titanium extra ports +input reset_a; +input addren_a; + +input reset_b; +input addren_b; + +////////////////// wires ////////////////// +wire w_clk_a; +wire w_clke_a; +wire [BYTEEN_WIDTH_A-1:0] w_byteen_a; +wire w_we_a; + +wire w_clk_b; +wire w_clke_b; +wire [BYTEEN_WIDTH_B-1:0] w_byteen_b; +wire w_we_b; + +wire w_reset_a; +wire w_addren_a; + +wire w_reset_b; +wire w_addren_b; + + +assign w_clk_a = (CLK_MODE==2) ? clk_a : clk; +assign w_clke_a = (CLKEA_ENABLE==1) ? ((CLK_MODE==2) ? clke_a : clke) : CLKEA_POLARITY; +assign w_byteen_a = (BYTEENA_ENABLE==1)? byteen_a : {BYTEEN_WIDTH_A{BYTEENA_POLARITY}}; +assign w_we_a = (WEA_ENABLE==1) ? we_a : WEA_POLARITY; + +assign w_clk_b = (CLK_MODE==2) ? clk_b : clk; +assign w_clke_b = (CLKEB_ENABLE==1) ? ((CLK_MODE==2) ? clke_b : clke) : CLKEB_POLARITY; +assign w_byteen_b = (BYTEENB_ENABLE==1)? byteen_b : {BYTEEN_WIDTH_B{BYTEENB_POLARITY}}; +assign w_we_b = (WEB_ENABLE==1) ? we_b : WEB_POLARITY; + + +//Titanium extra ports +assign w_reset_a = (RESET_A_ENABLE==1) ? reset_a : (RSTA_POLARITY==1'b1) ? 1'b0: 1'b1; +assign w_addren_a = (ADDREN_A_ENABLE==1) ? addren_a : ADDRENA_POLARITY; + +assign w_reset_b = (RESET_B_ENABLE==1) ? reset_b : (RSTB_POLARITY==1'b1) ? 1'b0: 1'b1; +assign w_addren_b = (ADDREN_B_ENABLE==1) ? addren_b : ADDRENB_POLARITY; + + +localparam CLKA_POLARITY_LC = (CLK_MODE==2) ? CLKA_POLARITY : CLK_POLARITY; +localparam CLKB_POLARITY_LC = (CLK_MODE==2) ? CLKB_POLARITY : CLK_POLARITY; + +localparam CLKEA_POLARITY_LC = (CLK_MODE==2) ? CLKEA_POLARITY : CLKE_POLARITY; +localparam CLKEB_POLARITY_LC = (CLK_MODE==2) ? CLKEB_POLARITY : CLKE_POLARITY; + + `IP_MODULE_NAME(dpram_wrapper_mwm) #( + //Trion and Titanium parameters + .CLKA_POLARITY(CLKA_POLARITY_LC), + .CLKEA_POLARITY(CLKEA_POLARITY_LC), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + + .OUTPUT_REG_A(OUTPUT_REG_A), + .BYTEENA_POLARITY(BYTEENA_POLARITY), + + .CLKB_POLARITY(CLKB_POLARITY_LC), + .CLKEB_POLARITY(CLKEB_POLARITY_LC), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + + .OUTPUT_REG_B(OUTPUT_REG_B), + .BYTEENB_POLARITY(BYTEENB_POLARITY), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY), + + .DATA_WIDTH_A(DATA_WIDTH_A), + .DATA_WIDTH_B(DATA_WIDTH_B), + .ADDR_WIDTH_A(ADDR_WIDTH_A), + .ADDR_WIDTH_B(ADDR_WIDTH_B), + .BYTEEN_WIDTH_A(BYTEEN_WIDTH_A), + .BYTEEN_WIDTH_B(BYTEEN_WIDTH_B), + + .FAMILY(FAMILY) + + + ) brams ( + //Trion and Titanium ports + .clk_a(w_clk_a), + .clke_a(w_clke_a), + .byteen_a(w_byteen_a), + .we_a(w_we_a), + .addr_a(addr_a), + .wdata_a(wdata_a), + .rdata_a(rdata_a), + + .clk_b(w_clk_b), + .clke_b(w_clke_b), + .byteen_b(w_byteen_b), + .we_b(w_we_b), + .addr_b(addr_b), + .wdata_b(wdata_b), + .rdata_b(rdata_b), + + //Titanium extra ports + .reset_a(w_reset_a), + .addren_a(w_addren_a), + .reset_b(w_reset_b), + .addren_b(w_addren_b) + + ); + + + +endmodule +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/my_bram_ip_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/my_bram_ip_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..f7e5ae0550c31f2dda23480dde3443f9bd41c78c --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/my_bram_ip_define.vh @@ -0,0 +1,114 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam ADDR_WIDTH_A = 11; +localparam ADDR_WIDTH_B = 11; +localparam RESET_A_ENABLE = 0; +localparam RESET_B_ENABLE = 0; +localparam RSTA_POLARITY = 1; +localparam RSTB_POLARITY = 1; +localparam FAMILY = "TITANIUM"; +localparam MEMORY_MODE = "SPEED"; +localparam WRITE_MODE_A = "READ_FIRST"; +localparam WRITE_MODE_B = "READ_FIRST"; +localparam OUTPUT_REG_A = 0; +localparam OUTPUT_REG_B = 0; +localparam MEMORY_TYPE = "TDP_RAM"; +localparam GROUP_DATA_WIDTH_B = 8; +localparam BYTEENA_ENABLE = 0; +localparam BYTEENB_ENABLE = 0; +localparam BYTEENA_POLARITY = 1; +localparam BYTEENB_POLARITY = 1; +localparam BYTEEN_WIDTH_A = 1; +localparam BYTEEN_WIDTH_B = 1; +localparam BYTEEN_ENABLE = 0; +localparam BYTEEN_POLARITY = 1; +localparam GROUP_DATA_WIDTH = 8; +localparam BYTEEN_WIDTH = 1; +localparam WIDTH_RATIO = 4; +localparam GROUP_DATA_WIDTH_A = 8; +localparam DATA_WIDTH_A = 8; +localparam DATA_WIDTH_B = 8; +localparam ADDREN_ENABLE = 1; +localparam ADDREN_POLARITY = 1; +localparam CLK_MODE = 2; +localparam CLKA_POLARITY = 1; +localparam CLKB_POLARITY = 1; +localparam CLKE_POLARITY = 1; +localparam CLKEA_POLARITY = 1; +localparam CLKEA_ENABLE = 0; +localparam RESET_OUTREG_A = "ASYNC"; +localparam RESET_OUTREG_B = "ASYNC"; +localparam RESET_RAM_B = "ASYNC"; +localparam WEA_ENABLE = 1; +localparam WEA_POLARITY = 1; +localparam WEB_ENABLE = 1; +localparam WEB_POLARITY = 1; +localparam RADDREN_ENABLE = 1; +localparam RADDREN_POLARITY = 1; +localparam WADDREN_ENABLE = 1; +localparam WADDREN_POLARITY = 1; +localparam RCLK_POLARITY = 1; +localparam ADDREN_A_ENABLE = 0; +localparam ADDREN_B_ENABLE = 0; +localparam ADDRENA_POLARITY = 1; +localparam ADDRENB_POLARITY = 1; +localparam WE_ENABLE = 1; +localparam WE_POLARITY = 1; +localparam WCLKE_ENABLE = 1; +localparam WCLKE_POLARITY = 1; +localparam WCLK_POLARITY = 1; +localparam RESET_RAM_A = "ASYNC"; +localparam RESET_RAM = "ASYNC"; +localparam CLK_POLARITY = 1; +localparam OUTPUT_REG = 0; +localparam RE_POLARITY = 1; +localparam RE_ENABLE = 1; +localparam WRITE_MODE = "READ_FIRST"; +localparam RESET_OUTREG = "ASYNC"; +localparam RESET_ENABLE = 1; +localparam RST_POLARITY = 1; +localparam CLKEB_POLARITY = 1; +localparam CLKEB_ENABLE = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/signal_gen_sdp.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/signal_gen_sdp.v new file mode 100644 index 0000000000000000000000000000000000000000..8b553a55dcc4ce104a6ecad60555067822f13100 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/signal_gen_sdp.v @@ -0,0 +1,462 @@ + +module signal_gen_sdp ( + wclk, + rclk, + rstn, + rdata_b, + bram_rst, + wclke, + we, + re, + byteen, + waddr, + raddr, + wdata_a, + waddren, + raddren, + sim_end +); +//`include "bram_decompose.vh" +parameter MEMORY_TYPE = "SP_RAM"; +parameter RESET_RAM = "ASYNC"; +parameter RESET_OUTREG = "ASYNC"; +parameter [0:0] WCLK_POLARITY = 1'b1; +parameter [0:0] RCLK_POLARITY = 1'b1; +parameter [0:0] WCLKE_POLARITY = 1'b1; +parameter [0:0] WE_POLARITY = 1'b1; +parameter [0:0] RE_POLARITY = 1'b1; +parameter [0:0] OUTPUT_REG = 1'b1; +parameter [0:0] BYTEEN_POLARITY = 1'b1; +parameter [0:0] WCLKE_ENABLE = 1'b1; +parameter [0:0] WE_ENABLE = 1'b1; +parameter [0:0] RE_ENABLE = 1'b1; +parameter [0:0] BYTEEN_ENABLE = 1'b1; +parameter [0:0] RST_POLARITY = 1'b1; +parameter [0:0] WADDREN_POLARITY = 1'b1; +parameter [0:0] RADDREN_POLARITY = 1'b1; +parameter [0:0] RESET_ENABLE = 1'b1; +parameter [0:0] WADDREN_ENABLE = 1'b1; +parameter [0:0] RADDREN_ENABLE = 1'b1; + +parameter FAMILY = "TITANIUM"; +parameter DATA_WIDTH_A = 16; +parameter DATA_WIDTH_B = 16; +parameter ADDR_WIDTH_A = 4; +parameter ADDR_WIDTH_B = 4; +parameter BYTEEN_WIDTH = 2; + +input wclk; +input rclk; +input rstn; + +input [DATA_WIDTH_B-1:0] rdata_b; +output bram_rst; +output wclke; +output we; +output re; +output [BYTEEN_WIDTH-1:0] byteen; +output reg [ADDR_WIDTH_A-1:0] waddr = {ADDR_WIDTH_A{1'b0}}; +output reg [ADDR_WIDTH_B-1:0] raddr = {ADDR_WIDTH_B{1'b0}}; +output reg [DATA_WIDTH_A-1:0] wdata_a = {DATA_WIDTH_A{1'b0}}; +//Titanium extra ports +output waddren; +output raddren; +output reg sim_end = 0; + +localparam TEST_INIT = 0; +localparam TEST_INIT_VAL = 1; +localparam TEST_NORMAL_SCAN = 2; +localparam TEST_CLKEN_DISABLE = 3; +localparam TEST_CLKEN_DISABLE_RAND = 4; +localparam TEST_WEN_DISABLE = 5; +localparam TEST_WEN_DISABLE_RAND = 6; +localparam TEST_ADDREN_DISABLE = 7; +localparam TEST_ADDREN_DISABLE_RAND = 8; +localparam TEST_BYTEEN_DISABLE = 9; +localparam TEST_BYTEEN_DISABLE_RAND = 10; +localparam TEST_REN_DISABLE = 11; +localparam TEST_REN_DISABLE_RAND = 12; +localparam TEST_WR_SIMULT = 13; +localparam TEST_RST = 14; +localparam TEST_RANDOM1 = 15; +localparam TEST_RANDOM2 = 16; +localparam TEST_RANDOM3 = 17; +localparam TEST_END = 18; +localparam TEST_READOUT = 999; + +localparam MAX_ADDR = ADDR_WIDTH_A > ADDR_WIDTH_B ? ADDR_WIDTH_A : ADDR_WIDTH_B; + +wire rclk_i; +wire wclk_i; +assign rclk_i = RCLK_POLARITY ^~ rclk; +assign wclk_i = WCLK_POLARITY ^~ wclk; + +reg r_wclke = ~WCLKE_POLARITY; +reg r_we = ~WE_POLARITY; +reg r_re = ~RE_POLARITY; +reg [BYTEEN_WIDTH-1:0] r_byteen = {BYTEEN_WIDTH{~BYTEEN_POLARITY}}; +reg r_waddren = ~WADDREN_POLARITY; +reg r_raddren = ~RADDREN_POLARITY; +reg r_bram_rst = ~RST_POLARITY; +assign wclke = WCLKE_ENABLE ? r_wclke : WCLKE_POLARITY; +assign we = WE_ENABLE ? r_we : WE_POLARITY; +assign re = RE_ENABLE ? r_re : RE_POLARITY; +assign byteen = BYTEEN_ENABLE ? r_byteen : {BYTEEN_WIDTH{BYTEEN_POLARITY}}; +assign waddren = FAMILY == "TRION" ? WADDREN_POLARITY : WADDREN_ENABLE ? r_waddren : WADDREN_POLARITY; +assign raddren = FAMILY == "TRION" ? RADDREN_POLARITY : RADDREN_ENABLE ? r_raddren : RADDREN_POLARITY; +assign bram_rst = RESET_ENABLE ? r_bram_rst : ~RST_POLARITY; + +integer state = TEST_INIT; +integer next_state = TEST_INIT; +integer dummy = 0; +integer read_cnt = 0; +integer write_cnt = 0; + +function [DATA_WIDTH_A-1:0] get_rand_dataa(input integer dummy); + reg [DATA_WIDTH_A-1:0] temp; + integer i; + begin + temp = {DATA_WIDTH_A{1'b0}}; + for(i=0 ; i<$rtoi($ceil(DATA_WIDTH_A/32.0)) ; i=i+1) begin + temp = temp << 32 | $random(); + end + get_rand_dataa = temp; + end +endfunction + +function [DATA_WIDTH_B-1:0] get_rand_datab(input integer dummy); + reg [DATA_WIDTH_B-1:0] temp; + integer i; + begin + temp = {DATA_WIDTH_B{1'b0}}; + for(i=0 ; i<$rtoi($ceil(DATA_WIDTH_B/32.0)) ; i=i+1) begin + temp = temp << 32 | $random(); + end + + get_rand_datab = temp; + end +endfunction + +function [ADDR_WIDTH_A-1:0] get_rand_addra(input integer dummy); + reg [ADDR_WIDTH_A-1:0] temp; + integer i; + begin + temp = {ADDR_WIDTH_A{1'b0}}; + for(i=0 ; i<$rtoi($ceil(ADDR_WIDTH_A/32.0)) ; i=i+1) begin + temp = temp << 32 | $random(); + end + get_rand_addra = temp; + end +endfunction + +function [ADDR_WIDTH_B-1:0] get_rand_addrb(input integer dummy); + reg [ADDR_WIDTH_B-1:0] temp; + integer i; + begin + temp = {ADDR_WIDTH_B{1'b0}}; + for(i=0 ; i<$rtoi($ceil(ADDR_WIDTH_B/32.0)) ; i=i+1) begin + temp = temp << 32 | $random(); + end + get_rand_addrb = temp; + end +endfunction + +function get_rand_en(input integer dummy); + integer random; + integer temp; + integer i; + begin + temp = 0; + random = $random(); + for(i=0 ; i<32 ; i=i+1) begin + temp = temp + random[0]; + random = random >> 1; + end + get_rand_en = temp[0]; + end +endfunction + +function [BYTEEN_WIDTH-1:0] get_rand_byteen(input integer dummy); + reg [BYTEEN_WIDTH-1:0] temp; + integer i; + begin + temp = {BYTEEN_WIDTH{1'b0}}; + for(i=0 ; i (1< latest recheck can + r_byteen <= get_rand_byteen(dummy); + r_bram_rst <= get_rand_en(dummy); + $display("%t ps - write data %h to address: %d ", $time(), wdata_a, waddr); + end + end + + TEST_END: begin + r_wclke <= ~WCLKE_POLARITY; + r_we <= ~WE_POLARITY; + r_byteen <= ~{BYTEEN_WIDTH{BYTEEN_POLARITY}}; + r_waddren <= ~WADDREN_POLARITY; + waddr <= {ADDR_WIDTH_A{1'b1}}; + wdata_a <= 0; + state <= state; + + if (write_cnt > 5) begin + sim_end <= 1; + end else begin + write_cnt <= write_cnt + 1; + end + end + + TEST_READOUT: begin + r_wclke <= ~WCLKE_POLARITY; + r_we <= ~WE_POLARITY; + r_byteen <= ~{BYTEEN_WIDTH{BYTEEN_POLARITY}}; + wdata_a <= 0; + + if (read_cnt == (1< latest recheck can + raddr <= get_rand_addrb(dummy); + read_cnt <= 0; + end + + default: begin + r_re <= ~RE_POLARITY; + r_raddren <= ~RADDREN_POLARITY; + read_cnt <= 0; + raddr <= {ADDR_WIDTH_B{1'b0}}; + end + endcase +end + +initial begin + $display("================"); + $display("Testbench begin!"); + $display("================"); +end + +always @(state) begin + $display("\nSTATE : %d \n", state); +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/signal_gen_sp.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/signal_gen_sp.v new file mode 100644 index 0000000000000000000000000000000000000000..6c9ffb06a7887c5480a845a4bacf0ebea9c023b3 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Testbench/signal_gen_sp.v @@ -0,0 +1,380 @@ + +module signal_gen_sp ( + clk, + rstn, + rdata_a, + bram_rst, + wclke, + we, + re, + byteen, + addr, + wdata_a, + addren, + sim_end +); +//`include "bram_decompose.vh" +parameter RESET_RAM = "ASYNC"; +parameter RESET_OUTREG = "ASYNC"; +parameter [0:0] CLK_POLARITY = 1'b1; +parameter [0:0] WCLKE_POLARITY = 1'b1; +parameter [0:0] WE_POLARITY = 1'b1; +parameter [0:0] RE_POLARITY = 1'b1; +parameter [0:0] OUTPUT_REG = 1'b1; +parameter [0:0] BYTEEN_POLARITY = 1'b1; +parameter [0:0] WCLKE_ENABLE = 1'b1; +parameter [0:0] WE_ENABLE = 1'b1; +parameter [0:0] RE_ENABLE = 1'b1; +parameter [0:0] BYTEEN_ENABLE = 1'b1; +parameter [0:0] RST_POLARITY = 1'b1; +parameter [0:0] ADDREN_POLARITY = 1'b1; +parameter [0:0] RESET_ENABLE = 1'b1; +parameter [0:0] ADDREN_ENABLE = 1'b1; +parameter DATA_WIDTH_A = 16; +parameter DATA_WIDTH_B = 16; +parameter ADDR_WIDTH_A = 4; +parameter BYTEEN_WIDTH = 2; +parameter FAMILY = "TITANIUM"; + + +input clk; +input rstn; +input [DATA_WIDTH_A-1:0] rdata_a; +output bram_rst; +output wclke; +output we; +output re; +output [BYTEEN_WIDTH-1:0] byteen; +output reg [ADDR_WIDTH_A-1:0] addr = {ADDR_WIDTH_A{1'b0}}; +output reg [DATA_WIDTH_A-1:0] wdata_a = {DATA_WIDTH_A{1'b0}}; +//Titanium extra ports +output addren; +output reg sim_end = 0; +localparam TEST_INIT = 0; +localparam TEST_INIT_VAL = 1; +localparam TEST_NORMAL_SCAN = 2; +localparam TEST_CLKEN_DISABLE = 3; +localparam TEST_CLKEN_DISABLE_RAND = 4; +localparam TEST_WEN_DISABLE = 5; +localparam TEST_WEN_DISABLE_RAND = 6; +localparam TEST_ADDREN_DISABLE = 7; +localparam TEST_ADDREN_DISABLE_RAND = 8; +localparam TEST_BYTEEN_DISABLE = 9; +localparam TEST_BYTEEN_DISABLE_RAND = 10; +localparam TEST_REN_DISABLE = 11; +localparam TEST_REN_DISABLE_RAND = 12; +localparam TEST_WR_SIMULT = 13; +localparam TEST_RST = 14; +localparam TEST_RANDOM1 = 15; +localparam TEST_RANDOM2 = 16; +localparam TEST_RANDOM3 = 17; +localparam TEST_END = 18; +localparam TEST_READOUT = 999; + +wire clk_i; +assign clk_i = CLK_POLARITY ~^ clk; + +reg r_wclke = ~WCLKE_POLARITY; +reg r_we = ~WE_POLARITY; +reg r_re = ~RE_POLARITY; +reg [BYTEEN_WIDTH-1:0] r_byteen = {BYTEEN_WIDTH{~BYTEEN_POLARITY}}; +reg r_addren = ~ADDREN_POLARITY; +reg r_bram_rst = ~RST_POLARITY; +assign wclke = WCLKE_ENABLE ? r_wclke : WCLKE_POLARITY; +assign we = WE_ENABLE ? r_we : WE_POLARITY; +assign re = RE_ENABLE ? r_re : RE_POLARITY; +assign byteen = BYTEEN_ENABLE ? r_byteen : {BYTEEN_WIDTH{BYTEEN_POLARITY}}; +assign addren = FAMILY == "TRION" ? ADDREN_POLARITY : ADDREN_ENABLE ? r_addren : ADDREN_POLARITY; +assign bram_rst = RESET_ENABLE ? r_bram_rst : ~RST_POLARITY; + +integer state = TEST_INIT; +integer next_state = TEST_INIT; +integer dummy = 0; +integer read_cnt = 0; +integer write_cnt = 0; + +function [DATA_WIDTH_A-1:0] get_rand_wr_data(input integer dummy); + reg [DATA_WIDTH_A-1:0] temp; + integer i; + begin + temp = {DATA_WIDTH_A{1'b0}}; + for(i=0 ; i<$rtoi($ceil(DATA_WIDTH_A/32.0)) ; i=i+1) begin + temp = temp << 32 | $random(); + end + + get_rand_wr_data = temp; + end +endfunction + +function [ADDR_WIDTH_A-1:0] get_rand_addr(input integer dummy); + reg [ADDR_WIDTH_A-1:0] temp; + integer i; + begin + temp = {ADDR_WIDTH_A{1'b0}}; + for(i=0 ; i<$rtoi($ceil(ADDR_WIDTH_A/32.0)) ; i=i+1) begin + temp = temp << 32 | $random(); + end + + get_rand_addr = temp; + end +endfunction + +function get_rand_en(input integer dummy); + integer random; + integer temp; + integer i; + begin + temp = 0; + random = $random(); + for(i=0 ; i<32 ; i=i+1) begin + temp = temp + random[0]; + random = random >> 1; + end + get_rand_en = temp[0]; + end +endfunction + +function [BYTEEN_WIDTH-1:0] get_rand_byteen(input integer dummy); + reg [BYTEEN_WIDTH-1:0] temp; + integer i; + begin + temp = {BYTEEN_WIDTH{1'b0}}; + for(i=0 ; i 5) begin + sim_end <= 1; + end else begin + write_cnt <= write_cnt + 1; + end + end + + TEST_READOUT: begin + r_wclke <= ~WCLKE_POLARITY; + r_we <= ~WE_POLARITY; + r_byteen <= ~{BYTEEN_WIDTH{BYTEEN_POLARITY}}; + wdata_a <= 0; + + if (read_cnt == (1<> 1; + end + get_rand_en = temp[0]; + end +endfunction + +function [BYTEEN_WIDTH-1:0] get_rand_byteen(input integer dummy); + reg [BYTEEN_WIDTH-1:0] temp; + integer i; + begin + temp = {BYTEEN_WIDTH{1'b0}}; + for(i=0 ; i 5) begin + sim_end <= 1; + end + end + + TEST_READOUT: begin + r_wclke <= ~WCLKE_POLARITY; + r_we <= ~WE_POLARITY; + r_byteen <= ~{BYTEEN_WIDTH{BYTEEN_POLARITY}}; + wdata_a <= 0; + r_re <= RE_POLARITY; + r_addren <= ADDREN_POLARITY; + addr <= read_cnt[0 +: ADDR_WIDTH_A]; + read_cnt <= read_cnt + 1; + + if (read_cnt == (1<> 1; + end + get_rand_en = temp[0]; + end +endfunction + +function [BYTEEN_WIDTH-1:0] get_rand_byteen(input integer dummy); + reg [BYTEEN_WIDTH-1:0] temp; + integer i; + begin + temp = {BYTEEN_WIDTH{1'b0}}; + for(i=0 ; i 5) begin + sim_end <= 1; + end else begin + write_cnt <= write_cnt + 1; + end + end + + TEST_READOUT: begin + clke <= 1; + we <= 0; + byteen <= ~{BYTEEN_WIDTH{1'b1}}; + wdata <= 0; + + if (read_cnt == (1<1) + assign w_wen_ram10[1] = WE[1]; + else if (WRITE_DATA_WIDTH >= 16 ) + assign w_wen_ram10[1] = WE[0]; + else + assign w_wen_ram10[1] = 1'b0; + + EFX_RAM10 # ( + + .WRITE_WIDTH (WRITE_WIDTH), + .WCLK_POLARITY (WCLK_POLARITY), + .WCLKE_POLARITY (WCLKE_POLARITY), + .WE_POLARITY ({2{WE_POLARITY}}), + .WRITE_MODE (WRITE_MODE), + + .READ_WIDTH (READ_WIDTH), + .RCLK_POLARITY (RCLK_POLARITY), + .RE_POLARITY (RE_POLARITY), + .OUTPUT_REG (OUTPUT_REG), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY), // rst polarity + .RESET_RAM (RESET_RAM), // reset mode on ram + .RESET_OUTREG (RESET_OUTREG), // reset mode on output register + .WADDREN_POLARITY (WADDREN_POLARITY), // waddren polarity + .RADDREN_POLARITY (RADDREN_POLARITY), // raddren polarity + + + .INIT_0 (bram_ini_table(ini_index, 16'h0 )), + .INIT_1 (bram_ini_table(ini_index, 16'h1 )), + .INIT_2 (bram_ini_table(ini_index, 16'h2 )), + .INIT_3 (bram_ini_table(ini_index, 16'h3 )), + .INIT_4 (bram_ini_table(ini_index, 16'h4 )), + .INIT_5 (bram_ini_table(ini_index, 16'h5 )), + .INIT_6 (bram_ini_table(ini_index, 16'h6 )), + .INIT_7 (bram_ini_table(ini_index, 16'h7 )), + .INIT_8 (bram_ini_table(ini_index, 16'h8 )), + .INIT_9 (bram_ini_table(ini_index, 16'h9 )), + .INIT_A (bram_ini_table(ini_index, 16'hA )), + .INIT_B (bram_ini_table(ini_index, 16'hB )), + .INIT_C (bram_ini_table(ini_index, 16'hC )), + .INIT_D (bram_ini_table(ini_index, 16'hD )), + .INIT_E (bram_ini_table(ini_index, 16'hE )), + .INIT_F (bram_ini_table(ini_index, 16'hF )), + .INIT_10 (bram_ini_table(ini_index, 16'h10)), + .INIT_11 (bram_ini_table(ini_index, 16'h11)), + .INIT_12 (bram_ini_table(ini_index, 16'h12)), + .INIT_13 (bram_ini_table(ini_index, 16'h13)), + .INIT_14 (bram_ini_table(ini_index, 16'h14)), + .INIT_15 (bram_ini_table(ini_index, 16'h15)), + .INIT_16 (bram_ini_table(ini_index, 16'h16)), + .INIT_17 (bram_ini_table(ini_index, 16'h17)), + .INIT_18 (bram_ini_table(ini_index, 16'h18)), + .INIT_19 (bram_ini_table(ini_index, 16'h19)), + .INIT_1A (bram_ini_table(ini_index, 16'h1A)), + .INIT_1B (bram_ini_table(ini_index, 16'h1B)), + .INIT_1C (bram_ini_table(ini_index, 16'h1C)), + .INIT_1D (bram_ini_table(ini_index, 16'h1D)), + .INIT_1E (bram_ini_table(ini_index, 16'h1E)), + .INIT_1F (bram_ini_table(ini_index, 16'h1F)), + .INIT_20 (bram_ini_table(ini_index, 16'h20)), + .INIT_21 (bram_ini_table(ini_index, 16'h21)), + .INIT_22 (bram_ini_table(ini_index, 16'h22)), + .INIT_23 (bram_ini_table(ini_index, 16'h23)), + .INIT_24 (bram_ini_table(ini_index, 16'h24)), + .INIT_25 (bram_ini_table(ini_index, 16'h25)), + .INIT_26 (bram_ini_table(ini_index, 16'h26)), + .INIT_27 (bram_ini_table(ini_index, 16'h27)) + + ) + ram10k( + + .WCLK(WCLK), // Write clock input + .WE(w_wen_ram10), // Write-enable input + .WCLKE(WCLKE), // Write clock-enable input + .WADDR(WADDR), // Write address input + .WDATA(WDATA), // Write data input + + .RCLK(RCLK), // Read clock input + .RE(RE), // Read-enable input + .RADDR(RADDR), // Read address input + .RDATA(RDATA), // Read data output + + //Titanium extra ports + .RST (RST), // reset + .WADDREN (WADDREN), // write address enable + .RADDREN (RADDREN) // read address enable + + ); + end + endgenerate + +endmodule \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/bram_top.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/bram_top.sdc new file mode 100644 index 0000000000000000000000000000000000000000..661aa4e945f0d6c0419b505a9c9b009c8d747a45 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/bram_top.sdc @@ -0,0 +1,3 @@ +create_clock -period 40.00 i_fb_clk +create_clock -period 10.00 i_wclk +create_clock -waveform {2.500 7.500} -period 10.00 i_rclk \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/bram_wrapper_mwm.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/bram_wrapper_mwm.v new file mode 100644 index 0000000000000000000000000000000000000000..d34f673a25aa290e64cf1168c1eac0ab676bfc25 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/bram_wrapper_mwm.v @@ -0,0 +1,779 @@ +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// Modified on 23 September 2022 +// ******************************* + +module bram_wrapper_mwm #( + parameter FAMILY = "TITANIUM", + + //Trion and Titanium parameters + parameter WCLK_POLARITY = 1'b1, //wclk polarity, 0:falling edge, 1:rising edge + parameter WCLKE_POLARITY = 1'b1, //wclke polarity, 0:active low, 1:active high + parameter WE_POLARITY = 1'b1, //we polarity, 0:active low, 1:active high + parameter WRITE_MODE = "READ_FIRST",//write mode, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter RCLK_POLARITY = 1'b1, // rclk polarity, 0:falling edge, 1:rising edge + parameter RE_POLARITY = 1'b1, // re polarity, 0:active low , 1:active high + parameter OUTPUT_REG = 1'b0, // Output register enable, 1:add pipe-line read register + + parameter BYTEEN_POLARITY = 1'b1, // byteen polarity 0:active low, 1:active high + + //Titanium extra paramters + parameter RST_POLARITY = 1'b1, // rst polarity + parameter RESET_RAM = "ASYNC", // reset mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG = "ASYNC", // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter WADDREN_POLARITY = 1'b1, // waddren polarity + parameter RADDREN_POLARITY = 1'b1, // raddren polarity + + parameter DATA_WIDTH_A = 16, + parameter DATA_WIDTH_B = 16, + parameter ADDR_WIDTH_A = 4, + parameter ADDR_WIDTH_B = 4, + parameter BYTEEN_WIDTH = 2 + +) +( + //Trion and Titanium ports + wclk, // Write clock input + wclke, // Write clock-enable input + byteen, // Byteen input + we, // Write-enable input + waddr, // Write address input + wdata, // Write data input + + rclk, // Read clock input + re, // Read-enable input + raddr, // Read address input + rdata, // Read data output + + //Titanium extra ports + reset, // reset + waddren, // write address enable + raddren // read address enable + + ); + + +`include "bram_decompose.vh" +//`include "bram_feature.vh" + +input wclk; +input wclke; +input we; +input [BYTEEN_WIDTH-1:0] byteen; +input [ADDR_WIDTH_A-1:0 ] waddr; +input [DATA_WIDTH_A-1:0 ] wdata; + +input rclk; +input re; +input [ADDR_WIDTH_B-1:0 ] raddr; +output [DATA_WIDTH_B-1:0 ]rdata; + +input reset; +input waddren; +input raddren; + +localparam MAP_ADDR_WIDTH_A = (address_mapping_table_A_size!=0)?address_mapping_table_A_size:ADDR_WIDTH_A; +localparam MAP_ADDR_WIDTH_B = (address_mapping_table_B_size!=0)?address_mapping_table_B_size:ADDR_WIDTH_B; +initial begin + $display("MAP_ADDR_WIDTH_A: %d", MAP_ADDR_WIDTH_A); + $display("MAP_ADDR_WIDTH_B: %d", MAP_ADDR_WIDTH_B); +end + +wire [MAP_ADDR_WIDTH_A-1:0 ] w_waddr_map; +wire [DATA_WIDTH_A-1:0 ] w_wdata_map; + +wire [MAP_ADDR_WIDTH_B-1:0 ] w_raddr_map; +wire [DATA_WIDTH_B-1:0 ] w_rdata_map; + +wire rclk_i; +wire wclk_i; +assign rclk_i = rclk ~^ RCLK_POLARITY; +assign wclk_i = wclk ~^ WCLK_POLARITY; + +function integer get_current_row_index; +input integer row;//Mode type +integer x; + begin + get_current_row_index = 0; + for (x=0; x1) + begin + assign w_we[1] = ((we == WE_POLARITY) & wen_decode[WRSEL_INDEX] & (byteen[BYTEEN_INDEX] == BYTEEN_POLARITY) ) ? WE_POLARITY: !WE_POLARITY; + end + + bram_primitive #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH(WDATA_WIDTH_ROW), + .WCLK_POLARITY(WCLK_POLARITY), + .WCLKE_POLARITY(WCLKE_POLARITY), + .WE_POLARITY(WE_POLARITY), + .WRITE_MODE(WRITE_MODE), + + .READ_WIDTH(RDATA_WIDTH_ROW), + .RCLK_POLARITY(RCLK_POLARITY), + .RE_POLARITY(RE_POLARITY), + .OUTPUT_REG(OUTPUT_REG), + + //Titanium extra paramters + .RST_POLARITY(RST_POLARITY), + .RESET_RAM(RESET_RAM), + .RESET_OUTREG(RESET_OUTREG), + .WADDREN_POLARITY(WADDREN_POLARITY), + .RADDREN_POLARITY(RADDREN_POLARITY), + + .WEN_WIDTH(WEN_WIDTH_ROW), + + .ini_index(DATA_MAP_INDEX) + + ) bram ( + //Trion and Titanium ports + .WCLK(wclk), // Write clock input + .WCLKE(wclke), // Write clock-enable input + .WE(w_we), // Write-enable input + .WADDR(w_waddr), // Write address input + .WDATA(w_wdata), // Write data input + + .RCLK(rclk), // Read clock input + .RE(re), // Read-enable input + .RADDR(w_raddr), // Read address input + .RDATA(w_rdata), // Read data output + + //Titanium extra ports + .RST(reset), // reset + .WADDREN(waddren), // write address enable + .RADDREN(raddren) // read address enable + ); + end + end + + end + else if (bram_table_loop_mode == 1 ) + begin:scan_row + initial begin + $display("Scan Row Loop:(Speed)"); + end + + for (gen_y=0; gen_y1) + begin + assign w_we[1] = ((we == WE_POLARITY) & wen_decode[WRSEL_INDEX] & (byteen[BYTEEN_INDEX] == BYTEEN_POLARITY)) ? WE_POLARITY: !WE_POLARITY; + end + + bram_primitive #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH(WDATA_WIDTH_ROW), + .WCLK_POLARITY(WCLK_POLARITY), + .WCLKE_POLARITY(WCLKE_POLARITY), + .WE_POLARITY(WE_POLARITY), + .WRITE_MODE(WRITE_MODE), + + .READ_WIDTH(RDATA_WIDTH_ROW), + .RCLK_POLARITY(RCLK_POLARITY), + .RE_POLARITY(RE_POLARITY), + .OUTPUT_REG(OUTPUT_REG), + + //Titanium extra paramters + .RST_POLARITY(RST_POLARITY), + .RESET_RAM(RESET_RAM), + .RESET_OUTREG(RESET_OUTREG), + .WADDREN_POLARITY(WADDREN_POLARITY), + .RADDREN_POLARITY(RADDREN_POLARITY), + + .WEN_WIDTH(WEN_WIDTH_ROW), + + .ini_index(DATA_MAP_INDEX) + + ) bram ( + //Trion and Titanium ports + .WCLK(wclk), // Write clock input + .WCLKE(wclke), // Write clock-enable input + .WE(w_we), // Write-enable input + .WADDR(w_waddr), // Write address input + .WDATA(w_wdata), // Write data input + + .RCLK(rclk), // Read clock input + .RE(re), // Read-enable input + .RADDR(w_raddr), // Read address input + .RDATA(w_rdata), // Read data output + + //Titanium extra ports + .RST(reset), // reset + .WADDREN(waddren), // write address enable + .RADDREN(raddren) // read address enable + ); + end + end + + end + endgenerate + + +endmodule \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/debug_profile.wizard.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/debug_profile.wizard.json new file mode 100644 index 0000000000000000000000000000000000000000..5288eb1b69a47185be8e82554a3e2feeabcea1d1 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/debug_profile.wizard.json @@ -0,0 +1,261 @@ +{ + "debug_cores": [ + { + "name": "la0", + "type": "la", + "uuid": "7f4dddfb44c7404e99f4fa1bc59ffe07", + "trigin_en": false, + "trigout_en": false, + "auto_inserted": true, + "capture_control": false, + "data_depth": 1024, + "input_pipeline": 1, + "probes": [ + { + "name": "w_rdata", + "width": 16, + "probe_type": 1 + } + ] + } + ], + "connections": [ + { + "command": "add_ports", + "id": 1, + "args": { + "netlist": "dpram_top_titanium", + "ports": [ + { + "name": "jtag_inst1_CAPTURE", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_DRCK", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_RESET", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_RUNTEST", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_SEL", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_SHIFT", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_TCK", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_TDI", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_TMS", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_UPDATE", + "dir": "in", + "width": 1 + }, + { + "name": "jtag_inst1_TDO", + "dir": "out", + "width": 1 + } + ] + } + }, + { + "command": "instantiate", + "netlist": "edb_top", + "id": 2, + "instance": "edb_top_inst" + }, + { + "command": "connect", + "id": 3, + "args": { + "instance": "edb_top_inst", + "ports": [ + { + "name": "bscan_CAPTURE", + "net": "jtag_inst1_CAPTURE" + }, + { + "name": "bscan_DRCK", + "net": "jtag_inst1_DRCK" + }, + { + "name": "bscan_RESET", + "net": "jtag_inst1_RESET" + }, + { + "name": "bscan_RUNTEST", + "net": "jtag_inst1_RUNTEST" + }, + { + "name": "bscan_SEL", + "net": "jtag_inst1_SEL" + }, + { + "name": "bscan_SHIFT", + "net": "jtag_inst1_SHIFT" + }, + { + "name": "bscan_TCK", + "net": "jtag_inst1_TCK" + }, + { + "name": "bscan_TDI", + "net": "jtag_inst1_TDI" + }, + { + "name": "bscan_TMS", + "net": "jtag_inst1_TMS" + }, + { + "name": "bscan_UPDATE", + "net": "jtag_inst1_UPDATE" + }, + { + "name": "bscan_TDO", + "net": "jtag_inst1_TDO" + }, + { + "name": "la0_clk", + "net": "i_wclk", + "path": [] + }, + { + "name": "la0_probe0[0]", + "net": "w_rdata[0]", + "path": [] + }, + { + "name": "la0_probe0[1]", + "net": "w_rdata[1]", + "path": [] + }, + { + "name": "la0_probe0[2]", + "net": "w_rdata[2]", + "path": [] + }, + { + "name": "la0_probe0[3]", + "net": "w_rdata[3]", + "path": [] + }, + { + "name": "la0_probe0[4]", + "net": "w_rdata[4]", + "path": [] + }, + { + "name": "la0_probe0[5]", + "net": "w_rdata[5]", + "path": [] + }, + { + "name": "la0_probe0[6]", + "net": "w_rdata[6]", + "path": [] + }, + { + "name": "la0_probe0[7]", + "net": "w_rdata[7]", + "path": [] + }, + { + "name": "la0_probe0[8]", + "net": "w_rdata[8]", + "path": [] + }, + { + "name": "la0_probe0[9]", + "net": "w_rdata[9]", + "path": [] + }, + { + "name": "la0_probe0[10]", + "net": "w_rdata[10]", + "path": [] + }, + { + "name": "la0_probe0[11]", + "net": "w_rdata[11]", + "path": [] + }, + { + "name": "la0_probe0[12]", + "net": "w_rdata[12]", + "path": [] + }, + { + "name": "la0_probe0[13]", + "net": "w_rdata[13]", + "path": [] + }, + { + "name": "la0_probe0[14]", + "net": "w_rdata[14]", + "path": [] + }, + { + "name": "la0_probe0[15]", + "net": "w_rdata[15]", + "path": [] + } + ] + } + } + ], + "vdbs": [ + { + "file": "debug_top.post.vdb", + "instance": "edb_top_inst" + } + ], + "session": { + "wizard": { + "data_depth": 1024, + "capture_control": false, + "selected_nets": [ + { + "name": "w_rdata", + "width": 16, + "clk_domain": "i_wclk", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [], + "net_idx_left": 15, + "net_idx_right": 0 + } + ], + "top_module": "dpram_top_titanium", + "db_checksum": "ba5fce12098a2c03e7bae2e9a172d1842464edfca8e284870b3519e987537970", + "src": "elaborate", + "jtag_user": "USER1", + "input_pipeline": 1 + } + } +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/dpram_top_titanium.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/dpram_top_titanium.v new file mode 100644 index 0000000000000000000000000000000000000000..93df8c54ccc54cc9e61b69fd55dfc5b652a692d0 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/dpram_top_titanium.v @@ -0,0 +1,916 @@ + +//`define TEST_SP_RAM +`define TEST_SDP_RAM +//`define TEST_TDP_RAM +//`define TEST_SP_ROM +//`define TEST_TDP_ROM + + + +module dpram_top_titanium #( +) +( + i_arstn, + + o_pll_bram_RSTN, + i_pll_bram_LOCKED, + i_wclk, + i_rclk, + + + o_led0_r, + o_led0_g, + o_led0_b, + + o_led1_r, + o_led1_g, + o_led1_b, + + i_sw0, + i_sw1, + i_sw2, + + ); + +`ifdef TEST_SP_RAM +`define SINGLE_TEST + +//Trion and Titanium parameters + parameter CLK_POLARITY = 1'b1; //clk polarity, 0:falling edge, 1:rising edge + + parameter WCLKE_POLARITY = 1'b1; //wclke polarity, 0:active low, 1:active high + parameter WE_POLARITY = 1'b1; //we polarity, 0:active low, 1:active high + parameter WRITE_MODE = "WRITE_FIRST";//write mode, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter RE_POLARITY = 1'b1; // re polarity, 0:active low , 1:active high + parameter OUTPUT_REG = 1'b1; // Output register enable, 1:add pipe-line read register + + parameter BYTEEN_POLARITY = 1'b1; //byteen polarity, 0:active low, 1:active high + + //Port Enable + parameter WCLKE_ENABLE = 1'b1; //1: Enalbe the port for waddren pin , 0: dislable + + parameter WE_ENABLE = 1'b1; //1: Enalbe the port for WE pin , 0: dislable + parameter RE_ENABLE = 1'b1; //1: Enalbe the port for RE pin , 0: dislable + parameter BYTEEN_ENABLE = 1'b1; //1: Enalbe the port for Byteen pins , 0: dislable + + //Titanium extra paramters + parameter RST_POLARITY = 1'b1; // rst polarity + parameter RESET_RAM = "ASYNC"; // reset mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG = "ASYNC"; // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDREN_POLARITY = 1'b1; // addren polarity + + + //Port Enable + parameter RESET_ENABLE = 1'b1; //1: Enalbe the port for reset pin , 0: dislable + + parameter ADDREN_ENABLE = 1'b1; //1: Enalbe the port for addren pin , 0: dislable + +`endif + +`ifdef TEST_SDP_RAM +`define SINGLE_TEST + +//Trion and Titanium parameters + parameter CLK_POLARITY = 1'b1; //clk polarity, 0:falling edge, 1:rising edge + + parameter WCLK_POLARITY = 1'b1; //wclk polarity, 0:falling edge, 1:rising edge + + parameter WCLKE_POLARITY = 1'b1; //wclke polarity, 0:active low, 1:active high + parameter WE_POLARITY = 1'b1; //we polarity, 0:active low, 1:active high + parameter WRITE_MODE = "READ_FIRST";//write mode, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + parameter RCLK_POLARITY = 1'b1; // rclk polarity, 0:falling edge, 1:rising edge + parameter RE_POLARITY = 1'b1; // re polarity, 0:active low , 1:active high + parameter OUTPUT_REG = 1'b0; // Output register enable, 1:add pipe-line read register + + parameter BYTEEN_POLARITY = 1'b1; //byteen polarity, 0:active low, 1:active high + + //Port Enable + parameter CLK_MODE = 2; //1: ONE CLK Mode, CLK pin will provide the clock source to the memory + //2: TWO CLK Mode, wclk pin will provide the clock source for write operation , rclk pin will provide the clock source for read operation + + parameter WCLKE_ENABLE = 1'b1; //1: Enalbe the port for waddren pin , 0: dislable + + parameter WE_ENABLE = 1'b1; //1: Enalbe the port for WE pin , 0: dislable + parameter RE_ENABLE = 1'b1; //1: Enalbe the port for RE pin , 0: dislable + parameter BYTEEN_ENABLE = 1'b1; //1: Enalbe the port for Byteen pins , 0: dislable + + //Titanium extra paramters + parameter RST_POLARITY = 1'b1; // rst polarity + parameter RESET_RAM = "ASYNC"; // reset mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG = "ASYNC"; // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter WADDREN_POLARITY = 1'b1; // waddren polarity + parameter RADDREN_POLARITY = 1'b1; // raddren polarity + + + //Port Enable + parameter RESET_ENABLE = 1'b1; //1: Enalbe the port for reset pin , 0: dislable + + parameter WADDREN_ENABLE = 1'b1; //1: Enalbe the port for waddren pin , 0: dislable + parameter RADDREN_ENABLE = 1'b1; //1: Enalbe the port for raddren pin , 0: dislable + parameter DATA_WIDTH_A = 16; + parameter DATA_WIDTH_B = 16; + parameter ADDR_WIDTH_A = 3; + parameter ADDR_WIDTH_B = 3; + parameter BYTEEN_WIDTH = 1; + parameter GROUP_DATA_WIDTH = 16; + parameter FAMILY = "TITANIUM"; + +`endif + +`ifdef TEST_TDP_RAM +`define DUAL_TEST + + //Trion and Titanium parameters + parameter CLK_POLARITY = 1'b1; //clk polarity for one clk mode, 0:falling edge, 1:rising edge + parameter CLKE_POLARITY = 1'b1; //clke polarity for one clk mode, 0:active low, 1:active high + + parameter CLKA_POLARITY = 1'b1; //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEA_POLARITY = 1'b1; //clke A polarity, 0:active low, 1:active high + parameter WEA_POLARITY = 1'b0; //we A polarity, 0:active low, 1:active high + parameter WRITE_MODE_A = "WRITE_FIRST";//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter OUTPUT_REG_A = 1'b1; // Output register enable, 1:add pipe-line read register + parameter BYTEENA_POLARITY = 1'b1; // byteen polarity 0:active low, 1:active high + + parameter CLKB_POLARITY = 1'b1; //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEB_POLARITY = 1'b1; //clke A polarity, 0:active low, 1:active high + parameter WEB_POLARITY = 1'b0; //we B polarity, 0:active low, 1:active high + parameter WRITE_MODE_B = "WRITE_FIRST";//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter OUTPUT_REG_B = 1'b1; // Output register enable, 1:add pipe-line read register + parameter BYTEENB_POLARITY = 1'b1; // byteen polarity 0:active low, 1:active high + + + //Port Enable + parameter CLK_MODE = 1; //1: ONE CLK Mode, CLK pin will provide the clock source to the memory + //2: TWO CLK Mode, clk_a and clk_b + parameter CLKEA_ENABLE = 1'b1; //1: Enalbe the port for clke_a pin , 0: dislable + parameter WEA_ENABLE = 1'b1; //1: Enable the port for we_a pin , 0: disable + parameter BYTEENA_ENABLE = 1'b1; //1: Enable the port for Byteen_a pins , 0: disable + + parameter CLKEB_ENABLE = 1'b1; //1: Enalbe the port for clke_b pin , 0: dislable + parameter WEB_ENABLE = 1'b1; //1: Enable the port for we_b pin , 0: disable + parameter BYTEENB_ENABLE = 1'b1; //1: Enable the port for Byteen_b pins , 0: disable + + + //Titanium extra paramters + parameter RSTA_POLARITY = 1'b1; // rst A polarity + parameter RESET_RAM_A = "ASYNC"; // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_A = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENA_POLARITY = 1'b1; // addrena polarity + + parameter RSTB_POLARITY = 1'b1; // rst A polarity + parameter RESET_RAM_B = "ASYNC"; // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_B = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENB_POLARITY = 1'b1; // addrenb polarity + + //Port Enable + parameter RESET_A_ENABLE = 1'b1; //1: Enable the port for reset_a pin , 0: disable + parameter ADDREN_A_ENABLE = 1'b1; //1: Enable the port for addren_a pin , 0: disable + + parameter RESET_B_ENABLE = 1'b1; //1: Enable the port for reset_b pin , 0: disable + parameter ADDREN_B_ENABLE = 1'b1; //1: Enable the port for addren_b pin , 0: disable + +`endif + + +`ifdef TEST_SP_ROM + `define SINGLE_TEST + parameter WE_POLARITY = 1'b1; // re polarity, 0:active low , 1:active high + + +//Trion and Titanium parameters + parameter CLK_POLARITY = 1'b1; //clk polarity, 0:falling edge, 1:rising edge + + parameter RE_POLARITY = 1'b1; // re polarity, 0:active low , 1:active high + parameter OUTPUT_REG = 1'b0; // Output register enable, 1:add pipe-line read register + + parameter RE_ENABLE = 1'b1; //1: Enable the port for RE pin , 0: disable + parameter BYTEEN_ENABLE = 1'b1; //1: Enable the port for Byteen pins , 0: disable + + //Titanium extra paramters + parameter RST_POLARITY = 1'b1; // rst polarity + parameter RESET_RAM = "ASYNC"; // reset mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG = "ASYNC"; // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDREN_POLARITY = 1'b1; // addren polarity + + + //Port Enable + parameter RESET_ENABLE = 1'b1; //1: Enable the port for reset pin , 0: disable + + parameter ADDREN_ENABLE = 1'b1; //1: Enable the port for addren pin , 0: disable + + +`endif + +`ifdef TEST_TDP_ROM + `define DUAL_TEST + parameter WEA_POLARITY = 1'b1; //we A polarity, 0:active low, 1:active high + parameter WEB_POLARITY = 1'b1; //we A polarity, 0:active low, 1:active high + + + + //Trion and Titanium parameters + parameter CLK_POLARITY = 1'b1; //clk polarity for one clk mode, 0:falling edge, 1:rising edge + parameter CLKE_POLARITY = 1'b1; //clke polarity for one clk mode, 0:active low, 1:active high + + parameter CLKA_POLARITY = 1'b1; //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEA_POLARITY = 1'b1; //clke A polarity, 0:active low, 1:active high + + parameter OUTPUT_REG_A = 1'b0; // Output register enable, 1:add pipe-line read register + parameter BYTEENA_POLARITY = 1'b1; // byteen polarity 0:active low, 1:active high + + parameter CLKB_POLARITY = 1'b1; //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEB_POLARITY = 1'b1; //clke A polarity, 0:active low, 1:active high + + parameter OUTPUT_REG_B = 1'b0; // Output register enable, 1:add pipe-line read register + parameter BYTEENB_POLARITY = 1'b1; // byteen polarity 0:active low, 1:active high + + + //Port Enable + parameter CLK_MODE = 2; //1: ONE CLK Mode, CLK pin will provide the clock source to the memory + //2: TWO CLK Mode, clk_a and clk_b + parameter CLKEA_ENABLE = 1'b1; //1: Enalbe the port for clke_a pin , 0: dislable + + parameter CLKEB_ENABLE = 1'b1; //1: Enalbe the port for clke_b pin , 0: dislable + + + //Titanium extra paramters + parameter RSTA_POLARITY = 1'b1; // rst A polarity + parameter RESET_RAM_A = "ASYNC"; // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_A = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENA_POLARITY = 1'b1; // addrena polarity + + parameter RSTB_POLARITY = 1'b1; // rst A polarity + parameter RESET_RAM_B = "ASYNC"; // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_B = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENB_POLARITY = 1'b1; // addrenb polarity + + //Port Enable + parameter RESET_A_ENABLE = 1'b1; //1: Enable the port for reset_a pin , 0: disable + parameter ADDREN_A_ENABLE = 1'b1; //1: Enable the port for addren_a pin , 0: disable + + parameter RESET_B_ENABLE = 1'b1; //1: Enable the port for reset_b pin , 0: disable + parameter ADDREN_B_ENABLE = 1'b1; //1: Enable the port for addren_b pin , 0: disable +`endif + + + +`include "bram_decompose.vh" + + + input i_arstn; + + output o_pll_bram_RSTN; + input i_pll_bram_LOCKED; + input i_wclk; + input i_rclk; + + + output o_led0_r; + output o_led0_g; + output o_led0_b; + + output o_led1_r; + output o_led1_g; + output o_led1_b; + + input i_sw0; + input i_sw1; + input i_sw2; + + // output [DATA_WIDTH_B-1:0] rdata; + + + + + + + +assign o_pll_bram_RSTN = 1'b1;//i_arstn; + +//assign w_re = RE_POLARITY; + +reg [2:0] r_led0_rgb; +reg [2:0] r_led1_rgb; + +wire w_pattern_rst; +wire w_bram_rst; +wire [2:0] w_state; + +assign {o_led0_r,o_led0_g,o_led0_b} = r_led0_rgb; +assign {o_led1_r,o_led1_g,o_led1_b} = r_led1_rgb; + + + + +`ifdef DUAL_TEST + +reset_ctrl +#( + .NUM_RST (2), + .CYCLE (10), + .IN_RST_ACTIVE (2'b00), + .OUT_RST_ACTIVE ({2{ RSTA_POLARITY }}) +) +inst_reset_mcu_ctrl +( + .i_arst ({2{i_pll_bram_LOCKED}}), + .i_clk ({2{i_wclk}}), + .o_srst ({w_pattern_rst,w_bram_rst}) +); + +wire w_wclke; +wire [BYTEEN_WIDTH_A-1:0] w_byteen_A; + +//Titanium extra ports +wire w_addren_A; +wire [ADDR_WIDTH_A-1:0] w_addr_A; +wire w_we_A; +wire [DATA_WIDTH_A-1:0] w_wdata_A; + +wire w_raddren_A; +wire w_re_A; +wire [DATA_WIDTH_A-1:0] w_rdata_A; + +wire [2:0] w_state_A; + + +wire [BYTEEN_WIDTH_B-1:0] w_byteen_B; +wire w_addren_B; +wire [ADDR_WIDTH_B-1:0] w_addr_B; +wire w_we_B; +wire [DATA_WIDTH_B-1:0] w_wdata_B; + +wire w_raddren_B; +wire w_re_B; +wire [DATA_WIDTH_B-1:0] w_rdata_B; + +wire [2:0] w_state_B; + + +localparam TEST_PORT_WRITE = 1; //0: write port A, 1: write port B +localparam TEST_BYTEEN_A = 0; //1: Shifting the Byten Enable in test. +localparam TEST_BYTEEN_B = 0; //1: Shifting the Byten Enable in test. + + +localparam TEST_PATTERN_A = (TEST_PORT_WRITE ==0)? "WriteRead": "READ"; +localparam TEST_PATTERN_B = (TEST_PORT_WRITE ==0)? "READ": "WriteRead"; + + + + wire w_compare_A; + test_pattern #( + //Trion and Titanium parameters + .WADDR_WIDTH (ADDR_WIDTH_A), + .WDATA_WIDTH (DATA_WIDTH_A), + .WRITE_COUNT (TOTAL_SIZE_A), + .BYTEEN_WIDTH(BYTEEN_WIDTH_A), + + .TEST_PATTERN(TEST_PATTERN_A), + .TEST_BYTEEN(TEST_BYTEEN_A), + + .WE_POLARITY (WEA_POLARITY), + + + .RADDR_WIDTH (ADDR_WIDTH_A), + .RDATA_WIDTH (DATA_WIDTH_A), + .READ_COUNT (TOTAL_SIZE_A), + .RE_POLARITY (WEA_POLARITY), + .OUTPUT_REG (OUTPUT_REG_A), + + .GROUP_DATA (GROUP_DATA_WIDTH) + ) + inst_test_pattern_A + ( + //Trion and Titanium ports + .clk(i_wclk), // clock input for one clock mode + + .reset(w_pattern_rst), + + .start_in(i_sw0), + .rd_start_in(i_sw2), + + .we(w_we_A), // write enale output + .waddr(w_addr_A), // Write address output + .wdata(w_wdata_A), // Write data output + .byteen(w_byteen_A), + + + .re(w_re_A), // read enale output + .raddr(), // read address output + .rdata(w_rdata_A), // read data output + + .state(w_state), + .compare(w_compare_A) + ); + + + wire w_compare_B; + test_pattern #( + //Trion and Titanium parameters + .WADDR_WIDTH (ADDR_WIDTH_B), + .WDATA_WIDTH (DATA_WIDTH_B), + .WRITE_COUNT (TOTAL_SIZE_B), + .BYTEEN_WIDTH(BYTEEN_WIDTH_B), + + .TEST_PATTERN(TEST_PATTERN_B), + .TEST_BYTEEN(TEST_BYTEEN_B), + + .WE_POLARITY (WEB_POLARITY), + + + .RADDR_WIDTH (ADDR_WIDTH_B), + .RDATA_WIDTH (DATA_WIDTH_B), + .READ_COUNT (TOTAL_SIZE_B), + .RE_POLARITY (WEB_POLARITY), + .OUTPUT_REG (OUTPUT_REG_B), + + .GROUP_DATA (GROUP_DATA_WIDTH) + ) + inst_test_pattern_B + ( + //Trion and Titanium ports + .clk(i_wclk), // clock input for one clock mode + + .reset(w_pattern_rst), + + .start_in(i_sw1), + .rd_start_in(i_sw2), + + .we(w_we_B), // write enale output + .waddr(w_addr_B), // Write address output + .wdata(w_wdata_B), // Write data output + .byteen(w_byteen_B), + + + .re(w_re_B), // read enale output + .raddr(), // read address output + .rdata(w_rdata_B), // read data output + + .state(w_state_B), + .compare(w_compare_B) + ); + + always@(*) + begin + + if (w_compare_A) + r_led1_rgb <= 3'b100; + else + r_led1_rgb <= 3'b001; + + // r_led0_rgb = w_state; + end + + always@(*) + begin + + if (w_compare_B) + r_led0_rgb <= 3'b100; + else + r_led0_rgb <= 3'b001; + + //r_led0_rgb = w_state; + end + +`else + + +reset_ctrl +#( + .NUM_RST (2), + .CYCLE (10), + .IN_RST_ACTIVE (2'b00), + .OUT_RST_ACTIVE ({2{ RST_POLARITY }}) +) +inst_reset_mcu_ctrl +( + .i_arst ({2{i_pll_bram_LOCKED}}), + .i_clk ({2{i_wclk}}), + .o_srst ({w_pattern_rst,w_bram_rst}) +); + +wire w_wclke; +wire [BYTEEN_WIDTH-1:0] w_byteen; + +//Titanium extra ports +wire w_waddren; +wire [ADDR_WIDTH_A-1:0] w_waddr; +wire w_we; +wire [DATA_WIDTH_A-1:0] w_wdata; + +wire w_raddren; +wire [ADDR_WIDTH_B-1:0] w_raddr; +wire [DATA_WIDTH_B-1:0] w_rdata; +wire w_wr_start; +wire w_wr_end; + + + +wire w_re; + +localparam TEST_PATTERN = "WriteRead"; + wire w_compare; +test_pattern #( + .TEST_PATTERN(TEST_PATTERN), + +//Trion and Titanium parameters + .WADDR_WIDTH (ADDR_WIDTH_A), + .WDATA_WIDTH (DATA_WIDTH_A), + .WRITE_COUNT (TOTAL_SIZE_A), + .WE_POLARITY (WE_POLARITY), + + + .RADDR_WIDTH (ADDR_WIDTH_B), + .RDATA_WIDTH (DATA_WIDTH_B), + .READ_COUNT (TOTAL_SIZE_B), + .RE_POLARITY (RE_POLARITY), + .OUTPUT_REG (OUTPUT_REG) +) +inst_test_pattern +( + //Trion and Titanium ports + .clk(i_wclk), // clock input for one clock mode + + .reset(w_pattern_rst), + + .start_in(i_sw0), + + .we(w_we), // write enale output + .waddr(w_waddr), // Write address output + .wdata(w_wdata), // Write data output + + + .re(w_re), // read enale output + .raddr(w_raddr), // read address output + .rdata(w_rdata), // read data output + + .state(w_state), + .compare(w_compare) + ); + +always@(*) +begin + + if (w_compare) + r_led1_rgb <= 3'b100; //FAIL + else + r_led1_rgb <= 3'b001; //PASS (only blue light ON on D17 LED) + + r_led0_rgb = w_state; +end + + + `endif + + + + + +`ifdef TEST_SP_RAM + +assign w_waddren = ADDREN_POLARITY; + +assign w_wclke = WCLKE_POLARITY; +assign w_byteen ={BYTEEN_WIDTH {BYTEEN_POLARITY} }; + + + efx_single_port_ram #( + .CLK_POLARITY (CLK_POLARITY ), + .WCLKE_POLARITY (WCLKE_POLARITY ), + .WE_POLARITY (WE_POLARITY ), + .WRITE_MODE (WRITE_MODE ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .BYTEEN_POLARITY (BYTEEN_POLARITY), + .WCLKE_ENABLE (WCLKE_ENABLE ), + .WE_ENABLE (WE_ENABLE ), + .RE_ENABLE (RE_ENABLE ), + .BYTEEN_ENABLE (BYTEEN_ENABLE ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .ADDREN_POLARITY (ADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .ADDREN_ENABLE (ADDREN_ENABLE ) + +) +inst_memory +( + .clk (i_wclk ), + .wclke (w_wclke ), + .byteen (w_byteen ), + .we (w_we ), + .addr (w_waddr), + .wdata (w_wdata), + .re (w_re ), + .rdata (w_rdata), + .reset (w_bram_rst), + .addren (w_waddren ) + ); + + `endif + + + `ifdef TEST_SP_ROM + +assign w_waddren = ADDREN_POLARITY; + + + + efx_single_port_rom #( + .CLK_POLARITY (CLK_POLARITY ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .RE_ENABLE (RE_ENABLE ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .ADDREN_POLARITY (ADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .ADDREN_ENABLE (ADDREN_ENABLE ) + +) +inst_memory +( + .clk (i_wclk ), + .addr (w_waddr), + .re (w_re ), + .rdata (w_rdata), + .reset (w_bram_rst), + .addren (w_waddren ) + ); + + `endif + +`ifdef TEST_SDP_RAM + + +assign w_waddren = WADDREN_POLARITY; +assign w_raddren = RADDREN_POLARITY; +assign w_wclke = WCLKE_POLARITY; +assign w_byteen = {BYTEEN_WIDTH {BYTEEN_POLARITY} }; + + efx_simple_dual_port_ram #( + .CLK_POLARITY (CLK_POLARITY ), + + .WCLK_POLARITY (WCLK_POLARITY ), + .WCLKE_POLARITY (WCLKE_POLARITY ), + .WE_POLARITY (WE_POLARITY ), + .WRITE_MODE (WRITE_MODE ), + + .RCLK_POLARITY (RCLK_POLARITY ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .BYTEEN_POLARITY (BYTEEN_POLARITY), + .CLK_MODE (CLK_MODE), + .WCLKE_ENABLE (WCLKE_ENABLE ), + .WE_ENABLE (WE_ENABLE ), + .RE_ENABLE (RE_ENABLE ), + .BYTEEN_ENABLE (BYTEEN_ENABLE ), + + .DATA_WIDTH_A (DATA_WIDTH_A ), + .DATA_WIDTH_B (DATA_WIDTH_B ), + .ADDR_WIDTH_A (ADDR_WIDTH_A ), + .ADDR_WIDTH_B (ADDR_WIDTH_B ), + .BYTEEN_WIDTH (BYTEEN_WIDTH ), + .FAMILY (FAMILY ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .RADDREN_POLARITY (RADDREN_POLARITY), + .WADDREN_POLARITY (WADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .RADDREN_ENABLE (RADDREN_ENABLE ), + .WADDREN_ENABLE (WADDREN_ENABLE ) + +) +inst_memory +( + .clk (i_wclk ), //for 1 clock mode + + .wclk (i_wclk ), //for 2 clock mode + .wclke (w_wclke ), + .byteen (w_byteen ), + .we (w_we ), + .waddr (w_waddr), + .wdata ({~w_wdata[7:0],w_wdata[7:0]}), + + .rclk (i_wclk ), //i_rclk for 2 clock mode + .re (w_re ), + .raddr (w_raddr), + .rdata (w_rdata), + + .reset (w_bram_rst), + .waddren (w_waddren ), + .raddren (w_raddren ) + ); + + `endif + + `ifdef TEST_TDP_RAM + + +assign w_addren_A = ADDRENA_POLARITY; +assign w_clke_A = CLKEA_POLARITY; +assign w_byteen_A ={BYTEEN_WIDTH {BYTEENA_POLARITY} }; + +assign w_addren_B = ADDRENB_POLARITY; +assign w_clke_B = CLKEB_POLARITY; +assign w_byteen_B ={BYTEEN_WIDTH {BYTEENB_POLARITY} }; + + + efx_true_dual_port_ram #( + + //Trion and Titanium parameters + .CLK_POLARITY ( CLK_POLARITY ), + .CLKE_POLARITY ( CLKE_POLARITY ), + .CLKA_POLARITY ( CLKA_POLARITY ), + .CLKEA_POLARITY ( CLKEA_POLARITY ), + .WEA_POLARITY ( WEA_POLARITY ), + .WRITE_MODE_A ( WRITE_MODE_A ), + .OUTPUT_REG_A ( OUTPUT_REG_A ), + .BYTEENA_POLARITY( BYTEENA_POLARITY), + .CLKB_POLARITY ( CLKB_POLARITY ), + .CLKEB_POLARITY ( CLKEB_POLARITY ), + .WEB_POLARITY ( WEB_POLARITY ), + .WRITE_MODE_B ( WRITE_MODE_B ), + .OUTPUT_REG_B ( OUTPUT_REG_B ), + .BYTEENB_POLARITY(BYTEENB_POLARITY), + + + //Port Enable + .CLK_MODE (CLK_MODE ), + .CLKEA_ENABLE (CLKEA_ENABLE ), + .WEA_ENABLE (WEA_ENABLE ), + .BYTEENA_ENABLE (BYTEENA_ENABLE ), + .CLKEB_ENABLE (CLKEB_ENABLE ), + .WEB_ENABLE (WEB_ENABLE ), + .BYTEENB_ENABLE (BYTEENB_ENABLE ), + + + //Titanium extra paramters + .RSTA_POLARITY (RSTA_POLARITY ), + .RESET_RAM_A (RESET_RAM_A ), + .RESET_OUTREG_A (RESET_OUTREG_A ), + .ADDRENA_POLARITY (ADDRENA_POLARITY ), + .RSTB_POLARITY (RSTB_POLARITY ), + .RESET_RAM_B (RESET_RAM_B ), + .RESET_OUTREG_B (RESET_OUTREG_B ), + .ADDRENB_POLARITY (ADDRENB_POLARITY ), + + //Port Enable + .RESET_A_ENABLE (RESET_A_ENABLE ), + .ADDREN_A_ENABLE (ADDREN_A_ENABLE), + .RESET_B_ENABLE (RESET_B_ENABLE ), + .ADDREN_B_ENABLE (ADDREN_B_ENABLE) +) +inst_memory +( + //Trion and Titanium ports + .clk(i_wclk), // for 1 clock mode + .clke(w_clke_A), // for 1 clock mode + + .clk_a(i_wclk), //for 2 clock mode + .clke_a(w_clke_A), + .byteen_a(w_byteen_A), + .we_a(w_we_A), + .addr_a(w_addr_A), + .wdata_a(w_wdata_A), + .rdata_a(w_rdata_A), + + .clk_b(i_rclk), //for 2 clock mode + .clke_b(w_clke_B), + .byteen_b(w_byteen_B), + .we_b(w_we_B), + .addr_b(w_addr_B), + .wdata_b(w_wdata_B), + .rdata_b(w_rdata_B), + + //Titanium extra ports + .reset_a(w_bram_rst), + .addren_a(w_addren_A), + .reset_b(w_bram_rst), + .addren_b(w_addren_B) + + ); + + `endif + + + +`ifdef TEST_TDP_ROM + + +assign w_addren_A = ADDRENA_POLARITY; +assign w_clke_A = CLKEA_POLARITY; +assign w_byteen_A ={BYTEEN_WIDTH {BYTEENA_POLARITY} }; + +assign w_addren_B = ADDRENB_POLARITY; +assign w_clke_B = CLKEB_POLARITY; +assign w_byteen_B ={BYTEEN_WIDTH {BYTEENB_POLARITY} }; + + + efx_true_dual_port_rom #( + + //Trion and Titanium parameters + .CLK_POLARITY ( CLK_POLARITY ), + .CLKE_POLARITY ( CLKE_POLARITY ), + .CLKA_POLARITY ( CLKA_POLARITY ), + .CLKEA_POLARITY ( CLKEA_POLARITY ), + + .OUTPUT_REG_A ( OUTPUT_REG_A ), + .CLKB_POLARITY ( CLKB_POLARITY ), + .CLKEB_POLARITY ( CLKEB_POLARITY ), + .OUTPUT_REG_B ( OUTPUT_REG_B ), + + + //Port Enable + .CLK_MODE (CLK_MODE ), + .CLKEA_ENABLE (CLKEA_ENABLE ), + .CLKEB_ENABLE (CLKEB_ENABLE ), + + + //Titanium extra paramters + .RSTA_POLARITY (RSTA_POLARITY ), + .RESET_RAM_A (RESET_RAM_A ), + .RESET_OUTREG_A (RESET_OUTREG_A ), + .ADDRENA_POLARITY (ADDRENA_POLARITY ), + .RSTB_POLARITY (RSTB_POLARITY ), + .RESET_RAM_B (RESET_RAM_B ), + .RESET_OUTREG_B (RESET_OUTREG_B ), + .ADDRENB_POLARITY (ADDRENB_POLARITY ), + + //Port Enable + .RESET_A_ENABLE (RESET_A_ENABLE ), + .ADDREN_A_ENABLE (ADDREN_A_ENABLE), + .RESET_B_ENABLE (RESET_B_ENABLE ), + .ADDREN_B_ENABLE (ADDREN_B_ENABLE) +) +inst_memory +( + //Trion and Titanium ports + .clk(i_wclk), // for 1 clock mode + .clke(w_clke_A), // for 1 clock mode + + .clk_a(i_wclk), //for 2 clock mode + .clke_a(w_clke_A), + .addr_a(w_addr_A), + .rdata_a(w_rdata_A), + + .clk_b(i_rclk), //for 2 clock mode + .clke_b(w_clke_B), + .addr_b(w_addr_B), + .rdata_b(w_rdata_B), + + //Titanium extra ports + .reset_a(w_bram_rst), + .addren_a(w_addren_A), + .reset_b(w_bram_rst), + .addren_b(w_addren_B) + + ); + + `endif + +endmodule \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/efx_simple_dual_port_ram.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/efx_simple_dual_port_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..0fd0d6e3f814aa2f14c0a5f0827740923356fd25 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/efx_simple_dual_port_ram.v @@ -0,0 +1,194 @@ +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// +// ******************************* + +module efx_simple_dual_port_ram ( + //Trion and Titanium ports + clk, // clock input for one clock mode + + + wclk, // Write clock input for two clock mode + wclke, // Write clock-enable input + byteen, // Byteen input + we, // Write-enable input + waddr, // Write address input + wdata, // Write data input + + rclk, // Read clock input for two clock mode + re, // Read-enable input + raddr, // Read address input + rdata, // Read data output + + //Titanium extra ports + reset, // reset + waddren, // write address enable + raddren // read address enable +); + +//`include "bram_decompose.vh" + +//Trion and Titanium parameters +parameter CLK_POLARITY = 1'b1; //clk polarity; 0:falling edge; 1:rising edge + +parameter WCLK_POLARITY = 1'b1; //wclk polarity; 0:falling edge; 1:rising edge +parameter WCLKE_POLARITY = 1'b1; //wclke polarity; 0:active low; 1:active high +parameter WE_POLARITY = 1'b1; //we polarity; 0:active low; 1:active high + +parameter RCLK_POLARITY = 1'b1; // rclk polarity; 0:falling edge; 1:rising edge +parameter RE_POLARITY = 1'b1; // re polarity; 0:active low ; 1:active high +parameter OUTPUT_REG = 1'b0; // Output register enable; 1:add pipe-line read register + +parameter BYTEEN_POLARITY = 1'b1; //byteen polarity; 0:active low; 1:active high + +//Port Enable +parameter CLK_MODE = 2; //1: ONE CLK Mode; CLK pin will provide the clock source to the memory + //2: TWO CLK Mode; wclk pin will provide the clock source for write operation ; rclk pin will provide the clock source for read operation +parameter WCLKE_ENABLE = 1'b1; //1: Enalbe the port for waddren pin ; 0: dislable + +parameter WE_ENABLE = 1'b1; //1: Enable the port for WE pin ; 0: disable +parameter RE_ENABLE = 1'b1; //1: Enable the port for RE pin ; 0: disable +parameter BYTEEN_ENABLE = 1'b1; //1: Enable the port for Byteen pins ; 0: disable + +//Titanium extra paramters +parameter RST_POLARITY = 1'b1; // rst polarity +parameter RESET_RAM = "ASYNC"; // reset mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG = "ASYNC"; // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter WADDREN_POLARITY = 1'b1; // waddren polarity +parameter RADDREN_POLARITY = 1'b1; // raddren polarity + + +//Port Enable +parameter RESET_ENABLE = 1'b1; //1: Enable the port for reset pin ; 0: disable + +parameter WADDREN_ENABLE = 1'b1; //1: Enable the port for waddren pin ; 0: disable +parameter RADDREN_ENABLE = 1; //1: Enable the port for raddren pin ; 0: disable + +parameter WRITE_MODE = "READ_FIRST"; + +parameter DATA_WIDTH_A = 16; +parameter DATA_WIDTH_B = 16; +parameter ADDR_WIDTH_A = 3; +parameter ADDR_WIDTH_B = 3; +parameter BYTEEN_WIDTH = 2; +parameter FAMILY = "TITANIUM"; + +//Trion and Titanium ports +input clk; + +input wclk; +input wclke; +input [BYTEEN_WIDTH-1:0] byteen; +input we; +input [ADDR_WIDTH_A-1:0] waddr; +input [DATA_WIDTH_A-1:0] wdata; + +input rclk; +input re; +input [ADDR_WIDTH_B-1:0] raddr; +output [DATA_WIDTH_B-1:0] rdata; + +//Titanium extra ports +input reset; +input waddren; +input raddren; + +//localparam WRITE_MODE = DECOMPOSE_WRITE_MODE; // "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + + +wire w_wclk; +wire w_rclk; +wire w_wclke; +wire [BYTEEN_WIDTH-1:0] w_byteen; +wire w_we; +wire w_re; +wire w_reset; +wire w_waddren; +wire w_raddren; + +assign w_wclk = (CLK_MODE==2) ? wclk : clk; +assign w_rclk = (CLK_MODE==2) ? rclk : clk; +assign w_wclke = (WCLKE_ENABLE==1) ? wclke : WCLKE_POLARITY; +assign w_byteen= (BYTEEN_ENABLE==1) ? byteen : {BYTEEN_WIDTH{BYTEEN_POLARITY}}; +assign w_we = (WE_ENABLE==1) ? we : WE_POLARITY; +assign w_re = (RE_ENABLE==1) ? re : RE_POLARITY; + +//Titanium extra ports +assign w_reset = (RESET_ENABLE==1) ? reset : (RST_POLARITY==1'b1) ? 1'b0: 1'b1; +assign w_waddren = (WADDREN_ENABLE==1)? waddren : WADDREN_POLARITY; +assign w_raddren = (RADDREN_ENABLE==1)? raddren : RADDREN_POLARITY; + + +localparam WCLK_POLARITY_LC = (CLK_MODE==2) ? WCLK_POLARITY : CLK_POLARITY; +localparam RCLK_POLARITY_LC = (CLK_MODE==2) ? RCLK_POLARITY : CLK_POLARITY; + + + + bram_wrapper_mwm #( + //Trion and Titanium parameters + .WCLK_POLARITY(WCLK_POLARITY_LC), + .WCLKE_POLARITY(WCLKE_POLARITY), + .WE_POLARITY(WE_POLARITY), + .WRITE_MODE(WRITE_MODE), + + .RCLK_POLARITY(RCLK_POLARITY_LC), + .RE_POLARITY(RE_POLARITY), + .OUTPUT_REG(OUTPUT_REG), + + .BYTEEN_POLARITY(BYTEEN_POLARITY), + + .DATA_WIDTH_A(DATA_WIDTH_A), + .DATA_WIDTH_B(DATA_WIDTH_B), + .ADDR_WIDTH_A(ADDR_WIDTH_A), + .ADDR_WIDTH_B(ADDR_WIDTH_B), + .BYTEEN_WIDTH(BYTEEN_WIDTH), + .FAMILY(FAMILY), + + //Titanium extra paramters + .RST_POLARITY(RST_POLARITY), + .RESET_RAM(RESET_RAM), + .RESET_OUTREG(RESET_OUTREG), + .WADDREN_POLARITY(WADDREN_POLARITY), + .RADDREN_POLARITY(RADDREN_POLARITY) + + ) brams ( + .wclk(w_wclk), + .wclke(w_wclke), + .we(w_we), + .byteen(w_byteen), + + .waddr(waddr), + .wdata(wdata), + + .rclk(w_rclk), + .re(w_re), + .raddr(raddr), + .rdata(rdata), + + + //Titanium extra ports + .reset(w_reset), // reset + .waddren(w_waddren), // write address enable + .raddren(w_raddren) // read address enable + ); + + +endmodule \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/my_bram_ip.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/my_bram_ip.v new file mode 100644 index 0000000000000000000000000000000000000000..79d9b4df6c85e2e89787a5132ab876cb32cfc6bd --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/my_bram_ip.v @@ -0,0 +1,2110 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _f3a990bbbff84057a1e36dad7040b59c +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module my_bram_ip ( +input we_a, +input we_b, +input [10:0] addr_a, +input [7:0] wdata_a, +output [7:0] rdata_a, +output [7:0] rdata_b, +input [10:0] addr_b, +input [7:0] wdata_b, +input clk_a, +input clk_b +); +`IP_MODULE_NAME(efx_bram) #( +.ADDR_WIDTH_A (11), +.ADDR_WIDTH_B (11), +.RESET_A_ENABLE (0), +.RESET_B_ENABLE (0), +.RSTA_POLARITY (1), +.RSTB_POLARITY (1), +.FAMILY ("TITANIUM"), +.MEMORY_MODE ("SPEED"), +.WRITE_MODE_A ("READ_FIRST"), +.WRITE_MODE_B ("READ_FIRST"), +.OUTPUT_REG_A (0), +.OUTPUT_REG_B (0), +.MEMORY_TYPE ("TDP_RAM"), +.GROUP_DATA_WIDTH_B (8), +.BYTEENA_ENABLE (0), +.BYTEENB_ENABLE (0), +.BYTEENA_POLARITY (1), +.BYTEENB_POLARITY (1), +.BYTEEN_WIDTH_A (1), +.BYTEEN_WIDTH_B (1), +.BYTEEN_ENABLE (0), +.BYTEEN_POLARITY (1), +.GROUP_DATA_WIDTH (8), +.BYTEEN_WIDTH (1), +.WIDTH_RATIO (4), +.GROUP_DATA_WIDTH_A (8), +.DATA_WIDTH_A (8), +.DATA_WIDTH_B (8), +.ADDREN_ENABLE (1), +.ADDREN_POLARITY (1), +.CLK_MODE (2), +.CLKA_POLARITY (1), +.CLKB_POLARITY (1), +.CLKE_POLARITY (1), +.CLKEA_POLARITY (1), +.CLKEA_ENABLE (0), +.RESET_OUTREG_A ("ASYNC"), +.RESET_OUTREG_B ("ASYNC"), +.RESET_RAM_B ("ASYNC"), +.WEA_ENABLE (1), +.WEA_POLARITY (1), +.WEB_ENABLE (1), +.WEB_POLARITY (1), +.RADDREN_ENABLE (1), +.RADDREN_POLARITY (1), +.WADDREN_ENABLE (1), +.WADDREN_POLARITY (1), +.RCLK_POLARITY (1), +.ADDREN_A_ENABLE (0), +.ADDREN_B_ENABLE (0), +.ADDRENA_POLARITY (1), +.ADDRENB_POLARITY (1), +.WE_ENABLE (1), +.WE_POLARITY (1), +.WCLKE_ENABLE (1), +.WCLKE_POLARITY (1), +.WCLK_POLARITY (1), +.RESET_RAM_A ("ASYNC"), +.RESET_RAM ("ASYNC"), +.CLK_POLARITY (1), +.OUTPUT_REG (0), +.RE_POLARITY (1), +.RE_ENABLE (1), +.WRITE_MODE ("READ_FIRST"), +.RESET_OUTREG ("ASYNC"), +.RESET_ENABLE (1), +.RST_POLARITY (1), +.CLKEB_POLARITY (1), +.CLKEB_ENABLE (0) +) u_efx_bram( +.we_a ( we_a ), +.we_b ( we_b ), +.addr_a ( addr_a ), +.wdata_a ( wdata_a ), +.rdata_a ( rdata_a ), +.rdata_b ( rdata_b ), +.addr_b ( addr_b ), +.wdata_b ( wdata_b ), +.clk_a ( clk_a ), +.clk_b ( clk_b ) +); + +endmodule + +module `IP_MODULE_NAME(efx_bram) #( + +parameter CLK_POLARITY = 1'b1, //clk polarity; 0:falling edge; 1:rising edge +parameter CLKE_POLARITY = 1'b1, //clke polarity for one clk mode; 0:active low; 1:active high +parameter CLKA_POLARITY = 1'b1, //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEA_POLARITY = 1'b1, //clke A polarity; 0:active low; 1:active high +parameter WEA_POLARITY = 1'b1, //we A polarity; 0:active low; 1:active high +parameter OUTPUT_REG_A = 1'b0, // Output register enable; 1:add pipe-line read register +parameter BYTEENA_POLARITY = 1'b1, // byteen polarity 0:active low; 1:active high +parameter CLKB_POLARITY = 1'b1, //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEB_POLARITY = 1'b1, //clke A polarity; 0:active low; 1:active high +parameter WEB_POLARITY = 1'b1, //we B polarity; 0:active low; 1:active high +parameter OUTPUT_REG_B = 1'b0, // Output register enable; 1:add pipe-line read register +parameter BYTEENB_POLARITY = 1'b1, // byteen polarity 0:active low; 1:active high +parameter WCLKE_POLARITY = 1'b1, //wclke polarity; 0:active low; 1:active high +parameter WCLK_POLARITY = 1'b1, //wclk polarity; 0:falling edge; 1:rising edge +parameter RCLK_POLARITY = 1'b1, // rclk polarity; 0:falling edge; 1:rising edge +parameter WE_POLARITY = 1'b1, //we polarity; 0:active low; 1:active high +parameter RE_POLARITY = 1'b1, // re polarity; 0:active low ; 1:active high +parameter OUTPUT_REG = 1'b0, // Output register enable; 1:add pipe-line read register +parameter BYTEEN_POLARITY = 1'b1, //byteen polarity; 0:active low; 1:active high +parameter WCLKE_ENABLE = 1'b1, //1: Enable the port for waddren pin ; 0: disable +parameter WE_ENABLE = 1'b1, //1: Enable the port for WE pin ; 0: disable +parameter RE_ENABLE = 1'b1, //1: Enable the port for RE pin ; 0: disable +parameter BYTEEN_ENABLE = 1'b1, //1: Enable the port for Byteen pins ; 0: disable +parameter RST_POLARITY = 1'b1, // rst polarity +parameter RESET_RAM = "ASYNC", // reset mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG = "ASYNC", // reset mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDREN_POLARITY = 1'b1, // addren polarity +parameter RESET_ENABLE = 1'b1, //1: Enable the port for reset pin ; 0: disable +parameter ADDREN_ENABLE = 1'b1, //1: Enable the port for addren pin ; 0: disable +parameter CLK_MODE = 2, //1: ONE CLK Mode; CLK pin will provide the clock source to the memory + //2: TWO CLK Mode; wclk pin will provide the clock source for write operation ; rclk pin will provide the clock source for read operation +parameter WADDREN_POLARITY = 1'b1, // waddren polarity +parameter RADDREN_POLARITY = 1'b1, // raddren polarity +parameter CLKEA_ENABLE = 1'b1, //1: Enalbe the port for clke_a pin ; 0: dislable +parameter WEA_ENABLE = 1'b1, //1: Enable the port for we_a pin ; 0: disable +parameter BYTEENA_ENABLE = 1'b1, //1: Enable the port for Byteen_a pins ; 0: disable + // +parameter CLKEB_ENABLE = 1'b1, //1: Enalbe the port for clke_b pin ; 0: dislable +parameter WEB_ENABLE = 1'b1, //1: Enable the port for we_b pin ; 0: disable +parameter BYTEENB_ENABLE = 1'b1, //1: Enable the port for Byteen_b pins ; 0: disable +parameter RSTA_POLARITY = 1'b1, // rst A polarity +parameter RESET_RAM_A = "ASYNC", // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_A = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENA_POLARITY = 1'b1, // addrena polarity +parameter RSTB_POLARITY = 1'b1, // rst A polarity +parameter RESET_RAM_B = "ASYNC", // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_B = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENB_POLARITY = 1'b1, // addrenb polarity +parameter RESET_A_ENABLE = 1'b1, //1: Enable the port for reset_a pin ; 0: disable +parameter ADDREN_A_ENABLE = 1'b1, //1: Enable the port for addren_a pin ; 0: disable +parameter RESET_B_ENABLE = 1'b1, //1: Enable the port for reset_b pin ; 0: disable +parameter ADDREN_B_ENABLE = 1'b1, //1: Enable the port for addren_b pin ; 0: disable +parameter WADDREN_ENABLE = 1'b1, //1: Enable the port for waddren pin ; 0: disable +parameter RADDREN_ENABLE = 1'b1, //1: Enable the port for raddren pin ; 0: disable + +parameter ADDR_WIDTH_A = 3, +parameter DATA_WIDTH_A = 16, +parameter ADDR_WIDTH_B = 3, +parameter DATA_WIDTH_B = 16, +parameter BYTEEN_WIDTH = 2, +parameter BYTEEN_WIDTH_A = 2, +parameter BYTEEN_WIDTH_B = 2, +parameter MEMORY_TYPE = "SP_RAM", //1:sp_ram, 2:sdp_ram, 3:tdp_ram +parameter WRITE_MODE = "READ_FIRST", +parameter WRITE_MODE_A = "READ_FIRST", +parameter WRITE_MODE_B = "READ_FIRST", +parameter FAMILY = "TITANIUM", //1:Titanium, 0:Trion +parameter GROUP_DATA_WIDTH = 8, +parameter GROUP_DATA_WIDTH_A= 8, +parameter GROUP_DATA_WIDTH_B= 8, +parameter MEMORY_MODE = "SPEED", //1:speed, 2:area +parameter WIDTH_RATIO = 4 +) + + +( +//////////// data input/output /////////////////// +input wire [DATA_WIDTH_A-1:0] wdata_a, +input wire [DATA_WIDTH_B-1:0] wdata_b, +output wire [DATA_WIDTH_A-1:0] rdata_a, +output wire [DATA_WIDTH_B-1:0] rdata_b, + +///////// Single Port RAM/ROM ports //////////// +input wire clk, +input wire [ADDR_WIDTH_A-1:0] addr, +input wire wclke, +input wire [BYTEEN_WIDTH-1:0] byteen, +input wire we, +input wire re, +//Titanium extra ports +input wire reset, +input wire addren, + +//////////// Simple Dual Port RAM ports /////////// +input wire wclk, +input wire [ADDR_WIDTH_A-1:0] waddr, +input wire rclk, +input wire [ADDR_WIDTH_B-1:0] raddr, +//Titanium extra ports +input wire waddren, +input wire raddren, + +//////////True Dual Port RAM/ROM ports //////////////// +input wire clke, +input wire clk_a, +input wire clke_a, +input wire we_a, +input wire [BYTEEN_WIDTH_A-1:0] byteen_a, +input wire [ADDR_WIDTH_A-1:0 ] addr_a, +input wire clk_b, +input wire clke_b, +input wire we_b, +input wire [BYTEEN_WIDTH_B-1:0] byteen_b, +input wire [ADDR_WIDTH_B-1:0 ] addr_b, +//Titanium extra ports +input wire reset_a, +input wire addren_a, +input wire reset_b, +input wire addren_b +); + +generate + if (MEMORY_TYPE == "SP_RAM") //Single Port RAM + begin + //if (BYTEEN_ENABLE == 1) + //begin + + `IP_MODULE_NAME(efx_single_port_ram) #( + .CLK_POLARITY (CLK_POLARITY ), + .WCLKE_POLARITY (WCLKE_POLARITY ), + .WE_POLARITY (WE_POLARITY ), + .WRITE_MODE (WRITE_MODE ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .BYTEEN_POLARITY (BYTEEN_POLARITY), + .WCLKE_ENABLE (WCLKE_ENABLE ), + .WE_ENABLE (WE_ENABLE ), + .RE_ENABLE (RE_ENABLE ), + .BYTEEN_ENABLE (BYTEEN_ENABLE ), + + .BYTEEN_WIDTH (BYTEEN_WIDTH ), + .ADDR_WIDTH_A (ADDR_WIDTH_A ), + .DATA_WIDTH_A (DATA_WIDTH_A ), + + .FAMILY (FAMILY ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .ADDREN_POLARITY (ADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .ADDREN_ENABLE (ADDREN_ENABLE ) + ) + spram_inst + ( + .clk (clk ), + .addr (addr ), + .wclke (wclke ), + .byteen (byteen ), + .we (we ), + .wdata_a (wdata_a), + .re (re ), + .rdata_a (rdata_a), + .reset (reset ), + .addren (addren ) + ); + //end + //else if (BYTEEN_ENABLE == 0) + //begin + // + // `IP_MODULE_NAME(efx_single_port_ram) #( + // .CLK_POLARITY (CLK_POLARITY ), + // .WCLKE_POLARITY (WCLKE_POLARITY ), + // .WE_POLARITY (WE_POLARITY ), + // .WRITE_MODE (WRITE_MODE ), + // .RE_POLARITY (RE_POLARITY ), + // .OUTPUT_REG (OUTPUT_REG ), + // .BYTEEN_POLARITY (BYTEEN_POLARITY), + // .WCLKE_ENABLE (WCLKE_ENABLE ), + // .WE_ENABLE (WE_ENABLE ), + // .RE_ENABLE (RE_ENABLE ), + // .BYTEEN_ENABLE (BYTEEN_ENABLE ), + // + // .BYTEEN_WIDTH (BYTEEN_WIDTH ), + // .ADDR_WIDTH_A (ADDR_WIDTH_A ), + // .DATA_WIDTH_A (DATA_WIDTH_A ), + // .DATA_WIDTH_B (DATA_WIDTH_B ), + // + // .FAMILY (FAMILY ), + // + // //Titanium extra paramters + // .RST_POLARITY (RST_POLARITY ), + // .RESET_RAM (RESET_RAM ), + // .RESET_OUTREG (RESET_OUTREG ), + // .ADDREN_POLARITY (ADDREN_POLARITY), + // .RESET_ENABLE (RESET_ENABLE ), + // .ADDREN_ENABLE (ADDREN_ENABLE ) + // ) + // spram_inst + // ( + // .clk (clk ), + // .addr (addr ), + // .wclke (wclke ), + // .we (we ), + // .wdata_a(wdata_a), + // .re (re ), + // .rdata_a(rdata_a), + // .reset (reset ), + // .addren (addren ) + // ); + //end + end + else if (MEMORY_TYPE == "SDP_RAM") //Simple Dual Port RAM + begin + + `IP_MODULE_NAME(efx_simple_dual_port_ram) #( + .CLK_POLARITY (CLK_POLARITY ), + .WCLK_POLARITY (WCLK_POLARITY ), + .WCLKE_POLARITY (WCLKE_POLARITY ), + .WE_POLARITY (WE_POLARITY ), + .WRITE_MODE (WRITE_MODE ), + + .RCLK_POLARITY (RCLK_POLARITY ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .BYTEEN_POLARITY (BYTEEN_POLARITY), + .CLK_MODE (CLK_MODE), + .WCLKE_ENABLE (WCLKE_ENABLE ), + .WE_ENABLE (WE_ENABLE ), + .RE_ENABLE (RE_ENABLE ), + .BYTEEN_ENABLE (BYTEEN_ENABLE ), + + .BYTEEN_WIDTH (BYTEEN_WIDTH ), + .ADDR_WIDTH_A (ADDR_WIDTH_A ), + .DATA_WIDTH_A (DATA_WIDTH_A ), + .ADDR_WIDTH_B (ADDR_WIDTH_B ), + .DATA_WIDTH_B (DATA_WIDTH_B ), + + .FAMILY (FAMILY ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .RADDREN_POLARITY (RADDREN_POLARITY), + .WADDREN_POLARITY (WADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .RADDREN_ENABLE (RADDREN_ENABLE ), + .WADDREN_ENABLE (WADDREN_ENABLE) + ) + sdpram_inst + ( + .clk (clk ), + .wclk (wclk ), + .wclke (wclke ), + .byteen (byteen ), + .we (we ), + .waddr (waddr ), + .wdata_a (wdata_a ), + .rclk (rclk ), + .re (re ), + .raddr (raddr ), + .rdata_b (rdata_b ), + .reset (reset ), + .waddren (waddren ), + .raddren (raddren ) + + ); + + end + else if (MEMORY_TYPE == "TDP_RAM") //True Dual Port RAM + begin + + `IP_MODULE_NAME(efx_true_dual_port_ram) #( + + //Trion and Titanium parameters + .CLK_POLARITY (CLK_POLARITY ), + .CLKE_POLARITY (CLKE_POLARITY ), + .CLKA_POLARITY (CLKA_POLARITY ), + .CLKEA_POLARITY (CLKEA_POLARITY ), + .WEA_POLARITY (WEA_POLARITY ), + .WRITE_MODE_A (WRITE_MODE_A ), + .OUTPUT_REG_A (OUTPUT_REG_A ), + .BYTEENA_POLARITY(BYTEENA_POLARITY), + .CLKB_POLARITY (CLKB_POLARITY ), + .CLKEB_POLARITY (CLKEB_POLARITY ), + .WEB_POLARITY (WEB_POLARITY ), + .WRITE_MODE_B (WRITE_MODE_B ), + .OUTPUT_REG_B (OUTPUT_REG_B ), + .BYTEENB_POLARITY(BYTEENB_POLARITY), + + .BYTEEN_WIDTH_A (BYTEEN_WIDTH_A ), + .BYTEEN_WIDTH_B (BYTEEN_WIDTH_B ), + .ADDR_WIDTH_A (ADDR_WIDTH_A ), + .DATA_WIDTH_A (DATA_WIDTH_A ), + .ADDR_WIDTH_B (ADDR_WIDTH_B ), + .DATA_WIDTH_B (DATA_WIDTH_B ), + + .FAMILY (FAMILY ), + + + //Port Enable + .CLK_MODE (CLK_MODE ), + .CLKEA_ENABLE (CLKEA_ENABLE ), + .WEA_ENABLE (WEA_ENABLE ), + .BYTEENA_ENABLE (BYTEENA_ENABLE ), + .CLKEB_ENABLE (CLKEB_ENABLE ), + .WEB_ENABLE (WEB_ENABLE ), + .BYTEENB_ENABLE (BYTEENB_ENABLE ), + + + //Titanium extra paramters + .RSTA_POLARITY (RSTA_POLARITY ), + .RESET_RAM_A (RESET_RAM_A ), + .RESET_OUTREG_A (RESET_OUTREG_A ), + .ADDRENA_POLARITY (ADDRENA_POLARITY ), + .RSTB_POLARITY (RSTB_POLARITY ), + .RESET_RAM_B (RESET_RAM_B ), + .RESET_OUTREG_B (RESET_OUTREG_B ), + .ADDRENB_POLARITY (ADDRENB_POLARITY ), + + //Port Enable + .RESET_A_ENABLE (RESET_A_ENABLE ), + .ADDREN_A_ENABLE (ADDREN_A_ENABLE), + .RESET_B_ENABLE (RESET_B_ENABLE ), + .ADDREN_B_ENABLE (ADDREN_B_ENABLE) + ) + tdpram_inst + ( + .clk (clk ), + .clke (clke ), + .clk_a (clk_a ), + .clke_a (clke_a ), + .we_a (we_a ), + .byteen_a (byteen_a), + .addr_a (addr_a ), + .wdata_a (wdata_a), + .rdata_a (rdata_a), + .clk_b (clk_b ), + .clke_b (clke_b ), + .we_b (we_b ), + .byteen_b (byteen_b), + .addr_b (addr_b ), + .wdata_b (wdata_b), + .rdata_b (rdata_b), + .reset_a (reset_a), + .addren_a (addren_a), + .reset_b (reset_b), + .addren_b (addren_b) + + ); + end + else if (MEMORY_TYPE == "SP_ROM") //Single Port ROM + begin + + `IP_MODULE_NAME(efx_single_port_rom) #( + + .CLK_POLARITY (CLK_POLARITY ), + .RE_POLARITY (RE_POLARITY ), + .OUTPUT_REG (OUTPUT_REG ), + .RE_ENABLE (RE_ENABLE ), + + .BYTEEN_WIDTH (BYTEEN_WIDTH ), + .ADDR_WIDTH_A (ADDR_WIDTH_A ), + .DATA_WIDTH_A (DATA_WIDTH_A ), + .FAMILY (FAMILY ), + + //Titanium extra paramters + .RST_POLARITY (RST_POLARITY ), + .RESET_RAM (RESET_RAM ), + .RESET_OUTREG (RESET_OUTREG ), + .ADDREN_POLARITY (ADDREN_POLARITY), + .RESET_ENABLE (RESET_ENABLE ), + .ADDREN_ENABLE (ADDREN_ENABLE ) + + ) + sprom_inst + ( + .clk (clk ), + .addr (addr ), + .re (re ), + .rdata_a (rdata_a), + .reset (reset ), + .addren (addren) + + ); + end + else if (MEMORY_TYPE == "DP_ROM") //Dual Port ROM + begin + + `IP_MODULE_NAME(efx_dual_port_rom) #( + + //Trion and Titanium parameters + .CLK_POLARITY ( CLK_POLARITY ), + .CLKE_POLARITY ( CLKE_POLARITY ), + .CLKA_POLARITY ( CLKA_POLARITY ), + .CLKEA_POLARITY ( CLKEA_POLARITY ), + + .OUTPUT_REG_A ( OUTPUT_REG_A ), + .CLKB_POLARITY ( CLKB_POLARITY ), + .CLKEB_POLARITY ( CLKEB_POLARITY ), + .OUTPUT_REG_B ( OUTPUT_REG_B ), + + + //Port Enable + .CLK_MODE (CLK_MODE ), + .CLKEA_ENABLE (CLKEA_ENABLE ), + .CLKEB_ENABLE (CLKEB_ENABLE ), + + + //Titanium extra paramters + .RSTA_POLARITY (RSTA_POLARITY ), + .RESET_RAM_A (RESET_RAM_A ), + .RESET_OUTREG_A (RESET_OUTREG_A ), + .ADDRENA_POLARITY (ADDRENA_POLARITY ), + .RSTB_POLARITY (RSTB_POLARITY ), + .RESET_RAM_B (RESET_RAM_B ), + .RESET_OUTREG_B (RESET_OUTREG_B ), + .ADDRENB_POLARITY (ADDRENB_POLARITY ), + + //Port Enable + .RESET_A_ENABLE (RESET_A_ENABLE ), + .ADDREN_A_ENABLE (ADDREN_A_ENABLE), + .RESET_B_ENABLE (RESET_B_ENABLE ), + .ADDREN_B_ENABLE (ADDREN_B_ENABLE), + + //DATA and ADDR + .DATA_WIDTH_A (DATA_WIDTH_A), + .DATA_WIDTH_B (DATA_WIDTH_B), + .ADDR_WIDTH_A (ADDR_WIDTH_A), + .ADDR_WIDTH_B (ADDR_WIDTH_B), + .FAMILY (FAMILY) + ) + dprom_inst + ( + .clk (clk ), + .clke (clke ), + .clk_a (clk_a ), + .clke_a (clke_a ), + .addr_a (addr_a ), + .rdata_a (rdata_a), + .clk_b (clk_b ), + .clke_b (clke_b ), + .addr_b (addr_b ), + .rdata_b (rdata_b), + .reset_a (reset_a), + .addren_a (addren_a), + .reset_b (reset_b), + .addren_b (addren_b) + + ); + end +endgenerate + +endmodule + + + + + + + + + + + + + + + + + + + + + + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(dpbram_primitive) #( + parameter FAMILY = "TITANIUM", //0:Trion, 1:Titanium + + //Trion and Titanium parameters + parameter WRITE_WIDTH_A = 8, // write width + parameter CLKA_POLARITY = 1'b1, //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEA_POLARITY = 1'b1, //clke A polarity, 0:active low, 1:active high + parameter WEA_POLARITY = 1'b1, //we A polarity, 0:active low, 1:active high + parameter WRITE_MODE_A = "READ_FIRST",//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter READ_WIDTH_A = 8, // read width A + parameter OUTPUT_REG_A = 1'b1, // Output register enable, 1:add pipe-line read register + + parameter WRITE_WIDTH_B = 8, // write width + parameter CLKB_POLARITY = 1'b1, //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEB_POLARITY = 1'b1, //clke A polarity, 0:active low, 1:active high + parameter WEB_POLARITY = 1'b1, //we A polarity, 0:active low, 1:active high + parameter WRITE_MODE_B = "READ_FIRST",//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict. + parameter READ_WIDTH_B = 8, // read width A + parameter OUTPUT_REG_B = 1'b0, // Output register enable, 1:add pipe-line read register + + //Titanium extra paramters + parameter RSTA_POLARITY = 1'b1, // rst A polarity + parameter RESET_RAM_A = "ASYNC", // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_A = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENA_POLARITY = 1'b1, // addrena polarity + + parameter RSTB_POLARITY = 1'b1, // rst A polarity + parameter RESET_RAM_B = "ASYNC", // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_B = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENB_POLARITY = 1'b1, // addrenb polarity + + //Titanium Option for byte enable in WEN width = 2 when it is Mode 512x16 or 512x20 + + parameter ini_index = 0 + +) +( +//Trion and Titanium ports + CLKA, // A-port clk + CLKEA, // A-port clk enable + WEA, // A-port write enable + ADDRA, // A-port address input + WDATAA, // A-port write data input + RDATAA, // A-port read address output + + CLKB, // B-port clk + CLKEB, // B-port clk enable + WEB, // B-port write enable + ADDRB, // B-port address input + WDATAB, // B-port write data input + RDATAB, // B-port read address output + + //Titanium extra ports + + RSTA, // A-port reset + ADDRENA, // A-port address enable + + RSTB, // B-port reset + ADDRENB // B-port address enable + + ); +function integer address_map; +input integer index;//Input data width parameter +input integer type_; //Mapped data width, Mapped Address Width for Ram 5K(Trion), Mapped Address Width for Ram 10K(Titanium), WEN width for Ram 5K(Trion), WEN width for Ram 10K(Titanium) +case (index) +0 : address_map= (type_==0)? 1 :(type_==1)? 12 :(type_==2)? 13 :1; +1 : address_map= (type_==0)? 1 :(type_==1)? 12 :(type_==2)? 13 :1; +2 : address_map= (type_==0)? 2 :(type_==1)? 11 :(type_==2)? 12 :1; +3 : address_map= (type_==0)? 4 :(type_==1)? 10 :(type_==2)? 11 :1; +4 : address_map= (type_==0)? 4 :(type_==1)? 10 :(type_==2)? 11 :1; +5 : address_map= (type_==0)? 5 :(type_==1)? 10 :(type_==2)? 11 :1; +6 : address_map= (type_==0)? 8 :(type_==1)? 9 :(type_==2)? 10 :1; +7 : address_map= (type_==0)? 8 :(type_==1)? 9 :(type_==2)? 10 :1; +8 : address_map= (type_==0)? 8 :(type_==1)? 9 :(type_==2)? 10 :1; +9 : address_map= (type_==0)? 10 :(type_==1)? 9 :(type_==2)? 10 :1; +10 : address_map= (type_==0)? 10 :(type_==1)? 9 :(type_==2)? 10 :1; + endcase +endfunction + +localparam WRITE_DATA_WIDTH_A = address_map(WRITE_WIDTH_A,0); +localparam WRITE_ADDRESS_WIDTH_A = address_map(WRITE_WIDTH_A,(FAMILY=="TRION")?1:2); + +localparam WRITE_DATA_WIDTH_B = address_map(WRITE_WIDTH_B,0); +localparam WRITE_ADDRESS_WIDTH_B = address_map(WRITE_WIDTH_B,(FAMILY=="TRION")?1:2); + +//Trion and Titanium ports +input CLKA; // A-port clk +input CLKEA; // A-port clk enable +input [0:0] WEA; // A-port write enable +input [WRITE_ADDRESS_WIDTH_A-1:0] ADDRA; // A-port address input +input [WRITE_DATA_WIDTH_A-1:0] WDATAA; // A-port write data input +output [WRITE_DATA_WIDTH_A-1:0] RDATAA; // A-port read address output + +input CLKB; // B-port clk +input CLKEB; // B-port clk enable +input [0:0] WEB; // B-port write enable +input [WRITE_ADDRESS_WIDTH_B-1:0] ADDRB; // B-port address input +input [WRITE_DATA_WIDTH_B-1:0] WDATAB; // B-port write data input +output [WRITE_DATA_WIDTH_B-1:0] RDATAB; // B-port read address output + + //Titanium extra ports + +input RSTA; // A-port reset +input ADDRENA; // A-port address enable + +input RSTB; // B-port reset +input ADDRENB; // B-port address enable + + +`include "bram_ini.vh" + + generate + if (FAMILY=="TRION") + begin + EFX_DPRAM_5K # ( + .WRITE_WIDTH_A (WRITE_WIDTH_A), + .CLKA_POLARITY (CLKA_POLARITY), // clka polarity + .CLKEA_POLARITY (CLKEA_POLARITY), // clkea polarity + .WEA_POLARITY (WEA_POLARITY), // wea polarity + .WRITE_MODE_A (WRITE_MODE_A), // A-port write mode + + .READ_WIDTH_A (READ_WIDTH_A), // A-port read width + .OUTPUT_REG_A (OUTPUT_REG_A), // A-port output register enable + + + .WRITE_WIDTH_B (WRITE_WIDTH_B), // B-port write width + .CLKB_POLARITY (CLKB_POLARITY), // clkb polarity + .CLKEB_POLARITY(CLKEB_POLARITY), // clkeb polarity + .WEB_POLARITY (WEB_POLARITY), // web polarity + .WRITE_MODE_B (WRITE_MODE_B), // B-port write mode + + .READ_WIDTH_B (READ_WIDTH_B), // B-port read width + .OUTPUT_REG_B (OUTPUT_REG_B), // B-port output register enable + + + .INIT_0 (bram_ini_table(ini_index,16'h0 )), + .INIT_1 (bram_ini_table(ini_index,16'h1 )), + .INIT_2 (bram_ini_table(ini_index,16'h2 )), + .INIT_3 (bram_ini_table(ini_index,16'h3 )), + .INIT_4 (bram_ini_table(ini_index,16'h4 )), + .INIT_5 (bram_ini_table(ini_index,16'h5 )), + .INIT_6 (bram_ini_table(ini_index,16'h6 )), + .INIT_7 (bram_ini_table(ini_index,16'h7 )), + .INIT_8 (bram_ini_table(ini_index,16'h8 )), + .INIT_9 (bram_ini_table(ini_index,16'h9 )), + .INIT_A (bram_ini_table(ini_index,16'hA )), + .INIT_B (bram_ini_table(ini_index,16'hB )), + .INIT_C (bram_ini_table(ini_index,16'hC )), + .INIT_D (bram_ini_table(ini_index,16'hD )), + .INIT_E (bram_ini_table(ini_index,16'hE )), + .INIT_F (bram_ini_table(ini_index,16'hF )), + .INIT_10 (bram_ini_table(ini_index,16'h10)), + .INIT_11 (bram_ini_table(ini_index,16'h11)), + .INIT_12 (bram_ini_table(ini_index,16'h12)), + .INIT_13 (bram_ini_table(ini_index,16'h13)) + ) + dpram5k ( + //Trion and Titanium ports + .CLKA (CLKA), // A-port clk + .CLKEA (CLKEA), // A-port clk enable + .WEA (WEA), // A-port write enable + .ADDRA (ADDRA), // A-port address input + .WDATAA (WDATAA), // A-port write data input + .RDATAA (RDATAA), // A-port read address output + + .CLKB (CLKB), // B-port clk + .CLKEB (CLKEB), // B-port clk enable + .WEB (WEB), // B-port write enable + .ADDRB (ADDRB), // B-port address input + .WDATAB (WDATAB), // B-port write data input + .RDATAB (RDATAB) // B-port read address output + + ); + end + else + begin + + EFX_DPRAM10 # ( + + .WRITE_WIDTH_A (WRITE_WIDTH_A), + .CLKA_POLARITY (CLKA_POLARITY), // clka polarity + .CLKEA_POLARITY (CLKEA_POLARITY), // clkea polarity + .WEA_POLARITY (WEA_POLARITY), // wea polarity + .WRITE_MODE_A (WRITE_MODE_A), // A-port write mode + + .READ_WIDTH_A (READ_WIDTH_A), // A-port read width + .OUTPUT_REG_A (OUTPUT_REG_A), // A-port output register enable + + + .WRITE_WIDTH_B (WRITE_WIDTH_B), // B-port write width + .CLKB_POLARITY (CLKB_POLARITY), // clkb polarity + .CLKEB_POLARITY(CLKEB_POLARITY), // clkeb polarity + .WEB_POLARITY (WEB_POLARITY), // web polarity + .WRITE_MODE_B (WRITE_MODE_B), // B-port write mode + + .READ_WIDTH_B (READ_WIDTH_B), // B-port read width + .OUTPUT_REG_B (OUTPUT_REG_B), // B-port output register enable + + + //Titanium extra paramters + .RSTA_POLARITY (RSTA_POLARITY), // rsta polarity + .RESET_RAM_A (RESET_RAM_A), // A-port reset mode on ram + .RESET_OUTREG_A (RESET_OUTREG_A), // A-port reset mode on output register + .ADDRENA_POLARITY (ADDRENA_POLARITY), // addrena polarity + + .RSTB_POLARITY (RSTB_POLARITY), // rstb polarity + .RESET_RAM_B (RESET_RAM_B), // B-port reset mode on ram + .RESET_OUTREG_B (RESET_OUTREG_B), // B-port reset mode on output register + .ADDRENB_POLARITY (ADDRENB_POLARITY), // addrenb polarity + + + .INIT_0 (bram_ini_table(ini_index, 16'h0 )), + .INIT_1 (bram_ini_table(ini_index, 16'h1 )), + .INIT_2 (bram_ini_table(ini_index, 16'h2 )), + .INIT_3 (bram_ini_table(ini_index, 16'h3 )), + .INIT_4 (bram_ini_table(ini_index, 16'h4 )), + .INIT_5 (bram_ini_table(ini_index, 16'h5 )), + .INIT_6 (bram_ini_table(ini_index, 16'h6 )), + .INIT_7 (bram_ini_table(ini_index, 16'h7 )), + .INIT_8 (bram_ini_table(ini_index, 16'h8 )), + .INIT_9 (bram_ini_table(ini_index, 16'h9 )), + .INIT_A (bram_ini_table(ini_index, 16'hA )), + .INIT_B (bram_ini_table(ini_index, 16'hB )), + .INIT_C (bram_ini_table(ini_index, 16'hC )), + .INIT_D (bram_ini_table(ini_index, 16'hD )), + .INIT_E (bram_ini_table(ini_index, 16'hE )), + .INIT_F (bram_ini_table(ini_index, 16'hF )), + .INIT_10 (bram_ini_table(ini_index, 16'h10)), + .INIT_11 (bram_ini_table(ini_index, 16'h11)), + .INIT_12 (bram_ini_table(ini_index, 16'h12)), + .INIT_13 (bram_ini_table(ini_index, 16'h13)), + .INIT_14 (bram_ini_table(ini_index, 16'h14)), + .INIT_15 (bram_ini_table(ini_index, 16'h15)), + .INIT_16 (bram_ini_table(ini_index, 16'h16)), + .INIT_17 (bram_ini_table(ini_index, 16'h17)), + .INIT_18 (bram_ini_table(ini_index, 16'h18)), + .INIT_19 (bram_ini_table(ini_index, 16'h19)), + .INIT_1A (bram_ini_table(ini_index, 16'h1A)), + .INIT_1B (bram_ini_table(ini_index, 16'h1B)), + .INIT_1C (bram_ini_table(ini_index, 16'h1C)), + .INIT_1D (bram_ini_table(ini_index, 16'h1D)), + .INIT_1E (bram_ini_table(ini_index, 16'h1E)), + .INIT_1F (bram_ini_table(ini_index, 16'h1F)), + .INIT_20 (bram_ini_table(ini_index, 16'h20)), + .INIT_21 (bram_ini_table(ini_index, 16'h21)), + .INIT_22 (bram_ini_table(ini_index, 16'h22)), + .INIT_23 (bram_ini_table(ini_index, 16'h23)), + .INIT_24 (bram_ini_table(ini_index, 16'h24)), + .INIT_25 (bram_ini_table(ini_index, 16'h25)), + .INIT_26 (bram_ini_table(ini_index, 16'h26)), + .INIT_27 (bram_ini_table(ini_index, 16'h27)) + + ) + dpram10k( + //Trion and Titanium ports + .CLKA (CLKA), // A-port clk + .CLKEA (CLKEA), // A-port clk enable + .WEA (WEA), // A-port write enable + .ADDRA (ADDRA), // A-port address input + .WDATAA (WDATAA), // A-port write data input + .RDATAA (RDATAA), // A-port read address output + + .CLKB (CLKB), // B-port clk + .CLKEB (CLKEB), // B-port clk enable + .WEB (WEB), // B-port write enable + .ADDRB (ADDRB), // B-port address input + .WDATAB (WDATAB), // B-port write data input + .RDATAB (RDATAB), // B-port read address output + + + //Titanium extra ports + + .RSTA (RSTA), // A-port reset + .ADDRENA (ADDRENA), // A-port address enable + + .RSTB (RSTB), // B-port reset + .ADDRENB (ADDRENB) // B-port address enable + + + ); + end + endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// Modified on 23 September 2022 +// ******************************* + +module `IP_MODULE_NAME(dpram_wrapper_mwm) #( + //Trion and Titanium parameters + parameter CLKA_POLARITY = 1'b1, //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEA_POLARITY = 1'b1, //clke A polarity, 0:active low, 1:active high + parameter WEA_POLARITY = 1'b1, //we A polarity, 0:active low, 1:active high + parameter WRITE_MODE_A = "READ_FIRST",//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "NO_CHANGE": Previously read data is held. + + parameter OUTPUT_REG_A = 1'b0, // Output register enable, 1:add pipe-line read register + parameter BYTEENA_POLARITY = 1'b1, // byteen polarity 0:active low, 1:active high + + parameter CLKB_POLARITY = 1'b1, //clk A polarity, 0:falling edge, 1:rising edge + parameter CLKEB_POLARITY = 1'b1, //clke A polarity, 0:active low, 1:active high + parameter WEB_POLARITY = 1'b1, //we B polarity, 0:active low, 1:active high + parameter WRITE_MODE_B = "READ_FIRST",//write mode A, "READ_FIRST" :Old memory content is read. (default) + // "WRITE_FIRST" :Write data is passed to the read port. + // "NO_CHANGE": Previously read data is held. + + parameter OUTPUT_REG_B = 1'b0, // Output register enable, 1:add pipe-line read register + parameter BYTEENB_POLARITY = 1'b1, // byteen polarity 0:active low, 1:active high + + //Titanium extra paramters + parameter RSTA_POLARITY = 1'b1, // rst A polarity + parameter RESET_RAM_A = "ASYNC", // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_A = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENA_POLARITY = 1'b1, // addrena polarity + + parameter RSTB_POLARITY = 1'b1, // rst A polarity + parameter RESET_RAM_B = "ASYNC", // reset A mode on ram, "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. + parameter RESET_OUTREG_B = "ASYNC", // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. + parameter ADDRENB_POLARITY = 1'b1, // addrenb polarity + + parameter DATA_WIDTH_A = 16, + parameter DATA_WIDTH_B = 16, + parameter ADDR_WIDTH_A = 4, + parameter ADDR_WIDTH_B = 4, + parameter BYTEEN_WIDTH_A = 2, + parameter BYTEEN_WIDTH_B = 2, + parameter FAMILY = "TITANIUM" + + + //Titanium Option for byte enable in WEN width = 2 when it is Mode 512x16 or 512x20 +) +( + //Trion and Titanium ports + clk_a, // A-port clk + clke_a, // A-port clk enable + byteen_a, // A-port Byteen input + we_a, // A-port write enable + addr_a, // A-port address input + wdata_a, // A-port write data input + rdata_a, // A-port read address output + + clk_b, // B-port clk + clke_b, // B-port clk enable + byteen_b, // B-port Byteen input + we_b, // B-port write enable + addr_b, // B-port address input + wdata_b, // B-port write data input + rdata_b, // B-port read address output + + //Titanium extra ports + reset_a, // A-port reset + addren_a, // A-port address enable + + reset_b, // B-port reset + addren_b // B-port address enable + + ); + +`include "bram_decompose.vh" +//`include "bram_feature.vh" + +input clk_a; +input clke_a; +input we_a; +input [BYTEEN_WIDTH_A-1:0] byteen_a; +input [ADDR_WIDTH_A-1:0 ] addr_a; +input [DATA_WIDTH_A-1:0 ] wdata_a; +output [DATA_WIDTH_A-1:0 ]rdata_a; + +input clk_b; +input clke_b; +input we_b; +input [BYTEEN_WIDTH_B-1:0] byteen_b; +input [ADDR_WIDTH_B-1:0 ] addr_b; +input [DATA_WIDTH_B-1:0 ] wdata_b; +output [DATA_WIDTH_B-1:0 ]rdata_b; + +input reset_a; +input addren_a; + +input reset_b; +input addren_b; + + +localparam MAP_ADDR_WIDTH_A = (address_mapping_table_A_size!=0)?address_mapping_table_A_size:ADDR_WIDTH_A; +localparam MAP_ADDR_WIDTH_B = (address_mapping_table_B_size!=0)?address_mapping_table_B_size:ADDR_WIDTH_B; + + + +wire [MAP_ADDR_WIDTH_A-1:0 ] w_addr_map_a; +wire [DATA_WIDTH_A-1:0 ] w_wdata_map_a; +wire [DATA_WIDTH_A-1:0 ] w_rdata_map_a; + +wire [MAP_ADDR_WIDTH_B-1:0 ] w_addr_map_b; +wire [DATA_WIDTH_B-1:0 ] w_wdata_map_b; +wire [DATA_WIDTH_B-1:0 ] w_rdata_map_b; + +wire clk_a_i; +wire clk_b_i; +assign clk_a_i = clk_a ~^ CLKA_POLARITY; +assign clk_b_i = clk_b ~^ CLKB_POLARITY; + +function integer get_current_row_index; +input integer row;//Mode type +integer x; + begin + get_current_row_index = 0; + for (x=0; x1) + begin + assign w_we_a[1] = ( (we_a == WEA_POLARITY) & wen_decode_a[WRSEL_INDEX_A] & (byteen_a[BYTEEN_INDEX_A] == BYTEENA_POLARITY) ) ? WEA_POLARITY: !WEA_POLARITY; + end + + assign w_we_b[0] = ( (we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY) ) ? WEB_POLARITY: !WEB_POLARITY; + if ( WEN_WIDTH_ROW_B >1) + begin + assign w_we_b[1] =((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY) )? WEB_POLARITY: !WEB_POLARITY ; + end + + `IP_MODULE_NAME(dpbram_primitive) #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH_A(DATA_WIDTH_ROW_A), + .READ_WIDTH_A(DATA_WIDTH_ROW_A), + + .CLKA_POLARITY(CLKA_POLARITY), + .CLKEA_POLARITY(CLKEA_POLARITY), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + .OUTPUT_REG_A(OUTPUT_REG_A), + + .WRITE_WIDTH_B(DATA_WIDTH_ROW_B), + .READ_WIDTH_B(DATA_WIDTH_ROW_B), + + .CLKB_POLARITY(CLKB_POLARITY), + .CLKEB_POLARITY(CLKEB_POLARITY), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + .OUTPUT_REG_B(OUTPUT_REG_B), + + .ini_index(DATA_MAP_INDEX), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY) + + + + ) bram ( + //Trion and Titanium ports + .CLKA (clk_a), // A-port clk + .CLKEA (clke_a), // A-port clk enable + .WEA (w_we_a), // A-port write enable + .ADDRA (w_addr_a), // A-port address input + .WDATAA(w_wdata_a), // A-port write data input + .RDATAA(w_rdata_a), // A-port read address output + + .CLKB (clk_b), // B-port clk + .CLKEB (clke_b), // B-port clk enable + .WEB (w_we_b), // B-port write enable + .ADDRB (w_addr_b), // B-port address input + .WDATAB(w_wdata_b), // B-port write data input + .RDATAB(w_rdata_b), // B-port read address output + + //Titanium extra ports + + .RSTA (reset_a), // A-port reset + .ADDRENA(addren_a), // A-port address enable + + .RSTB(reset_b), // B-port reset + .ADDRENB(addren_b) // B-port address enable + ); + end + end + + end + else if (bram_table_loop_mode == 1 ) + begin:scan_row + for (gen_y=0; gen_y ADDR_WIDTH_A )? ADDR_WIDTH_A:ADDR_WIDTH_ROW_A; + + + localparam ADDR_WIDTH_ROW_B = bram_feature_table(bram_mode_b,0); + localparam DATA_WIDTH_ROW_B = bram_feature_table(bram_mode_b,1); + localparam WEN_WIDTH_ROW_B = bram_feature_table(bram_mode_b,2); + localparam ADDR_WIDTH_ROW_MAP_B = (ADDR_WIDTH_ROW_B > ADDR_WIDTH_B )? ADDR_WIDTH_B:ADDR_WIDTH_ROW_B; + + + + localparam START_ROW_INDEX = get_current_row_index(gen_y); + + + for (gen_x=0; gen_x1) + begin + assign w_we_a[1] = ((we_a == WEA_POLARITY) & wen_decode_a[WRSEL_INDEX_A] & (byteen_a[BYTEEN_INDEX_A] == BYTEENA_POLARITY) ) ? WEA_POLARITY: !WEA_POLARITY; + end + + assign w_we_b[0] = ((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY)) ? WEB_POLARITY: !WEB_POLARITY; + if ( WEN_WIDTH_ROW_B >1) + begin + assign w_we_b[1] = ((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY)) ? WEB_POLARITY : !WEB_POLARITY; + end + + `IP_MODULE_NAME(dpbram_primitive) #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH_A(DATA_WIDTH_ROW_A), + .READ_WIDTH_A(DATA_WIDTH_ROW_A), + + .CLKA_POLARITY(CLKA_POLARITY), + .CLKEA_POLARITY(CLKEA_POLARITY), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + .OUTPUT_REG_A(OUTPUT_REG_A), + + .WRITE_WIDTH_B(DATA_WIDTH_ROW_B), + .READ_WIDTH_B(DATA_WIDTH_ROW_B), + + .CLKB_POLARITY(CLKB_POLARITY), + .CLKEB_POLARITY(CLKEB_POLARITY), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + .OUTPUT_REG_B(OUTPUT_REG_B), + + .ini_index(DATA_MAP_INDEX), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY) + + + ) bram ( + //Trion and Titanium ports + .CLKA (clk_a), // A-port clk + .CLKEA (clke_a), // A-port clk enable + .WEA (w_we_a), // A-port write enable + .ADDRA (w_addr_a), // A-port address input + .WDATAA(w_wdata_a), // A-port write data input + .RDATAA(w_rdata_a), // A-port read address output + + .CLKB (clk_b), // B-port clk + .CLKEB (clke_b), // B-port clk enable + .WEB (w_we_b), // B-port write enable + .ADDRB (w_addr_b), // B-port address input + .WDATAB(w_wdata_b), // B-port write data input + .RDATAB(w_rdata_b), // B-port read address output + + //Titanium extra ports + + .RSTA (reset_a), // A-port reset + .ADDRENA(addren_a), // A-port address enable + + .RSTB(reset_b), // B-port reset + .ADDRENB(addren_b) // B-port address enable + ); + + + + end + end + + end + endgenerate + + +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_true_dual_port_ram) ( + //Trion and Titanium ports + clk, // clock input for one clock mode + clke, // clk enable + + clk_a, // A-port clk + clke_a, // A-port clk enable + byteen_a, // A-port Byteen input + we_a, // A-port write enable + addr_a, // A-port address input + wdata_a, // A-port write data input + rdata_a, // A-port read address output + + clk_b, // B-port clk + clke_b, // B-port clk enable + byteen_b, // B-port Byteen input + we_b, // B-port write enable + addr_b, // B-port address input + wdata_b, // B-port write data input + rdata_b, // B-port read address output + + //Titanium extra ports + reset_a, // A-port reset + addren_a, // A-port address enable + + reset_b, // B-port reset + addren_b // B-port address enable + + ); + +//`include "bram_decompose.vh" + +//Trion and Titanium parameters +parameter CLK_POLARITY = 1'b1; //clk polarity for one clk mode; 0:falling edge; 1:rising edge +parameter CLKE_POLARITY = 1'b1; //clke polarity for one clk mode; 0:active low; 1:active high + +parameter CLKA_POLARITY = 1'b1; //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEA_POLARITY = 1'b1; //clke A polarity; 0:active low; 1:active high +parameter WEA_POLARITY = 1'b1; //we A polarity; 0:active low; 1:active high + +parameter OUTPUT_REG_A = 1'b0; // Output register enable; 1:add pipe-line read register +parameter BYTEENA_POLARITY = 1'b1; // byteen polarity 0:active low; 1:active high + +parameter CLKB_POLARITY = 1'b1; //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEB_POLARITY = 1'b1; //clke A polarity; 0:active low; 1:active high +parameter WEB_POLARITY = 1'b1; //we B polarity; 0:active low; 1:active high + +parameter OUTPUT_REG_B = 1'b0; // Output register enable; 1:add pipe-line read register +parameter BYTEENB_POLARITY = 1'b1; // byteen polarity 0:active low; 1:active high + + +//Port Enable +parameter CLK_MODE = 2; //1: ONE CLK Mode; CLK pin will provide the clock source to the memory + //2: TWO CLK Mode; clk_a and clk_b +parameter CLKEA_ENABLE = 1'b1; //1: Enalbe the port for clke_a pin ; 0: dislable +parameter WEA_ENABLE = 1'b1; //1: Enable the port for we_a pin ; 0: disable +parameter BYTEENA_ENABLE = 1'b1; //1: Enable the port for Byteen_a pins ; 0: disable + +parameter CLKEB_ENABLE = 1'b1; //1: Enalbe the port for clke_b pin ; 0: dislable +parameter WEB_ENABLE = 1'b1; //1: Enable the port for we_b pin ; 0: disable +parameter BYTEENB_ENABLE = 1'b1; //1: Enable the port for Byteen_b pins ; 0: disable + + +//Titanium extra paramters +parameter RSTA_POLARITY = 1'b1; // rst A polarity +parameter RESET_RAM_A = "ASYNC"; // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_A = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENA_POLARITY = 1'b1; // addrena polarity + +parameter RSTB_POLARITY = 1'b1; // rst A polarity +parameter RESET_RAM_B = "ASYNC"; // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_B = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENB_POLARITY = 1'b1; // addrenb polarity + +//Port Enable +parameter RESET_A_ENABLE = 1'b1; //1: Enable the port for reset_a pin ; 0: disable +parameter ADDREN_A_ENABLE = 1'b1; //1: Enable the port for addren_a pin ; 0: disable + +parameter RESET_B_ENABLE = 1'b1; //1: Enable the port for reset_b pin ; 0: disable +parameter ADDREN_B_ENABLE = 1'b1; //1: Enable the port for addren_b pin ; 0: disable + +parameter WRITE_MODE_A = "READ_FIRST"; +parameter WRITE_MODE_B = "READ_FIRST"; +parameter DATA_WIDTH_A = 16; +parameter DATA_WIDTH_B = 16; +parameter ADDR_WIDTH_A = 4; +parameter ADDR_WIDTH_B = 4; +parameter BYTEEN_WIDTH_A = 2; +parameter BYTEEN_WIDTH_B = 2; +parameter FAMILY = "TITANIUM"; + +//Trion and Titanium ports +input clk; +input clke; + +input clk_a; +input clke_a; +input we_a; +input [BYTEEN_WIDTH_A-1:0] byteen_a; +input [ADDR_WIDTH_A-1:0 ] addr_a; +input [DATA_WIDTH_A-1:0 ] wdata_a; +output [DATA_WIDTH_A-1:0 ]rdata_a; + +input clk_b; +input clke_b; +input we_b; +input [BYTEEN_WIDTH_B-1:0] byteen_b; +input [ADDR_WIDTH_B-1:0 ] addr_b; +input [DATA_WIDTH_B-1:0 ] wdata_b; +output [DATA_WIDTH_B-1:0 ]rdata_b; + +//Titanium extra ports +input reset_a; +input addren_a; + +input reset_b; +input addren_b; + +////////////////// wires ////////////////// +wire w_clk_a; +wire w_clke_a; +wire [BYTEEN_WIDTH_A-1:0] w_byteen_a; +wire w_we_a; + +wire w_clk_b; +wire w_clke_b; +wire [BYTEEN_WIDTH_B-1:0] w_byteen_b; +wire w_we_b; + +wire w_reset_a; +wire w_addren_a; + +wire w_reset_b; +wire w_addren_b; + + +assign w_clk_a = (CLK_MODE==2) ? clk_a : clk; +assign w_clke_a = (CLKEA_ENABLE==1) ? ((CLK_MODE==2) ? clke_a : clke) : CLKEA_POLARITY; +assign w_byteen_a = (BYTEENA_ENABLE==1)? byteen_a : {BYTEEN_WIDTH_A{BYTEENA_POLARITY}}; +assign w_we_a = (WEA_ENABLE==1) ? we_a : WEA_POLARITY; + +assign w_clk_b = (CLK_MODE==2) ? clk_b : clk; +assign w_clke_b = (CLKEB_ENABLE==1) ? ((CLK_MODE==2) ? clke_b : clke) : CLKEB_POLARITY; +assign w_byteen_b = (BYTEENB_ENABLE==1)? byteen_b : {BYTEEN_WIDTH_B{BYTEENB_POLARITY}}; +assign w_we_b = (WEB_ENABLE==1) ? we_b : WEB_POLARITY; + + +//Titanium extra ports +assign w_reset_a = (RESET_A_ENABLE==1) ? reset_a : (RSTA_POLARITY==1'b1) ? 1'b0: 1'b1; +assign w_addren_a = (ADDREN_A_ENABLE==1) ? addren_a : ADDRENA_POLARITY; + +assign w_reset_b = (RESET_B_ENABLE==1) ? reset_b : (RSTB_POLARITY==1'b1) ? 1'b0: 1'b1; +assign w_addren_b = (ADDREN_B_ENABLE==1) ? addren_b : ADDRENB_POLARITY; + + +localparam CLKA_POLARITY_LC = (CLK_MODE==2) ? CLKA_POLARITY : CLK_POLARITY; +localparam CLKB_POLARITY_LC = (CLK_MODE==2) ? CLKB_POLARITY : CLK_POLARITY; + +localparam CLKEA_POLARITY_LC = (CLK_MODE==2) ? CLKEA_POLARITY : CLKE_POLARITY; +localparam CLKEB_POLARITY_LC = (CLK_MODE==2) ? CLKEB_POLARITY : CLKE_POLARITY; + + `IP_MODULE_NAME(dpram_wrapper_mwm) #( + //Trion and Titanium parameters + .CLKA_POLARITY(CLKA_POLARITY_LC), + .CLKEA_POLARITY(CLKEA_POLARITY_LC), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + + .OUTPUT_REG_A(OUTPUT_REG_A), + .BYTEENA_POLARITY(BYTEENA_POLARITY), + + .CLKB_POLARITY(CLKB_POLARITY_LC), + .CLKEB_POLARITY(CLKEB_POLARITY_LC), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + + .OUTPUT_REG_B(OUTPUT_REG_B), + .BYTEENB_POLARITY(BYTEENB_POLARITY), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY), + + .DATA_WIDTH_A(DATA_WIDTH_A), + .DATA_WIDTH_B(DATA_WIDTH_B), + .ADDR_WIDTH_A(ADDR_WIDTH_A), + .ADDR_WIDTH_B(ADDR_WIDTH_B), + .BYTEEN_WIDTH_A(BYTEEN_WIDTH_A), + .BYTEEN_WIDTH_B(BYTEEN_WIDTH_B), + + .FAMILY(FAMILY) + + + ) brams ( + //Trion and Titanium ports + .clk_a(w_clk_a), + .clke_a(w_clke_a), + .byteen_a(w_byteen_a), + .we_a(w_we_a), + .addr_a(addr_a), + .wdata_a(wdata_a), + .rdata_a(rdata_a), + + .clk_b(w_clk_b), + .clke_b(w_clke_b), + .byteen_b(w_byteen_b), + .we_b(w_we_b), + .addr_b(addr_b), + .wdata_b(wdata_b), + .rdata_b(rdata_b), + + //Titanium extra ports + .reset_a(w_reset_a), + .addren_a(w_addren_a), + .reset_b(w_reset_b), + .addren_b(w_addren_b) + + ); + + + +endmodule +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/my_bram_ip_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/my_bram_ip_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..f7e5ae0550c31f2dda23480dde3443f9bd41c78c --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/my_bram_ip_define.vh @@ -0,0 +1,114 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam ADDR_WIDTH_A = 11; +localparam ADDR_WIDTH_B = 11; +localparam RESET_A_ENABLE = 0; +localparam RESET_B_ENABLE = 0; +localparam RSTA_POLARITY = 1; +localparam RSTB_POLARITY = 1; +localparam FAMILY = "TITANIUM"; +localparam MEMORY_MODE = "SPEED"; +localparam WRITE_MODE_A = "READ_FIRST"; +localparam WRITE_MODE_B = "READ_FIRST"; +localparam OUTPUT_REG_A = 0; +localparam OUTPUT_REG_B = 0; +localparam MEMORY_TYPE = "TDP_RAM"; +localparam GROUP_DATA_WIDTH_B = 8; +localparam BYTEENA_ENABLE = 0; +localparam BYTEENB_ENABLE = 0; +localparam BYTEENA_POLARITY = 1; +localparam BYTEENB_POLARITY = 1; +localparam BYTEEN_WIDTH_A = 1; +localparam BYTEEN_WIDTH_B = 1; +localparam BYTEEN_ENABLE = 0; +localparam BYTEEN_POLARITY = 1; +localparam GROUP_DATA_WIDTH = 8; +localparam BYTEEN_WIDTH = 1; +localparam WIDTH_RATIO = 4; +localparam GROUP_DATA_WIDTH_A = 8; +localparam DATA_WIDTH_A = 8; +localparam DATA_WIDTH_B = 8; +localparam ADDREN_ENABLE = 1; +localparam ADDREN_POLARITY = 1; +localparam CLK_MODE = 2; +localparam CLKA_POLARITY = 1; +localparam CLKB_POLARITY = 1; +localparam CLKE_POLARITY = 1; +localparam CLKEA_POLARITY = 1; +localparam CLKEA_ENABLE = 0; +localparam RESET_OUTREG_A = "ASYNC"; +localparam RESET_OUTREG_B = "ASYNC"; +localparam RESET_RAM_B = "ASYNC"; +localparam WEA_ENABLE = 1; +localparam WEA_POLARITY = 1; +localparam WEB_ENABLE = 1; +localparam WEB_POLARITY = 1; +localparam RADDREN_ENABLE = 1; +localparam RADDREN_POLARITY = 1; +localparam WADDREN_ENABLE = 1; +localparam WADDREN_POLARITY = 1; +localparam RCLK_POLARITY = 1; +localparam ADDREN_A_ENABLE = 0; +localparam ADDREN_B_ENABLE = 0; +localparam ADDRENA_POLARITY = 1; +localparam ADDRENB_POLARITY = 1; +localparam WE_ENABLE = 1; +localparam WE_POLARITY = 1; +localparam WCLKE_ENABLE = 1; +localparam WCLKE_POLARITY = 1; +localparam WCLK_POLARITY = 1; +localparam RESET_RAM_A = "ASYNC"; +localparam RESET_RAM = "ASYNC"; +localparam CLK_POLARITY = 1; +localparam OUTPUT_REG = 0; +localparam RE_POLARITY = 1; +localparam RE_ENABLE = 1; +localparam WRITE_MODE = "READ_FIRST"; +localparam RESET_OUTREG = "ASYNC"; +localparam RESET_ENABLE = 1; +localparam RST_POLARITY = 1; +localparam CLKEB_POLARITY = 1; +localparam CLKEB_ENABLE = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/reset.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/reset.v new file mode 100644 index 0000000000000000000000000000000000000000..db7ee8d9308129b57e029d1364626aaedfb7b316 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/reset.v @@ -0,0 +1,213 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// Description: +// System Reset Control +// +// Language: Verilog 2001 +// +// ------------------------------------------------------------------------------ +///////////////////////////////////////////////////////////////////////////////// + +module reset_ctrl +#( + parameter NUM_RST = 1, + parameter CYCLE = 1, + parameter IN_RST_ACTIVE = 1'b1, + parameter OUT_RST_ACTIVE = 1'b1 +) +( + input [NUM_RST-1:0] i_arst, + input [NUM_RST-1:0] i_clk, + output [NUM_RST-1:0] o_srst +); + +genvar i; +generate + for (i=0; i1) ? BYTEEN_WIDTH: 2; + +localparam TEST_PATTERN_WD_WIDTH = ((WDATA_WIDTH/BYTEEN_WIDTH)1) ? (WDATA_WIDTH/BYTEEN_WIDTH): WADDR_WIDTH : WADDR_WIDTH; +localparam TEST_PATTERN_RD_WIDTH = ((RDATA_WIDTH/BYTEEN_WIDTH)1) ? (RDATA_WIDTH/BYTEEN_WIDTH): RADDR_WIDTH : RADDR_WIDTH; + +input clk; + +input reset; +input start_in; +input rd_start_in; +output reg we; +output reg [WADDR_WIDTH-1:0] waddr; +output reg [WDATA_WIDTH-1:0] wdata; +output [BYTEEN_WIDTH_-1:0]byteen; + +output reg re; +output reg [RADDR_WIDTH-1:0] raddr; +input wire [RDATA_WIDTH-1:0] rdata; + +output [3:0] state; +output reg compare; + +reg [WADDR_WIDTH-1:0] r_wcount; +reg [RADDR_WIDTH-1:0] r_rcount; + +reg [BYTEEN_WIDTH_-1:0] r_shiftbyte; + + +reg [RADDR_WIDTH-1:0] r_rcount_1P; +reg [RADDR_WIDTH-1:0] r_rcount_2P; +reg [RADDR_WIDTH-1:0] r_rcount_3P; + + + +reg r_start_in_1P; +reg r_start_in_2P; + +reg r_rd_start_in_1P; +reg r_rd_start_in_2P; + +reg r_re_1p; +reg r_re_2p; + + +reg [3:0] test_state; + +reg [BYTEEN_WIDTH_-1:0] r_byteen; + +reg [RDATA_WIDTH-1:0] r_rdata_1P; + +assign state = test_state; + +localparam STATE_IDLE = 4'd0; +localparam STATE_START = 4'd1; +localparam STATE_WE_START = 4'd2; +localparam STATE_WE = 4'd3; +localparam STATE_WE_END = 4'd4; +localparam STATE_RE_START = 4'd5; +localparam STATE_RE = 4'd6; +localparam STATE_RE_EXTRA = 4'd7; + +localparam STATE_RE_END = 4'd8; + + + +localparam FIRST_ACCESS = (TEST_PATTERN=="READ")?STATE_RE_START:(TEST_PATTERN=="WriteRead")?STATE_WE_START:STATE_WE_START; + +assign byteen = (TEST_BYTEEN==0)? {BYTEEN_WIDTH_{1'b1}} : (BYTEEN_WIDTH >1)?r_byteen:2'b11; + +localparam COMPARE_WIDTH = (RADDR_WIDTH>=RDATA_WIDTH)?RDATA_WIDTH: RADDR_WIDTH; + +localparam DATA_MULTI_W = (WDATA_WIDTH<=TEST_PATTERN_WD_WIDTH) ?1: (WDATA_WIDTH/TEST_PATTERN_WD_WIDTH)+1; +localparam DATA_MULTI_R = (RDATA_WIDTH<=TEST_PATTERN_RD_WIDTH) ?1: (RDATA_WIDTH/TEST_PATTERN_RD_WIDTH)+1; + +always@(posedge clk or posedge reset) +begin + if(reset) + begin + + test_state <= STATE_IDLE; + + r_start_in_1P <= 1'b0; + r_start_in_2P <= 1'b0; + + r_rd_start_in_1P <= 1'b0; + r_rd_start_in_2P <= 1'b0; + + + r_wcount <= {WADDR_WIDTH{1'b0}}; + r_rcount <= {RADDR_WIDTH{1'b0}}; + r_shiftbyte <= {BYTEEN_WIDTH_{1'b0}}; + + r_rdata_1P <= {RDATA_WIDTH{1'b0}}; + + + end + else + begin + + r_start_in_1P <= start_in; + r_start_in_2P <= r_start_in_1P; + + r_rd_start_in_1P <= rd_start_in; + r_rd_start_in_2P <= r_rd_start_in_1P; + + r_rdata_1P <= rdata; + + case (test_state) + STATE_IDLE : + begin + if (r_start_in_1P & ~r_start_in_2P) + begin + test_state <= STATE_START; + end + else if (r_rd_start_in_1P & ~r_rd_start_in_2P) + begin + test_state <= STATE_RE_START; + end + end + STATE_START : + begin + test_state <= FIRST_ACCESS; //STATE_RE_START;//STATE_WE_START; + end + STATE_WE_START: + begin + r_wcount <= {WADDR_WIDTH{1'b0}}; + r_shiftbyte <= 1'b1; + test_state <= STATE_WE; + end + STATE_WE: + begin + if (r_wcount == (TEST_WRITE_COUNT-1)) + begin + test_state <= STATE_WE_END; + end + else + begin + r_wcount <= r_wcount+1'b1; + test_state <= STATE_WE; + end + + r_shiftbyte <= {r_shiftbyte[BYTEEN_WIDTH_-2:0], r_shiftbyte[BYTEEN_WIDTH_-1]}; + + end + STATE_WE_END : + begin + test_state <= STATE_RE_START; + end + STATE_RE_START : + begin + r_rcount <= {WADDR_WIDTH{1'b0}}; + test_state <= STATE_RE; + end + STATE_RE: + begin + if (r_rcount == (TEST_READ_COUNT-1)) + begin + if (OUTPUT_REG == 1'b0) + begin + test_state <= STATE_RE_END; + end + else + begin + test_state <= STATE_RE_EXTRA; + end + end + else + begin + r_rcount <= r_rcount+1'b1; + test_state <= STATE_RE; + end + end + STATE_RE_EXTRA: + begin + test_state <= STATE_RE_END; + end + STATE_RE_END : + begin + test_state <= STATE_IDLE; + end + + endcase + + end + +end + + +always@(posedge clk or posedge reset) +begin + if(reset) + begin + + we <= ~WE_POLARITY; + waddr <= {WADDR_WIDTH{1'b0}}; + wdata <= {WDATA_WIDTH{1'b0}}; + r_byteen<= {BYTEEN_WIDTH_{1'b0}}; + + re <= ~RE_POLARITY; + raddr <= {RADDR_WIDTH{1'b0}}; + compare <= 1'b0; + + r_rcount_1P <= {RADDR_WIDTH{1'b0}}; + r_rcount_2P <= {RADDR_WIDTH{1'b0}}; + r_rcount_3P <= {RADDR_WIDTH{1'b0}}; + + r_re_1p <= 1'b0; + r_re_2p <= 1'b0; + + end + else + begin + + r_rcount_1P <= r_rcount; + r_rcount_2P <= r_rcount_1P; + r_rcount_3P <= r_rcount_2P; + + r_re_1p <= re; + r_re_2p <= r_re_1p; + + if(test_state == STATE_WE) + begin + we <= WE_POLARITY; + waddr <= r_wcount; + // wdata <= {DATA_MULTI_W{r_wcount[TEST_PATTERN_WD_WIDTH-1:0]}}; + wdata <= (GROUP_DATA==0)? r_wcount : ({(WDATA_WIDTH/WADDR_WIDTH){r_wcount[WADDR_WIDTH-1:0]}}); + r_byteen <= r_shiftbyte; + re <= ~RE_POLARITY; + raddr <= r_rcount; + + compare <= 1'b0; + + + end + else if((test_state == STATE_RE)||(test_state == STATE_RE_EXTRA)) + begin + we <= ~WE_POLARITY; + waddr <= r_rcount; + wdata <= {WDATA_WIDTH{1'b0}}; + r_byteen<= {BYTEEN_WIDTH_{1'b0}}; + + re <= RE_POLARITY; + raddr <= r_rcount; + end + else + begin + we <= ~WE_POLARITY; + waddr <= {WADDR_WIDTH{1'b0}}; + wdata <= {WDATA_WIDTH{1'b0}}; + r_byteen<= {BYTEEN_WIDTH_{1'b0}}; + + + re <= ~RE_POLARITY; + raddr <= {RADDR_WIDTH{1'b0}}; + + compare <= 1'b0; + end + + + + if (OUTPUT_REG == 1'b0) + begin + if (r_re_1p== RE_POLARITY) + begin + + //if( rdata == {DATA_MULTI_R{r_rcount_2P[TEST_PATTERN_RD_WIDTH-1:0]}} ) + if(r_rcount_2P[COMPARE_WIDTH-1:0] == rdata[COMPARE_WIDTH-1:0]) + begin + compare <= 1'b0; + end + else + begin + compare <= 1'b1; + + end + end + end + else + begin + if (r_re_2p== RE_POLARITY) + begin + + //if( rdata == {DATA_MULTI_R{r_rcount_2P[TEST_PATTERN_RD_WIDTH-1:0]}} ) + if(r_rcount_3P[COMPARE_WIDTH-1:0] == rdata[COMPARE_WIDTH-1:0]) + begin + compare <= 1'b0; + end + else + begin + compare <= 1'b1; + + end + end + + end + end + +end + + + +endmodule \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/write_pattern.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/write_pattern.v new file mode 100644 index 0000000000000000000000000000000000000000..8f42734cd28d405ad8150840207a8d785d542ab9 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/Ti60F225_devkit/write_pattern.v @@ -0,0 +1,132 @@ +module write_pattern #( +//Trion and Titanium parameters + parameter ADDR_WIDTH = 14, + parameter DATA_WIDTH = 32, + parameter PATTERN_COUNT = 100, + parameter WE_POLARITY = 1'b1 +) +( + //Trion and Titanium ports + clk, // clock input for one clock mode + + reset, + + start_in, + + we, // write enale output + addr, // Write address output + data, // Write data output + + start_out, + end_out + + ); + +function integer log2; + input integer val; + integer i; + begin + log2 = 0; + for (i=0; 2**i1) + begin + assign w_we_a[1] = ( (we_a == WEA_POLARITY) & wen_decode_a[WRSEL_INDEX_A] & (byteen_a[BYTEEN_INDEX_A] == BYTEENA_POLARITY) ) ? WEA_POLARITY: !WEA_POLARITY; + end + + assign w_we_b[0] = ( (we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY) ) ? WEB_POLARITY: !WEB_POLARITY; + if ( WEN_WIDTH_ROW_B >1) + begin + assign w_we_b[1] =((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY) )? WEB_POLARITY: !WEB_POLARITY ; + end + + `IP_MODULE_NAME(dpbram_primitive) #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH_A(DATA_WIDTH_ROW_A), + .READ_WIDTH_A(DATA_WIDTH_ROW_A), + + .CLKA_POLARITY(CLKA_POLARITY), + .CLKEA_POLARITY(CLKEA_POLARITY), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + .OUTPUT_REG_A(OUTPUT_REG_A), + + .WRITE_WIDTH_B(DATA_WIDTH_ROW_B), + .READ_WIDTH_B(DATA_WIDTH_ROW_B), + + .CLKB_POLARITY(CLKB_POLARITY), + .CLKEB_POLARITY(CLKEB_POLARITY), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + .OUTPUT_REG_B(OUTPUT_REG_B), + + .ini_index(DATA_MAP_INDEX), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY) + + + + ) bram ( + //Trion and Titanium ports + .CLKA (clk_a), // A-port clk + .CLKEA (clke_a), // A-port clk enable + .WEA (w_we_a), // A-port write enable + .ADDRA (w_addr_a), // A-port address input + .WDATAA(w_wdata_a), // A-port write data input + .RDATAA(w_rdata_a), // A-port read address output + + .CLKB (clk_b), // B-port clk + .CLKEB (clke_b), // B-port clk enable + .WEB (w_we_b), // B-port write enable + .ADDRB (w_addr_b), // B-port address input + .WDATAB(w_wdata_b), // B-port write data input + .RDATAB(w_rdata_b), // B-port read address output + + //Titanium extra ports + + .RSTA (reset_a), // A-port reset + .ADDRENA(addren_a), // A-port address enable + + .RSTB(reset_b), // B-port reset + .ADDRENB(addren_b) // B-port address enable + ); + end + end + + end + else if (bram_table_loop_mode == 1 ) + begin:scan_row + for (gen_y=0; gen_y ADDR_WIDTH_A )? ADDR_WIDTH_A:ADDR_WIDTH_ROW_A; + + + localparam ADDR_WIDTH_ROW_B = bram_feature_table(bram_mode_b,0); + localparam DATA_WIDTH_ROW_B = bram_feature_table(bram_mode_b,1); + localparam WEN_WIDTH_ROW_B = bram_feature_table(bram_mode_b,2); + localparam ADDR_WIDTH_ROW_MAP_B = (ADDR_WIDTH_ROW_B > ADDR_WIDTH_B )? ADDR_WIDTH_B:ADDR_WIDTH_ROW_B; + + + + localparam START_ROW_INDEX = get_current_row_index(gen_y); + + + for (gen_x=0; gen_x1) + begin + assign w_we_a[1] = ((we_a == WEA_POLARITY) & wen_decode_a[WRSEL_INDEX_A] & (byteen_a[BYTEEN_INDEX_A] == BYTEENA_POLARITY) ) ? WEA_POLARITY: !WEA_POLARITY; + end + + assign w_we_b[0] = ((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY)) ? WEB_POLARITY: !WEB_POLARITY; + if ( WEN_WIDTH_ROW_B >1) + begin + assign w_we_b[1] = ((we_b == WEB_POLARITY) & wen_decode_b[WRSEL_INDEX_B] & (byteen_b[BYTEEN_INDEX_B] == BYTEENB_POLARITY)) ? WEB_POLARITY : !WEB_POLARITY; + end + + `IP_MODULE_NAME(dpbram_primitive) #( + .FAMILY(FAMILY), + + //Trion and Titanium parameters + .WRITE_WIDTH_A(DATA_WIDTH_ROW_A), + .READ_WIDTH_A(DATA_WIDTH_ROW_A), + + .CLKA_POLARITY(CLKA_POLARITY), + .CLKEA_POLARITY(CLKEA_POLARITY), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + .OUTPUT_REG_A(OUTPUT_REG_A), + + .WRITE_WIDTH_B(DATA_WIDTH_ROW_B), + .READ_WIDTH_B(DATA_WIDTH_ROW_B), + + .CLKB_POLARITY(CLKB_POLARITY), + .CLKEB_POLARITY(CLKEB_POLARITY), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + .OUTPUT_REG_B(OUTPUT_REG_B), + + .ini_index(DATA_MAP_INDEX), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY) + + + ) bram ( + //Trion and Titanium ports + .CLKA (clk_a), // A-port clk + .CLKEA (clke_a), // A-port clk enable + .WEA (w_we_a), // A-port write enable + .ADDRA (w_addr_a), // A-port address input + .WDATAA(w_wdata_a), // A-port write data input + .RDATAA(w_rdata_a), // A-port read address output + + .CLKB (clk_b), // B-port clk + .CLKEB (clke_b), // B-port clk enable + .WEB (w_we_b), // B-port write enable + .ADDRB (w_addr_b), // B-port address input + .WDATAB(w_wdata_b), // B-port write data input + .RDATAB(w_rdata_b), // B-port read address output + + //Titanium extra ports + + .RSTA (reset_a), // A-port reset + .ADDRENA(addren_a), // A-port address enable + + .RSTB(reset_b), // B-port reset + .ADDRENB(addren_b) // B-port address enable + ); + + + + end + end + + end + endgenerate + + +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / tb_top.v +// / / .' / +// __/ /.' / Description: +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 0.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_true_dual_port_ram) ( + //Trion and Titanium ports + clk, // clock input for one clock mode + clke, // clk enable + + clk_a, // A-port clk + clke_a, // A-port clk enable + byteen_a, // A-port Byteen input + we_a, // A-port write enable + addr_a, // A-port address input + wdata_a, // A-port write data input + rdata_a, // A-port read address output + + clk_b, // B-port clk + clke_b, // B-port clk enable + byteen_b, // B-port Byteen input + we_b, // B-port write enable + addr_b, // B-port address input + wdata_b, // B-port write data input + rdata_b, // B-port read address output + + //Titanium extra ports + reset_a, // A-port reset + addren_a, // A-port address enable + + reset_b, // B-port reset + addren_b // B-port address enable + + ); + +//`include "bram_decompose.vh" + +//Trion and Titanium parameters +parameter CLK_POLARITY = 1'b1; //clk polarity for one clk mode; 0:falling edge; 1:rising edge +parameter CLKE_POLARITY = 1'b1; //clke polarity for one clk mode; 0:active low; 1:active high + +parameter CLKA_POLARITY = 1'b1; //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEA_POLARITY = 1'b1; //clke A polarity; 0:active low; 1:active high +parameter WEA_POLARITY = 1'b1; //we A polarity; 0:active low; 1:active high + +parameter OUTPUT_REG_A = 1'b0; // Output register enable; 1:add pipe-line read register +parameter BYTEENA_POLARITY = 1'b1; // byteen polarity 0:active low; 1:active high + +parameter CLKB_POLARITY = 1'b1; //clk A polarity; 0:falling edge; 1:rising edge +parameter CLKEB_POLARITY = 1'b1; //clke A polarity; 0:active low; 1:active high +parameter WEB_POLARITY = 1'b1; //we B polarity; 0:active low; 1:active high + +parameter OUTPUT_REG_B = 1'b0; // Output register enable; 1:add pipe-line read register +parameter BYTEENB_POLARITY = 1'b1; // byteen polarity 0:active low; 1:active high + + +//Port Enable +parameter CLK_MODE = 2; //1: ONE CLK Mode; CLK pin will provide the clock source to the memory + //2: TWO CLK Mode; clk_a and clk_b +parameter CLKEA_ENABLE = 1'b1; //1: Enalbe the port for clke_a pin ; 0: dislable +parameter WEA_ENABLE = 1'b1; //1: Enable the port for we_a pin ; 0: disable +parameter BYTEENA_ENABLE = 1'b1; //1: Enable the port for Byteen_a pins ; 0: disable + +parameter CLKEB_ENABLE = 1'b1; //1: Enalbe the port for clke_b pin ; 0: dislable +parameter WEB_ENABLE = 1'b1; //1: Enable the port for we_b pin ; 0: disable +parameter BYTEENB_ENABLE = 1'b1; //1: Enable the port for Byteen_b pins ; 0: disable + + +//Titanium extra paramters +parameter RSTA_POLARITY = 1'b1; // rst A polarity +parameter RESET_RAM_A = "ASYNC"; // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_A = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENA_POLARITY = 1'b1; // addrena polarity + +parameter RSTB_POLARITY = 1'b1; // rst A polarity +parameter RESET_RAM_B = "ASYNC"; // reset A mode on ram; "NONE": RST signals does not affect the RAM output. + // "ASYNC": RAM output resets asynchronously to RCLK. + // "SYNC": RAM output resets synchronously to RCLK. +parameter RESET_OUTREG_B = "ASYNC"; // reset A mode on output register + // "NONE": RST signals does not affect the RAM output register + // "ASYNC": RAM output register resets asynchronously to RCLK. +parameter ADDRENB_POLARITY = 1'b1; // addrenb polarity + +//Port Enable +parameter RESET_A_ENABLE = 1'b1; //1: Enable the port for reset_a pin ; 0: disable +parameter ADDREN_A_ENABLE = 1'b1; //1: Enable the port for addren_a pin ; 0: disable + +parameter RESET_B_ENABLE = 1'b1; //1: Enable the port for reset_b pin ; 0: disable +parameter ADDREN_B_ENABLE = 1'b1; //1: Enable the port for addren_b pin ; 0: disable + +parameter WRITE_MODE_A = "READ_FIRST"; +parameter WRITE_MODE_B = "READ_FIRST"; +parameter DATA_WIDTH_A = 16; +parameter DATA_WIDTH_B = 16; +parameter ADDR_WIDTH_A = 4; +parameter ADDR_WIDTH_B = 4; +parameter BYTEEN_WIDTH_A = 2; +parameter BYTEEN_WIDTH_B = 2; +parameter FAMILY = "TITANIUM"; + +//Trion and Titanium ports +input clk; +input clke; + +input clk_a; +input clke_a; +input we_a; +input [BYTEEN_WIDTH_A-1:0] byteen_a; +input [ADDR_WIDTH_A-1:0 ] addr_a; +input [DATA_WIDTH_A-1:0 ] wdata_a; +output [DATA_WIDTH_A-1:0 ]rdata_a; + +input clk_b; +input clke_b; +input we_b; +input [BYTEEN_WIDTH_B-1:0] byteen_b; +input [ADDR_WIDTH_B-1:0 ] addr_b; +input [DATA_WIDTH_B-1:0 ] wdata_b; +output [DATA_WIDTH_B-1:0 ]rdata_b; + +//Titanium extra ports +input reset_a; +input addren_a; + +input reset_b; +input addren_b; + +////////////////// wires ////////////////// +wire w_clk_a; +wire w_clke_a; +wire [BYTEEN_WIDTH_A-1:0] w_byteen_a; +wire w_we_a; + +wire w_clk_b; +wire w_clke_b; +wire [BYTEEN_WIDTH_B-1:0] w_byteen_b; +wire w_we_b; + +wire w_reset_a; +wire w_addren_a; + +wire w_reset_b; +wire w_addren_b; + + +assign w_clk_a = (CLK_MODE==2) ? clk_a : clk; +assign w_clke_a = (CLKEA_ENABLE==1) ? ((CLK_MODE==2) ? clke_a : clke) : CLKEA_POLARITY; +assign w_byteen_a = (BYTEENA_ENABLE==1)? byteen_a : {BYTEEN_WIDTH_A{BYTEENA_POLARITY}}; +assign w_we_a = (WEA_ENABLE==1) ? we_a : WEA_POLARITY; + +assign w_clk_b = (CLK_MODE==2) ? clk_b : clk; +assign w_clke_b = (CLKEB_ENABLE==1) ? ((CLK_MODE==2) ? clke_b : clke) : CLKEB_POLARITY; +assign w_byteen_b = (BYTEENB_ENABLE==1)? byteen_b : {BYTEEN_WIDTH_B{BYTEENB_POLARITY}}; +assign w_we_b = (WEB_ENABLE==1) ? we_b : WEB_POLARITY; + + +//Titanium extra ports +assign w_reset_a = (RESET_A_ENABLE==1) ? reset_a : (RSTA_POLARITY==1'b1) ? 1'b0: 1'b1; +assign w_addren_a = (ADDREN_A_ENABLE==1) ? addren_a : ADDRENA_POLARITY; + +assign w_reset_b = (RESET_B_ENABLE==1) ? reset_b : (RSTB_POLARITY==1'b1) ? 1'b0: 1'b1; +assign w_addren_b = (ADDREN_B_ENABLE==1) ? addren_b : ADDRENB_POLARITY; + + +localparam CLKA_POLARITY_LC = (CLK_MODE==2) ? CLKA_POLARITY : CLK_POLARITY; +localparam CLKB_POLARITY_LC = (CLK_MODE==2) ? CLKB_POLARITY : CLK_POLARITY; + +localparam CLKEA_POLARITY_LC = (CLK_MODE==2) ? CLKEA_POLARITY : CLKE_POLARITY; +localparam CLKEB_POLARITY_LC = (CLK_MODE==2) ? CLKEB_POLARITY : CLKE_POLARITY; + + `IP_MODULE_NAME(dpram_wrapper_mwm) #( + //Trion and Titanium parameters + .CLKA_POLARITY(CLKA_POLARITY_LC), + .CLKEA_POLARITY(CLKEA_POLARITY_LC), + .WEA_POLARITY(WEA_POLARITY), + .WRITE_MODE_A(WRITE_MODE_A), + + .OUTPUT_REG_A(OUTPUT_REG_A), + .BYTEENA_POLARITY(BYTEENA_POLARITY), + + .CLKB_POLARITY(CLKB_POLARITY_LC), + .CLKEB_POLARITY(CLKEB_POLARITY_LC), + .WEB_POLARITY(WEB_POLARITY), + .WRITE_MODE_B(WRITE_MODE_B), + + .OUTPUT_REG_B(OUTPUT_REG_B), + .BYTEENB_POLARITY(BYTEENB_POLARITY), + + //Titanium extra paramters + .RSTA_POLARITY(RSTA_POLARITY), + .RESET_RAM_A(RESET_RAM_A), + .RESET_OUTREG_A(RESET_OUTREG_A), + .ADDRENA_POLARITY(ADDRENA_POLARITY), + + .RSTB_POLARITY(RSTB_POLARITY), + .RESET_RAM_B(RESET_RAM_B), + .RESET_OUTREG_B(RESET_OUTREG_B), + .ADDRENB_POLARITY(ADDRENB_POLARITY), + + .DATA_WIDTH_A(DATA_WIDTH_A), + .DATA_WIDTH_B(DATA_WIDTH_B), + .ADDR_WIDTH_A(ADDR_WIDTH_A), + .ADDR_WIDTH_B(ADDR_WIDTH_B), + .BYTEEN_WIDTH_A(BYTEEN_WIDTH_A), + .BYTEEN_WIDTH_B(BYTEEN_WIDTH_B), + + .FAMILY(FAMILY) + + + ) brams ( + //Trion and Titanium ports + .clk_a(w_clk_a), + .clke_a(w_clke_a), + .byteen_a(w_byteen_a), + .we_a(w_we_a), + .addr_a(addr_a), + .wdata_a(wdata_a), + .rdata_a(rdata_a), + + .clk_b(w_clk_b), + .clke_b(w_clke_b), + .byteen_b(w_byteen_b), + .we_b(w_we_b), + .addr_b(addr_b), + .wdata_b(wdata_b), + .rdata_b(rdata_b), + + //Titanium extra ports + .reset_a(w_reset_a), + .addren_a(w_addren_a), + .reset_b(w_reset_b), + .addren_b(w_addren_b) + + ); + + + +endmodule +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/my_bram_ip_define.vh b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/my_bram_ip_define.vh new file mode 100644 index 0000000000000000000000000000000000000000..f7e5ae0550c31f2dda23480dde3443f9bd41c78c --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/my_bram_ip_define.vh @@ -0,0 +1,114 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2023.2.307 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam ADDR_WIDTH_A = 11; +localparam ADDR_WIDTH_B = 11; +localparam RESET_A_ENABLE = 0; +localparam RESET_B_ENABLE = 0; +localparam RSTA_POLARITY = 1; +localparam RSTB_POLARITY = 1; +localparam FAMILY = "TITANIUM"; +localparam MEMORY_MODE = "SPEED"; +localparam WRITE_MODE_A = "READ_FIRST"; +localparam WRITE_MODE_B = "READ_FIRST"; +localparam OUTPUT_REG_A = 0; +localparam OUTPUT_REG_B = 0; +localparam MEMORY_TYPE = "TDP_RAM"; +localparam GROUP_DATA_WIDTH_B = 8; +localparam BYTEENA_ENABLE = 0; +localparam BYTEENB_ENABLE = 0; +localparam BYTEENA_POLARITY = 1; +localparam BYTEENB_POLARITY = 1; +localparam BYTEEN_WIDTH_A = 1; +localparam BYTEEN_WIDTH_B = 1; +localparam BYTEEN_ENABLE = 0; +localparam BYTEEN_POLARITY = 1; +localparam GROUP_DATA_WIDTH = 8; +localparam BYTEEN_WIDTH = 1; +localparam WIDTH_RATIO = 4; +localparam GROUP_DATA_WIDTH_A = 8; +localparam DATA_WIDTH_A = 8; +localparam DATA_WIDTH_B = 8; +localparam ADDREN_ENABLE = 1; +localparam ADDREN_POLARITY = 1; +localparam CLK_MODE = 2; +localparam CLKA_POLARITY = 1; +localparam CLKB_POLARITY = 1; +localparam CLKE_POLARITY = 1; +localparam CLKEA_POLARITY = 1; +localparam CLKEA_ENABLE = 0; +localparam RESET_OUTREG_A = "ASYNC"; +localparam RESET_OUTREG_B = "ASYNC"; +localparam RESET_RAM_B = "ASYNC"; +localparam WEA_ENABLE = 1; +localparam WEA_POLARITY = 1; +localparam WEB_ENABLE = 1; +localparam WEB_POLARITY = 1; +localparam RADDREN_ENABLE = 1; +localparam RADDREN_POLARITY = 1; +localparam WADDREN_ENABLE = 1; +localparam WADDREN_POLARITY = 1; +localparam RCLK_POLARITY = 1; +localparam ADDREN_A_ENABLE = 0; +localparam ADDREN_B_ENABLE = 0; +localparam ADDRENA_POLARITY = 1; +localparam ADDRENB_POLARITY = 1; +localparam WE_ENABLE = 1; +localparam WE_POLARITY = 1; +localparam WCLKE_ENABLE = 1; +localparam WCLKE_POLARITY = 1; +localparam WCLK_POLARITY = 1; +localparam RESET_RAM_A = "ASYNC"; +localparam RESET_RAM = "ASYNC"; +localparam CLK_POLARITY = 1; +localparam OUTPUT_REG = 0; +localparam RE_POLARITY = 1; +localparam RE_ENABLE = 1; +localparam WRITE_MODE = "READ_FIRST"; +localparam RESET_OUTREG = "ASYNC"; +localparam RESET_ENABLE = 1; +localparam RST_POLARITY = 1; +localparam CLKEB_POLARITY = 1; +localparam CLKEB_ENABLE = 0; diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/my_bram_ip_tmpl.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/my_bram_ip_tmpl.v new file mode 100644 index 0000000000000000000000000000000000000000..dcc1a3e2b6e814530cfb061fde6a421798fdd2a2 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/my_bram_ip_tmpl.v @@ -0,0 +1,51 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +my_bram_ip u_my_bram_ip( +.we_a ( we_a ), +.we_b ( we_b ), +.addr_a ( addr_a ), +.wdata_a ( wdata_a ), +.rdata_a ( rdata_a ), +.rdata_b ( rdata_b ), +.addr_b ( addr_b ), +.wdata_b ( wdata_b ), +.clk_a ( clk_a ), +.clk_b ( clk_b ) +); diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/my_bram_ip_tmpl.vhd b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/my_bram_ip_tmpl.vhd new file mode 100644 index 0000000000000000000000000000000000000000..20c66e38c6fb47be3930d3c9d2dbe5fe160b6141 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/my_bram_ip_tmpl.vhd @@ -0,0 +1,68 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +COMPONENT my_bram_ip is +PORT ( +we_a : in std_logic; +we_b : in std_logic; +addr_a : in std_logic_vector(10 downto 0); +wdata_a : in std_logic_vector(7 downto 0); +rdata_a : out std_logic_vector(7 downto 0); +rdata_b : out std_logic_vector(7 downto 0); +addr_b : in std_logic_vector(10 downto 0); +wdata_b : in std_logic_vector(7 downto 0); +clk_a : in std_logic; +clk_b : in std_logic); +END COMPONENT; +---------------------- End COMPONENT Declaration ------------ + +------------- Begin Cut here for INSTANTIATION Template ----- +u_my_bram_ip : my_bram_ip +PORT MAP ( +we_a => we_a, +we_b => we_b, +addr_a => addr_a, +wdata_a => wdata_a, +rdata_a => rdata_a, +rdata_b => rdata_b, +addr_b => addr_b, +wdata_b => wdata_b, +clk_a => clk_a, +clk_b => clk_b); +------------------------ End INSTANTIATION Template --------- diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/settings.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..bdf37c1afabfe510e04a1ce3bf4d052a6cc0118b --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/ip/my_bram_ip/settings.json @@ -0,0 +1,149 @@ +{ + "args": [ + "-o", + "my_bram_ip", + "--base_path", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_bram", + "version": "5.4" + } + ], + "conf": { + "ADDR_WIDTH_A": "11", + "RESET_A_ENABLE": "0", + "RESET_B_ENABLE": "0", + "RSTA_POLARITY": "1", + "RSTB_POLARITY": "1", + "FAMILY": "\"TITANIUM\"", + "MEMORY_MODE": "\"SPEED\"", + "WRITE_MODE_A": "\"READ_FIRST\"", + "WRITE_MODE_B": "\"READ_FIRST\"", + "OUTPUT_REG_A": "0", + "OUTPUT_REG_B": "0", + "MEMORY_TYPE": "\"TDP_RAM\"", + "BYTEENA_ENABLE": "0", + "BYTEENA_POLARITY": "1", + "BYTEENB_POLARITY": "1", + "BYTEEN_ENABLE": "0", + "BYTEEN_POLARITY": "1", + "HexFile_PathEnable": "0", + "HexFile_Path": "\"''\"", + "WIDTH_RATIO": "4", + "DATA_WIDTH_A": "8", + "ADDREN_ENABLE": "1", + "ADDREN_POLARITY": "1", + "CLKA_POLARITY": "1", + "CLKB_POLARITY": "1", + "CLKE_POLARITY": "1", + "CLKEA_POLARITY": "1", + "RESET_OUTREG_A": "\"ASYNC\"", + "RESET_OUTREG_B": "\"ASYNC\"", + "RESET_RAM_B": "\"ASYNC\"", + "WEA_ENABLE": "1", + "WEA_POLARITY": "1", + "WEB_ENABLE": "1", + "WEB_POLARITY": "1", + "RADDREN_ENABLE": "1", + "RADDREN_POLARITY": "1", + "WADDREN_ENABLE": "1", + "WADDREN_POLARITY": "1", + "RCLK_POLARITY": "1", + "ADDREN_A_ENABLE": "0", + "ADDREN_B_ENABLE": "0", + "ADDRENA_POLARITY": "1", + "ADDRENB_POLARITY": "1", + "WE_ENABLE": "1", + "WE_POLARITY": "1", + "WCLKE_ENABLE": "1", + "WCLKE_POLARITY": "1", + "WCLK_POLARITY": "1", + "RESET_RAM_A": "\"ASYNC\"", + "RESET_RAM": "\"ASYNC\"", + "CLK_POLARITY": "1", + "OUTPUT_REG": "0", + "RE_POLARITY": "1", + "RE_ENABLE": "1", + "WRITE_MODE": "\"READ_FIRST\"", + "RESET_OUTREG": "\"ASYNC\"", + "RESET_ENABLE": "1", + "RST_POLARITY": "1", + "CLKEB_POLARITY": "1", + "CLK_MODE_SDP": "1", + "CLK_MODE_TDP_DP": "2", + "CLKE_ENABLE": "1", + "CLKEA_ENABLE_INT": "0", + "CLKEB_ENABLE_INT": "0" + }, + "output": { + "external_script_script": [], + "external_source_source": [ + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\my_bram_ip_define.vh", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\my_bram_ip.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\my_bram_ip_tmpl.vhd", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\my_bram_ip_tmpl.v" + ], + "external_example_example": [ + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\bram.peri.xml", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\bram.xml", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\debug_profile.wizard.json", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\bram_top.sdc", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\efx_simple_dual_port_ram.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\bram_wrapper_mwm.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\bram_primitive.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\dpram_top_titanium.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\reset.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\test_pattern.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\write_pattern.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\bram_decompose.vh", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\bram_ini.vh", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\my_bram_ip.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Ti60F225_devkit\\my_bram_ip_define.vh" + ], + "external_example_example_2": [ + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\bram.peri.xml", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\bram.xml", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\debug_profile.wizard.json", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\bram_top.sdc", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\bram_wrapper_mwm.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\bram_primitive.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\dpram_top_trion.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\reset.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\test_pattern.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\write_pattern.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\efx_simple_dual_port_ram.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\bram_decompose.vh", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\bram_ini.vh", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\my_bram_ip.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\T120F576_devkit\\my_bram_ip_define.vh" + ], + "external_testbench_testbench": [ + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\tb.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\efx_dpram_5k.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\efx_dpram10.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\efx_ram_5k.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\efx_ram10.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\signal_gen_sp.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\signal_gen_sprom.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\monitor_sp.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\signal_gen_sdp.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\monitor_sdp.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\signal_gen_tdp.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\monitor_tdp.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\tdp_test_pattern.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\dp_test_pattern_rom.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\modelsim.do", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\flist", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\bram_decompose.vh", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\bram_ini.vh", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\init_hex.mem", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\my_bram_ip.v", + "C:\\Users\\32954\\Desktop\\FPGA\\1080\\1051\\ip\\my_bram_ip\\Testbench\\my_bram_ip_define.vh" + ] + }, + "sw_version": "2023.2.307", + "generated_date": "2024-11-12T12:06:02.293548" +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/outflow/Ti60_Demo.prevpr.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/outflow/Ti60_Demo.prevpr.v new file mode 100644 index 0000000000000000000000000000000000000000..82613f6f65f1550443f4329b73c08c5403306191 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/outflow/Ti60_Demo.prevpr.v @@ -0,0 +1,103245 @@ + +// +// Verific Verilog Description of module example_top +// + +module example_top (clk_24m, clk_25m, sys_pll_rstn_o, clk_sys, clk_pixel, + clk_pixel_2x, clk_pixel_10x, sys_pll_lock, dsi_pll_rstn_o, + dsi_refclk_i, dsi_byteclk_i, dsi_serclk_i, dsi_txcclk_i, + dsi_pll_lock, ddr_pll_rstn_o, tdqss_clk, core_clk, tac_clk, + twd_clk, ddr_pll_lock, shift, shift_sel, shift_ena, lvds_pll_rstn_o, + clk_lvds_1x, clk_lvds_7x, clk_27m, clk_54m, lvds_pll_lock, + addr, ba, we, reset, ras, cas, odt, cke, cs, i_dq_hi, + i_dq_lo, o_dq_hi, o_dq_lo, o_dq_oe, o_dm_hi, o_dm_lo, + i_dqs_hi, i_dqs_lo, i_dqs_n_hi, i_dqs_n_lo, o_dqs_hi, + o_dqs_lo, o_dqs_n_hi, o_dqs_n_lo, o_dqs_oe, o_dqs_n_oe, + clk_p_hi, clk_p_lo, clk_n_hi, clk_n_lo, csi_ctl0_o, csi_ctl0_oe, + csi_ctl0_i, csi_ctl1_o, csi_ctl1_oe, csi_ctl1_i, csi_scl_o, + csi_scl_oe, csi_scl_i, csi_sda_o, csi_sda_oe, csi_sda_i, + csi_rxc_lp_p_i, csi_rxc_lp_n_i, csi_rxc_hs_en_o, csi_rxc_hs_term_en_o, + csi_rxc_i, csi_rxd0_rst_o, csi_rxd0_hs_en_o, csi_rxd0_hs_term_en_o, + csi_rxd0_lp_p_i, csi_rxd0_lp_n_i, csi_rxd0_hs_i, csi_rxd1_rst_o, + csi_rxd1_hs_en_o, csi_rxd1_hs_term_en_o, csi_rxd1_lp_n_i, + csi_rxd1_lp_p_i, csi_rxd1_hs_i, csi_rxd2_rst_o, csi_rxd2_hs_en_o, + csi_rxd2_hs_term_en_o, csi_rxd2_lp_p_i, csi_rxd2_lp_n_i, csi_rxd2_hs_i, + csi_rxd3_rst_o, csi_rxd3_hs_en_o, csi_rxd3_hs_term_en_o, csi_rxd3_lp_p_i, + csi_rxd3_lp_n_i, csi_rxd3_hs_i, dsi_pwm_o, dsi_resetn_o, + dsi_txc_rst_o, dsi_txc_lp_p_oe, dsi_txc_lp_p_o, dsi_txc_lp_n_oe, + dsi_txc_lp_n_o, dsi_txc_hs_oe, dsi_txc_hs_o, dsi_txd0_rst_o, + dsi_txd0_hs_oe, dsi_txd0_hs_o, dsi_txd0_lp_p_oe, dsi_txd0_lp_p_o, + dsi_txd0_lp_n_oe, dsi_txd0_lp_n_o, dsi_txd1_rst_o, dsi_txd1_lp_p_oe, + dsi_txd1_lp_p_o, dsi_txd1_lp_n_oe, dsi_txd1_lp_n_o, dsi_txd1_hs_oe, + dsi_txd1_hs_o, dsi_txd2_rst_o, dsi_txd2_lp_p_oe, dsi_txd2_lp_p_o, + dsi_txd2_lp_n_oe, dsi_txd2_lp_n_o, dsi_txd2_hs_oe, dsi_txd2_hs_o, + dsi_txd3_rst_o, dsi_txd3_lp_p_oe, dsi_txd3_lp_p_o, dsi_txd3_lp_n_oe, + dsi_txd3_lp_n_o, dsi_txd3_hs_oe, dsi_txd3_hs_o, dsi_txd0_lp_p_i, + dsi_txd0_lp_n_i, dsi_txd1_lp_p_i, dsi_txd1_lp_n_i, dsi_txd2_lp_p_i, + dsi_txd2_lp_n_i, dsi_txd3_lp_p_i, dsi_txd3_lp_n_i, uart_rx_i, + uart_tx_o, led_o, cmos_sclk, cmos_sdat_IN, cmos_sdat_OUT, + cmos_sdat_OE, cmos_pclk, cmos_vsync, cmos_href, cmos_data, + cmos_ctl1, cmos_ctl2, cmos_ctl3, hdmi_txc_oe, hdmi_txd0_oe, + hdmi_txd1_oe, hdmi_txd2_oe, hdmi_txc_rst_o, hdmi_txd0_rst_o, + hdmi_txd1_rst_o, hdmi_txd2_rst_o, hdmi_txc_o, hdmi_txd0_o, + hdmi_txd1_o, hdmi_txd2_o, lvds_txc_oe, lvds_txc_o, lvds_txc_rst_o, + lvds_txd0_oe, lvds_txd0_o, lvds_txd0_rst_o, lvds_txd1_oe, + lvds_txd1_o, lvds_txd1_rst_o, lvds_txd2_oe, lvds_txd2_o, + lvds_txd2_rst_o, lvds_txd3_oe, lvds_txd3_o, lvds_txd3_rst_o, + lcd_tp_sda_o, lcd_tp_sda_oe, lcd_tp_sda_i, lcd_tp_scl_o, + lcd_tp_scl_oe, lcd_tp_scl_i, lcd_tp_int_o, lcd_tp_int_oe, + lcd_tp_int_i, lcd_tp_rst_o, lcd_pwm_o, lcd_blen_o, lcd_vs_o, + lcd_hs_o, lcd_de_o, lcd_b7_0_o, lcd_g7_0_o, lcd_r7_0_o, + lcd_b7_0_oe, lcd_g7_0_oe, lcd_r7_0_oe, lcd_b7_0_i, lcd_g7_0_i, + lcd_r7_0_i, spi_sck_o, spi_ssn_o); + input clk_24m /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input clk_25m /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output sys_pll_rstn_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input clk_sys /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input clk_pixel /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input clk_pixel_2x /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input clk_pixel_10x /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input sys_pll_lock /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output dsi_pll_rstn_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input dsi_refclk_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input dsi_byteclk_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input dsi_serclk_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input dsi_txcclk_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input dsi_pll_lock /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output ddr_pll_rstn_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input tdqss_clk /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input core_clk /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input tac_clk /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input twd_clk /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input ddr_pll_lock /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output [2:0]shift /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [4:0]shift_sel /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output shift_ena /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lvds_pll_rstn_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input clk_lvds_1x /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input clk_lvds_7x /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input clk_27m /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input clk_54m /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input lvds_pll_lock /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output [15:0]addr /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [2:0]ba /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output we /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output reset /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output ras /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output cas /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output odt /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output cke /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output cs /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input [15:0]i_dq_hi /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input [15:0]i_dq_lo /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output [15:0]o_dq_hi /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [15:0]o_dq_lo /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [15:0]o_dq_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [1:0]o_dm_hi /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [1:0]o_dm_lo /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input [1:0]i_dqs_hi /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input [1:0]i_dqs_lo /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input [1:0]i_dqs_n_hi /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input [1:0]i_dqs_n_lo /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output [1:0]o_dqs_hi /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [1:0]o_dqs_lo /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [1:0]o_dqs_n_hi /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [1:0]o_dqs_n_lo /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [1:0]o_dqs_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [1:0]o_dqs_n_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output clk_p_hi /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output clk_p_lo /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output clk_n_hi /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output clk_n_lo /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_ctl0_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_ctl0_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input csi_ctl0_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output csi_ctl1_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_ctl1_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input csi_ctl1_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output csi_scl_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_scl_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input csi_scl_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output csi_sda_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_sda_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input csi_sda_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input csi_rxc_lp_p_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input csi_rxc_lp_n_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output csi_rxc_hs_en_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_rxc_hs_term_en_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input csi_rxc_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output csi_rxd0_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_rxd0_hs_en_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_rxd0_hs_term_en_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input csi_rxd0_lp_p_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input csi_rxd0_lp_n_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input [7:0]csi_rxd0_hs_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output csi_rxd1_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_rxd1_hs_en_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_rxd1_hs_term_en_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input csi_rxd1_lp_n_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input csi_rxd1_lp_p_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input [7:0]csi_rxd1_hs_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output csi_rxd2_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_rxd2_hs_en_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_rxd2_hs_term_en_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input csi_rxd2_lp_p_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input csi_rxd2_lp_n_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input [7:0]csi_rxd2_hs_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output csi_rxd3_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_rxd3_hs_en_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output csi_rxd3_hs_term_en_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input csi_rxd3_lp_p_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input csi_rxd3_lp_n_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input [7:0]csi_rxd3_hs_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output dsi_pwm_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_resetn_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txc_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txc_lp_p_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txc_lp_p_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txc_lp_n_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txc_lp_n_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txc_hs_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [7:0]dsi_txc_hs_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd0_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd0_hs_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [7:0]dsi_txd0_hs_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd0_lp_p_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd0_lp_p_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd0_lp_n_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd0_lp_n_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd1_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd1_lp_p_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd1_lp_p_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd1_lp_n_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd1_lp_n_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd1_hs_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [7:0]dsi_txd1_hs_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd2_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd2_lp_p_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd2_lp_p_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd2_lp_n_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd2_lp_n_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd2_hs_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [7:0]dsi_txd2_hs_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd3_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd3_lp_p_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd3_lp_p_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd3_lp_n_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd3_lp_n_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output dsi_txd3_hs_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [7:0]dsi_txd3_hs_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input dsi_txd0_lp_p_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input dsi_txd0_lp_n_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input dsi_txd1_lp_p_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input dsi_txd1_lp_n_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input dsi_txd2_lp_p_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input dsi_txd2_lp_n_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input dsi_txd3_lp_p_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input dsi_txd3_lp_n_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input uart_rx_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output uart_tx_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [5:0]led_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output cmos_sclk /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input cmos_sdat_IN /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output cmos_sdat_OUT /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output cmos_sdat_OE /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input cmos_pclk /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input cmos_vsync /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input cmos_href /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input [7:0]cmos_data /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input cmos_ctl1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output cmos_ctl2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output cmos_ctl3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output hdmi_txc_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output hdmi_txd0_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output hdmi_txd1_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output hdmi_txd2_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output hdmi_txc_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output hdmi_txd0_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output hdmi_txd1_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output hdmi_txd2_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [9:0]hdmi_txc_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [9:0]hdmi_txd0_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [9:0]hdmi_txd1_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [9:0]hdmi_txd2_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lvds_txc_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [6:0]lvds_txc_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lvds_txc_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lvds_txd0_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [6:0]lvds_txd0_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lvds_txd0_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lvds_txd1_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [6:0]lvds_txd1_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lvds_txd1_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lvds_txd2_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [6:0]lvds_txd2_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lvds_txd2_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lvds_txd3_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [6:0]lvds_txd3_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lvds_txd3_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lcd_tp_sda_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lcd_tp_sda_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input lcd_tp_sda_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output lcd_tp_scl_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lcd_tp_scl_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input lcd_tp_scl_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output lcd_tp_int_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lcd_tp_int_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input lcd_tp_int_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output lcd_tp_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lcd_pwm_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lcd_blen_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lcd_vs_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lcd_hs_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output lcd_de_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [7:0]lcd_b7_0_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [7:0]lcd_g7_0_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [7:0]lcd_r7_0_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [7:0]lcd_b7_0_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [7:0]lcd_g7_0_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output [7:0]lcd_r7_0_oe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + input [7:0]lcd_b7_0_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input [7:0]lcd_g7_0_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + input [7:0]lcd_r7_0_i /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + output spi_sck_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + output spi_ssn_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[7] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[2] /* verific async_reg="true" */ ; + wire \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] /* verific async_reg="true" */ ; + wire \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0] /* verific async_reg="true" */ ; + wire \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] /* verific async_reg="true" */ ; + wire \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0] /* verific async_reg="true" */ ; + wire \hdmi_txd0_o[2]_2 ; + wire \hdmi_txd0_o[4]_2 ; + wire \hdmi_txd0_o[6]_2 ; + wire \hdmi_txd0_o[8]_2 ; + wire \hdmi_txd0_o[9]_2 ; + wire \hdmi_txd1_o[2]_2 ; + wire \hdmi_txd1_o[4]_2 ; + wire \hdmi_txd1_o[6]_2 ; + wire \hdmi_txd1_o[8]_2 ; + wire \hdmi_txd1_o[9]_2 ; + wire \hdmi_txd2_o[2]_2 ; + wire \hdmi_txd2_o[4]_2 ; + wire \hdmi_txd2_o[6]_2 ; + wire \hdmi_txd2_o[9]_2 ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[4] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[3] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[2] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[1] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[5] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[6] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[0] /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p1 /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p /* verific async_reg="true" */ ; + wire \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[1] /* verific async_reg="true" */ ; + wire n1406_2; + wire n1413_2; + wire \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0] /* verific async_reg="true" */ ; + wire \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] /* verific async_reg="true" */ ; + wire \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0] /* verific async_reg="true" */ ; + wire \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] /* verific async_reg="true" */ ; + + wire rstn_sys, rstn_pixel, r_ddr_unlock, \r_cmos_rx_vsync0_in[0] , + r_XYCrop_frame_vsync, \r_XYCrop_frame_Gray[0] , r_XYCrop_frame_href, + r_XYCrop_frame_de, \r_cmos_rx_vsync0_in[1] , n170, n171, n172, + n173, n176, n177, n178, n179, n180, n181, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_en , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_en , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wready , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wvalid , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_awaddr_fifo_rd_en , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_awvalid , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_flag , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_empty[0] , + n207, n208, n209, n210, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[32] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[48] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[52] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[64] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[65] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[68] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[69] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[70] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[71] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[72] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[73] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[74] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[75] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[76] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[77] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[78] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[79] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[80] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[81] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[82] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[83] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[84] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[85] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[86] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[87] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[88] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[89] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[90] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[91] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[92] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[93] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[94] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[95] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[96] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[97] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[98] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[99] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[100] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[101] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[102] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[103] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[104] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[105] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[106] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[107] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[108] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[109] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[110] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[111] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[112] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[113] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[114] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[115] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[116] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[117] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[118] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[119] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[120] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[121] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[122] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[123] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[124] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[125] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[126] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[127] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[15] , + n515, n516, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[0][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[0][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arburst_full , + n532, n533, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5] , + n540, n541, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_araddr_full , + n767, n768, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5] , + n775, n776, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_full , + n1016, n1017, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5] , + n1024, n1025, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awid_full , + n1027, n1028, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5] , + n1035, n1036, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arid_full , + n1038, n1039, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5] , + n1046, n1047, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full , + n1049, n1050, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5] , + n1057, n1058, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_full , + n1116, n1117, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5] , + n1124, n1125, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Wr_Full , + n1183, n1184, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5] , + n1191, n1192, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awlen_full , + n1250, n1251, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn , + n1259, n1260, n1262, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_start_p0 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_en , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_en , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena , + \ddr3_ctl_axi/cal_fail_log[0] , \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_read , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0] , + n1335, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5] , + n1403, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0] , + n1422, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5] , + n1490, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0] , + n1511, n1512, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[48] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[52] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[64] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[65] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[68] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[69] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[70] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[71] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[72] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[73] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[74] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[75] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[76] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[77] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[78] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[79] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[80] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[81] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[82] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[83] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[84] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[85] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[86] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[87] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[88] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[89] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[90] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[91] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[92] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[93] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[94] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[95] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[96] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[97] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[98] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[99] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[100] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[101] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[102] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[103] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[104] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[105] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[106] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[107] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[108] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[109] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[110] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[111] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[112] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[113] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[114] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[115] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[116] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[117] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[118] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[119] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[120] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[121] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[122] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[123] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[124] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[125] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[126] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[127] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[15] , + n1675, n1676, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[32] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0] , + n1732, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_data[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] , + n1804, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5] , + n2004, n2005, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5] , + n2076, n2077, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[32] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[48] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[51] , + n2115, n2116, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_1 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i112_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i113_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i114_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i115_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i116_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i117_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i118_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i119_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i12_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i121_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i122_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i123_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i124_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i125_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i126_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i97_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i98_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i99_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i1_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i101_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i102_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i103_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i104_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i105_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i106_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i107_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i108_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i109_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i11_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i111_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe_p0[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i10_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i82_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i83_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i84_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i85_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i86_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i87_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i88_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i89_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i9_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i91_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i92_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i93_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i94_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i95_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i96_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_rd_fifo_wr_en_p[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i67_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i68_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i69_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i7_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i71_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i72_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i73_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i74_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i75_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i76_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i77_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i78_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i79_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i8_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i81_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][82] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][83] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][84] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][85] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][86] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][87] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][88] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][89] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][90] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][91] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][92] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][93] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][94] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][95] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][96] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][97] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][98] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][99] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][100] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][101] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][102] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][103] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][104] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][105] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][106] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][107] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][108] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][109] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][110] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][111] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][112] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][113] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][114] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][115] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][116] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][117] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][118] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][119] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][120] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][121] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][122] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][123] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][124] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][125] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][126] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][127] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][15] , + \u_axi4_ctrl/dff_138/i10_rst_0 , \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_3 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_pre , + \u_axi4_ctrl/rfifo_wr_rst_busy_dly[9] , \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_en , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i52_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i53_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i54_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i55_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i56_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i57_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i58_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i59_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i6_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i61_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i62_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i63_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i64_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i65_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i66_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][32] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][48] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][52] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][64] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][65] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][68] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][69] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][70] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][71] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][72] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][73] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][74] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][75] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][76] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][77] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][78] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][79] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][80] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][81] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i37_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i38_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i39_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i4_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i41_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i42_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i43_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i44_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i45_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i46_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i47_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i48_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i49_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i5_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i51_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i22_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i23_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i24_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i25_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i26_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i27_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i28_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i29_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i3_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i31_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i32_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i33_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i34_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i35_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i36_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_3 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i80_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i90_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i100_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i110_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i120_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i128_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i13_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i14_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i15_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i16_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i17_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i18_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i19_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i2_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i21_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i15_pre , + \u_axi4_ctrl/dff_138/i10_rst_1 , \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i20_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i30_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i40_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i50_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i60_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i70_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0] , + n2603, n2604, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i127_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i16_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i2_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i3_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i4_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i5_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i6_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i7_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i8_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i9_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i1_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i11_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i12_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i13_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i14_pre , + n2642, n2643, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[2] , + n2646, n2647, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[0] , + n2660, n2661, n2662, n2663, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_start_count , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_addr_re , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_addr_re , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_push , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cs , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ras , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cas , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_we , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cke , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cs , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ras , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cas , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_we , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cke , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p0 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[69] , + n2966, n2967, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_busy , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/ena_p , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] , + \ddr3_ctl_axi/cal_shift_val[0] , \ddr3_ctl_axi/cal_shift_val[1] , + \ddr3_ctl_axi/cal_shift_val[2] , \ddr3_ctl_axi/cal_fail_log[1] , + \ddr3_ctl_axi/cal_fail_log[2] , \ddr3_ctl_axi/cal_fail_log[3] , + \ddr3_ctl_axi/cal_fail_log[4] , \ddr3_ctl_axi/cal_fail_log[5] , + \ddr3_ctl_axi/cal_fail_log[6] , \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15] , + \axi4_awar_mux/rs_req[0] , w_ddr3_awready, w_ddr3_avalid, w_ddr3_arready, + \axi4_awar_mux/rs_req[1] , n3678, n3679, \u_i2c_timing_ctrl_16bit/clk_cnt[0] , + n3681, n3682, \u_i2c_timing_ctrl_16bit/i2c_ctrl_clk , \u_i2c_timing_ctrl_16bit/i2c_transfer_en , + \sc130_i2c_config_index[0] , n3687, n3688, \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0] , + \u_i2c_timing_ctrl_16bit/i2c_wdata[0] , \u_i2c_timing_ctrl_16bit/delay_cnt[0] , + \u_i2c_timing_ctrl_16bit/clk_cnt[1] , \u_i2c_timing_ctrl_16bit/clk_cnt[2] , + \u_i2c_timing_ctrl_16bit/clk_cnt[3] , \u_i2c_timing_ctrl_16bit/clk_cnt[4] , + \u_i2c_timing_ctrl_16bit/clk_cnt[5] , \u_i2c_timing_ctrl_16bit/clk_cnt[6] , + \u_i2c_timing_ctrl_16bit/clk_cnt[7] , \u_i2c_timing_ctrl_16bit/clk_cnt[8] , + \u_i2c_timing_ctrl_16bit/clk_cnt[9] , \u_i2c_timing_ctrl_16bit/clk_cnt[10] , + \u_i2c_timing_ctrl_16bit/clk_cnt[11] , \u_i2c_timing_ctrl_16bit/clk_cnt[12] , + \u_i2c_timing_ctrl_16bit/clk_cnt[13] , \u_i2c_timing_ctrl_16bit/clk_cnt[14] , + \u_i2c_timing_ctrl_16bit/clk_cnt[15] , \u_i2c_timing_ctrl_16bit/current_state[0] , + \u_i2c_timing_ctrl_16bit/current_state[1] , \u_i2c_timing_ctrl_16bit/current_state[2] , + \u_i2c_timing_ctrl_16bit/current_state[3] , \sc130_i2c_config_index[1] , + \sc130_i2c_config_index[2] , \sc130_i2c_config_index[3] , \sc130_i2c_config_index[4] , + \sc130_i2c_config_index[5] , \sc130_i2c_config_index[6] , \sc130_i2c_config_index[7] , + \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1] , \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2] , + \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3] , \u_i2c_timing_ctrl_16bit/i2c_wdata[1] , + \u_i2c_timing_ctrl_16bit/i2c_wdata[2] , \u_i2c_timing_ctrl_16bit/i2c_wdata[3] , + \u_i2c_timing_ctrl_16bit/i2c_wdata[4] , \u_i2c_timing_ctrl_16bit/i2c_wdata[5] , + \u_i2c_timing_ctrl_16bit/i2c_wdata[6] , \u_i2c_timing_ctrl_16bit/i2c_wdata[7] , + \u_i2c_timing_ctrl_16bit/delay_cnt[1] , \u_i2c_timing_ctrl_16bit/delay_cnt[2] , + \u_i2c_timing_ctrl_16bit/delay_cnt[3] , \u_i2c_timing_ctrl_16bit/delay_cnt[4] , + \u_i2c_timing_ctrl_16bit/delay_cnt[5] , \u_i2c_timing_ctrl_16bit/delay_cnt[6] , + \u_i2c_timing_ctrl_16bit/delay_cnt[7] , \u_i2c_timing_ctrl_16bit/delay_cnt[8] , + \u_i2c_timing_ctrl_16bit/delay_cnt[9] , \u_i2c_timing_ctrl_16bit/delay_cnt[10] , + \u_i2c_timing_ctrl_16bit/delay_cnt[11] , \u_i2c_timing_ctrl_16bit/delay_cnt[12] , + \u_i2c_timing_ctrl_16bit/delay_cnt[13] , \u_i2c_timing_ctrl_16bit/delay_cnt[14] , + \u_i2c_timing_ctrl_16bit/delay_cnt[15] , \u_i2c_timing_ctrl_16bit/delay_cnt[16] , + \u_i2c_timing_ctrl_16bit/delay_cnt[17] , \u_i2c_timing_ctrl_16bit/delay_cnt[18] , + \u_i2c_timing_ctrl_16bit/delay_cnt[19] , \u_axi4_ctrl/dff_138/i10_rst_7 , + n3754, n3755, \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0] , n3757, + n3758, \u_i2c_timing_ctrl_16reg_16bit/current_state[0] , \u_i2c_timing_ctrl_16reg_16bit/i2c_ctrl_clk , + \u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en , \ar0135_i2c_config_index[0] , + n3764, n3765, \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15] , \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14] , + \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13] , \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12] , + \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11] , \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10] , + \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9] , \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8] , + \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7] , \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6] , + \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5] , \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4] , + \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3] , \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2] , + \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1] , \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0] , + \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0] , \u_i2c_timing_ctrl_16reg_16bit/i2c_ack5 , + \u_i2c_timing_ctrl_16reg_16bit/i2c_ack4 , \u_i2c_timing_ctrl_16reg_16bit/i2c_ack3 , + \u_i2c_timing_ctrl_16reg_16bit/i2c_ack2 , \u_i2c_timing_ctrl_16reg_16bit/i2c_ack1 , + \u_i2c_timing_ctrl_16reg_16bit/i2c_ack , \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0] , + \u_i2c_timing_ctrl_16reg_16bit/current_state[1] , \u_i2c_timing_ctrl_16reg_16bit/current_state[2] , + \u_i2c_timing_ctrl_16reg_16bit/current_state[3] , \u_i2c_timing_ctrl_16reg_16bit/current_state[4] , + \ar0135_i2c_config_index[1] , \ar0135_i2c_config_index[2] , \ar0135_i2c_config_index[3] , + \ar0135_i2c_config_index[4] , \ar0135_i2c_config_index[5] , \ar0135_i2c_config_index[6] , + \ar0135_i2c_config_index[7] , \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1] , + \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2] , \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3] , + \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1] , \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2] , + \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3] , \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4] , + \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5] , \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6] , + \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7] , \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1] , + \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2] , \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3] , + \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4] , \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5] , + \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6] , \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7] , + \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8] , \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9] , + \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10] , \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11] , + \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12] , \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13] , + \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14] , \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15] , + \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16] , \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17] , + \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18] , \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19] , + \r_cmos_fv_o[0] , \r_cmos_fv_o[1] , \r_cmos_fv_o[2] , n3844, + n3845, \dsi_pwm/rc_pwm[0] , \dsi_pwm/rc_pwm[1] , \dsi_pwm/rc_pwm[2] , + \dsi_pwm/rc_pwm[3] , \dsi_pwm/rc_pwm[4] , \dsi_pwm/rc_pwm[5] , + \dsi_pwm/rc_pwm[6] , \u_Sensor_Image_XYCrop/image_ypos[11] , \u_Sensor_Image_XYCrop/image_ypos[10] , + \u_Sensor_Image_XYCrop/image_ypos[9] , \u_Sensor_Image_XYCrop/image_ypos[0] , + \u_Sensor_Image_XYCrop/image_ypos[8] , \u_Sensor_Image_XYCrop/image_ypos[7] , + \XYCrop_frame_Gray[5] , \u_Sensor_Image_XYCrop/image_ypos[6] , \u_Sensor_Image_XYCrop/image_ypos[5] , + n3864, n3865, \u_Sensor_Image_XYCrop/image_xpos[0] , \XYCrop_frame_Gray[3] , + \u_Sensor_Image_XYCrop/image_ypos[4] , \u_Sensor_Image_XYCrop/image_ypos[3] , + \XYCrop_frame_Gray[4] , \u_Sensor_Image_XYCrop/image_ypos[2] , n3872, + n3873, \u_Sensor_Image_XYCrop/image_ypos[1] , \XYCrop_frame_Gray[6] , + \XYCrop_frame_Gray[7] , \XYCrop_frame_Gray[2] , \XYCrop_frame_Gray[1] , + \u_Sensor_Image_XYCrop/image_xpos[1] , \u_Sensor_Image_XYCrop/image_xpos[2] , + \u_Sensor_Image_XYCrop/image_xpos[3] , \u_Sensor_Image_XYCrop/image_xpos[4] , + \u_Sensor_Image_XYCrop/image_xpos[5] , \u_Sensor_Image_XYCrop/image_xpos[6] , + \u_Sensor_Image_XYCrop/image_xpos[7] , \u_Sensor_Image_XYCrop/image_xpos[8] , + \u_Sensor_Image_XYCrop/image_xpos[9] , \u_Sensor_Image_XYCrop/image_xpos[10] , + \u_Sensor_Image_XYCrop/image_xpos[11] , \r_XYCrop_frame_Gray[1] , + \r_XYCrop_frame_Gray[2] , \r_XYCrop_frame_Gray[3] , \r_XYCrop_frame_Gray[4] , + \r_XYCrop_frame_Gray[5] , \r_XYCrop_frame_Gray[6] , \r_XYCrop_frame_Gray[7] , + \w_ddr3_araddr[22] , \u_axi4_ctrl/r_wframe_index_last[0] , n3905, + n3906, \u_axi4_ctrl/r_wframe_sync[0] , \u_axi4_ctrl/rc_w_eof[0] , + \u_axi4_ctrl/r_wframe_index_last[1] , w_ddr3_awvalid, \u_axi4_ctrl/rc_burst[0] , + \u_axi4_ctrl/r_weof_pending , \u_axi4_ctrl/r_wframe_inc , \u_axi4_ctrl/rframe_vsync_dly , + n3918, n3919, \u_axi4_ctrl/rfifo_cnt[0] , \u_axi4_ctrl/rfifo_rst , + \u_axi4_ctrl/rfifo_wr_rst_busy_dly[0] , \u_axi4_ctrl/rd_state[0] , + w_ddr3_arvalid, \u_axi4_ctrl/r_rd_pend , \u_axi4_ctrl/rfifo_wenb , + \w_ddr3_araddr[23] , \u_axi4_ctrl/r_w_rst , \w_ddr3_awaddr[4] , + \w_ddr3_awaddr[5] , \w_ddr3_awaddr[6] , \w_ddr3_awaddr[7] , \w_ddr3_awaddr[8] , + \w_ddr3_awaddr[9] , \w_ddr3_awaddr[10] , \w_ddr3_awaddr[11] , + \w_ddr3_awaddr[12] , \w_ddr3_awaddr[13] , \w_ddr3_awaddr[14] , + \w_ddr3_awaddr[15] , \w_ddr3_awaddr[16] , \w_ddr3_awaddr[17] , + \w_ddr3_awaddr[18] , \w_ddr3_awaddr[19] , \w_ddr3_awaddr[20] , + \w_ddr3_awaddr[21] , \u_axi4_ctrl/r_wframe_sync[1] , \u_axi4_ctrl/rc_burst[1] , + \u_axi4_ctrl/rc_burst[2] , \u_axi4_ctrl/rc_burst[3] , \u_axi4_ctrl/rc_burst[4] , + \u_axi4_ctrl/rc_burst[5] , \u_axi4_ctrl/rc_burst[6] , \u_axi4_ctrl/rc_burst[7] , + n4064, n4065, \u_axi4_ctrl/w_wfifo_empty , n4099, n4100, \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] , + n4102, n4103, \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[0] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[0] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[0] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] , \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2] , \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] , \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] , \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] , \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] , \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] , \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13] , + n4122, n4123, n4124, \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] , \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] , \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] , \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] , \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[12] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[13] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i38_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i21_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i22_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i23_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i24_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i25_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i26_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i27_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i28_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i29_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_0 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_1 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_2 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_3 , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i33_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i34_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i35_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i36_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i37_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i39_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i40_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i41_pre , + \u_axi4_ctrl/rfifo_cnt[1] , \u_axi4_ctrl/rfifo_cnt[2] , \u_axi4_ctrl/rfifo_cnt[3] , + \u_axi4_ctrl/rfifo_cnt[4] , n4222, n4223, n4225, n4226, \u_axi4_ctrl/w_rfifo_empty , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] , n4230, + n4231, \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] , + n4234, \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[0] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[0] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] , \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] , \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] , \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] , \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1] , \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3] , \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] , \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] , \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] , \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] , \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[13] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[13] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i33_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i34_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i35_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i36_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i37_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i38_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i39_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i40_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i41_pre , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i21_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i22_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i23_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i24_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i25_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i26_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i27_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i28_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i29_pre , + \u_axi4_ctrl/rfifo_wr_rst_busy_dly[1] , \u_axi4_ctrl/dff_138/i15_rst_4 , + \u_axi4_ctrl/dff_138/i15_pre , \u_axi4_ctrl/rfifo_wr_rst_busy_dly[15] , + n4351, n4352, \u_axi4_ctrl/rd_state[1] , \w_ddr3_araddr[11] , + \w_ddr3_araddr[12] , \w_ddr3_araddr[13] , \w_ddr3_araddr[14] , + \w_ddr3_araddr[15] , \w_ddr3_araddr[16] , \w_ddr3_araddr[17] , + \w_ddr3_araddr[18] , \w_ddr3_araddr[19] , \w_ddr3_araddr[20] , + \w_ddr3_araddr[21] , \u_axi4_ctrl/rfifo_wdata[0] , \u_axi4_ctrl/rfifo_wdata[1] , + \u_axi4_ctrl/rfifo_wdata[2] , \u_axi4_ctrl/rfifo_wdata[3] , \u_axi4_ctrl/rfifo_wdata[4] , + \u_axi4_ctrl/rfifo_wdata[5] , \u_axi4_ctrl/rfifo_wdata[6] , \u_axi4_ctrl/rfifo_wdata[7] , + \u_axi4_ctrl/rfifo_wdata[8] , \u_axi4_ctrl/rfifo_wdata[9] , \u_axi4_ctrl/rfifo_wdata[10] , + \u_axi4_ctrl/rfifo_wdata[11] , \u_axi4_ctrl/rfifo_wdata[12] , \u_axi4_ctrl/rfifo_wdata[13] , + \u_axi4_ctrl/rfifo_wdata[14] , \u_axi4_ctrl/rfifo_wdata[15] , \u_axi4_ctrl/rfifo_wdata[16] , + \u_axi4_ctrl/rfifo_wdata[17] , \u_axi4_ctrl/rfifo_wdata[18] , \u_axi4_ctrl/rfifo_wdata[19] , + \u_axi4_ctrl/rfifo_wdata[20] , \u_axi4_ctrl/rfifo_wdata[21] , \u_axi4_ctrl/rfifo_wdata[22] , + \u_axi4_ctrl/rfifo_wdata[23] , \u_axi4_ctrl/rfifo_wdata[24] , \u_axi4_ctrl/rfifo_wdata[25] , + \u_axi4_ctrl/rfifo_wdata[26] , \u_axi4_ctrl/rfifo_wdata[27] , \u_axi4_ctrl/rfifo_wdata[28] , + \u_axi4_ctrl/rfifo_wdata[29] , \u_axi4_ctrl/rfifo_wdata[30] , \u_axi4_ctrl/rfifo_wdata[31] , + \u_axi4_ctrl/rfifo_wdata[32] , \u_axi4_ctrl/rfifo_wdata[33] , \u_axi4_ctrl/rfifo_wdata[34] , + \u_axi4_ctrl/rfifo_wdata[35] , \u_axi4_ctrl/rfifo_wdata[36] , \u_axi4_ctrl/rfifo_wdata[37] , + \u_axi4_ctrl/rfifo_wdata[38] , \u_axi4_ctrl/rfifo_wdata[39] , \u_axi4_ctrl/rfifo_wdata[40] , + \u_axi4_ctrl/rfifo_wdata[41] , \u_axi4_ctrl/rfifo_wdata[42] , \u_axi4_ctrl/rfifo_wdata[43] , + \u_axi4_ctrl/rfifo_wdata[44] , \u_axi4_ctrl/rfifo_wdata[45] , \u_axi4_ctrl/rfifo_wdata[46] , + \u_axi4_ctrl/rfifo_wdata[47] , \u_axi4_ctrl/rfifo_wdata[48] , \u_axi4_ctrl/rfifo_wdata[49] , + \u_axi4_ctrl/rfifo_wdata[50] , \u_axi4_ctrl/rfifo_wdata[51] , \u_axi4_ctrl/rfifo_wdata[52] , + \u_axi4_ctrl/rfifo_wdata[53] , \u_axi4_ctrl/rfifo_wdata[54] , \u_axi4_ctrl/rfifo_wdata[55] , + \u_axi4_ctrl/rfifo_wdata[56] , \u_axi4_ctrl/rfifo_wdata[57] , \u_axi4_ctrl/rfifo_wdata[58] , + \u_axi4_ctrl/rfifo_wdata[59] , \u_axi4_ctrl/rfifo_wdata[60] , \u_axi4_ctrl/rfifo_wdata[61] , + \u_axi4_ctrl/rfifo_wdata[62] , \u_axi4_ctrl/rfifo_wdata[63] , \u_axi4_ctrl/rfifo_wdata[64] , + \u_axi4_ctrl/rfifo_wdata[65] , \u_axi4_ctrl/rfifo_wdata[66] , \u_axi4_ctrl/rfifo_wdata[67] , + \u_axi4_ctrl/rfifo_wdata[68] , \u_axi4_ctrl/rfifo_wdata[69] , \u_axi4_ctrl/rfifo_wdata[70] , + \u_axi4_ctrl/rfifo_wdata[71] , \u_axi4_ctrl/rfifo_wdata[72] , \u_axi4_ctrl/rfifo_wdata[73] , + \u_axi4_ctrl/rfifo_wdata[74] , \u_axi4_ctrl/rfifo_wdata[75] , \u_axi4_ctrl/rfifo_wdata[76] , + \u_axi4_ctrl/rfifo_wdata[77] , \u_axi4_ctrl/rfifo_wdata[78] , \u_axi4_ctrl/rfifo_wdata[79] , + \u_axi4_ctrl/rfifo_wdata[80] , \u_axi4_ctrl/rfifo_wdata[81] , \u_axi4_ctrl/rfifo_wdata[82] , + \u_axi4_ctrl/rfifo_wdata[83] , \u_axi4_ctrl/rfifo_wdata[84] , \u_axi4_ctrl/rfifo_wdata[85] , + \u_axi4_ctrl/rfifo_wdata[86] , \u_axi4_ctrl/rfifo_wdata[87] , \u_axi4_ctrl/rfifo_wdata[88] , + \u_axi4_ctrl/rfifo_wdata[89] , \u_axi4_ctrl/rfifo_wdata[90] , \u_axi4_ctrl/rfifo_wdata[91] , + \u_axi4_ctrl/rfifo_wdata[92] , \u_axi4_ctrl/rfifo_wdata[93] , \u_axi4_ctrl/rfifo_wdata[94] , + \u_axi4_ctrl/rfifo_wdata[95] , \u_axi4_ctrl/rfifo_wdata[96] , \u_axi4_ctrl/rfifo_wdata[97] , + \u_axi4_ctrl/rfifo_wdata[98] , \u_axi4_ctrl/rfifo_wdata[99] , \u_axi4_ctrl/rfifo_wdata[100] , + \u_axi4_ctrl/rfifo_wdata[101] , \u_axi4_ctrl/rfifo_wdata[102] , + \u_axi4_ctrl/rfifo_wdata[103] , \u_axi4_ctrl/rfifo_wdata[104] , + \u_axi4_ctrl/rfifo_wdata[105] , \u_axi4_ctrl/rfifo_wdata[106] , + \u_axi4_ctrl/rfifo_wdata[107] , \u_axi4_ctrl/rfifo_wdata[108] , + \u_axi4_ctrl/rfifo_wdata[109] , \u_axi4_ctrl/rfifo_wdata[110] , + \u_axi4_ctrl/rfifo_wdata[111] , \u_axi4_ctrl/rfifo_wdata[112] , + \u_axi4_ctrl/rfifo_wdata[113] , \u_axi4_ctrl/rfifo_wdata[114] , + \u_axi4_ctrl/rfifo_wdata[115] , \u_axi4_ctrl/rfifo_wdata[116] , + \u_axi4_ctrl/rfifo_wdata[117] , \u_axi4_ctrl/rfifo_wdata[118] , + \u_axi4_ctrl/rfifo_wdata[119] , \u_axi4_ctrl/rfifo_wdata[120] , + \u_axi4_ctrl/rfifo_wdata[121] , \u_axi4_ctrl/rfifo_wdata[122] , + \u_axi4_ctrl/rfifo_wdata[123] , \u_axi4_ctrl/rfifo_wdata[124] , + \u_axi4_ctrl/rfifo_wdata[125] , \u_axi4_ctrl/rfifo_wdata[126] , + \u_axi4_ctrl/rfifo_wdata[127] , n4503, n4504, \u_lcd_driver/vcnt[0] , + lcd_hs, lcd_de, lcd_request, \u_lcd_driver/hcnt[0] , \u_lcd_driver/vcnt[1] , + \u_lcd_driver/vcnt[2] , \u_lcd_driver/vcnt[3] , \u_lcd_driver/vcnt[4] , + \u_lcd_driver/vcnt[5] , \u_lcd_driver/vcnt[6] , \u_lcd_driver/vcnt[7] , + \u_lcd_driver/vcnt[8] , \u_lcd_driver/vcnt[9] , \u_lcd_driver/vcnt[10] , + \u_lcd_driver/vcnt[11] , \u_lcd_driver/r_lcd_rgb[0] , \u_lcd_driver/r_lcd_rgb[1] , + \u_lcd_driver/r_lcd_rgb[2] , \u_lcd_driver/r_lcd_rgb[3] , \u_lcd_driver/r_lcd_rgb[4] , + \u_lcd_driver/r_lcd_rgb[5] , \u_lcd_driver/r_lcd_rgb[6] , \u_lcd_driver/r_lcd_rgb[7] , + \u_lcd_driver/hcnt[1] , \u_lcd_driver/hcnt[2] , \u_lcd_driver/hcnt[3] , + \u_lcd_driver/hcnt[4] , \u_lcd_driver/hcnt[5] , \u_lcd_driver/hcnt[6] , + \u_lcd_driver/hcnt[7] , \u_lcd_driver/hcnt[8] , \u_lcd_driver/hcnt[9] , + \u_lcd_driver/hcnt[10] , \u_lcd_driver/hcnt[11] , \u_lcd_driver/hcnt[12] , + \u_lcd_driver/hcnt[13] , n4543, n4544, \u_rgb2dvi/enc_0/acc[0] , + \u_rgb2dvi/enc_0/acc[1] , \u_rgb2dvi/enc_0/acc[2] , \u_rgb2dvi/enc_0/acc[3] , + \u_rgb2dvi/enc_0/acc[4] , n4560, n4561, \u_rgb2dvi/enc_1/acc[0] , + n4564, n4565, \u_rgb2dvi/enc_1/acc[1] , \u_rgb2dvi/enc_1/acc[2] , + \u_rgb2dvi/enc_1/acc[3] , \u_rgb2dvi/enc_1/acc[4] , n4579, n4580, + \u_rgb2dvi/enc_2/acc[0] , n4583, n4584, n4585, n4586, \u_rgb2dvi/enc_2/acc[1] , + \u_rgb2dvi/enc_2/acc[2] , \u_rgb2dvi/enc_2/acc[3] , \u_rgb2dvi/enc_2/acc[4] , + n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606, + n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, + n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, + n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, + n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638, + n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646, + n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, + n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, + n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, + n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678, + n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4693, + n4694, n4695, n4697, n4699, n4701, n4703, n4705, n4707, + n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716, + n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, + n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, + n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, + n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748, + n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756, + n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, + n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, + n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, + n4781, n4782, n4783, n4784, n4785, n4786, n4787, n4788, + n4789, n4790, n4791, n4792, n4793, n4794, n4795, n4796, + n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, + n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812, + n4813, n4814, n4815, n4816, n4817, n4818, n4832, n4833, + n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, + n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, + n4850, n4851, n4852, n4853, n4854, n4855, n4856, n4857, + n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865, + n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, + n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, + n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, + n4890, n4891, n4892, n4893, n4894, n4895, n4896, n4897, + n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905, + n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, + n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, + n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, + n4930, n4931, n4932, n4933, n4934, n4935, n4936, n4937, + n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945, + n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, + n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, + n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969, + n4970, n4971, n4972, n4973, n4974, n4975, n4976, n4977, + n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985, + n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, + n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, + n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009, + n5010, n5011, n5012, n5013, n5014, n5015, n5016, n5017, + n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025, + n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, + n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, + n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049, + n5050, n5051, n5052, n5053, n5054, n5055, n5056, n5057, + n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065, + n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, + n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, + n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089, + n5090, n5091, n5092, n5093, n5094, n5095, n5096, n5097, + n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105, + n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, + n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, + n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129, + n5130, n5131, n5132, n5133, n5134, n5135, n5136, n5137, + n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145, + n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, + n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, + n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169, + n5170, n5171, n5172, n5173, n5174, n5175, n5176, n5177, + n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185, + n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, + n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, + n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209, + n5210, n5211, n5212, n5213, n5214, n5215, n5216, n5217, + n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225, + n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, + n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, + n5242, n5243, n5244, n5245, n5246, n5248, n5249, n5250, + n5251, n5252, n5253, n5254, n5255, n5256, n5257, n5258, + n5259, n5260, n5261, n5262, n5263, n5264, n5265, n5266, + n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, + n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282, + n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, + n5291, n5292, n5293, n5294, n5295, n5297, n5298, n5299, + n5300, n5301, n5302, n5303, n5304, n5305, n5306, n5307, + n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315, + n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, + n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, + n5332, n5333, n5334, n5335, n5336, n5337, n5338, n5339, + n5340, n5341, n5342, n5343, n5344, n5345, n5346, n5347, + n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355, + n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, + n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, + n5372, n5373, n5374, n5375, n5376, n5377, n5378, n5379, + n5380, n5381, n5382, n5383, n5384, n5385, n5386, n5387, + n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395, + n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, + n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, + n5412, n5413, n5414, n5415, n5416, n5417, n5418, n5419, + n5420, n5421, n5422, n5423, n5424, n5425, n5426, n5427, + n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435, + n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, + n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, + n5452, n5453, n5454, n5455, n5456, n5457, n5458, n5459, + n5460, n5461, n5462, n5463, n5464, n5465, n5466, n5467, + n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475, + n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, + n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, + n5492, n5493, n5494, n5495, n5496, n5497, n5498, n5499, + n5500, n5501, n5502, n5503, n5504, n5505, n5506, n5507, + n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515, + n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, + n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, + n5532, n5533, n5534, n5535, n5536, n5537, n5538, n5539, + n5540, n5541, n5542, n5543, n5544, n5545, n5546, n5547, + n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555, + n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, + n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, + n5572, n5573, n5574, n5575, n5576, n5577, n5578, n5579, + n5580, n5581, n5582, n5583, n5584, n5585, n5586, n5587, + n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595, + n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, + n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, + n5612, n5613, n5614, n5615, n5616, n5617, n5618, n5619, + n5620, n5621, n5622, n5623, n5624, n5625, n5626, n5627, + n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635, + n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, + n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, + n5652, n5653, n5654, n5655, n5656, n5657, n5658, n5659, + n5660, n5661, n5694, n5696, n5697, n5698, n5699, n5700, + n5701, n5702, n5703, n5704, n5705, n5706, n5707, n5708, + n5709, n5710, n5711, n5712, n5713, n5714, n5715, n5716, + n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, + n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, + n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, + n5741, n5742, n5743, n5744, n5745, n5746, n5747, n5753, + n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762, + n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770, + n5771, n5772, n5773, n5774, n5775, n5776, n5777, n5778, + n5779, n5780, n5781, n5782, n5783, n5784, n5785, n5786, + n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, + n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802, + n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810, + n5811, n5812, n5813, n5814, n5815, n5816, n5817, n5818, + n5819, n5820, n5821, n5822, n5823, n5824, n5825, n5826, + n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, + n5835, w_pll_lock, w_ddr3_cal_done, XYCrop_frame_vsync, \XYCrop_frame_Gray[0] , + XYCrop_frame_href, XYCrop_frame_de, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1263 , + ceg_net2, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1004 , + ceg_net5, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1037 , + ceg_net539, \w_ddr3_wdata[0] , \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1089 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1071 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1193 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_fifo_aw[40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_i_arburst_fifo[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1378 , + ceg_net376, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1054 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n95 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1090 , + w_ddr3_wready, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_fifo_rd_en , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_i_awvalid , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n572 , + ceg_net2477, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1088 , + ceg_net541, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/not_equal_72/n31 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1337 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n111 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1262 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1261 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1260 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1259 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1258 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1257 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1256 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1255 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1254 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1253 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1252 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1251 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1250 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1249 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1248 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1247 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1246 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1245 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1244 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1243 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1242 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1241 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1240 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1239 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1238 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1237 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1236 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1235 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1003 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1002 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1001 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1000 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n999 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n998 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n997 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n996 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n995 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n994 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n993 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n992 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n991 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n990 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n989 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n988 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n987 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n986 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n985 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n984 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n983 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n982 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n981 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n980 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n979 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n978 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n977 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n976 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1036 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1035 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1034 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1033 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1032 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1031 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1030 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1029 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1028 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1027 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1026 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1025 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1024 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1023 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1022 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1021 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1020 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1019 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1018 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1017 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1016 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1015 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1014 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1013 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1012 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1011 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1010 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1009 , + \w_ddr3_wdata[1] , \w_ddr3_wdata[2] , \w_ddr3_wdata[3] , \w_ddr3_wdata[4] , + \w_ddr3_wdata[5] , \w_ddr3_wdata[6] , \w_ddr3_wdata[7] , \w_ddr3_wdata[8] , + \w_ddr3_wdata[9] , \w_ddr3_wdata[10] , \w_ddr3_wdata[11] , \w_ddr3_wdata[12] , + \w_ddr3_wdata[13] , \w_ddr3_wdata[14] , \w_ddr3_wdata[15] , \w_ddr3_wdata[16] , + \w_ddr3_wdata[17] , \w_ddr3_wdata[18] , \w_ddr3_wdata[19] , \w_ddr3_wdata[20] , + \w_ddr3_wdata[21] , \w_ddr3_wdata[22] , \w_ddr3_wdata[23] , \w_ddr3_wdata[24] , + \w_ddr3_wdata[25] , \w_ddr3_wdata[26] , \w_ddr3_wdata[27] , \w_ddr3_wdata[28] , + \w_ddr3_wdata[29] , \w_ddr3_wdata[30] , \w_ddr3_wdata[31] , \w_ddr3_wdata[32] , + \w_ddr3_wdata[33] , \w_ddr3_wdata[34] , \w_ddr3_wdata[35] , \w_ddr3_wdata[36] , + \w_ddr3_wdata[37] , \w_ddr3_wdata[38] , \w_ddr3_wdata[39] , \w_ddr3_wdata[40] , + \w_ddr3_wdata[41] , \w_ddr3_wdata[42] , \w_ddr3_wdata[43] , \w_ddr3_wdata[44] , + \w_ddr3_wdata[45] , \w_ddr3_wdata[46] , \w_ddr3_wdata[47] , \w_ddr3_wdata[48] , + \w_ddr3_wdata[49] , \w_ddr3_wdata[50] , \w_ddr3_wdata[51] , \w_ddr3_wdata[52] , + \w_ddr3_wdata[53] , \w_ddr3_wdata[54] , \w_ddr3_wdata[55] , \w_ddr3_wdata[56] , + \w_ddr3_wdata[57] , \w_ddr3_wdata[58] , \w_ddr3_wdata[59] , \w_ddr3_wdata[60] , + \w_ddr3_wdata[61] , \w_ddr3_wdata[62] , \w_ddr3_wdata[63] , \w_ddr3_wdata[64] , + \w_ddr3_wdata[65] , \w_ddr3_wdata[66] , \w_ddr3_wdata[67] , \w_ddr3_wdata[68] , + \w_ddr3_wdata[69] , \w_ddr3_wdata[70] , \w_ddr3_wdata[71] , \w_ddr3_wdata[72] , + \w_ddr3_wdata[73] , \w_ddr3_wdata[74] , \w_ddr3_wdata[75] , \w_ddr3_wdata[76] , + \w_ddr3_wdata[77] , \w_ddr3_wdata[78] , \w_ddr3_wdata[79] , \w_ddr3_wdata[80] , + \w_ddr3_wdata[81] , \w_ddr3_wdata[82] , \w_ddr3_wdata[83] , \w_ddr3_wdata[84] , + \w_ddr3_wdata[85] , \w_ddr3_wdata[86] , \w_ddr3_wdata[87] , \w_ddr3_wdata[88] , + \w_ddr3_wdata[89] , \w_ddr3_wdata[90] , \w_ddr3_wdata[91] , \w_ddr3_wdata[92] , + \w_ddr3_wdata[93] , \w_ddr3_wdata[94] , \w_ddr3_wdata[95] , \w_ddr3_wdata[96] , + \w_ddr3_wdata[97] , \w_ddr3_wdata[98] , \w_ddr3_wdata[99] , \w_ddr3_wdata[100] , + \w_ddr3_wdata[101] , \w_ddr3_wdata[102] , \w_ddr3_wdata[103] , + \w_ddr3_wdata[104] , \w_ddr3_wdata[105] , \w_ddr3_wdata[106] , + \w_ddr3_wdata[107] , \w_ddr3_wdata[108] , \w_ddr3_wdata[109] , + \w_ddr3_wdata[110] , \w_ddr3_wdata[111] , \w_ddr3_wdata[112] , + \w_ddr3_wdata[113] , \w_ddr3_wdata[114] , \w_ddr3_wdata[115] , + \w_ddr3_wdata[116] , \w_ddr3_wdata[117] , \w_ddr3_wdata[118] , + \w_ddr3_wdata[119] , \w_ddr3_wdata[120] , \w_ddr3_wdata[121] , + \w_ddr3_wdata[122] , \w_ddr3_wdata[123] , \w_ddr3_wdata[124] , + \w_ddr3_wdata[125] , \w_ddr3_wdata[126] , \w_ddr3_wdata[127] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1070 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1069 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1068 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1067 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1066 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1065 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1064 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1063 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1062 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1061 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1060 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1059 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1058 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1057 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1056 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_fifo_aw[41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_i_arburst_fifo[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1377 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1376 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1375 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1374 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1373 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1372 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1371 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1370 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1053 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1052 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n571 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n570 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n569 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n568 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n567 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n566 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n565 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n564 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n563 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n562 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n561 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n560 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n559 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n558 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n557 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1087 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1086 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1085 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1084 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1083 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1082 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1081 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1080 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1079 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1078 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1077 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1076 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1075 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1074 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1073 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/equal_40/n11 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n332 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n49 , + ceg_net577, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n48 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n47 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n46 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n45 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n44 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/equal_40/n11 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n860 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n73 , + ceg_net595, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n72 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n71 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n70 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n69 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n68 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][19] , + \axi4_awar_mux/n14 , \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/equal_40/n11 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n1212 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n89 , + ceg_net649, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n88 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n87 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n86 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n85 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n84 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/equal_40/n11 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n332 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n49 , + ceg_net685, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n48 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n47 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n46 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n45 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n44 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/equal_40/n11 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n332 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n49 , + ceg_net721, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n48 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n47 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n46 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n45 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n44 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/equal_40/n11 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Fifo_Wr_En , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n332 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n49 , + ceg_net739, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n48 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n47 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n46 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n45 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n44 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/equal_40/n11 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n332 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n49 , + ceg_net793, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n48 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n47 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n46 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n45 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n44 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/equal_40/n11 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n332 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n49 , + ceg_net811, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n48 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n47 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n46 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n45 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n44 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/equal_40/n11 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n332 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n49 , + ceg_net847, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n48 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n47 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n46 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n45 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n44 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done , + n8257, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2698 , + ceg_net4213, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7743 , + ceg_net3077, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8147 , + ceg_net879, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1742 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9160 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7719 , + ceg_net3886, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n3461 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n3529 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2838 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2896 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8144 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2863 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8304 , + ceg_net886, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7076 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2398 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2589 , + ceg_net894, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2554 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2631 , + ceg_net917, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2673 , + ceg_net930, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7690 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8321 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7686 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2839 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n735 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n714 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n715 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n716 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n717 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n718 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n739 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n740 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n713 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 , + n8360, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n442 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n447 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n452 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n457 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n462 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n467 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n293 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n292 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n291 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n290 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n289 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n477 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n482 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n487 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n492 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n497 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n502 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n335 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n334 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n333 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n332 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n331 , + n8436, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 , + n8472, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n442 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n447 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n452 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n457 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n462 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n293 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n292 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n291 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n290 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n289 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n467 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n477 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n482 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n487 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n492 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n497 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n502 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n335 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n334 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n333 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n332 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n331 , + n8547, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 , + n8583, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1002 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1007 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1012 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1017 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1022 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1027 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n741 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n740 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n739 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n738 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n737 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1037 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1042 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1047 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1052 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1057 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1062 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n783 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n782 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n781 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n780 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n779 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[48] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[52] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[64] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[65] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[68] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[69] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[70] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[71] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[72] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[73] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[74] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[75] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[76] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[77] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[78] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[79] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[80] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[81] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[82] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[83] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[84] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[85] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[86] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[87] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[88] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[89] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[90] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[91] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[92] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[93] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[94] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[95] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[96] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[97] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[98] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[99] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[100] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[101] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[102] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[103] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[104] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[105] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[106] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[107] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[108] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[109] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[110] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[111] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[112] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[113] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[114] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[115] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[116] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[117] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[118] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[119] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[120] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[121] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[122] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[123] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[124] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[125] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[126] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[127] , + n8791, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[32] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n308 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n303 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n298 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n293 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n288 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n283 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5] , + n8862, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n166 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n165 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n164 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n163 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n162 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n318 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n323 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n328 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n333 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n338 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n343 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n208 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n207 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n206 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n205 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n204 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n922 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n927 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n932 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n937 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n942 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6] , + n8961, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n677 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n676 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n675 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n674 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n673 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n947 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n957 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n962 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n967 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n972 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n977 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n982 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n719 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n718 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n717 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n716 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n715 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n317 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n312 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n307 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n302 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n297 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n292 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n173 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n172 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n171 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n170 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n169 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n327 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n332 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n337 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n342 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n347 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n352 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n215 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n214 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n213 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n212 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n211 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n542 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n547 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n552 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n557 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n562 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n567 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n373 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n372 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n371 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n370 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n369 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n577 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n582 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n587 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n592 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n597 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n602 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n415 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n414 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n413 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n412 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n411 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n734 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n733 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n732 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n731 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n730 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n729 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n728 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n727 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n726 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n725 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n724 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n723 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n722 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n721 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n720 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n738 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n737 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst , + ceg_net932, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_0 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1626 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1625 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1624 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1623 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1622 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1621 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1620 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1619 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1618 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1617 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1616 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1615 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1614 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1613 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1612 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1646 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8136 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1650 , + ceg_net938, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1649 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2553 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1643 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1642 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1641 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1640 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1639 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1638 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1637 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1636 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1635 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1634 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1633 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1632 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1631 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1630 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1629 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1521 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][82] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][83] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][84] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][85] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][86] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][87] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][88] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][89] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][90] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][91] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][92] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][93] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][94] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][95] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][96] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][97] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][98] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][99] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][100] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][101] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][102] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][103] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][104] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][105] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][106] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][107] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][108] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][109] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][110] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][111] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][112] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][113] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][114] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][115] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][116] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][117] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][118] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][119] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][120] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][121] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][122] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][123] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][124] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][125] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][126] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][127] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][15] , + \u_axi4_ctrl/r_rfifo_rst , \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_2 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_1 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_0 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_7 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_rd_fifo_wr_en_p[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1512 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][97] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][98] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][99] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][100] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][101] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][102] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][103] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][104] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][105] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][106] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][107] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][108] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][109] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][110] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][111] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][112] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][113] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][114] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][115] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][116] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][117] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][118] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][119] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][120] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][121] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][122] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][123] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][124] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][125] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][126] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][127] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][32] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][48] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][52] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][64] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][65] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][68] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][69] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][70] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][71] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][72] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][73] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][74] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][75] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][76] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][77] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][78] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][79] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][80] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][81] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][32] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][48] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][52] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][64] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][65] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][68] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][69] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][70] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][71] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][72] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][73] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][74] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][75] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][76] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][77] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][78] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][79] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][80] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][81] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][82] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][83] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][84] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][85] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][86] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][87] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][88] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][89] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][90] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][91] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][92] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][93] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][94] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][95] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][96] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_2 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2471 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1502 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2472 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1644 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1627 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1647 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/equal_1648/n7 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2072 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2185 , + ceg_net947, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2184 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2183 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2182 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2181 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2180 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2179 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2178 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2177 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2176 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2175 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2174 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2173 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2172 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2169 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2475 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2474 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2473 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8010 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2073 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2170 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2476 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1977 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4141 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2529 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1503 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2470 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2469 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2531 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2530 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4694 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4684 , + ceg_net4223, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4658 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4602 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8097 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_p , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4679 , + ceg_net1009, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_ack , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_ack , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4651 , + ceg_net1122, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[28] , + ceg_net1019, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8092 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8089 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3413 , + ceg_net1023, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3858 , + ceg_net2599, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 , + ceg_net1030, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8096 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4712 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3139 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4892 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4893 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cs_p , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ras_p , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cas_p , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_we_p , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3146 , + ceg_net1036, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3143 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3164 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p1 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cs_p , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8016 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ras_p , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cas_p , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_we_p , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3147 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3185 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3190 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[68] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[65] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3091 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[32] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3101 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2528 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2527 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2526 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2525 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2524 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2468 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2467 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2466 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2465 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2464 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2463 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2462 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2461 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2523 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2522 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2521 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2520 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2519 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2518 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2517 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2516 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1513 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4693 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4692 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4691 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4690 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4689 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4688 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4687 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4686 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4683 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4682 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3438 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3437 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3436 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4650 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4649 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4648 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4647 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4646 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4645 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4644 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3857 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3856 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3855 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3854 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3853 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3852 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3851 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3850 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3849 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3848 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3847 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3846 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3845 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3844 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3843 , + ceg_net2663, ceg_net2727, ceg_net2791, ceg_net2855, ceg_net2919, + ceg_net2983, ceg_net3047, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4728 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4727 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4726 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4725 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4724 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4723 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4722 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4721 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4720 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4719 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4718 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4717 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4716 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4715 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4714 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4711 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4710 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4709 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4708 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4707 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4706 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4705 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4704 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4703 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4702 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4701 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4700 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4699 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4698 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4697 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3331 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3330 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3329 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3328 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3327 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3326 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3325 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3324 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3323 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3322 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3321 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3320 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3319 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3318 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3317 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3138 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3137 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3136 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3135 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3134 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3133 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3132 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3131 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3130 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3129 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3128 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3127 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3126 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3125 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3124 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3142 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3141 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3163 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3162 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3161 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3160 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3159 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3158 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3157 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3156 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3155 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3154 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3153 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3152 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3151 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3150 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3149 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3184 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3183 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[48] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[52] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3090 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3089 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3088 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3087 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3086 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3085 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3084 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3083 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3082 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3061 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3060 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3059 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3058 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3057 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3056 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3100 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3099 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n45 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n44 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n43 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n42 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n41 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n40 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n39 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n38 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n37 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n36 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n35 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n34 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n33 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n32 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n31 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n55 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n50 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n43 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n97 , + ceg_net1790, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n54 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n53 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n52 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n42 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n41 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2697 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2696 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2695 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6308 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1658 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1652 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5630 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5637 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5644 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5651 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5658 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5665 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5672 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5679 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5686 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5693 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5700 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5707 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5714 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5721 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5728 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5735 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5742 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5749 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5756 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5763 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5770 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5777 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5784 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5791 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5798 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5805 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5812 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5819 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5826 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5833 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5840 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7726 , + ceg_net4402, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5847 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5854 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5861 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5868 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5875 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5882 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5889 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5896 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5903 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5910 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5917 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5924 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5931 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5938 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5945 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5952 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5959 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5966 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5973 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5980 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5987 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5994 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6001 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6008 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6015 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6022 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6029 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6036 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6043 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6050 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6057 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7737 , + ceg_net3459, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2837 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2836 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2835 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2834 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2833 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2832 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2831 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2830 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2829 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2828 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2827 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2826 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2825 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2824 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2823 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2822 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2821 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2820 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2819 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2818 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2817 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2816 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2815 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2814 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2813 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2812 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2811 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2810 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2809 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2808 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2807 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2895 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2894 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2893 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2892 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2891 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2890 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2889 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2888 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2887 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2886 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2885 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2884 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2883 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2882 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2881 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2880 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2879 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2878 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2877 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2876 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2875 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2874 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2873 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2872 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2871 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2870 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2869 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2868 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2867 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2866 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2865 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2862 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2693 , + ceg_net3510, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2692 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2691 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2397 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2396 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2395 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2394 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2393 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2392 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2391 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2588 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5447 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2553 , + ceg_net2135, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2630 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5457 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2672 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5469 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5542 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5546 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5550 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5530 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5534 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5538 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1336 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1335 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1334 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1333 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1332 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1331 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1330 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1329 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1328 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1327 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1326 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1325 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1324 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1323 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1322 , + \axi4_awar_mux/n50 , w_ddr3_atype, \axi4_awar_mux/n129 , \axi4_awar_mux/n52 , + \axi4_awar_mux/n45 , \axi4_awar_mux/n49 , \u_i2c_timing_ctrl_16bit/n137 , + \u_i2c_timing_ctrl_16bit/n138 , \u_i2c_timing_ctrl_16bit/n139 , + \u_i2c_timing_ctrl_16bit/n198 , \u_i2c_timing_ctrl_16bit/n497 , + \u_i2c_timing_ctrl_16bit/n333 , ceg_net2242, \u_i2c_timing_ctrl_16bit/n818 , + ceg_net4099, \u_i2c_timing_ctrl_16bit/n7 , \u_i2c_timing_ctrl_16bit/n328 , + ceg_net4409, \u_i2c_timing_ctrl_16bit/n136 , \u_i2c_timing_ctrl_16bit/n135 , + \u_i2c_timing_ctrl_16bit/n134 , \u_i2c_timing_ctrl_16bit/n133 , + \u_i2c_timing_ctrl_16bit/n132 , \u_i2c_timing_ctrl_16bit/n131 , + \u_i2c_timing_ctrl_16bit/n130 , \u_i2c_timing_ctrl_16bit/n129 , + \u_i2c_timing_ctrl_16bit/n128 , \u_i2c_timing_ctrl_16bit/n127 , + \u_i2c_timing_ctrl_16bit/n126 , \u_i2c_timing_ctrl_16bit/n125 , + \u_i2c_timing_ctrl_16bit/n124 , \u_i2c_timing_ctrl_16bit/n123 , + \u_i2c_timing_ctrl_16bit/n122 , \u_i2c_timing_ctrl_16bit/next_state[0] , + \u_i2c_timing_ctrl_16bit/next_state[1] , \u_i2c_timing_ctrl_16bit/next_state[2] , + \u_i2c_timing_ctrl_16bit/next_state[3] , \u_i2c_timing_ctrl_16bit/n197 , + \u_i2c_timing_ctrl_16bit/n196 , \u_i2c_timing_ctrl_16bit/n195 , + \u_i2c_timing_ctrl_16bit/n194 , \u_i2c_timing_ctrl_16bit/n193 , + \u_i2c_timing_ctrl_16bit/n192 , \u_i2c_timing_ctrl_16bit/n191 , + \u_i2c_timing_ctrl_16bit/n332 , \u_i2c_timing_ctrl_16bit/n331 , + \u_i2c_timing_ctrl_16bit/n330 , \u_i2c_timing_ctrl_16bit/n719 , + \u_i2c_timing_ctrl_16bit/n727 , \u_i2c_timing_ctrl_16bit/n735 , + \u_i2c_timing_ctrl_16bit/n743 , \u_i2c_timing_ctrl_16bit/n751 , + \u_i2c_timing_ctrl_16bit/n759 , \u_i2c_timing_ctrl_16bit/n767 , + \u_axi4_ctrl/dff_138/i10_rst_6 , \u_i2c_timing_ctrl_16reg_16bit/n137 , + \u_i2c_timing_ctrl_16reg_16bit/next_state[0] , \u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en , + \u_i2c_timing_ctrl_16reg_16bit/n138 , \u_i2c_timing_ctrl_16reg_16bit/n139 , + \u_i2c_timing_ctrl_16reg_16bit/n140 , \u_i2c_timing_ctrl_16reg_16bit/n205 , + \u_i2c_timing_ctrl_16reg_16bit/n846 , \u_axi4_ctrl/dff_138/i10_rst_5 , + \u_i2c_timing_ctrl_16reg_16bit/n122 , \u_i2c_timing_ctrl_16reg_16bit/n123 , + \u_i2c_timing_ctrl_16reg_16bit/n124 , \u_i2c_timing_ctrl_16reg_16bit/n125 , + \u_i2c_timing_ctrl_16reg_16bit/n126 , \u_i2c_timing_ctrl_16reg_16bit/n127 , + \u_i2c_timing_ctrl_16reg_16bit/n128 , \u_i2c_timing_ctrl_16reg_16bit/n129 , + \u_i2c_timing_ctrl_16reg_16bit/n130 , \u_i2c_timing_ctrl_16reg_16bit/n131 , + \u_i2c_timing_ctrl_16reg_16bit/n132 , \u_i2c_timing_ctrl_16reg_16bit/n133 , + \u_i2c_timing_ctrl_16reg_16bit/n134 , \u_i2c_timing_ctrl_16reg_16bit/n135 , + \u_i2c_timing_ctrl_16reg_16bit/n136 , \u_axi4_ctrl/dff_138/i10_rst_4 , + \u_axi4_ctrl/dff_138/i10_rst_3 , \u_axi4_ctrl/dff_138/i10_rst_2 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_6 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_5 , + \u_i2c_timing_ctrl_16reg_16bit/n500 , ceg_net4141, \u_i2c_timing_ctrl_16reg_16bit/n509 , + ceg_net4466, \u_i2c_timing_ctrl_16reg_16bit/n567 , \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_4 , + \u_i2c_timing_ctrl_16reg_16bit/n570 , \u_i2c_timing_ctrl_16reg_16bit/n573 , + \u_i2c_timing_ctrl_16reg_16bit/n576 , \u_i2c_timing_ctrl_16reg_16bit/n579 , + \u_i2c_timing_ctrl_16reg_16bit/n581 , \u_i2c_timing_ctrl_16reg_16bit/n7 , + \u_i2c_timing_ctrl_16reg_16bit/n495 , ceg_net4426, \u_i2c_timing_ctrl_16reg_16bit/next_state[1] , + \u_i2c_timing_ctrl_16reg_16bit/next_state[2] , \u_i2c_timing_ctrl_16reg_16bit/next_state[3] , + \u_i2c_timing_ctrl_16reg_16bit/next_state[4] , \u_i2c_timing_ctrl_16reg_16bit/n204 , + \u_i2c_timing_ctrl_16reg_16bit/n203 , \u_i2c_timing_ctrl_16reg_16bit/n202 , + \u_i2c_timing_ctrl_16reg_16bit/n201 , \u_i2c_timing_ctrl_16reg_16bit/n200 , + \u_i2c_timing_ctrl_16reg_16bit/n199 , \u_i2c_timing_ctrl_16reg_16bit/n198 , + \u_i2c_timing_ctrl_16reg_16bit/n499 , \u_i2c_timing_ctrl_16reg_16bit/n498 , + \u_i2c_timing_ctrl_16reg_16bit/n497 , \u_i2c_timing_ctrl_16reg_16bit/n508 , + \u_i2c_timing_ctrl_16reg_16bit/n507 , \u_i2c_timing_ctrl_16reg_16bit/n506 , + \u_i2c_timing_ctrl_16reg_16bit/n505 , \u_i2c_timing_ctrl_16reg_16bit/n504 , + \u_i2c_timing_ctrl_16reg_16bit/n503 , \u_i2c_timing_ctrl_16reg_16bit/n502 , + n1418, n1423, \dsi_pwm/n14 , \u_Sensor_Image_XYCrop/n55 , ceg_net2404, + \u_Sensor_Image_XYCrop/n56 , \u_Sensor_Image_XYCrop/n57 , \u_Sensor_Image_XYCrop/n66 , + \u_Sensor_Image_XYCrop/n58 , \u_Sensor_Image_XYCrop/n59 , \u_Sensor_Image_XYCrop/n60 , + \u_Sensor_Image_XYCrop/n61 , \u_Sensor_Image_XYCrop/n111 , \u_Sensor_Image_XYCrop/n62 , + \u_Sensor_Image_XYCrop/n63 , \u_Sensor_Image_XYCrop/n64 , \u_Sensor_Image_XYCrop/w_image_out_href , + \u_Sensor_Image_XYCrop/n65 , \u_Sensor_Image_XYCrop/n110 , \u_Sensor_Image_XYCrop/n109 , + \u_Sensor_Image_XYCrop/n108 , \u_Sensor_Image_XYCrop/n107 , \u_Sensor_Image_XYCrop/n106 , + \u_Sensor_Image_XYCrop/n105 , \u_Sensor_Image_XYCrop/n104 , \u_Sensor_Image_XYCrop/n103 , + \u_Sensor_Image_XYCrop/n102 , \u_Sensor_Image_XYCrop/n101 , \u_Sensor_Image_XYCrop/n100 , + \u_axi4_ctrl/n1484 , \u_axi4_ctrl/r_rframe_inc , \w_ddr3_awaddr[22] , + \u_axi4_ctrl/n1518 , \u_axi4_ctrl/n262 , \u_axi4_ctrl/n261 , \u_axi4_ctrl/n288 , + \w_ddr3_awaddr[23] , \u_axi4_ctrl/n1315 , ceg_net2429, \u_axi4_ctrl/n257 , + \u_axi4_ctrl/n251 , \u_axi4_ctrl/n234 , ceg_net2431, \u_axi4_ctrl/n263 , + lcd_vs, \u_axi4_ctrl/n664 , \u_axi4_ctrl/n1318 , \u_axi4_ctrl/equal_129/n9 , + \u_axi4_ctrl/w_rfifo_rst , \u_axi4_ctrl/n773 , \u_axi4_ctrl/equal_139/n3 , + \u_axi4_ctrl/n1516 , ceg_net2434, ceg_net2437, w_ddr3_rvalid, + \u_axi4_ctrl/n1477 , \u_axi4_ctrl/w_wframe_index_next[0] , ceg_net3678, + \u_axi4_ctrl/n189 , \u_axi4_ctrl/equal_68/n7 , \u_axi4_ctrl/n283 , + \u_axi4_ctrl/n282 , \u_axi4_ctrl/n281 , \u_axi4_ctrl/n280 , \u_axi4_ctrl/n279 , + \u_axi4_ctrl/n278 , \u_axi4_ctrl/n277 , \u_axi4_ctrl/n276 , \u_axi4_ctrl/n275 , + \u_axi4_ctrl/n274 , \u_axi4_ctrl/n273 , \u_axi4_ctrl/n272 , \u_axi4_ctrl/n271 , + \u_axi4_ctrl/n270 , \u_axi4_ctrl/n269 , \u_axi4_ctrl/n268 , \u_axi4_ctrl/n267 , + \u_axi4_ctrl/n266 , \u_axi4_ctrl/n250 , \u_axi4_ctrl/n249 , \u_axi4_ctrl/n248 , + \u_axi4_ctrl/n247 , \u_axi4_ctrl/n246 , \u_axi4_ctrl/n245 , \u_axi4_ctrl/n244 , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int , ceg_net2444, + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[0] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[0] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int , n11392, + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i30_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[12] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i42_pre , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_w[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_6 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_5 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_4 , + \u_axi4_ctrl/n663 , \u_axi4_ctrl/n662 , \u_axi4_ctrl/n661 , \u_axi4_ctrl/n660 , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int , ceg_net2451, + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int , \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[0] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[0] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i42_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i30_pre , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[13] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1 , + \u_axi4_ctrl/dff_138/i15_rst_3 , \u_axi4_ctrl/dff_138/i15_rst_2 , + \u_axi4_ctrl/dff_138/i15_rst_1 , \u_axi4_ctrl/dff_138/i15_rst_0 , + \u_axi4_ctrl/rfifo_wr_rst_busy_dly[14] , \u_axi4_ctrl/n772 , \u_axi4_ctrl/n785 , + \w_ddr3_rdata[0] , \w_ddr3_rdata[1] , \w_ddr3_rdata[2] , \w_ddr3_rdata[3] , + \w_ddr3_rdata[4] , \w_ddr3_rdata[5] , \w_ddr3_rdata[6] , \w_ddr3_rdata[7] , + \w_ddr3_rdata[8] , \w_ddr3_rdata[9] , \w_ddr3_rdata[10] , \w_ddr3_rdata[11] , + \w_ddr3_rdata[12] , \w_ddr3_rdata[13] , \w_ddr3_rdata[14] , \w_ddr3_rdata[15] , + \w_ddr3_rdata[16] , \w_ddr3_rdata[17] , \w_ddr3_rdata[18] , \w_ddr3_rdata[19] , + \w_ddr3_rdata[20] , \w_ddr3_rdata[21] , \w_ddr3_rdata[22] , \w_ddr3_rdata[23] , + \w_ddr3_rdata[24] , \w_ddr3_rdata[25] , \w_ddr3_rdata[26] , \w_ddr3_rdata[27] , + \w_ddr3_rdata[28] , \w_ddr3_rdata[29] , \w_ddr3_rdata[30] , \w_ddr3_rdata[31] , + \w_ddr3_rdata[32] , \w_ddr3_rdata[33] , \w_ddr3_rdata[34] , \w_ddr3_rdata[35] , + \w_ddr3_rdata[36] , \w_ddr3_rdata[37] , \w_ddr3_rdata[38] , \w_ddr3_rdata[39] , + \w_ddr3_rdata[40] , \w_ddr3_rdata[41] , \w_ddr3_rdata[42] , \w_ddr3_rdata[43] , + \w_ddr3_rdata[44] , \w_ddr3_rdata[45] , \w_ddr3_rdata[46] , \w_ddr3_rdata[47] , + \w_ddr3_rdata[48] , \w_ddr3_rdata[49] , \w_ddr3_rdata[50] , \w_ddr3_rdata[51] , + \w_ddr3_rdata[52] , \w_ddr3_rdata[53] , \w_ddr3_rdata[54] , \w_ddr3_rdata[55] , + \w_ddr3_rdata[56] , \w_ddr3_rdata[57] , \w_ddr3_rdata[58] , \w_ddr3_rdata[59] , + \w_ddr3_rdata[60] , \w_ddr3_rdata[61] , \w_ddr3_rdata[62] , \w_ddr3_rdata[63] , + \w_ddr3_rdata[64] , \w_ddr3_rdata[65] , \w_ddr3_rdata[66] , \w_ddr3_rdata[67] , + \w_ddr3_rdata[68] , \w_ddr3_rdata[69] , \w_ddr3_rdata[70] , \w_ddr3_rdata[71] , + \w_ddr3_rdata[72] , \w_ddr3_rdata[73] , \w_ddr3_rdata[74] , \w_ddr3_rdata[75] , + \w_ddr3_rdata[76] , \w_ddr3_rdata[77] , \w_ddr3_rdata[78] , \w_ddr3_rdata[79] , + \w_ddr3_rdata[80] , \w_ddr3_rdata[81] , \w_ddr3_rdata[82] , \w_ddr3_rdata[83] , + \w_ddr3_rdata[84] , \w_ddr3_rdata[85] , \w_ddr3_rdata[86] , \w_ddr3_rdata[87] , + \w_ddr3_rdata[88] , \w_ddr3_rdata[89] , \w_ddr3_rdata[90] , \w_ddr3_rdata[91] , + \w_ddr3_rdata[92] , \w_ddr3_rdata[93] , \w_ddr3_rdata[94] , \w_ddr3_rdata[95] , + \w_ddr3_rdata[96] , \w_ddr3_rdata[97] , \w_ddr3_rdata[98] , \w_ddr3_rdata[99] , + \w_ddr3_rdata[100] , \w_ddr3_rdata[101] , \w_ddr3_rdata[102] , + \w_ddr3_rdata[103] , \w_ddr3_rdata[104] , \w_ddr3_rdata[105] , + \w_ddr3_rdata[106] , \w_ddr3_rdata[107] , \w_ddr3_rdata[108] , + \w_ddr3_rdata[109] , \w_ddr3_rdata[110] , \w_ddr3_rdata[111] , + \w_ddr3_rdata[112] , \w_ddr3_rdata[113] , \w_ddr3_rdata[114] , + \w_ddr3_rdata[115] , \w_ddr3_rdata[116] , \w_ddr3_rdata[117] , + \w_ddr3_rdata[118] , \w_ddr3_rdata[119] , \w_ddr3_rdata[120] , + \w_ddr3_rdata[121] , \w_ddr3_rdata[122] , \w_ddr3_rdata[123] , + \w_ddr3_rdata[124] , \w_ddr3_rdata[125] , \w_ddr3_rdata[126] , + \w_ddr3_rdata[127] , \u_axi4_ctrl/w_wframe_index_next[1] , \u_lcd_driver/n89 , + \u_lcd_driver/equal_17/n27 , \u_lcd_driver/n39 , \u_lcd_driver/n90 , + \u_lcd_driver/n434 , \u_lcd_driver/n132 , \u_lcd_driver/n240 , + \u_lcd_driver/n38 , \u_lcd_driver/n88 , \u_lcd_driver/n87 , \u_lcd_driver/n86 , + \u_lcd_driver/n85 , \u_lcd_driver/n84 , \u_lcd_driver/n83 , \u_lcd_driver/n82 , + \u_lcd_driver/n81 , \u_lcd_driver/n80 , \u_lcd_driver/n79 , \u_lcd_driver/n78 , + \lcd_data[0] , \lcd_data[1] , \lcd_data[2] , \lcd_data[3] , + \lcd_data[4] , \lcd_data[5] , \lcd_data[6] , \lcd_data[7] , + \u_lcd_driver/n37 , \u_lcd_driver/n36 , \u_lcd_driver/n35 , \u_lcd_driver/n34 , + \u_lcd_driver/n33 , \u_lcd_driver/n32 , \u_lcd_driver/n31 , \u_lcd_driver/n30 , + \u_lcd_driver/n29 , \u_lcd_driver/n28 , \u_lcd_driver/n27 , \u_lcd_driver/n26 , + \u_lcd_driver/n25 , \u_rgb2dvi/enc_0/n886 , \u_rgb2dvi/enc_0/n765 , + \u_rgb2dvi/enc_0/n771 , \u_rgb2dvi/enc_0/n777 , \u_rgb2dvi/enc_0/n783 , + \u_rgb2dvi/enc_0/n789 , \u_rgb2dvi/enc_0/n795 , \u_rgb2dvi/enc_0/n801 , + \u_rgb2dvi/enc_0/n807 , \u_rgb2dvi/enc_0/n813 , \u_rgb2dvi/enc_1/q_out[0] , + n12107, \u_rgb2dvi/enc_1/q_out[1] , \u_rgb2dvi/enc_1/q_out[2] , + \u_rgb2dvi/enc_1/q_out[3] , \u_rgb2dvi/enc_1/q_out[4] , \u_rgb2dvi/enc_1/q_out[5] , + \u_rgb2dvi/enc_1/q_out[6] , \u_rgb2dvi/enc_1/q_out[7] , \u_rgb2dvi/enc_1/q_out[9] , + \u_rgb2dvi/enc_2/q_out[0] , n12124, \u_rgb2dvi/enc_2/q_out[1] , + \u_rgb2dvi/enc_2/q_out[2] , \u_rgb2dvi/enc_2/q_out[3] , \u_rgb2dvi/enc_2/q_out[4] , + \u_rgb2dvi/enc_2/q_out[5] , \u_rgb2dvi/enc_2/q_out[6] , \u_rgb2dvi/enc_2/q_out[7] , + \u_rgb2dvi/enc_2/q_out[9] , n12140, n12143, n12146, n12149, + n12152, n12155, n12158, n12163, n12166, n12169, n12172, + n12180, n12183, n12187, n12191, n12194, n12197, n12200, + n12315, n12318, n12321, n12324, n12327, n12330, n12333, + n12336, n12798, n12801, n12804, n12807, n12810, n12816, + n12819, n12822, n12825, n12828, n12833, n12836, n12839, + n12842, n12848, n12851, n12854, n12857, n12862, n12865, + n12868, n12871, n12876, n12879, n12882, n12885, n12888, + n15071, n15070, n15069, n15068, n15067, n15065, n15064, + n15063, n15062, n15061, n15060, n15059, n15058, n15057, + n15056, n15055, n15054, n15053, n15052, n15051, n15050, + n15049, n15048, n15047, n15046, n15045, n15044, n13395, + n13396, n13397, n13398, n13399, n13400, n13401, n13402, + n13403, n13404, n13405, n13406, n13407, n13408, n13409, + n13410, n13411, n13412, n13413, n13414, n13415, n13416, + n13417, n13418, n13419, n13420, n13421, n13422, n13423, + n13424, n13425, n13426, n13427, n13428, n13429, n13430, + n13431, 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n13684, n13685, n13686, n13687, + n13688, n13689, n13690, n13691, n13692, n13693, n13694, + n13695, n13696, n13697, n13698, n13699, n13700, n13701, + n13702, n13703, n13704, n13705, n13706, n13707, n13708, + n13709, n13710, n13711, n13712, n13713, n13714, n13715, + n13716, n13717, n13718, n13719, n13720, n13721, n13722, + n13723, n13724, n13725, n13726, n13727, n13728, n13729, + n13730, n13731, n13732, n13733, n13734, n13735, n13736, + n13737, n13738, n13739, n13740, n13741, n13742, n13743, + n13744, n13745, n13746, n13747, n13748, n13749, n13750, + n13751, n13752, n13753, n13754, n13755, n13756, n13757, + n13758, n13759, n13760, n13761, n13762, n13763, n13764, + n13765, n13766, n13767, n13768, n13769, n13770, n13771, + n13772, n13773, n13774, n13775, n13776, n13777, n13778, + n13779, n13780, n13781, n13782, n13783, n13784, n13785, + n13786, n13787, n13788, n13789, n13790, n13791, n13792, + n13793, n13794, n13795, n13796, n13797, n13798, n13799, + n13800, n13801, n13802, n13803, n13804, n13805, n13806, + n13807, n13808, n13809, n13810, n13811, n13812, n13813, + n13814, n13815, n13816, n13817, n13818, n13819, n13820, + n13821, n13822, n13823, n13824, n13825, n13826, n13827, + n13828, n13829, n13830, n13831, n13832, n13833, n13834, + n13835, n13836, n13837, n13838, n13839, n13840, n13841, + n13842, n13843, n13844, n13845, n13846, n13847, n13848, + n13849, n13850, n13851, n13852, n13853, n13854, n13855, + n13856, n13857, n13858, n13859, n13860, n13861, n13862, + n13863, n13864, n13865, n13866, n13867, n13868, n13869, + n13870, n13871, n13872, n13873, n13874, n13875, n13876, + n13877, n13878, n13879, n13880, n13881, n13882, n13883, + n13884, n13885, n13886, n13887, n13888, n13889, n13890, + n13891, n13892, n13893, n13894, n13895, n13896, n13897, + n13898, n13899, n13900, n13901, n13902, n13903, n13904, + n13905, n13906, n13907, n13908, n13909, n13910, n13911, + n13912, n13913, n13914, n13915, n13916, n13917, n13918, + n13919, n13920, n13921, n13922, n13923, n13924, n13925, + n13926, n13927, n13928, n13929, n13930, n13931, n13932, + n13933, n13934, n13935, n13936, n13937, n13938, n13939, + n13940, n13941, n13942, n13943, n13944, n13945, n13946, + n13947, n13948, n13949, n13950, n13951, n13952, n13953, + n13954, n13955, n13956, n13957, n13958, n13959, n13960, + n13961, n13962, n13963, n13964, n13965, n13966, n13967, + n13968, n13969, n13970, n13971, n13972, n13973, n13974, + n13975, n13976, n13977, n13978, n13979, n13980, n13981, + n13982, n13983, n13984, n13985, n13986, n13987, n13988, + n13989, n13990, n13991, n13992, n13993, n13994, n13995, + n13996, n13997, n13998, n13999, n14000, n14001, n14002, + n14003, n14004, n14005, n14006, n14007, n14008, n14009, + n14010, n14011, n14012, n14013, n14014, n14015, n14016, + n14017, n14018, n14019, n14020, n14021, n14022, n14023, + n14024, n14025, n14026, n14027, n14028, n14029, n14030, + n14031, n14032, n14033, n14034, n14035, n14036, n14037, + n14038, n14039, n14040, n14041, n14042, n14043, n14044, + n14045, n14046, n14047, n14048, n14049, n14050, n14051, + n14052, n14053, n14054, n14055, n14056, n14057, n14058, + n14059, n14060, n14061, n14062, n14063, n14064, n14065, + n14066, n14067, n14068, n14069, n14070, n14071, n14072, + n14073, n14074, n14075, n14076, n14077, n14078, n14079, + n14080, n14081, n14082, n14083, n14084, n14085, n14086, + n14087, n14088, n14089, n14090, n14091, n14092, n14093, + n14094, n14095, n14096, n14097, n14098, n14099, n14100, + n14101, n14102, n14103, n14104, n14105, n14106, n14107, + n14108, n14109, n14110, n14111, n14112, n14113, n14114, + n14115, n14116, n14117, n14118, n14119, n14120, n14121, + n14122, n14123, n14124, n14125, n14126, n14127, n14128, + n14129, n14130, n14131, n14132, n14133, n14134, n14135, + n14136, n14137, n14138, n14139, n14140, n14141, n14142, + n14143, n14144, n14145, n14146, n14147, n14148, n14149, + n14150, n14151, n14152, n14153, n14154, n14155, n14156, + n14157, n14158, n14159, n14160, n14161, n14162, n14163, + n14164, n14165, n14166, n14167, n14168, n14169, n14170, + n14171, n14172, n14173, n14174, n14175, n14176, n14177, + n14178, n14179, n14180, n14181, n14182, n14183, n14184, + n14185, n14186, n14187, n14188, n14189, n14190, n14191, + n14192, n14193, n14194, n14195, n14196, n14197, n14198, + n14199, n14200, n14201, n14202, n14203, n14204, n14205, + n14206, n14207, n14208, n14209, n14210, n14211, n14212, + n14213, n14214, n14215, n14216, n14217, n14218, n14219, + n14220, n14221, n14222, n14223, n14224, n14225, n14226, + n14227, n14228, n14229, n14230, n14231, n14232, n14233, + n14234, n14235, n14236, n14237, n14238, n14239, n14240, + n14241, n14242, n14243, n14244, n14245, n14246, n14247, + n14248, n14249, n14250, n14251, n14252, n14253, n14254, + n14255, n14256, n14257, n14258, n14259, n14260, n14261, + n14262, n14263, n14264, n14265, n14266, n14267, n14268, + n14269, n14270, n14271, n14272, n14273, n14274, n14275, + n14276, n14277, n14278, n14279, n14280, n14281, n14282, + n14283, n14284, n14285, n14286, n14287, n14288, n14289, + n14290, n14291, n14292, n14293, n14294, n14295, n14296, + n14297, n14298, n14299, n14300, n14301, n14302, n14303, + n14304, n14305, n14306, n14307, n14308, n14309, n14310, + n14311, n14312, n14313, n14314, n14315, n14316, n14317, + n14318, n14319, n14320, n14321, n14322, n14323, n14324, + n14325, n14326, n14327, n14328, n14329, n14330, n14331, + n14332, n14333, n14334, n14335, n14336, n14337, n14338, + n14339, n14340, n14341, n14342, n14343, n14344, n14345, + n14346, n14347, n14348, n14349, n14350, n14351, n14352, + n14353, n14354, n14355, n14356, n14357, n14358, n14359, + n14360, n14361, n14362, n14363, n14364, n14365, n14366, + n14367, n14368, n14369, n14370, n14371, n14372, n14373, + n14374, n14375, n14376, n14377, n14378, n14379, n14380, + n14381, n14382, n14383, n14384, n14385, n14386, n14387, + n14388, n14389, n14390, n14391, n14392, n14393, n14394, + n14395, n14396, n14397, n14398, n14399, n14400, n14401, + n14402, n14403, n14404, n14405, n14406, n14407, n14408, + n14409, n14410, n14411, n14412, n14413, n14414, n14415, + n14416, n14417, n14418, n14419, n14420, n14421, n14422, + n14423, n14424, n14425, n14426, n14427, n14428, n14429, + n14430, n14431, n14432, n14433, n14434, n14435, n14436, + n14437, n14438, n14439, n14440, n14441, n14442, n14443, + n14444, n14445, n14446, n14447, n14448, n14449, n14450, + n14451, n14452, n14453, n14454, n14455, n14456, n14457, + n14458, n14459, n14460, n14461, n14462, n14463, n14464, + n14465, n14466, n14467, n14468, n14469, n14470, n14471, + n14472, n14473, n14474, n14475, n14476, n14477, n14478, + n14479, n14480, n14481, n14482, n14483, n14484, n14485, + n14486, n14487, n14488, n14489, n14490, n14491, n14492, + n14493, n14494, n14495, n14496, n14497, n14498, n14499, + n14500, n14501, n14502, n14503, n14504, n14505, n14506, + n14507, n14508, n14509, n14510, n14511, n14512, n14513, + n14514, n14515, n14516, n14517, n14518, n14519, n14520, + n14521, n14522, n14523, n14524, n14525, n14526, n14527, + n14528, n14529, n14530, n14531, n14532, n14533, n14534, + n14535, n14536, n14537, n14538, n14539, n14540, n14541, + n14542, n14543, n14544, n14545, n14553, n14554, n14555, + n14556, n14557, n14558, n14559, n14560, n14561, n14562, + n14563, n14564, n14565, n14566, n14567, n14568, n14569, + n14570, n14571, n14572, n14573, n14574, n14575, n14576, + n14577, n14578, n14579, n14580, n14581, n14582, n14583, + n14584, n14585, n14586, n14587, n14588, n14589, n14590, + n14591, n14592, n14593, n14594, n14595, n14596, n14597, + n14598, n14599, n14600, n14601, n14602, n14603, n14604, + n14605, n14606, n14607, n14608, n14609, n14610, n14611, + n14612, n14613, n14614, n14615, n14616, n14617, n14618, + n14619, n14620, n14621, n14622, n14623, n14624, n14625, + n14626, n14627, n14628, n14629, n14630, n14631, n14632, + n14633, n14634, n14635, n14636, n14637, n14638, n14639, + n14640, n14641, n14642, n14643, n14644, n14645, n14646, + n14647, n14648, n14649, n14650, n14651, n14652, n14653, + n14654, n14655, n14656, n14657, n14658, n14659, n14660, + n14661, n14662, n14663, n14664, n14665, n14666, n14667, + n14668, n14669, n14670, n14671, n14672, n14673, n14674, + n14675, n14676, n14677, n14678, n14679, n14680, n14681, + n14682, n14683, n14684, n14685, n14686, n14687, n14688, + n14689, n14690, n14691, n14692, n14693, n14694, n14695, + n14696, n14697, n14698, n14699, n14700, n14701, n14702, + n14703, n14704, n14705, n14706, n14707, n14708, n14709, + n14710, n14711, n14712, n14713, n14714, n14715, n14716, + n14717, n14718, n14719, n14720, n14721, n14722, n14723, + n14724, n14725, n14726, n14727, n14728, n14729, n14730, + n14731, n14732, n14733, n14734, n14735, n14736, n14737, + n14738, n14739, n14740, n14741, n14742, n14743, n14744, + n14745, n14746, n14747, n14748, n14749, n14750, n14751, + n14752, n14753, n14754, n14755, n14756, n14757, n14758, + n14759, n14760, n14761, n14762, n14763, n14764, n14765, + n14766, n14767, n14768, n14769, n14770, n14771, n14772, + n14773, n14774, n14775, n14776, n14777, n14778, n14779, + n14780, n14781, n14782, n14783, n14784, n14785, n14786, + n14787, n14788, n14789, n14790, n14791, n14792, n14793, + n14794, n14795, n14796, n14797, n14798, n14799, n14800, + n14801, n14802, n14803, n14804, n14805, n14806, n14807, + n14808, n14809, n14810, n14811, n14812, n14813, n14814, + n14815, n14816, n14817, n14818, n14819, n14820, n14821, + n14822, n14823, n14824, n14825, n14826, n14827, n14828, + n14829, n14830, n14831, n14832, n14833, n14834, n14835, + n14836, n14837, n14838, n14839, n14840, n14841, n14842, + n14843, n14844, n14845, n14846, n14847, n14848, n14849, + n14850, n14851, n14852, n14853, n14854, n14855, n14856, + n14857, n14858, n14859, n14860, n14861, n14862, n14863, + n14864, n14865, n14866, n14867, n14868, n14869, n14870, + n14871, n14872, n14873, n14874, n14875, n14876, n14877, + n14878, n14879, n14880, n14881, n14882, n14883, n14884, + n14885, n14886, n14887, n14888, n14889, n14890, n14891, + n14892, n14893, n14894, n14895, n14896, n14897, n14898, + n14899, n14900, n14901, n14902, n14904, n14905, n14906, + n14907, n14908, n14909, n14910, n14911, n14912, n14913, + n14914, n14915, n14916, n14917, n14918, n14919, n14920, + n14921, n14922, n14925, n14926, n14927, n14928, n14929, + n14930, n14931, n14932, n14933, n14934, n14935, n14936, + n14937, n14938, n14939, n14940, n14941, n14942, n14943, + n14944, n14945, n14946, n14947, n14948, n14949, n14950, + n14951, n14952, n14953, n14954, n14955, n14956, n14957, + n14958, n14959, n14960, n14961, n14962, n14963, n14964, + n14965, n14966, n14967, n14968, n14969, n14970, n14971, + n14972, n14973, n14974, n14975, n14976, n14977, n14978, + n14979, n14980, n14981, n14982, n14983, n14984, n14985, + n14986, n14987, n14988, n14989, n14990, n14991, n14992, + n14993, n14994, n14995, n14996, n14997, n14998, n14999, + n15000, n15001, n15002, n15003, n15004, n15005, n15006, + n15007, n15008, n15009, n15010, n15011, n15012, n15013, + n15014, n15015, n15016, n15017, n15018, n15019, n15020, + n15021, n15022, n15023, n15024, n15025, n15026, n15027, + n15028, n15029, n15030, n15031, n15032, n15033, n15034, + n15035, n15036, n15037, n15038, n15039, n15040, n15041, + n15042, n15043; + + assign dsi_pll_rstn_o = sys_pll_lock /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE */ ; + assign ddr_pll_rstn_o = dsi_pll_rstn_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign shift_sel[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign shift_sel[2] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign shift_sel[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign shift_sel[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_pll_rstn_o = dsi_pll_rstn_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[14] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[13] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[12] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[11] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[10] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[9] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[8] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[7] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[6] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[5] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[4] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[3] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[2] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[1] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dq_oe[0] = o_dq_oe[15] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dqs_hi[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dqs_hi[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dqs_lo[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dqs_lo[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dqs_n_hi[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dqs_n_hi[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dqs_n_lo[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dqs_n_lo[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dqs_oe[0] = o_dqs_oe[1] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dqs_n_oe[1] = o_dqs_oe[1] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign o_dqs_n_oe[0] = o_dqs_oe[1] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign clk_p_hi = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign clk_p_lo = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign clk_n_hi = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign clk_n_lo = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_ctl0_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_ctl0_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_ctl1_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_ctl1_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_scl_oe = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxc_hs_en_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxc_hs_term_en_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd0_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd0_hs_en_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd0_hs_term_en_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd1_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd1_hs_en_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd1_hs_term_en_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd2_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd2_hs_en_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd2_hs_term_en_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd3_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd3_hs_en_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign csi_rxd3_hs_term_en_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_lp_p_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_lp_p_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_lp_n_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_lp_n_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_hs_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_hs_o[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_hs_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_hs_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_hs_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_hs_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_hs_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_hs_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txc_hs_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_hs_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_hs_o[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_hs_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_hs_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_hs_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_hs_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_hs_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_hs_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_hs_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_lp_p_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_lp_p_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_lp_n_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd0_lp_n_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_lp_p_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_lp_p_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_lp_n_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_lp_n_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_hs_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_hs_o[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_hs_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_hs_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_hs_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_hs_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_hs_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_hs_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd1_hs_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_lp_p_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_lp_p_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_lp_n_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_lp_n_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_hs_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_hs_o[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_hs_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_hs_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_hs_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_hs_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_hs_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_hs_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd2_hs_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_lp_p_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_lp_p_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_lp_n_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_lp_n_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_hs_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_hs_o[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_hs_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_hs_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_hs_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_hs_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_hs_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_hs_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign dsi_txd3_hs_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign uart_tx_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign led_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign cmos_ctl2 = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign cmos_ctl3 = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txc_oe = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txd0_oe = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txd1_oe = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txd2_oe = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txd0_rst_o = hdmi_txc_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txd1_rst_o = hdmi_txc_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txd2_rst_o = hdmi_txc_rst_o /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txc_o[9] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txc_o[8] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txc_o[7] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txc_o[6] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txc_o[5] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txc_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txc_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txc_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txc_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txc_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign hdmi_txd2_o[8] = hdmi_txd1_o[8] /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txc_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txc_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txc_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txc_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txc_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txc_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txc_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txc_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txc_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd0_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd0_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd0_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd0_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd0_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd0_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd0_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd0_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd0_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd1_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd1_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd1_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd1_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd1_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd1_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd1_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd1_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd1_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd2_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd2_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd2_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd2_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd2_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd2_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd2_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd2_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd2_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd3_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd3_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd3_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd3_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd3_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd3_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd3_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd3_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lvds_txd3_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_tp_sda_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_tp_sda_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_tp_scl_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_tp_scl_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_tp_int_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_tp_int_oe = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_tp_rst_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_pwm_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_blen_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_vs_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_hs_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_de_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_o[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_o[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_o[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_o[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_o[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_o[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_o[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_o[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_o[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_o[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_oe[7] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_oe[6] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_oe[5] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_oe[4] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_oe[3] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_oe[2] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_oe[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_b7_0_oe[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_oe[7] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_oe[6] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_oe[5] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_oe[4] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_oe[3] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_oe[2] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_oe[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_g7_0_oe[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_oe[7] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_oe[6] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_oe[5] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_oe[4] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_oe[3] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_oe[2] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_oe[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign lcd_r7_0_oe[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign spi_sck_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign spi_ssn_o = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE */ ; + assign sys_pll_rstn_o = 1'b1 /* verific EFX_ATTRIBUTE_CELL_NAME=VCC */ ; + assign shift_sel[4] = 1'b0 /* verific EFX_ATTRIBUTE_CELL_NAME=GND */ ; + EFX_LUT4 LUT__19466 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe_p0[15] ), + .O(o_dq_oe[15])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heeee */ ; + defparam LUT__19466.LUTMASK = 16'heeee; + EFX_FF \rstn_sys~FF (.D(1'b1), .CE(1'b1), .CLK(clk_sys), .SR(w_pll_lock), + .Q(rstn_sys)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(396) + defparam \rstn_sys~FF .CLK_POLARITY = 1'b1; + defparam \rstn_sys~FF .CE_POLARITY = 1'b1; + defparam \rstn_sys~FF .SR_POLARITY = 1'b0; + defparam \rstn_sys~FF .D_POLARITY = 1'b1; + defparam \rstn_sys~FF .SR_SYNC = 1'b0; + defparam \rstn_sys~FF .SR_VALUE = 1'b0; + defparam \rstn_sys~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \rstn_pixel~FF (.D(1'b1), .CE(1'b1), .CLK(clk_pixel), .SR(w_pll_lock), + .Q(rstn_pixel)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(397) + defparam \rstn_pixel~FF .CLK_POLARITY = 1'b1; + defparam \rstn_pixel~FF .CE_POLARITY = 1'b1; + defparam \rstn_pixel~FF .SR_POLARITY = 1'b0; + defparam \rstn_pixel~FF .D_POLARITY = 1'b1; + defparam \rstn_pixel~FF .SR_SYNC = 1'b0; + defparam \rstn_pixel~FF .SR_VALUE = 1'b0; + defparam \rstn_pixel~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_ddr_unlock~FF (.D(w_ddr3_cal_done), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(r_ddr_unlock)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(520) + defparam \r_ddr_unlock~FF .CLK_POLARITY = 1'b1; + defparam \r_ddr_unlock~FF .CE_POLARITY = 1'b1; + defparam \r_ddr_unlock~FF .SR_POLARITY = 1'b0; + defparam \r_ddr_unlock~FF .D_POLARITY = 1'b1; + defparam \r_ddr_unlock~FF .SR_SYNC = 1'b0; + defparam \r_ddr_unlock~FF .SR_VALUE = 1'b0; + defparam \r_ddr_unlock~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_cmos_rx_vsync0_in[0]~FF (.D(cmos_vsync), .CE(1'b1), .CLK(cmos_pclk), + .SR(1'b0), .Q(\r_cmos_rx_vsync0_in[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(747) + defparam \r_cmos_rx_vsync0_in[0]~FF .CLK_POLARITY = 1'b1; + defparam \r_cmos_rx_vsync0_in[0]~FF .CE_POLARITY = 1'b1; + defparam \r_cmos_rx_vsync0_in[0]~FF .SR_POLARITY = 1'b1; + defparam \r_cmos_rx_vsync0_in[0]~FF .D_POLARITY = 1'b1; + defparam \r_cmos_rx_vsync0_in[0]~FF .SR_SYNC = 1'b1; + defparam \r_cmos_rx_vsync0_in[0]~FF .SR_VALUE = 1'b0; + defparam \r_cmos_rx_vsync0_in[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_XYCrop_frame_vsync~FF (.D(XYCrop_frame_vsync), .CE(1'b1), + .CLK(cmos_pclk), .SR(1'b0), .Q(r_XYCrop_frame_vsync)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(911) + defparam \r_XYCrop_frame_vsync~FF .CLK_POLARITY = 1'b1; + defparam \r_XYCrop_frame_vsync~FF .CE_POLARITY = 1'b1; + defparam \r_XYCrop_frame_vsync~FF .SR_POLARITY = 1'b1; + defparam \r_XYCrop_frame_vsync~FF .D_POLARITY = 1'b1; + defparam \r_XYCrop_frame_vsync~FF .SR_SYNC = 1'b1; + defparam \r_XYCrop_frame_vsync~FF .SR_VALUE = 1'b0; + defparam \r_XYCrop_frame_vsync~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_XYCrop_frame_Gray[0]~FF (.D(\XYCrop_frame_Gray[0] ), .CE(1'b1), + .CLK(cmos_pclk), .SR(1'b0), .Q(\r_XYCrop_frame_Gray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(911) + defparam \r_XYCrop_frame_Gray[0]~FF .CLK_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[0]~FF .CE_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[0]~FF .SR_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[0]~FF .D_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[0]~FF .SR_SYNC = 1'b1; + defparam \r_XYCrop_frame_Gray[0]~FF .SR_VALUE = 1'b0; + defparam \r_XYCrop_frame_Gray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_XYCrop_frame_href~FF (.D(XYCrop_frame_href), .CE(1'b1), .CLK(cmos_pclk), + .SR(1'b0), .Q(r_XYCrop_frame_href)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(911) + defparam \r_XYCrop_frame_href~FF .CLK_POLARITY = 1'b1; + defparam \r_XYCrop_frame_href~FF .CE_POLARITY = 1'b1; + defparam \r_XYCrop_frame_href~FF .SR_POLARITY = 1'b1; + defparam \r_XYCrop_frame_href~FF .D_POLARITY = 1'b1; + defparam \r_XYCrop_frame_href~FF .SR_SYNC = 1'b1; + defparam \r_XYCrop_frame_href~FF .SR_VALUE = 1'b0; + defparam \r_XYCrop_frame_href~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_XYCrop_frame_de~FF (.D(XYCrop_frame_de), .CE(1'b1), .CLK(cmos_pclk), + .SR(1'b0), .Q(r_XYCrop_frame_de)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(911) + defparam \r_XYCrop_frame_de~FF .CLK_POLARITY = 1'b1; + defparam \r_XYCrop_frame_de~FF .CE_POLARITY = 1'b1; + defparam \r_XYCrop_frame_de~FF .SR_POLARITY = 1'b1; + defparam \r_XYCrop_frame_de~FF .D_POLARITY = 1'b1; + defparam \r_XYCrop_frame_de~FF .SR_SYNC = 1'b1; + defparam \r_XYCrop_frame_de~FF .SR_VALUE = 1'b0; + defparam \r_XYCrop_frame_de~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_cmos_rx_vsync0_in[1]~FF (.D(\r_cmos_rx_vsync0_in[0] ), .CE(1'b1), + .CLK(cmos_pclk), .SR(1'b0), .Q(\r_cmos_rx_vsync0_in[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(747) + defparam \r_cmos_rx_vsync0_in[1]~FF .CLK_POLARITY = 1'b1; + defparam \r_cmos_rx_vsync0_in[1]~FF .CE_POLARITY = 1'b1; + defparam \r_cmos_rx_vsync0_in[1]~FF .SR_POLARITY = 1'b1; + defparam \r_cmos_rx_vsync0_in[1]~FF .D_POLARITY = 1'b1; + defparam \r_cmos_rx_vsync0_in[1]~FF .SR_SYNC = 1'b1; + defparam \r_cmos_rx_vsync0_in[1]~FF .SR_VALUE = 1'b0; + defparam \r_cmos_rx_vsync0_in[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1263 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1004 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1037 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[0]~FF (.D(\w_ddr3_wdata[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_en~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1089 ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_en~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_en~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_en~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_en~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_en~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_en~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_en~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1071 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_en~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1193 ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_en~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_en~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_en~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_en~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_en~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_en~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_en~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_fifo_aw[40] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_i_arburst_fifo[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1378 ), + .CE(ceg_net376), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1054 ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n95 ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1090 ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wready~FF (.D(w_ddr3_wready), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wready )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wready~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wready~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wready~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wready~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wready~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wready~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wready~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wvalid~FF (.D(led_o[2]), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wvalid )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wvalid~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wvalid~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wvalid~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wvalid~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wvalid~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wvalid~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wvalid~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_awaddr_fifo_rd_en~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_fifo_rd_en ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_awaddr_fifo_rd_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_awaddr_fifo_rd_en~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_awaddr_fifo_rd_en~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_awaddr_fifo_rd_en~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_awaddr_fifo_rd_en~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_awaddr_fifo_rd_en~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_awaddr_fifo_rd_en~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_awaddr_fifo_rd_en~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_awvalid~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_i_awvalid ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_awvalid )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_awvalid~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_awvalid~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_awvalid~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_awvalid~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_awvalid~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_awvalid~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_awvalid~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n572 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1088 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[0]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[0]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_flag~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/not_equal_72/n31 ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_flag )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_flag~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_flag~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_flag~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_flag~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_flag~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_flag~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_flag~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1337 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_empty[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n111 ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_empty[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_empty[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_empty[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_empty[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_empty[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_empty[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_empty[0]~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_empty[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1262 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1261 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1260 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1259 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1258 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1257 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1256 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1255 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1254 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1253 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1252 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1251 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1250 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1249 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1248 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1247 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1246 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1245 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1244 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1243 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1242 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1241 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1240 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1239 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1238 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1237 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1236 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1235 ), + .CE(ceg_net2), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1003 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1002 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1001 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1000 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n999 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n998 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n997 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n996 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n995 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n994 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n993 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n992 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n991 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n990 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n989 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n988 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n987 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n986 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n985 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n984 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n983 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n982 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n981 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n980 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n979 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n978 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n977 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n976 ), + .CE(ceg_net5), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1036 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1035 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1034 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1033 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1032 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1031 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1030 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1029 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[8]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1028 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[9]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1027 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[10]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1026 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[11]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1025 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[12]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1024 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[13]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1023 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[14]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1022 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[15]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[16]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1021 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[16]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[16]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[16]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[16]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[16]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[16]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[17]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1020 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[17]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[17]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[17]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[17]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[17]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[17]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[18]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1019 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[18]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[18]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[18]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[18]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[18]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[18]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[19]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1018 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[19]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[19]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[19]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[19]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[19]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[19]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[20]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1017 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[20]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[20]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[20]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[20]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[20]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[20]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[21]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1016 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[21]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[21]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[21]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[21]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[21]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[21]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[22]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1015 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[22]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[22]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[22]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[22]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[22]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[22]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[23]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1014 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[23]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[23]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[23]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[23]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[23]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[23]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[24]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1013 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[24]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[24]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[24]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[24]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[24]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[24]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[25]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1012 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[25]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[25]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[25]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[25]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[25]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[25]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[26]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1011 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[26]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[26]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[26]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[26]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[26]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[26]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[27]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1010 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[27]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[27]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[27]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[27]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[27]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[27]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[28]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1009 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[28]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[28]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[28]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[28]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[28]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[28]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[1]~FF (.D(\w_ddr3_wdata[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[2]~FF (.D(\w_ddr3_wdata[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[3]~FF (.D(\w_ddr3_wdata[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[4]~FF (.D(\w_ddr3_wdata[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[5]~FF (.D(\w_ddr3_wdata[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[6]~FF (.D(\w_ddr3_wdata[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[7]~FF (.D(\w_ddr3_wdata[7] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[8]~FF (.D(\w_ddr3_wdata[8] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[9]~FF (.D(\w_ddr3_wdata[9] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[10]~FF (.D(\w_ddr3_wdata[10] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[11]~FF (.D(\w_ddr3_wdata[11] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[12]~FF (.D(\w_ddr3_wdata[12] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[13]~FF (.D(\w_ddr3_wdata[13] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[14]~FF (.D(\w_ddr3_wdata[14] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[15]~FF (.D(\w_ddr3_wdata[15] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[16]~FF (.D(\w_ddr3_wdata[16] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[16]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[16]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[16]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[16]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[16]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[16]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[17]~FF (.D(\w_ddr3_wdata[17] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[17]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[17]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[17]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[17]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[17]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[17]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[18]~FF (.D(\w_ddr3_wdata[18] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[18]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[18]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[18]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[18]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[18]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[18]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[19]~FF (.D(\w_ddr3_wdata[19] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[19]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[19]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[19]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[19]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[19]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[19]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[20]~FF (.D(\w_ddr3_wdata[20] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[20]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[20]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[20]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[20]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[20]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[20]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[21]~FF (.D(\w_ddr3_wdata[21] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[21]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[21]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[21]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[21]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[21]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[21]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[22]~FF (.D(\w_ddr3_wdata[22] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[22]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[22]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[22]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[22]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[22]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[22]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[23]~FF (.D(\w_ddr3_wdata[23] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[23]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[23]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[23]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[23]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[23]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[23]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[24]~FF (.D(\w_ddr3_wdata[24] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[24]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[24]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[24]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[24]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[24]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[24]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[25]~FF (.D(\w_ddr3_wdata[25] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[25]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[25]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[25]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[25]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[25]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[25]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[26]~FF (.D(\w_ddr3_wdata[26] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[26]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[26]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[26]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[26]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[26]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[26]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[27]~FF (.D(\w_ddr3_wdata[27] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[27]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[27]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[27]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[27]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[27]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[27]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[28]~FF (.D(\w_ddr3_wdata[28] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[28]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[28]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[28]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[28]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[28]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[28]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[29]~FF (.D(\w_ddr3_wdata[29] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[29]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[29]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[29]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[29]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[29]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[29]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[29]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[30]~FF (.D(\w_ddr3_wdata[30] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[30]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[30]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[30]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[30]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[30]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[30]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[30]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[31]~FF (.D(\w_ddr3_wdata[31] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[31]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[31]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[31]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[31]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[31]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[31]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[31]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[32]~FF (.D(\w_ddr3_wdata[32] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[32] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[32]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[32]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[32]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[32]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[32]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[32]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[32]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[33]~FF (.D(\w_ddr3_wdata[33] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[33] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[33]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[33]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[33]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[33]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[33]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[33]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[33]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[34]~FF (.D(\w_ddr3_wdata[34] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[34] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[34]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[34]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[34]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[34]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[34]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[34]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[34]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[35]~FF (.D(\w_ddr3_wdata[35] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[35] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[35]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[35]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[35]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[35]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[35]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[35]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[35]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[36]~FF (.D(\w_ddr3_wdata[36] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[36] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[36]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[36]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[36]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[36]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[36]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[36]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[36]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[37]~FF (.D(\w_ddr3_wdata[37] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[37] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[37]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[37]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[37]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[37]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[37]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[37]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[37]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[38]~FF (.D(\w_ddr3_wdata[38] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[38] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[38]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[38]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[38]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[38]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[38]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[38]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[38]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[39]~FF (.D(\w_ddr3_wdata[39] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[39] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[39]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[39]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[39]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[39]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[39]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[39]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[39]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[40]~FF (.D(\w_ddr3_wdata[40] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[40] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[40]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[40]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[40]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[40]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[40]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[40]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[40]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[41]~FF (.D(\w_ddr3_wdata[41] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[41] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[41]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[41]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[41]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[41]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[41]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[41]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[41]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[42]~FF (.D(\w_ddr3_wdata[42] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[42] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[42]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[42]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[42]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[42]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[42]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[42]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[42]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[43]~FF (.D(\w_ddr3_wdata[43] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[43] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[43]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[43]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[43]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[43]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[43]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[43]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[43]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[44]~FF (.D(\w_ddr3_wdata[44] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[44] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[44]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[44]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[44]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[44]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[44]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[44]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[44]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[45]~FF (.D(\w_ddr3_wdata[45] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[45] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[45]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[45]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[45]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[45]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[45]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[45]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[45]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[46]~FF (.D(\w_ddr3_wdata[46] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[46] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[46]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[46]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[46]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[46]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[46]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[46]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[46]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[47]~FF (.D(\w_ddr3_wdata[47] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[47] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[47]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[47]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[47]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[47]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[47]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[47]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[47]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[48]~FF (.D(\w_ddr3_wdata[48] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[48] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[48]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[48]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[48]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[48]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[48]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[48]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[48]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[49]~FF (.D(\w_ddr3_wdata[49] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[49] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[49]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[49]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[49]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[49]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[49]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[49]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[49]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[50]~FF (.D(\w_ddr3_wdata[50] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[50] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[50]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[50]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[50]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[50]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[50]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[50]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[50]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[51]~FF (.D(\w_ddr3_wdata[51] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[51] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[51]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[51]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[51]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[51]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[51]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[51]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[51]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[52]~FF (.D(\w_ddr3_wdata[52] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[52] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[52]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[52]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[52]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[52]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[52]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[52]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[52]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[53]~FF (.D(\w_ddr3_wdata[53] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[53] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[53]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[53]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[53]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[53]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[53]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[53]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[53]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[54]~FF (.D(\w_ddr3_wdata[54] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[54] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[54]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[54]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[54]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[54]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[54]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[54]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[54]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[55]~FF (.D(\w_ddr3_wdata[55] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[55] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[55]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[55]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[55]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[55]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[55]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[55]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[55]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[56]~FF (.D(\w_ddr3_wdata[56] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[56] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[56]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[56]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[56]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[56]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[56]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[56]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[56]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[57]~FF (.D(\w_ddr3_wdata[57] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[57] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[57]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[57]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[57]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[57]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[57]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[57]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[57]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[58]~FF (.D(\w_ddr3_wdata[58] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[58] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[58]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[58]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[58]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[58]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[58]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[58]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[58]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[59]~FF (.D(\w_ddr3_wdata[59] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[59] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[59]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[59]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[59]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[59]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[59]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[59]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[59]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[60]~FF (.D(\w_ddr3_wdata[60] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[60] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[60]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[60]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[60]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[60]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[60]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[60]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[60]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[61]~FF (.D(\w_ddr3_wdata[61] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[61] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[61]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[61]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[61]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[61]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[61]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[61]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[61]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[62]~FF (.D(\w_ddr3_wdata[62] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[62] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[62]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[62]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[62]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[62]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[62]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[62]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[62]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[63]~FF (.D(\w_ddr3_wdata[63] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[63] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[63]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[63]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[63]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[63]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[63]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[63]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[63]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[64]~FF (.D(\w_ddr3_wdata[64] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[64] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[64]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[64]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[64]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[64]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[64]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[64]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[64]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[65]~FF (.D(\w_ddr3_wdata[65] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[65] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[65]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[65]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[65]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[65]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[65]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[65]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[65]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[66]~FF (.D(\w_ddr3_wdata[66] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[66] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[66]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[66]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[66]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[66]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[66]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[66]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[66]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[67]~FF (.D(\w_ddr3_wdata[67] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[67] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[67]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[67]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[67]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[67]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[67]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[67]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[67]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[68]~FF (.D(\w_ddr3_wdata[68] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[68] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[68]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[68]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[68]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[68]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[68]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[68]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[68]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[69]~FF (.D(\w_ddr3_wdata[69] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[69] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[69]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[69]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[69]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[69]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[69]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[69]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[69]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[70]~FF (.D(\w_ddr3_wdata[70] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[70] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[70]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[70]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[70]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[70]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[70]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[70]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[70]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[71]~FF (.D(\w_ddr3_wdata[71] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[71] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[71]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[71]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[71]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[71]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[71]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[71]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[71]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[72]~FF (.D(\w_ddr3_wdata[72] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[72] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[72]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[72]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[72]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[72]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[72]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[72]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[72]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[73]~FF (.D(\w_ddr3_wdata[73] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[73] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[73]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[73]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[73]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[73]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[73]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[73]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[73]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[74]~FF (.D(\w_ddr3_wdata[74] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[74] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[74]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[74]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[74]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[74]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[74]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[74]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[74]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[75]~FF (.D(\w_ddr3_wdata[75] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[75] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[75]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[75]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[75]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[75]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[75]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[75]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[75]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[76]~FF (.D(\w_ddr3_wdata[76] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[76] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[76]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[76]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[76]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[76]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[76]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[76]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[76]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[77]~FF (.D(\w_ddr3_wdata[77] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[77] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[77]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[77]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[77]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[77]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[77]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[77]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[77]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[78]~FF (.D(\w_ddr3_wdata[78] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[78] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[78]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[78]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[78]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[78]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[78]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[78]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[78]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[79]~FF (.D(\w_ddr3_wdata[79] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[79] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[79]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[79]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[79]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[79]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[79]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[79]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[79]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[80]~FF (.D(\w_ddr3_wdata[80] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[80] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[80]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[80]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[80]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[80]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[80]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[80]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[80]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[81]~FF (.D(\w_ddr3_wdata[81] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[81] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[81]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[81]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[81]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[81]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[81]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[81]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[81]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[82]~FF (.D(\w_ddr3_wdata[82] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[82] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[82]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[82]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[82]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[82]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[82]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[82]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[82]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[83]~FF (.D(\w_ddr3_wdata[83] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[83] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[83]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[83]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[83]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[83]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[83]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[83]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[83]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[84]~FF (.D(\w_ddr3_wdata[84] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[84] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[84]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[84]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[84]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[84]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[84]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[84]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[84]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[85]~FF (.D(\w_ddr3_wdata[85] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[85] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[85]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[85]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[85]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[85]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[85]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[85]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[85]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[86]~FF (.D(\w_ddr3_wdata[86] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[86] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[86]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[86]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[86]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[86]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[86]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[86]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[86]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[87]~FF (.D(\w_ddr3_wdata[87] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[87] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[87]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[87]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[87]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[87]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[87]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[87]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[87]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[88]~FF (.D(\w_ddr3_wdata[88] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[88] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[88]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[88]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[88]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[88]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[88]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[88]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[88]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[89]~FF (.D(\w_ddr3_wdata[89] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[89] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[89]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[89]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[89]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[89]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[89]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[89]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[89]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[90]~FF (.D(\w_ddr3_wdata[90] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[90] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[90]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[90]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[90]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[90]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[90]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[90]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[90]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[91]~FF (.D(\w_ddr3_wdata[91] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[91] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[91]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[91]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[91]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[91]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[91]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[91]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[91]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[92]~FF (.D(\w_ddr3_wdata[92] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[92] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[92]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[92]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[92]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[92]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[92]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[92]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[92]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[93]~FF (.D(\w_ddr3_wdata[93] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[93] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[93]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[93]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[93]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[93]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[93]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[93]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[93]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[94]~FF (.D(\w_ddr3_wdata[94] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[94] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[94]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[94]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[94]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[94]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[94]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[94]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[94]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[95]~FF (.D(\w_ddr3_wdata[95] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[95] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[95]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[95]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[95]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[95]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[95]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[95]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[95]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[96]~FF (.D(\w_ddr3_wdata[96] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[96] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[96]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[96]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[96]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[96]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[96]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[96]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[96]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[97]~FF (.D(\w_ddr3_wdata[97] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[97] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[97]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[97]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[97]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[97]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[97]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[97]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[97]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[98]~FF (.D(\w_ddr3_wdata[98] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[98] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[98]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[98]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[98]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[98]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[98]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[98]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[98]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[99]~FF (.D(\w_ddr3_wdata[99] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[99] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[99]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[99]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[99]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[99]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[99]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[99]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[99]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[100]~FF (.D(\w_ddr3_wdata[100] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[100] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[100]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[100]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[100]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[100]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[100]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[100]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[100]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[101]~FF (.D(\w_ddr3_wdata[101] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[101] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[101]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[101]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[101]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[101]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[101]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[101]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[101]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[102]~FF (.D(\w_ddr3_wdata[102] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[102] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[102]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[102]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[102]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[102]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[102]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[102]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[102]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[103]~FF (.D(\w_ddr3_wdata[103] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[103] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[103]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[103]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[103]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[103]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[103]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[103]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[103]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[104]~FF (.D(\w_ddr3_wdata[104] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[104] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[104]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[104]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[104]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[104]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[104]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[104]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[104]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[105]~FF (.D(\w_ddr3_wdata[105] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[105] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[105]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[105]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[105]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[105]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[105]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[105]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[105]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[106]~FF (.D(\w_ddr3_wdata[106] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[106] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[106]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[106]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[106]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[106]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[106]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[106]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[106]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[107]~FF (.D(\w_ddr3_wdata[107] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[107] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[107]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[107]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[107]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[107]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[107]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[107]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[107]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[108]~FF (.D(\w_ddr3_wdata[108] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[108] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[108]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[108]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[108]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[108]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[108]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[108]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[108]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[109]~FF (.D(\w_ddr3_wdata[109] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[109] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[109]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[109]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[109]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[109]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[109]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[109]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[109]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[110]~FF (.D(\w_ddr3_wdata[110] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[110] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[110]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[110]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[110]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[110]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[110]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[110]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[110]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[111]~FF (.D(\w_ddr3_wdata[111] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[111] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[111]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[111]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[111]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[111]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[111]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[111]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[111]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[112]~FF (.D(\w_ddr3_wdata[112] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[112] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[112]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[112]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[112]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[112]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[112]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[112]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[112]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[113]~FF (.D(\w_ddr3_wdata[113] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[113] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[113]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[113]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[113]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[113]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[113]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[113]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[113]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[114]~FF (.D(\w_ddr3_wdata[114] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[114] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[114]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[114]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[114]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[114]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[114]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[114]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[114]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[115]~FF (.D(\w_ddr3_wdata[115] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[115] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[115]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[115]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[115]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[115]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[115]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[115]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[115]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[116]~FF (.D(\w_ddr3_wdata[116] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[116] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[116]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[116]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[116]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[116]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[116]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[116]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[116]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[117]~FF (.D(\w_ddr3_wdata[117] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[117] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[117]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[117]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[117]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[117]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[117]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[117]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[117]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[118]~FF (.D(\w_ddr3_wdata[118] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[118] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[118]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[118]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[118]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[118]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[118]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[118]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[118]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[119]~FF (.D(\w_ddr3_wdata[119] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[119] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[119]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[119]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[119]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[119]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[119]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[119]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[119]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[120]~FF (.D(\w_ddr3_wdata[120] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[120] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[120]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[120]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[120]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[120]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[120]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[120]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[120]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[121]~FF (.D(\w_ddr3_wdata[121] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[121] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[121]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[121]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[121]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[121]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[121]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[121]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[121]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[122]~FF (.D(\w_ddr3_wdata[122] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[122] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[122]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[122]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[122]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[122]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[122]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[122]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[122]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[123]~FF (.D(\w_ddr3_wdata[123] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[123] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[123]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[123]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[123]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[123]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[123]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[123]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[123]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[124]~FF (.D(\w_ddr3_wdata[124] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[124] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[124]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[124]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[124]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[124]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[124]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[124]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[124]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[125]~FF (.D(\w_ddr3_wdata[125] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[125] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[125]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[125]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[125]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[125]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[125]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[125]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[125]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[126]~FF (.D(\w_ddr3_wdata[126] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[126] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[126]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[126]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[126]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[126]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[126]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[126]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[126]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[127]~FF (.D(\w_ddr3_wdata[127] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[127] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[127]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[127]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[127]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[127]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[127]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[127]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[127]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1070 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1069 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1068 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1067 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1066 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1065 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1064 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1063 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1062 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1061 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1060 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1059 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1058 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1057 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1056 ), + .CE(ceg_net539), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[2] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[3] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[4] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[5] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[6] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[7] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_fifo_aw[41] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_i_arburst_fifo[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1377 ), + .CE(ceg_net376), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1376 ), + .CE(ceg_net376), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1375 ), + .CE(ceg_net376), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1374 ), + .CE(ceg_net376), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1373 ), + .CE(ceg_net376), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1372 ), + .CE(ceg_net376), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1371 ), + .CE(ceg_net376), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1370 ), + .CE(ceg_net376), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1053 ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1052 ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[7] ), + .CE(1'b1), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n571 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n570 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n569 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n568 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n567 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n566 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n565 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n564 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n563 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n562 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n561 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n560 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n559 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n558 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n557 ), + .CE(ceg_net2477), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1087 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[1]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[1]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1086 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[2]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[2]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1085 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[3]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[3]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1084 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[4]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[4]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1083 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[5]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[5]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1082 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[6]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[6]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1081 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[7]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[7]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1080 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[8]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[8]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1079 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[9]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[9]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1078 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[10]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[10]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1077 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[11]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[11]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1076 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[12]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[12]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1075 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[13]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[13]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1074 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[14]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[14]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1073 ), + .CE(ceg_net541), .CLK(clk_sys), .SR(1'b0), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[15]~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[15]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arburst_full~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/equal_40/n11 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n332 ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arburst_full )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arburst_full~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arburst_full~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arburst_full~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arburst_full~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arburst_full~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arburst_full~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arburst_full~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n49 ), + .CE(ceg_net577), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n48 ), + .CE(ceg_net577), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n47 ), + .CE(ceg_net577), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n46 ), + .CE(ceg_net577), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n45 ), + .CE(ceg_net577), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n44 ), + .CE(ceg_net577), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_araddr_full~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/equal_40/n11 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n860 ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_araddr_full )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_araddr_full~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_araddr_full~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_araddr_full~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_araddr_full~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_araddr_full~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_araddr_full~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_araddr_full~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n73 ), + .CE(ceg_net595), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n72 ), + .CE(ceg_net595), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n71 ), + .CE(ceg_net595), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n70 ), + .CE(ceg_net595), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n69 ), + .CE(ceg_net595), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n68 ), + .CE(ceg_net595), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_full~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/equal_40/n11 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n1212 ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_full )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_full~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_full~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_full~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_full~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_full~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_full~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_full~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n89 ), + .CE(ceg_net649), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n88 ), + .CE(ceg_net649), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n87 ), + .CE(ceg_net649), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n86 ), + .CE(ceg_net649), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n85 ), + .CE(ceg_net649), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n84 ), + .CE(ceg_net649), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awid_full~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/equal_40/n11 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n332 ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awid_full )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awid_full~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awid_full~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awid_full~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awid_full~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awid_full~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awid_full~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awid_full~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n49 ), + .CE(ceg_net685), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n48 ), + .CE(ceg_net685), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n47 ), + .CE(ceg_net685), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n46 ), + .CE(ceg_net685), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n45 ), + .CE(ceg_net685), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n44 ), + .CE(ceg_net685), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arid_full~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/equal_40/n11 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n332 ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arid_full )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arid_full~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arid_full~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arid_full~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arid_full~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arid_full~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arid_full~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arid_full~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n49 ), + .CE(ceg_net721), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n48 ), + .CE(ceg_net721), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n47 ), + .CE(ceg_net721), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n46 ), + .CE(ceg_net721), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n45 ), + .CE(ceg_net721), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n44 ), + .CE(ceg_net721), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/equal_40/n11 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Fifo_Wr_En ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n332 ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n49 ), + .CE(ceg_net739), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n48 ), + .CE(ceg_net739), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n47 ), + .CE(ceg_net739), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n46 ), + .CE(ceg_net739), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n45 ), + .CE(ceg_net739), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n44 ), + .CE(ceg_net739), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_full~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/equal_40/n11 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n332 ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_full )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_full~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_full~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_full~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_full~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_full~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_full~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_full~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n49 ), + .CE(ceg_net793), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n48 ), + .CE(ceg_net793), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n47 ), + .CE(ceg_net793), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n46 ), + .CE(ceg_net793), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n45 ), + .CE(ceg_net793), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n44 ), + .CE(ceg_net793), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Wr_Full~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/equal_40/n11 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n332 ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Wr_Full )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Wr_Full~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Wr_Full~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Wr_Full~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Wr_Full~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Wr_Full~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Wr_Full~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Wr_Full~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n49 ), + .CE(ceg_net811), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n48 ), + .CE(ceg_net811), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n47 ), + .CE(ceg_net811), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n46 ), + .CE(ceg_net811), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n45 ), + .CE(ceg_net811), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n44 ), + .CE(ceg_net811), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awlen_full~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/equal_40/n11 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n332 ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awlen_full )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awlen_full~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awlen_full~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awlen_full~FF .SR_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awlen_full~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awlen_full~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awlen_full~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awlen_full~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n49 ), + .CE(ceg_net847), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n48 ), + .CE(ceg_net847), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n47 ), + .CE(ceg_net847), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n46 ), + .CE(ceg_net847), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n45 ), + .CE(ceg_net847), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n44 ), + .CE(ceg_net847), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5]~FF .SR_SYNC = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2698 ), + .CE(ceg_net4213), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7743 ), + .CE(ceg_net3077), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_start_p0~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_start_p0 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_start_p0~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_start_p0~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_start_p0~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_start_p0~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_start_p0~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_start_p0~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_start_p0~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8147 ), + .CE(ceg_net879), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1742 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9160 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7719 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_en~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n3461 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_en~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_en~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_en~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_en~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_en~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_en~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_en~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_en~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n3529 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_en~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_en~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_en~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_en~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_en~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_en~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_en~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2838 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2896 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end~FF (.D(1'b1), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8144 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2863 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8304 ), + .CE(ceg_net886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7076 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/cal_fail_log[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2398 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/cal_fail_log[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/cal_fail_log[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2589 ), + .CE(ceg_net894), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2554 ), + .CE(ceg_net894), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2631 ), + .CE(ceg_net917), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2673 ), + .CE(ceg_net930), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7690 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8321 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_cal_done_2~FF (.D(1'b1), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8147 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(w_ddr3_cal_done)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \w_ddr3_cal_done_2~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_cal_done_2~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_cal_done_2~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_cal_done_2~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_cal_done_2~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_cal_done_2~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_cal_done_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7686 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8321 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_read~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2839 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_read )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_read~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_read~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_read~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_read~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_read~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_read~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_read~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel~FF (.D(w_ddr3_cal_done), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF (.D(1'b1), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \dsi_resetn_o~FF (.D(1'b1), .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), + .Q(dsi_resetn_o)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \dsi_resetn_o~FF .CLK_POLARITY = 1'b1; + defparam \dsi_resetn_o~FF .CE_POLARITY = 1'b1; + defparam \dsi_resetn_o~FF .SR_POLARITY = 1'b0; + defparam \dsi_resetn_o~FF .D_POLARITY = 1'b1; + defparam \dsi_resetn_o~FF .SR_SYNC = 1'b0; + defparam \dsi_resetn_o~FF .SR_VALUE = 1'b0; + defparam \dsi_resetn_o~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF (.D(dsi_resetn_o), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF (.D(1'b1), + .CE(1'b1), .CLK(core_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] ), + .CE(1'b1), .CLK(core_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] ), + .CE(1'b1), .CLK(core_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[3].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] ), + .CE(1'b1), .CLK(core_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[2].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF (.D(1'b1), + .CE(1'b1), .CLK(twd_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] ), + .CE(1'b1), .CLK(twd_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] ), + .CE(1'b1), .CLK(twd_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] ), + .CE(1'b1), .CLK(twd_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF (.D(1'b1), + .CE(1'b1), .CLK(tac_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] ), + .CE(1'b1), .CLK(tac_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] ), + .CE(1'b1), .CLK(tac_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[0] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[1] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl1/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n735 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[0]~FF .CLK_POLARITY = 1'b1; + defparam \addr[0]~FF .CE_POLARITY = 1'b1; + defparam \addr[0]~FF .SR_POLARITY = 1'b0; + defparam \addr[0]~FF .D_POLARITY = 1'b1; + defparam \addr[0]~FF .SR_SYNC = 1'b0; + defparam \addr[0]~FF .SR_VALUE = 1'b0; + defparam \addr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \cs~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n714 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(cs)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \cs~FF .CLK_POLARITY = 1'b1; + defparam \cs~FF .CE_POLARITY = 1'b1; + defparam \cs~FF .SR_POLARITY = 1'b0; + defparam \cs~FF .D_POLARITY = 1'b1; + defparam \cs~FF .SR_SYNC = 1'b0; + defparam \cs~FF .SR_VALUE = 1'b1; + defparam \cs~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ras~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n715 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(ras)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ras~FF .CLK_POLARITY = 1'b1; + defparam \ras~FF .CE_POLARITY = 1'b1; + defparam \ras~FF .SR_POLARITY = 1'b0; + defparam \ras~FF .D_POLARITY = 1'b1; + defparam \ras~FF .SR_SYNC = 1'b0; + defparam \ras~FF .SR_VALUE = 1'b1; + defparam \ras~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \cas~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n716 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(cas)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \cas~FF .CLK_POLARITY = 1'b1; + defparam \cas~FF .CE_POLARITY = 1'b1; + defparam \cas~FF .SR_POLARITY = 1'b0; + defparam \cas~FF .D_POLARITY = 1'b1; + defparam \cas~FF .SR_SYNC = 1'b0; + defparam \cas~FF .SR_VALUE = 1'b1; + defparam \cas~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \we~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n717 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(we)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \we~FF .CLK_POLARITY = 1'b1; + defparam \we~FF .CE_POLARITY = 1'b1; + defparam \we~FF .SR_POLARITY = 1'b0; + defparam \we~FF .D_POLARITY = 1'b1; + defparam \we~FF .SR_SYNC = 1'b0; + defparam \we~FF .SR_VALUE = 1'b1; + defparam \we~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \cke~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n718 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(cke)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \cke~FF .CLK_POLARITY = 1'b1; + defparam \cke~FF .CE_POLARITY = 1'b1; + defparam \cke~FF .SR_POLARITY = 1'b0; + defparam \cke~FF .D_POLARITY = 1'b1; + defparam \cke~FF .SR_SYNC = 1'b0; + defparam \cke~FF .SR_VALUE = 1'b0; + defparam \cke~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ba[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n739 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(ba[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ba[0]~FF .CLK_POLARITY = 1'b1; + defparam \ba[0]~FF .CE_POLARITY = 1'b1; + defparam \ba[0]~FF .SR_POLARITY = 1'b0; + defparam \ba[0]~FF .D_POLARITY = 1'b1; + defparam \ba[0]~FF .SR_SYNC = 1'b0; + defparam \ba[0]~FF .SR_VALUE = 1'b0; + defparam \ba[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \odt~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n740 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(odt)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \odt~FF .CLK_POLARITY = 1'b1; + defparam \odt~FF .CE_POLARITY = 1'b1; + defparam \odt~FF .SR_POLARITY = 1'b0; + defparam \odt~FF .D_POLARITY = 1'b1; + defparam \odt~FF .SR_SYNC = 1'b0; + defparam \odt~FF .SR_VALUE = 1'b0; + defparam \odt~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/rst_ctrl0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[2] ), + .CE(1'b1), .CLK(tac_clk), .SR(rstn_sys), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \reset~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n713 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(reset)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \reset~FF .CLK_POLARITY = 1'b1; + defparam \reset~FF .CE_POLARITY = 1'b1; + defparam \reset~FF .SR_POLARITY = 1'b0; + defparam \reset~FF .D_POLARITY = 1'b1; + defparam \reset~FF .SR_SYNC = 1'b0; + defparam \reset~FF .SR_VALUE = 1'b1; + defparam \reset~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n442 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n447 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n452 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n457 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n462 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n467 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n293 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n292 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n291 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n290 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n289 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n477 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n482 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n487 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n492 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n497 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n502 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n335 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n334 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n333 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n332 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n331 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n442 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n447 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n452 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n457 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n462 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n293 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n292 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n291 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n290 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n289 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n467 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n477 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n482 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n487 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n492 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n497 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n502 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n335 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n334 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n333 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n332 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n331 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1002 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1007 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1012 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1017 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1022 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1027 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n741 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n740 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n739 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n738 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n737 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1037 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1042 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1047 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1052 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1057 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1062 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n783 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n782 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n781 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n780 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n779 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n308 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n303 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n298 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n293 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n288 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n283 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n166 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n165 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n164 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n163 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n162 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n318 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n323 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n328 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n333 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n338 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n343 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n208 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n207 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n206 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n205 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n204 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n922 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n927 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n932 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n937 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n942 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n677 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n676 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n675 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n674 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n673 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n947 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 ), + .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n957 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n962 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n967 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n972 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n977 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n982 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n719 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n718 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n717 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n716 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n715 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n317 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n312 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n307 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n302 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n297 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n292 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n173 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n172 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n171 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n170 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n169 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n327 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n332 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n337 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n342 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n347 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n352 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n215 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n214 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n213 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n212 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n211 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n542 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n547 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n552 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n557 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n562 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n567 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[4] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[3] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[2] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[0] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[1] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[5] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[6] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc/buffers_0[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n373 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n372 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n371 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n370 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n369 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n577 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n582 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n587 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n592 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n597 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n602 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n415 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n414 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n413 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n412 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n411 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n734 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[1]~FF .CLK_POLARITY = 1'b1; + defparam \addr[1]~FF .CE_POLARITY = 1'b1; + defparam \addr[1]~FF .SR_POLARITY = 1'b0; + defparam \addr[1]~FF .D_POLARITY = 1'b1; + defparam \addr[1]~FF .SR_SYNC = 1'b0; + defparam \addr[1]~FF .SR_VALUE = 1'b0; + defparam \addr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n733 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[2]~FF .CLK_POLARITY = 1'b1; + defparam \addr[2]~FF .CE_POLARITY = 1'b1; + defparam \addr[2]~FF .SR_POLARITY = 1'b0; + defparam \addr[2]~FF .D_POLARITY = 1'b1; + defparam \addr[2]~FF .SR_SYNC = 1'b0; + defparam \addr[2]~FF .SR_VALUE = 1'b0; + defparam \addr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n732 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[3])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[3]~FF .CLK_POLARITY = 1'b1; + defparam \addr[3]~FF .CE_POLARITY = 1'b1; + defparam \addr[3]~FF .SR_POLARITY = 1'b0; + defparam \addr[3]~FF .D_POLARITY = 1'b1; + defparam \addr[3]~FF .SR_SYNC = 1'b0; + defparam \addr[3]~FF .SR_VALUE = 1'b0; + defparam \addr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n731 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[4])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[4]~FF .CLK_POLARITY = 1'b1; + defparam \addr[4]~FF .CE_POLARITY = 1'b1; + defparam \addr[4]~FF .SR_POLARITY = 1'b0; + defparam \addr[4]~FF .D_POLARITY = 1'b1; + defparam \addr[4]~FF .SR_SYNC = 1'b0; + defparam \addr[4]~FF .SR_VALUE = 1'b0; + defparam \addr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n730 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[5])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[5]~FF .CLK_POLARITY = 1'b1; + defparam \addr[5]~FF .CE_POLARITY = 1'b1; + defparam \addr[5]~FF .SR_POLARITY = 1'b0; + defparam \addr[5]~FF .D_POLARITY = 1'b1; + defparam \addr[5]~FF .SR_SYNC = 1'b0; + defparam \addr[5]~FF .SR_VALUE = 1'b0; + defparam \addr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n729 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[6])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[6]~FF .CLK_POLARITY = 1'b1; + defparam \addr[6]~FF .CE_POLARITY = 1'b1; + defparam \addr[6]~FF .SR_POLARITY = 1'b0; + defparam \addr[6]~FF .D_POLARITY = 1'b1; + defparam \addr[6]~FF .SR_SYNC = 1'b0; + defparam \addr[6]~FF .SR_VALUE = 1'b0; + defparam \addr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n728 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[7])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[7]~FF .CLK_POLARITY = 1'b1; + defparam \addr[7]~FF .CE_POLARITY = 1'b1; + defparam \addr[7]~FF .SR_POLARITY = 1'b0; + defparam \addr[7]~FF .D_POLARITY = 1'b1; + defparam \addr[7]~FF .SR_SYNC = 1'b0; + defparam \addr[7]~FF .SR_VALUE = 1'b0; + defparam \addr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n727 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[8])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[8]~FF .CLK_POLARITY = 1'b1; + defparam \addr[8]~FF .CE_POLARITY = 1'b1; + defparam \addr[8]~FF .SR_POLARITY = 1'b0; + defparam \addr[8]~FF .D_POLARITY = 1'b1; + defparam \addr[8]~FF .SR_SYNC = 1'b0; + defparam \addr[8]~FF .SR_VALUE = 1'b0; + defparam \addr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n726 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[9])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[9]~FF .CLK_POLARITY = 1'b1; + defparam \addr[9]~FF .CE_POLARITY = 1'b1; + defparam \addr[9]~FF .SR_POLARITY = 1'b0; + defparam \addr[9]~FF .D_POLARITY = 1'b1; + defparam \addr[9]~FF .SR_SYNC = 1'b0; + defparam \addr[9]~FF .SR_VALUE = 1'b0; + defparam \addr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n725 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[10])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[10]~FF .CLK_POLARITY = 1'b1; + defparam \addr[10]~FF .CE_POLARITY = 1'b1; + defparam \addr[10]~FF .SR_POLARITY = 1'b0; + defparam \addr[10]~FF .D_POLARITY = 1'b1; + defparam \addr[10]~FF .SR_SYNC = 1'b0; + defparam \addr[10]~FF .SR_VALUE = 1'b0; + defparam \addr[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n724 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[11])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[11]~FF .CLK_POLARITY = 1'b1; + defparam \addr[11]~FF .CE_POLARITY = 1'b1; + defparam \addr[11]~FF .SR_POLARITY = 1'b0; + defparam \addr[11]~FF .D_POLARITY = 1'b1; + defparam \addr[11]~FF .SR_SYNC = 1'b0; + defparam \addr[11]~FF .SR_VALUE = 1'b0; + defparam \addr[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n723 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[12])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[12]~FF .CLK_POLARITY = 1'b1; + defparam \addr[12]~FF .CE_POLARITY = 1'b1; + defparam \addr[12]~FF .SR_POLARITY = 1'b0; + defparam \addr[12]~FF .D_POLARITY = 1'b1; + defparam \addr[12]~FF .SR_SYNC = 1'b0; + defparam \addr[12]~FF .SR_VALUE = 1'b0; + defparam \addr[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n722 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[13])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[13]~FF .CLK_POLARITY = 1'b1; + defparam \addr[13]~FF .CE_POLARITY = 1'b1; + defparam \addr[13]~FF .SR_POLARITY = 1'b0; + defparam \addr[13]~FF .D_POLARITY = 1'b1; + defparam \addr[13]~FF .SR_SYNC = 1'b0; + defparam \addr[13]~FF .SR_VALUE = 1'b0; + defparam \addr[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n721 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[14])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[14]~FF .CLK_POLARITY = 1'b1; + defparam \addr[14]~FF .CE_POLARITY = 1'b1; + defparam \addr[14]~FF .SR_POLARITY = 1'b0; + defparam \addr[14]~FF .D_POLARITY = 1'b1; + defparam \addr[14]~FF .SR_SYNC = 1'b0; + defparam \addr[14]~FF .SR_VALUE = 1'b0; + defparam \addr[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \addr[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n720 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(addr[15])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \addr[15]~FF .CLK_POLARITY = 1'b1; + defparam \addr[15]~FF .CE_POLARITY = 1'b1; + defparam \addr[15]~FF .SR_POLARITY = 1'b0; + defparam \addr[15]~FF .D_POLARITY = 1'b1; + defparam \addr[15]~FF .SR_SYNC = 1'b0; + defparam \addr[15]~FF .SR_VALUE = 1'b0; + defparam \addr[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ba[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n738 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(ba[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ba[1]~FF .CLK_POLARITY = 1'b1; + defparam \ba[1]~FF .CE_POLARITY = 1'b1; + defparam \ba[1]~FF .SR_POLARITY = 1'b0; + defparam \ba[1]~FF .D_POLARITY = 1'b1; + defparam \ba[1]~FF .SR_SYNC = 1'b0; + defparam \ba[1]~FF .SR_VALUE = 1'b0; + defparam \ba[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ba[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n737 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(ba[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ba[2]~FF .CLK_POLARITY = 1'b1; + defparam \ba[2]~FF .CE_POLARITY = 1'b1; + defparam \ba[2]~FF .SR_POLARITY = 1'b0; + defparam \ba[2]~FF .D_POLARITY = 1'b1; + defparam \ba[2]~FF .SR_SYNC = 1'b0; + defparam \ba[2]~FF .SR_VALUE = 1'b0; + defparam \ba[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .CE(ceg_net932), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_1~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_0 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_1 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_1~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_1~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_1~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_1~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_1~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_1~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_1~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_0_2~FF (.D(1'b0), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_0 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_0_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_0_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_0_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_0_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_0_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_0_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_0_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[0] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1626 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[1]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[1]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[1]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[1]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[1]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[1]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1625 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[2]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[2]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[2]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[2]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[2]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[2]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1624 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[3])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[3]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[3]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[3]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[3]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[3]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[3]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1623 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[4])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[4]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[4]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[4]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[4]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[4]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[4]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1622 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[5])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[5]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[5]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[5]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[5]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[5]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[5]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1621 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[6])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[6]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[6]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[6]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[6]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[6]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[6]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1620 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[7])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[7]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[7]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[7]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[7]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[7]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[7]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1619 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[8])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[8]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[8]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[8]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[8]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[8]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[8]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1618 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[9])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[9]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[9]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[9]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[9]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[9]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[9]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1617 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[10])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[10]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[10]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[10]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[10]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[10]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[10]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1616 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[11])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[11]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[11]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[11]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[11]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[11]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[11]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1615 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[12])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[12]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[12]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[12]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[12]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[12]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[12]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1614 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[13])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[13]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[13]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[13]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[13]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[13]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[13]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1613 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[14])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[14]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[14]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[14]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[14]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[14]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[14]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1612 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[15])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[15]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[15]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[15]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[15]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[15]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[15]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe_p0[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe[15] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe_p0[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe_p0[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe_p0[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe_p0[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe_p0[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe_p0[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe_p0[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_dq_oe_p0[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1646 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8136 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1650 ), + .CE(ceg_net938), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1649 ), + .CE(ceg_net938), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1643 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[1]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[1]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[1]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[1]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[1]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[1]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1642 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[2]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[2]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[2]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[2]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[2]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[2]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1641 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[3])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[3]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[3]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[3]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[3]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[3]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[3]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1640 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[4])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[4]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[4]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[4]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[4]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[4]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[4]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1639 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[5])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[5]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[5]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[5]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[5]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[5]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[5]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1638 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[6])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[6]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[6]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[6]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[6]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[6]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[6]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1637 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[7])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[7]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[7]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[7]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[7]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[7]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[7]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1636 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[8])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[8]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[8]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[8]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[8]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[8]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[8]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1635 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[9])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[9]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[9]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[9]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[9]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[9]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[9]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1634 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[10])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[10]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[10]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[10]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[10]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[10]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[10]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1633 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[11])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[11]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[11]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[11]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[11]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[11]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[11]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1632 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[12])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[12]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[12]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[12]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[12]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[12]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[12]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1631 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[13])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[13]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[13]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[13]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[13]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[13]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[13]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1630 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[14])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[14]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[14]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[14]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[14]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[14]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[14]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1629 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[15])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[15]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[15]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[15]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[15]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[15]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[15]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1521 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[0] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[1] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[3] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[4] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[5] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[6] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[7] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][82]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][82] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][82] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][82]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][82]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][82]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][82]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][82]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][82]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][82]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][83]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][83] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][83] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][83]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][83]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][83]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][83]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][83]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][83]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][83]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][84]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][84] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][84] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][84]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][84]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][84]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][84]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][84]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][84]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][84]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][85]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][85] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][85] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][85]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][85]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][85]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][85]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][85]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][85]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][85]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][86]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][86] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][86] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][86]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][86]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][86]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][86]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][86]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][86]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][86]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][87]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][87] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][87] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][87]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][87]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][87]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][87]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][87]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][87]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][87]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][88]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][88] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][88] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][88]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][88]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][88]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][88]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][88]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][88]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][88]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][89]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][89] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][89] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][89]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][89]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][89]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][89]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][89]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][89]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][89]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][90]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][90] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][90] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][90]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][90]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][90]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][90]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][90]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][90]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][90]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][91]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][91] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][91] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][91]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][91]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][91]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][91]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][91]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][91]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][91]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][92]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][92] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][92] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][92]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][92]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][92]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][92]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][92]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][92]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][92]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][93]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][93] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][93] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][93]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][93]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][93]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][93]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][93]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][93]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][93]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][94]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][94] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][94] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][94]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][94]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][94]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][94]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][94]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][94]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][94]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][95]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][95] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][95] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][95]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][95]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][95]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][95]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][95]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][95]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][95]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][96]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][96] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][96] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][96]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][96]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][96]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][96]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][96]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][96]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][96]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][97]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][97] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][97] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][97]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][97]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][97]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][97]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][97]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][97]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][97]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][98]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][98] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][98] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][98]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][98]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][98]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][98]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][98]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][98]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][98]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][99]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][99] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][99] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][99]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][99]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][99]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][99]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][99]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][99]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][99]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][100]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][100] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][100] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][100]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][100]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][100]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][100]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][100]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][100]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][100]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][101]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][101] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][101] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][101]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][101]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][101]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][101]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][101]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][101]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][101]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][102]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][102] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][102] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][102]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][102]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][102]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][102]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][102]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][102]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][102]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][103]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][103] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][103] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][103]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][103]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][103]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][103]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][103]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][103]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][103]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][104]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][104] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][104] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][104]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][104]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][104]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][104]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][104]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][104]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][104]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][105]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][105] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][105] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][105]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][105]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][105]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][105]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][105]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][105]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][105]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][106]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][106] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][106] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][106]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][106]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][106]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][106]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][106]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][106]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][106]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][107]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][107] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][107] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][107]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][107]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][107]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][107]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][107]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][107]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][107]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][108]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][108] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][108] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][108]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][108]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][108]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][108]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][108]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][108]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][108]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][109]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][109] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][109] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][109]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][109]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][109]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][109]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][109]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][109]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][109]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][110]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][110] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][110] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][110]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][110]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][110]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][110]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][110]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][110]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][110]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][111]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][111] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][111] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][111]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][111]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][111]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][111]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][111]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][111]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][111]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][112]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][112] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][112] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][112]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][112]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][112]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][112]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][112]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][112]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][112]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][113]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][113] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][113] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][113]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][113]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][113]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][113]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][113]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][113]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][113]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][114]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][114] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][114] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][114]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][114]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][114]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][114]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][114]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][114]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][114]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][115]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][115] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][115] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][115]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][115]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][115]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][115]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][115]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][115]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][115]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][116]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][116] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][116] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][116]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][116]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][116]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][116]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][116]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][116]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][116]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][117]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][117] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][117] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][117]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][117]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][117]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][117]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][117]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][117]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][117]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][118]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][118] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][118] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][118]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][118]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][118]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][118]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][118]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][118]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][118]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][119]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][119] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][119] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][119]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][119]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][119]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][119]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][119]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][119]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][119]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][120]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][120] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][120] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][120]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][120]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][120]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][120]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][120]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][120]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][120]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][121]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][121] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][121] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][121]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][121]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][121]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][121]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][121]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][121]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][121]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][122]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][122] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][122] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][122]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][122]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][122]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][122]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][122]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][122]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][122]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][123]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][123] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][123] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][123]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][123]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][123]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][123]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][123]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][123]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][123]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][124]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][124] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][124] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][124]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][124]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][124]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][124]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][124]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][124]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][124]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][125]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][125] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][125] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][125]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][125]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][125]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][125]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][125]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][125]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][125]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][126]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][126] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][126] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][126]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][126]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][126]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][126]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][126]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][126]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][126]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][127]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][127] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][127] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][127]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][127]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][127]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][127]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][127]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][127]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][127]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][1] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][2] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][3] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][4] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][5] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][6] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][7] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][8] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][9] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][10] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][11] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][12] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][13] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][14] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][15] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i10_rst_0~FF (.D(1'b0), .CE(1'b1), .CLK(clk_sys), + .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i10_rst_0 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i10_rst_0~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_0~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_0~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_0~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_0~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i10_rst_0~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_0~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_3~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_2 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_3 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_3~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_3~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_3~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_3~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_3~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_3~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_3~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_2_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_1 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_2_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_2_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_2_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_2_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_2_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_2_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_2_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_1_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_0 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_1 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_1_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_1_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_1_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_1_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_1_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_1_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_1_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_0_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_7 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_0 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_0_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_0_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_0_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_0_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_0_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_0_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_0_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_en~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_rd_fifo_wr_en_p[11] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_en~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_en~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_en~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_en~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_en~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_en~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_en~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dm_lo[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1512 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dm_lo[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dm_lo[1]~FF .CLK_POLARITY = 1'b1; + defparam \o_dm_lo[1]~FF .CE_POLARITY = 1'b1; + defparam \o_dm_lo[1]~FF .SR_POLARITY = 1'b0; + defparam \o_dm_lo[1]~FF .D_POLARITY = 1'b1; + defparam \o_dm_lo[1]~FF .SR_SYNC = 1'b0; + defparam \o_dm_lo[1]~FF .SR_VALUE = 1'b0; + defparam \o_dm_lo[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][97]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][97] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][97] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][97]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][97]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][97]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][97]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][97]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][97]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][97]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][98]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][98] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][98] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][98]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][98]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][98]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][98]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][98]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][98]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][98]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][99]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][99] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][99] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][99]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][99]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][99]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][99]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][99]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][99]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][99]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][100]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][100] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][100] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][100]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][100]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][100]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][100]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][100]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][100]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][100]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][101]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][101] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][101] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][101]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][101]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][101]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][101]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][101]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][101]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][101]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][102]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][102] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][102] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][102]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][102]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][102]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][102]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][102]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][102]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][102]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][103]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][103] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][103] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][103]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][103]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][103]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][103]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][103]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][103]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][103]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][104]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][104] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][104] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][104]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][104]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][104]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][104]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][104]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][104]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][104]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][105]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][105] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][105] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][105]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][105]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][105]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][105]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][105]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][105]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][105]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][106]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][106] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][106] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][106]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][106]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][106]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][106]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][106]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][106]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][106]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][107]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][107] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][107] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][107]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][107]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][107]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][107]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][107]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][107]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][107]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][108]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][108] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][108] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][108]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][108]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][108]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][108]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][108]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][108]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][108]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][109]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][109] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][109] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][109]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][109]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][109]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][109]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][109]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][109]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][109]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][110]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][110] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][110] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][110]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][110]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][110]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][110]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][110]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][110]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][110]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][111]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][111] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][111] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][111]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][111]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][111]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][111]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][111]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][111]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][111]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][112]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][112] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][112] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][112]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][112]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][112]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][112]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][112]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][112]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][112]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][113]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][113] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][113] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][113]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][113]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][113]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][113]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][113]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][113]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][113]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][114]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][114] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][114] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][114]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][114]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][114]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][114]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][114]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][114]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][114]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][115]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][115] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][115] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][115]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][115]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][115]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][115]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][115]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][115]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][115]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][116]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][116] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][116] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][116]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][116]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][116]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][116]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][116]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][116]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][116]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][117]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][117] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][117] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][117]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][117]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][117]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][117]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][117]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][117]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][117]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][118]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][118] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][118] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][118]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][118]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][118]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][118]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][118]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][118]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][118]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][119]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][119] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][119] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][119]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][119]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][119]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][119]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][119]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][119]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][119]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][120]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][120] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][120] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][120]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][120]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][120]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][120]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][120]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][120]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][120]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][121]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][121] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][121] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][121]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][121]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][121]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][121]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][121]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][121]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][121]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][122]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][122] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][122] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][122]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][122]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][122]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][122]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][122]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][122]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][122]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][123]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][123] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][123] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][123]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][123]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][123]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][123]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][123]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][123]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][123]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][124]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][124] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][124] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][124]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][124]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][124]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][124]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][124]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][124]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][124]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][125]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][125] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][125] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][125]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][125]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][125]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][125]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][125]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][125]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][125]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][126]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][126] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][126] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][126]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][126]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][126]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][126]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][126]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][126]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][126]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][127]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][127] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][127] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][127]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][127]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][127]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][127]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][127]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][127]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][127]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][1] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][2] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][3] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][4] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][5] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][6] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][7]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][7] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][7]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][7]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][7]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][7]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][7]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][7]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][7]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][8]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][8] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][8]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][8]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][8]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][8]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][8]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][8]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][8]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][9]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][9] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][9]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][9]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][9]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][9]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][9]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][9]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][9]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][10]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][10] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][10]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][10]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][10]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][10]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][10]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][10]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][10]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][11]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][11] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][11]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][11]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][11]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][11]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][11]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][11]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][11]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][12]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][12] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][12]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][12]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][12]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][12]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][12]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][12]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][12]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][13]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][13] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][13]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][13]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][13]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][13]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][13]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][13]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][13]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][14]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][14] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][14]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][14]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][14]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][14]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][14]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][14]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][14]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][15]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][15] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][15]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][15]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][15]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][15]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][15]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][15]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][15]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][1] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][2] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][3] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][4] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][5] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][6] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][7] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][8] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][9] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][10] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][11] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][12] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][13] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][14] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][15] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][16]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][16] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][16]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][16]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][16]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][16]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][16]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][16]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][17]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][17] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][17]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][17]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][17]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][17]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][17]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][17]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][18]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][18] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][18]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][18]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][18]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][18]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][18]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][18]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][19]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][19] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][19]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][19]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][19]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][19]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][19]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][19]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][20]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][20] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][20]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][20]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][20]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][20]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][20]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][20]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][21]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][21] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][21]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][21]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][21]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][21]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][21]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][21]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][22]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][22] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][22]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][22]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][22]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][22]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][22]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][22]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][23]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][23] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][23]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][23]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][23]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][23]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][23]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][23]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][24]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][24] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][24]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][24]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][24]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][24]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][24]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][24]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][25]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][25] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][25]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][25]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][25]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][25]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][25]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][25]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][26]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][26] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][26]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][26]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][26]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][26]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][26]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][26]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][27]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][27] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][27]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][27]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][27]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][27]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][27]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][27]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][28]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][28] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][28]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][28]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][28]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][28]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][28]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][28]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][29]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][29] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][29]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][29]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][29]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][29]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][29]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][29]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][29]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][30]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][30] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][30]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][30]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][30]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][30]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][30]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][30]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][30]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][31]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][31] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][31]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][31]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][31]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][31]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][31]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][31]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][31]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][32]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][32] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][32] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][32]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][32]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][32]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][32]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][32]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][32]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][32]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][33]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][33] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][33] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][33]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][33]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][33]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][33]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][33]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][33]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][33]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][34]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][34] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][34] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][34]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][34]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][34]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][34]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][34]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][34]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][34]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][35]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][35] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][35] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][35]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][35]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][35]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][35]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][35]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][35]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][35]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][36]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][36] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][36] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][36]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][36]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][36]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][36]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][36]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][36]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][36]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][37]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][37] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][37] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][37]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][37]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][37]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][37]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][37]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][37]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][37]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][38]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][38] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][38] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][38]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][38]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][38]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][38]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][38]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][38]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][38]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][39]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][39] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][39] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][39]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][39]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][39]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][39]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][39]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][39]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][39]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][40]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][40] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][40] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][40]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][40]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][40]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][40]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][40]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][40]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][40]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][41]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][41] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][41] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][41]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][41]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][41]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][41]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][41]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][41]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][41]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][42]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][42] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][42] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][42]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][42]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][42]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][42]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][42]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][42]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][42]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][43]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][43] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][43] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][43]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][43]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][43]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][43]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][43]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][43]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][43]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][44]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][44] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][44] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][44]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][44]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][44]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][44]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][44]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][44]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][44]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][45]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][45] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][45] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][45]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][45]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][45]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][45]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][45]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][45]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][45]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][46]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][46] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][46] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][46]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][46]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][46]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][46]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][46]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][46]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][46]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][47]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][47] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][47] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][47]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][47]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][47]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][47]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][47]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][47]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][47]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][48]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][48] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][48] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][48]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][48]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][48]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][48]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][48]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][48]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][48]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][49]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][49] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][49] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][49]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][49]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][49]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][49]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][49]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][49]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][49]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][50]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][50] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][50] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][50]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][50]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][50]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][50]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][50]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][50]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][50]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][51]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][51] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][51] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][51]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][51]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][51]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][51]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][51]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][51]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][51]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][52]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][52] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][52] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][52]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][52]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][52]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][52]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][52]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][52]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][52]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][53]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][53] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][53] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][53]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][53]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][53]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][53]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][53]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][53]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][53]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][54]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][54] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][54] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][54]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][54]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][54]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][54]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][54]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][54]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][54]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][55]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][55] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][55] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][55]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][55]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][55]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][55]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][55]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][55]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][55]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][56]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][56] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][56] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][56]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][56]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][56]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][56]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][56]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][56]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][56]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][57]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][57] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][57] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][57]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][57]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][57]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][57]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][57]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][57]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][57]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][58]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][58] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][58] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][58]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][58]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][58]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][58]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][58]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][58]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][58]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][59]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][59] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][59] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][59]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][59]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][59]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][59]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][59]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][59]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][59]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][60]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][60] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][60] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][60]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][60]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][60]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][60]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][60]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][60]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][60]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][61]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][61] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][61] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][61]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][61]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][61]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][61]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][61]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][61]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][61]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][62]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][62] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][62] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][62]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][62]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][62]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][62]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][62]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][62]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][62]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][63]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][63] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][63] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][63]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][63]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][63]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][63]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][63]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][63]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][63]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][64]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][64] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][64] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][64]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][64]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][64]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][64]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][64]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][64]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][64]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][65]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][65] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][65] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][65]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][65]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][65]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][65]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][65]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][65]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][65]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][66]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][66] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][66] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][66]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][66]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][66]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][66]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][66]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][66]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][66]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][67]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][67] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][67] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][67]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][67]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][67]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][67]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][67]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][67]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][67]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][68]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][68] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][68] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][68]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][68]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][68]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][68]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][68]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][68]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][68]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][69]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][69] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][69] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][69]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][69]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][69]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][69]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][69]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][69]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][69]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][70]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][70] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][70] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][70]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][70]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][70]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][70]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][70]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][70]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][70]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][71]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][71] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][71] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][71]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][71]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][71]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][71]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][71]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][71]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][71]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][72]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][72] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][72] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][72]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][72]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][72]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][72]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][72]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][72]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][72]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][73]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][73] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][73] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][73]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][73]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][73]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][73]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][73]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][73]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][73]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][74]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][74] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][74] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][74]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][74]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][74]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][74]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][74]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][74]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][74]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][75]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][75] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][75] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][75]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][75]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][75]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][75]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][75]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][75]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][75]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][76]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][76] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][76] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][76]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][76]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][76]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][76]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][76]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][76]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][76]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][77]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][77] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][77] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][77]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][77]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][77]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][77]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][77]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][77]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][77]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][78]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][78] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][78] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][78]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][78]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][78]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][78]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][78]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][78]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][78]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][79]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][79] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][79] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][79]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][79]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][79]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][79]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][79]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][79]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][79]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][80]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][80] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][80] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][80]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][80]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][80]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][80]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][80]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][80]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][80]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][81]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][81] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][81] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][81]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][81]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][81]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][81]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][81]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][81]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][81]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][0] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][0] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][1] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][2]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][2] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][2]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][2]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][2]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][2]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][2]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][2]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][3]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][3] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][3]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][3]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][3]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][3]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][3]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][3]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][3]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][4]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][4] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][4]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][4]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][4]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][4]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][4]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][4]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][5]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][5] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][5]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][5]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][5]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][5]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][5]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][5]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][5]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][6]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][6] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][6]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][6]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][6]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][6]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][6]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][6]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][7]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][7] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][7]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][7]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][7]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][7]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][7]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][7]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][7]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][8]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][8] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][8]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][8]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][8]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][8]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][8]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][8]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][8]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][9]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][9] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][9]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][9]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][9]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][9]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][9]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][9]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][9]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][10]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][10] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][10]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][10]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][10]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][10]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][10]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][10]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][10]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][11]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][11] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][11]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][11]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][11]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][11]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][11]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][11]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][11]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][12]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][12] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][12]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][12]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][12]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][12]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][12]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][12]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][12]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][13]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][13] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][13]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][13]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][13]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][13]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][13]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][13]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][13]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][14]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][14] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][14]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][14]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][14]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][14]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][14]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][14]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][14]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][15]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][15] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][15]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][15]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][15]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][15]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][15]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][15]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][15]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][16]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][16] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][16]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][16]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][16]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][16]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][16]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][16]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][16]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][17]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][17] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][17]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][17]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][17]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][17]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][17]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][17]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][17]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][18]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][18] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][18]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][18]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][18]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][18]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][18]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][18]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][18]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][19]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][19] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][19]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][19]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][19]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][19]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][19]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][19]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][19]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][20]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][20] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][20]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][20]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][20]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][20]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][20]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][20]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][20]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][21]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][21] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][21]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][21]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][21]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][21]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][21]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][21]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][21]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][22]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][22] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][22]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][22]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][22]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][22]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][22]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][22]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][22]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][23]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][23] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][23]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][23]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][23]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][23]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][23]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][23]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][23]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][24]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][24] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][24]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][24]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][24]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][24]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][24]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][24]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][24]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][25]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][25] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][25]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][25]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][25]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][25]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][25]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][25]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][25]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][26]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][26] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][26]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][26]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][26]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][26]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][26]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][26]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][26]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][27]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][27] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][27]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][27]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][27]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][27]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][27]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][27]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][27]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][28]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][28] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][28]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][28]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][28]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][28]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][28]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][28]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][28]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][29]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][29] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][29]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][29]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][29]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][29]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][29]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][29]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][29]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][30]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][30] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][30]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][30]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][30]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][30]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][30]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][30]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][30]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][31]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][31] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][31]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][31]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][31]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][31]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][31]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][31]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][31]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][32]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][32] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][32] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][32]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][32]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][32]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][32]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][32]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][32]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][32]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][33]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][33] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][33] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][33]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][33]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][33]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][33]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][33]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][33]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][33]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][34]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][34] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][34] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][34]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][34]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][34]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][34]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][34]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][34]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][34]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][35]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][35] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][35] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][35]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][35]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][35]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][35]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][35]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][35]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][35]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][36]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][36] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][36] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][36]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][36]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][36]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][36]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][36]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][36]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][36]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][37]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][37] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][37] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][37]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][37]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][37]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][37]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][37]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][37]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][37]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][38]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][38] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][38] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][38]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][38]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][38]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][38]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][38]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][38]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][38]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][39]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][39] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][39] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][39]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][39]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][39]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][39]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][39]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][39]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][39]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][40]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][40] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][40] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][40]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][40]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][40]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][40]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][40]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][40]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][40]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][41]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][41] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][41] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][41]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][41]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][41]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][41]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][41]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][41]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][41]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][42]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][42] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][42] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][42]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][42]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][42]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][42]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][42]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][42]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][42]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][43]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][43] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][43] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][43]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][43]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][43]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][43]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][43]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][43]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][43]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][44]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][44] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][44] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][44]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][44]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][44]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][44]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][44]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][44]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][44]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][45]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][45] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][45] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][45]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][45]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][45]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][45]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][45]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][45]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][45]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][46]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][46] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][46] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][46]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][46]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][46]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][46]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][46]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][46]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][46]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][47]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][47] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][47] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][47]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][47]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][47]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][47]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][47]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][47]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][47]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][48]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][48] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][48] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][48]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][48]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][48]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][48]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][48]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][48]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][48]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][49]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][49] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][49] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][49]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][49]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][49]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][49]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][49]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][49]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][49]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][50]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][50] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][50] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][50]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][50]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][50]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][50]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][50]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][50]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][50]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][51]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][51] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][51] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][51]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][51]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][51]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][51]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][51]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][51]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][51]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][52]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][52] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][52] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][52]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][52]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][52]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][52]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][52]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][52]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][52]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][53]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][53] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][53] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][53]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][53]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][53]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][53]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][53]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][53]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][53]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][54]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][54] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][54] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][54]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][54]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][54]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][54]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][54]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][54]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][54]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][55]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][55] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][55] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][55]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][55]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][55]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][55]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][55]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][55]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][55]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][56]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][56] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][56] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][56]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][56]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][56]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][56]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][56]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][56]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][56]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][57]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][57] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][57] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][57]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][57]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][57]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][57]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][57]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][57]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][57]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][58]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][58] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][58] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][58]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][58]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][58]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][58]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][58]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][58]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][58]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][59]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][59] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][59] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][59]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][59]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][59]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][59]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][59]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][59]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][59]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][60]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][60] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][60] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][60]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][60]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][60]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][60]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][60]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][60]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][60]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][61]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][61] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][61] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][61]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][61]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][61]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][61]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][61]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][61]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][61]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][62]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][62] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][62] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][62]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][62]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][62]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][62]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][62]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][62]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][62]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][63]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][63] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][63] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][63]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][63]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][63]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][63]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][63]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][63]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][63]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][64]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][64] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][64] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][64]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][64]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][64]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][64]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][64]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][64]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][64]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][65]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][65] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][65] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][65]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][65]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][65]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][65]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][65]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][65]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][65]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][66]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][66] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][66] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][66]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][66]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][66]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][66]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][66]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][66]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][66]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][67]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][67] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][67] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][67]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][67]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][67]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][67]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][67]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][67]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][67]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][68]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][68] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][68] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][68]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][68]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][68]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][68]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][68]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][68]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][68]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][69]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][69] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][69] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][69]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][69]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][69]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][69]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][69]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][69]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][69]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][70]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][70] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][70] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][70]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][70]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][70]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][70]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][70]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][70]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][70]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][71]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][71] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][71] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][71]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][71]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][71]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][71]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][71]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][71]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][71]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][72]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][72] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][72] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][72]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][72]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][72]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][72]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][72]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][72]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][72]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][73]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][73] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][73] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][73]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][73]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][73]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][73]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][73]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][73]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][73]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][74]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][74] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][74] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][74]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][74]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][74]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][74]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][74]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][74]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][74]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][75]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][75] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][75] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][75]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][75]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][75]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][75]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][75]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][75]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][75]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][76]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][76] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][76] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][76]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][76]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][76]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][76]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][76]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][76]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][76]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][77]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][77] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][77] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][77]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][77]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][77]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][77]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][77]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][77]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][77]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][78]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][78] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][78] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][78]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][78]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][78]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][78]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][78]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][78]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][78]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][79]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][79] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][79] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][79]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][79]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][79]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][79]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][79]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][79]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][79]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][80]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][80] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][80] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][80]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][80]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][80]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][80]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][80]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][80]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][80]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][81]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][81] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][81] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][81]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][81]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][81]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][81]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][81]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][81]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][81]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][82]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][82] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][82] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][82]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][82]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][82]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][82]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][82]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][82]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][82]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][83]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][83] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][83] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][83]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][83]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][83]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][83]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][83]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][83]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][83]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][84]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][84] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][84] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][84]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][84]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][84]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][84]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][84]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][84]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][84]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][85]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][85] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][85] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][85]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][85]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][85]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][85]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][85]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][85]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][85]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][86]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][86] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][86] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][86]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][86]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][86]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][86]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][86]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][86]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][86]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][87]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][87] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][87] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][87]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][87]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][87]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][87]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][87]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][87]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][87]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][88]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][88] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][88] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][88]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][88]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][88]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][88]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][88]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][88]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][88]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][89]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][89] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][89] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][89]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][89]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][89]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][89]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][89]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][89]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][89]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][90]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][90] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][90] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][90]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][90]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][90]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][90]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][90]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][90]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][90]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][91]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][91] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][91] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][91]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][91]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][91]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][91]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][91]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][91]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][91]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][92]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][92] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][92] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][92]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][92]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][92]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][92]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][92]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][92]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][92]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][93]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][93] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][93] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][93]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][93]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][93]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][93]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][93]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][93]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][93]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][94]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][94] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][94] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][94]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][94]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][94]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][94]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][94]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][94]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][94]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][95]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][95] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][95] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][95]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][95]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][95]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][95]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][95]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][95]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][95]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][96]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][96] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][96] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][96]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][96]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][96]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][96]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][96]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][96]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][96]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[8][0] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[8][0] ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_3~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_2 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_3 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_3~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_3~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_3~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_3~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_3~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_3~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_3~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i10_rst_1~FF (.D(\u_axi4_ctrl/dff_138/i10_rst_0 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i10_rst_1 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i10_rst_1~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_1~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_1~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_1~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_1~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i10_rst_1~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_1~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2471 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dm_lo[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1502 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dm_lo[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dm_lo[0]~FF .CLK_POLARITY = 1'b1; + defparam \o_dm_lo[0]~FF .CE_POLARITY = 1'b1; + defparam \o_dm_lo[0]~FF .SR_POLARITY = 1'b0; + defparam \o_dm_lo[0]~FF .D_POLARITY = 1'b1; + defparam \o_dm_lo[0]~FF .SR_SYNC = 1'b0; + defparam \o_dm_lo[0]~FF .SR_VALUE = 1'b0; + defparam \o_dm_lo[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2472 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_hi[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1644 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_hi[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_hi[0]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_hi[0]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_hi[0]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_hi[0]~FF .D_POLARITY = 1'b1; + defparam \o_dq_hi[0]~FF .SR_SYNC = 1'b0; + defparam \o_dq_hi[0]~FF .SR_VALUE = 1'b0; + defparam \o_dq_hi[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dq_lo[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1627 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dq_lo[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dq_lo[0]~FF .CLK_POLARITY = 1'b1; + defparam \o_dq_lo[0]~FF .CE_POLARITY = 1'b1; + defparam \o_dq_lo[0]~FF .SR_POLARITY = 1'b0; + defparam \o_dq_lo[0]~FF .D_POLARITY = 1'b1; + defparam \o_dq_lo[0]~FF .SR_SYNC = 1'b0; + defparam \o_dq_lo[0]~FF .SR_VALUE = 1'b0; + defparam \o_dq_lo[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1647 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_2_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_1 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_2_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_2_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_2_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_2_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_2_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_2_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_2_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dqs_n_oe[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/equal_1648/n7 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8010 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(o_dqs_oe[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dqs_n_oe[1]~FF .CLK_POLARITY = 1'b1; + defparam \o_dqs_n_oe[1]~FF .CE_POLARITY = 1'b1; + defparam \o_dqs_n_oe[1]~FF .SR_POLARITY = 1'b0; + defparam \o_dqs_n_oe[1]~FF .D_POLARITY = 1'b1; + defparam \o_dqs_n_oe[1]~FF .SR_SYNC = 1'b0; + defparam \o_dqs_n_oe[1]~FF .SR_VALUE = 1'b0; + defparam \o_dqs_n_oe[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2072 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2185 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2184 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2183 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2182 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2181 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2180 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2179 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2178 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2177 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2176 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2175 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2174 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2173 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2172 ), + .CE(ceg_net947), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2169 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[0] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p1 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2475 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2474 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2473 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2073 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2170 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[0]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[0]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[0]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[0]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[0]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[0]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2476 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1977 ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[0]~FF (.D(i_dq_hi[0]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[0]~FF (.D(i_dqs_hi[0]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[1] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4141 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2529 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dm_hi[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1503 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dm_hi[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dm_hi[0]~FF .CLK_POLARITY = 1'b1; + defparam \o_dm_hi[0]~FF .CE_POLARITY = 1'b1; + defparam \o_dm_hi[0]~FF .SR_POLARITY = 1'b0; + defparam \o_dm_hi[0]~FF .D_POLARITY = 1'b1; + defparam \o_dm_hi[0]~FF .SR_SYNC = 1'b0; + defparam \o_dm_hi[0]~FF .SR_VALUE = 1'b0; + defparam \o_dm_hi[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2470 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2469 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2531 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2530 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4694 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4684 ), + .CE(ceg_net4223), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4658 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4602 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8097 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_p ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4679 ), + .CE(ceg_net1009), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_p_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_ack ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_p )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_p_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_p_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_p_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_p_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_p_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_p_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_p_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_ack ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p1_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_ack ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p1 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p1_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p1_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p1_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p1_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p1_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p1_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_wr_ack_p1_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4651 ), + .CE(ceg_net1122), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[28] ), + .CE(ceg_net1019), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done_2~FF (.D(1'b1), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8092 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_start_count~FF (.D(1'b0), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8089 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_start_count )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_start_count~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_start_count~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_start_count~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_start_count~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_start_count~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_start_count~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_start_count~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3413 ), + .CE(ceg_net1023), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3858 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[0]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[0]~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8096 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4712 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3139 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_addr_re~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4892 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_addr_re )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_addr_re~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_addr_re~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_addr_re~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_addr_re~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_addr_re~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_addr_re~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_addr_re~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_addr_re~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4893 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_addr_re )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_addr_re~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_addr_re~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_addr_re~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_addr_re~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_addr_re~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_addr_re~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_addr_re~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_push~FF (.D(1'b1), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_push )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_push~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_push~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_push~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_push~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_push~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_push~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_push~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cs~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cs_p ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cs )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cs~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cs~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cs~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cs~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cs~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cs~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cs~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ras~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ras_p ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ras )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ras~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ras~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ras~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ras~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ras~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ras~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ras~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cas~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cas_p ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cas )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cas~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cas~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cas~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cas~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cas~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cas~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cas~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_we~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_we_p ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_we )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_we~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_we~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_we~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_we~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_we~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_we~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_we~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cke~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3146 ), + .CE(ceg_net1036), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cke )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cke~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cke~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cke~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cke~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cke~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cke~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cke~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3143 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3164 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p1 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cs~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cs_p ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cs )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cs~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cs~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cs~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cs~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cs~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cs~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cs~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn~FF (.D(1'b1), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8016 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ras~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ras_p ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ras )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ras~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ras~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ras~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ras~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ras~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ras~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ras~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cas~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cas_p ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cas )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cas~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cas~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cas~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cas~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cas~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cas~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cas~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_we~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_we_p ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_we )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_we~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_we~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_we~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_we~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_we~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_we~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_we~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cke~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3147 ), + .CE(ceg_net1036), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cke )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cke~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cke~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cke~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cke~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cke~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cke~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cke~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3185 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[45] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p0~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3190 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p0 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p0~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p0~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p0~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p0~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p0~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p0~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p0~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p1_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p0 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p1 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p1_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p1_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p1_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p1_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p1_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p1_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_odt_p1_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cs_p_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[68] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cs_p )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cs_p_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cs_p_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cs_p_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cs_p_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cs_p_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cs_p_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cs_p_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ras_p_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[67] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ras_p )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ras_p_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ras_p_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ras_p_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ras_p_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ras_p_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ras_p_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ras_p_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cas_p_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[66] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cas_p )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cas_p_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cas_p_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cas_p_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cas_p_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cas_p_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cas_p_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_cas_p_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_we_p_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[65] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_we_p )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_we_p_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_we_p_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_we_p_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_we_p_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_we_p_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_we_p_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_we_p_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[61] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3091 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cs_p_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[32] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cs_p )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cs_p_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cs_p_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cs_p_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cs_p_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cs_p_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cs_p_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cs_p_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ras_p_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[31] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ras_p )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ras_p_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ras_p_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ras_p_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ras_p_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ras_p_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ras_p_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ras_p_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cas_p_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[30] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cas_p )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cas_p_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cas_p_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cas_p_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cas_p_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cas_p_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cas_p_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_cas_p_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_we_p_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[29] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_we_p )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_we_p_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_we_p_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_we_p_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_we_p_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_we_p_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_we_p_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_we_p_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3101 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[0]~FF (.D(1'b0), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[0]~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2528 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2527 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2526 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2525 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2524 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[16]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2468 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[16]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[16]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[16]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[16]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[16]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[16]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[17]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2467 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[17]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[17]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[17]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[17]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[17]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[17]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[18]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2466 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[18]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[18]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[18]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[18]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[18]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[18]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[19]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2465 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[19]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[19]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[19]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[19]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[19]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[19]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[20]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2464 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[20]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[20]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[20]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[20]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[20]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[20]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[21]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2463 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[21]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[21]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[21]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[21]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[21]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[21]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[22]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2462 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[22]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[22]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[22]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[22]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[22]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[22]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[23]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2461 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[23]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[23]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[23]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[23]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[23]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[23]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[24]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2523 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[24]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[24]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[24]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[24]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[24]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[24]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[25]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2522 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[25]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[25]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[25]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[25]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[25]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[25]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[26]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2521 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[26]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[26]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[26]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[26]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[26]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[26]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[27]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2520 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[27]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[27]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[27]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[27]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[27]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[27]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[28]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2519 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[28]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[28]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[28]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[28]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[28]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[28]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[29]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2518 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[29]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[29]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[29]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[29]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[29]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[29]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[29]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[30]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2517 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[30]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[30]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[30]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[30]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[30]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[30]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[30]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[31]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2516 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[31]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[31]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[31]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[31]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[31]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[31]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[31]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[0] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[1] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[2] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[3] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[4] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[5] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[6] ), + .CE(1'b1), .CLK(tdqss_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tdqss_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[1]~FF (.D(i_dq_hi[1]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[2]~FF (.D(i_dq_hi[2]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[3]~FF (.D(i_dq_hi[3]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[4]~FF (.D(i_dq_hi[4]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[5]~FF (.D(i_dq_hi[5]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[6]~FF (.D(i_dq_hi[6]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[7]~FF (.D(i_dq_hi[7]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[8]~FF (.D(i_dq_hi[8]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[9]~FF (.D(i_dq_hi[9]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[10]~FF (.D(i_dq_hi[10]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[11]~FF (.D(i_dq_hi[11]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[12]~FF (.D(i_dq_hi[12]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[13]~FF (.D(i_dq_hi[13]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[14]~FF (.D(i_dq_hi[14]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[15]~FF (.D(i_dq_hi[15]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[1]~FF (.D(i_dqs_hi[1]), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[16]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[16]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[16]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[16]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[16]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[16]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[16]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[17]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[17]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[17]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[17]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[17]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[17]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[17]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[18]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[18]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[18]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[18]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[18]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[18]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[18]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[19]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[19]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[19]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[19]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[19]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[19]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[19]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[20]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[20]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[20]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[20]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[20]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[20]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[20]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[21]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[21]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[21]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[21]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[21]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[21]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[21]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[22]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[22]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[22]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[22]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[22]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[22]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[22]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[23]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[23]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[23]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[23]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[23]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[23]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[23]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[24]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[24]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[24]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[24]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[24]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[24]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[24]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[25]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[25]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[25]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[25]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[25]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[25]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[25]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[26]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[26]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[26]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[26]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[26]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[26]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[26]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[27]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[27]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[27]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[27]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[27]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[27]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[27]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[28]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[28]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[28]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[28]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[28]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[28]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[28]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[29]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[29]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[29]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[29]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[29]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[29]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[29]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[29]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[30]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[30]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[30]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[30]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[30]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[30]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[30]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[30]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[31]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[31]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[31]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[31]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[31]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[31]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[31]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[31]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[0] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[1] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[2] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[3] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[4] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[5] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[6] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[7] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[8] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[9] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[10] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[11] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[12] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[13] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[14] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[15] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[16] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[17] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[18] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[19] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[20] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[21] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[22] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[23] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[24] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[25] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[26] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[27] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[28] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[29] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[30] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_buf[31] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[0] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1] ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \o_dm_hi[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1513 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(o_dm_hi[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \o_dm_hi[1]~FF .CLK_POLARITY = 1'b1; + defparam \o_dm_hi[1]~FF .CE_POLARITY = 1'b1; + defparam \o_dm_hi[1]~FF .SR_POLARITY = 1'b0; + defparam \o_dm_hi[1]~FF .D_POLARITY = 1'b1; + defparam \o_dm_hi[1]~FF .SR_SYNC = 1'b0; + defparam \o_dm_hi[1]~FF .SR_VALUE = 1'b0; + defparam \o_dm_hi[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4693 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4692 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4691 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4690 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4689 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4688 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4687 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7]~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4686 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4683 ), + .CE(ceg_net4223), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4682 ), + .CE(ceg_net4223), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[1]_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0, async_reg="true" */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[1]_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[1]_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[1]_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[1]_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[1]_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_a[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3438 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3190 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3437 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3190 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3436 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3190 ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4650 ), + .CE(ceg_net1122), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4649 ), + .CE(ceg_net1122), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4648 ), + .CE(ceg_net1122), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4647 ), + .CE(ceg_net1122), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4646 ), + .CE(ceg_net1122), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4645 ), + .CE(ceg_net1122), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4644 ), + .CE(ceg_net1122), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3857 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3856 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3855 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3854 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3853 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3852 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3851 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3850 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3849 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3848 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3847 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3846 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3845 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3844 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3843 ), + .CE(ceg_net2599), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3858 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3857 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3856 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3855 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3854 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3853 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3852 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3851 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3850 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3849 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3848 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3847 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3846 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3845 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3844 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3843 ), + .CE(ceg_net2663), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3858 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3857 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3856 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3855 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3854 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3853 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3852 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3851 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3850 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3849 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3848 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3847 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3846 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3845 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3844 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3843 ), + .CE(ceg_net2727), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3858 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3857 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3856 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3855 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3854 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3853 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3852 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3851 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3850 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3849 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3848 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3847 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3846 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3845 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3844 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3843 ), + .CE(ceg_net2791), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3858 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3857 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3856 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3855 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3854 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3853 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3852 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3851 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3850 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3849 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3848 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3847 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3846 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3845 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3844 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3843 ), + .CE(ceg_net2855), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3858 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3857 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3856 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3855 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3854 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3853 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3852 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3851 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3850 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3849 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3848 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3847 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3846 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3845 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3844 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3843 ), + .CE(ceg_net2919), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3858 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3857 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3856 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3855 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3854 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3853 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3852 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3851 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3850 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3849 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3848 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3847 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3846 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3845 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3844 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3843 ), + .CE(ceg_net2983), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3858 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3857 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3856 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3855 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3854 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3853 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3852 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3851 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3850 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3849 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3848 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3847 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3846 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3845 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3844 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3843 ), + .CE(ceg_net3047), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[7][15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[6][15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[5][15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[4][15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[3][15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[2][15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[1][15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][0] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated[0][15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4728 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4727 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4726 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4725 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4724 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4723 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4722 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4721 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4720 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4719 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4718 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4717 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4716 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4715 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4714 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4711 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4710 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4709 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4708 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4707 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4706 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4705 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4704 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4703 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4702 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4701 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4700 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4699 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4698 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4697 ), + .CE(ceg_net1030), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3331 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3330 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3329 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3328 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3327 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3326 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3325 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3324 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3323 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3322 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3321 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3320 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3319 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3318 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3317 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[16] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[17] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[18] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[19] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[20] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[21] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[22] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[23] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[24] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[25] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[26] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[27] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[28] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[16] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[17] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[18] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[19] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[20] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[21] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[22] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[23] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[24] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[25] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[26] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[27] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[28] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p0[9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p0[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p0[9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[1] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p0[2] ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3138 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3137 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3136 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3135 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3134 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3133 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3132 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3131 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3130 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3129 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3128 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3127 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3126 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3125 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3124 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3142 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3141 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3163 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3162 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3161 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3160 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3159 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3158 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3157 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3156 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3155 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3154 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3153 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3152 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3151 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3150 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3149 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3184 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3183 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[46] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[47] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[48] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[49] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[50] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[51] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[52] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[53] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[8]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[54] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[9]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[55] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[10]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[56] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[11]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[57] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[12]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[58] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[13]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[59] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[14]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[60] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[15]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[62] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[63] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3090 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3089 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3088 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3087 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3086 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3085 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3084 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3083 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3082 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3061 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3060 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3059 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3058 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3057 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3056 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3100 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3099 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n45 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n44 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n43 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n42 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n41 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n40 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n39 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n38 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n37 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n36 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n35 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n34 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n33 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n32 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n31 ), + .CE(1'b1), .CLK(core_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/core_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n55 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \shift_ena~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n50 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(shift_ena)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \shift_ena~FF .CLK_POLARITY = 1'b1; + defparam \shift_ena~FF .CE_POLARITY = 1'b1; + defparam \shift_ena~FF .SR_POLARITY = 1'b0; + defparam \shift_ena~FF .D_POLARITY = 1'b1; + defparam \shift_ena~FF .SR_SYNC = 1'b0; + defparam \shift_ena~FF .SR_VALUE = 1'b0; + defparam \shift_ena~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \shift[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n43 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(shift[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \shift[0]~FF .CLK_POLARITY = 1'b1; + defparam \shift[0]~FF .CE_POLARITY = 1'b1; + defparam \shift[0]~FF .SR_POLARITY = 1'b0; + defparam \shift[0]~FF .D_POLARITY = 1'b1; + defparam \shift[0]~FF .SR_SYNC = 1'b0; + defparam \shift[0]~FF .SR_VALUE = 1'b0; + defparam \shift[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_busy~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_busy )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_busy~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_busy~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_busy~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_busy~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_busy~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_busy~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_busy~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/ena_p~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/ena_p )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/ena_p~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/ena_p~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/ena_p~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/ena_p~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/ena_p~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/ena_p~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/ena_p~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n97 ), + .CE(ceg_net1790), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start_2~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start_2~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start_2~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n54 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n53 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n52 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \shift[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n42 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(shift[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \shift[1]~FF .CLK_POLARITY = 1'b1; + defparam \shift[1]~FF .CE_POLARITY = 1'b1; + defparam \shift[1]~FF .SR_POLARITY = 1'b0; + defparam \shift[1]~FF .D_POLARITY = 1'b1; + defparam \shift[1]~FF .SR_SYNC = 1'b0; + defparam \shift[1]~FF .SR_VALUE = 1'b0; + defparam \shift[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \shift[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n41 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(shift[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \shift[2]~FF .CLK_POLARITY = 1'b1; + defparam \shift[2]~FF .CE_POLARITY = 1'b1; + defparam \shift[2]~FF .SR_POLARITY = 1'b0; + defparam \shift[2]~FF .D_POLARITY = 1'b1; + defparam \shift[2]~FF .SR_SYNC = 1'b0; + defparam \shift[2]~FF .SR_VALUE = 1'b0; + defparam \shift[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2697 ), + .CE(ceg_net4213), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2696 ), + .CE(ceg_net4213), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2695 ), + .CE(ceg_net4213), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6308 ), + .CE(ceg_net3077), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1658 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9160 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9160 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1652 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9160 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1658 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9160 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9160 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1742 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9160 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1652 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9160 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5630 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5637 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5644 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5651 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5658 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5665 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5672 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5679 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5686 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5693 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5700 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5707 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5714 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5721 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5728 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5735 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5742 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5749 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5756 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5763 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5770 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5777 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5784 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5791 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5798 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5805 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5812 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5819 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5826 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5833 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5840 ), + .CE(ceg_net3886), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7726 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5847 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5854 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5861 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5868 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5875 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5882 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5889 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5896 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5903 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5910 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5917 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5924 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5931 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5938 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5945 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5952 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5959 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5966 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5973 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5980 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5987 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5994 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6001 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6008 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6015 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6022 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6029 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6036 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6043 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6050 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6057 ), + .CE(ceg_net4402), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7737 ), + .CE(ceg_net3459), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2837 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2836 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2835 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2834 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2833 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2832 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2831 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2830 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2829 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2828 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2827 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2826 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2825 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2824 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2823 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2822 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2821 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2820 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2819 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2818 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2817 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2816 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2815 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2814 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2813 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2812 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2811 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2810 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2809 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2808 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2807 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2895 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2894 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2893 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2892 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2891 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2890 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2889 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2888 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2887 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2886 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2885 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2884 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2883 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2882 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2881 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2880 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2879 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2878 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2877 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2876 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2875 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2874 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2873 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2872 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2871 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2870 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2869 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2868 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2867 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2866 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2865 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2862 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/cal_shift_val[0]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2693 ), + .CE(ceg_net3510), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/cal_shift_val[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/cal_shift_val[0]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_shift_val[0]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[0]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[0]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_shift_val[0]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[0]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/cal_shift_val[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2692 ), + .CE(ceg_net3510), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/cal_shift_val[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/cal_shift_val[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_shift_val[1]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_shift_val[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/cal_shift_val[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2691 ), + .CE(ceg_net3510), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/cal_shift_val[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/cal_shift_val[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_shift_val[2]~FF .CE_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_shift_val[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/cal_shift_val[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/cal_fail_log[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2397 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/cal_fail_log[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/cal_fail_log[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/cal_fail_log[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2396 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/cal_fail_log[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/cal_fail_log[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/cal_fail_log[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2395 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/cal_fail_log[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/cal_fail_log[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/cal_fail_log[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2394 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/cal_fail_log[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/cal_fail_log[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/cal_fail_log[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2393 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/cal_fail_log[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/cal_fail_log[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/cal_fail_log[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2392 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/cal_fail_log[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/cal_fail_log[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/cal_fail_log[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/cal_fail_log[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2391 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2588 ), + .CE(ceg_net894), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5447 ), + .CE(ceg_net894), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2553 ), + .CE(ceg_net894), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2]~FF (.D(ceg_net2135), + .CE(ceg_net894), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2630 ), + .CE(ceg_net917), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5457 ), + .CE(ceg_net917), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[3]~FF (.D(1'b1), + .CE(ceg_net917), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2672 ), + .CE(ceg_net930), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5469 ), + .CE(ceg_net930), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2]~FF .D_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5542 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8321 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5546 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8321 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5550 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8321 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5530 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8321 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5534 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8321 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5538 ), + .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8321 ), + .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1336 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1335 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1334 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1333 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1332 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1331 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1330 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1329 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1328 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1327 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1326 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1325 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1324 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1323 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15]~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1322 ), + .CE(w_ddr3_rvalid), .CLK(clk_sys), .SR(w_ddr3_cal_done), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15]~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15]~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15]~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15]~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15]~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15]~FF .SR_VALUE = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \axi4_awar_mux/rs_req[0]~FF (.D(\axi4_awar_mux/n50 ), .CE(1'b1), + .CLK(clk_sys), .SR(rstn_sys), .Q(\axi4_awar_mux/rs_req[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\AXI4_AWARMux.v(105) + defparam \axi4_awar_mux/rs_req[0]~FF .CLK_POLARITY = 1'b1; + defparam \axi4_awar_mux/rs_req[0]~FF .CE_POLARITY = 1'b1; + defparam \axi4_awar_mux/rs_req[0]~FF .SR_POLARITY = 1'b0; + defparam \axi4_awar_mux/rs_req[0]~FF .D_POLARITY = 1'b1; + defparam \axi4_awar_mux/rs_req[0]~FF .SR_SYNC = 1'b1; + defparam \axi4_awar_mux/rs_req[0]~FF .SR_VALUE = 1'b0; + defparam \axi4_awar_mux/rs_req[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awready~FF (.D(w_ddr3_atype), .CE(1'b1), .CLK(clk_sys), + .SR(\axi4_awar_mux/n129 ), .Q(w_ddr3_awready)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\AXI4_AWARMux.v(105) + defparam \w_ddr3_awready~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awready~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awready~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awready~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awready~FF .SR_SYNC = 1'b1; + defparam \w_ddr3_awready~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awready~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_avalid~FF (.D(\axi4_awar_mux/n52 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(w_ddr3_avalid)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\AXI4_AWARMux.v(105) + defparam \w_ddr3_avalid~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_avalid~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_avalid~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_avalid~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_avalid~FF .SR_SYNC = 1'b1; + defparam \w_ddr3_avalid~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_avalid~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_atype_2~FF (.D(w_ddr3_atype), .CE(\axi4_awar_mux/n45 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(w_ddr3_atype)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\AXI4_AWARMux.v(105) + defparam \w_ddr3_atype_2~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_atype_2~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_atype_2~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_atype_2~FF .D_POLARITY = 1'b0; + defparam \w_ddr3_atype_2~FF .SR_SYNC = 1'b1; + defparam \w_ddr3_atype_2~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_atype_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_arready~FF (.D(w_ddr3_atype), .CE(1'b1), .CLK(clk_sys), + .SR(\axi4_awar_mux/n129 ), .Q(w_ddr3_arready)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\AXI4_AWARMux.v(105) + defparam \w_ddr3_arready~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_arready~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_arready~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_arready~FF .D_POLARITY = 1'b0; + defparam \w_ddr3_arready~FF .SR_SYNC = 1'b1; + defparam \w_ddr3_arready~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_arready~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \axi4_awar_mux/rs_req[1]~FF (.D(\axi4_awar_mux/n49 ), .CE(1'b1), + .CLK(clk_sys), .SR(rstn_sys), .Q(\axi4_awar_mux/rs_req[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\AXI4_AWARMux.v(105) + defparam \axi4_awar_mux/rs_req[1]~FF .CLK_POLARITY = 1'b1; + defparam \axi4_awar_mux/rs_req[1]~FF .CE_POLARITY = 1'b1; + defparam \axi4_awar_mux/rs_req[1]~FF .SR_POLARITY = 1'b0; + defparam \axi4_awar_mux/rs_req[1]~FF .D_POLARITY = 1'b1; + defparam \axi4_awar_mux/rs_req[1]~FF .SR_SYNC = 1'b1; + defparam \axi4_awar_mux/rs_req[1]~FF .SR_VALUE = 1'b0; + defparam \axi4_awar_mux/rs_req[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[0]~FF (.D(\u_i2c_timing_ctrl_16bit/n137 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_ctrl_clk~FF (.D(\u_i2c_timing_ctrl_16bit/n138 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_ctrl_clk )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/i2c_ctrl_clk~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_ctrl_clk~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_ctrl_clk~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_ctrl_clk~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_ctrl_clk~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_ctrl_clk~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_ctrl_clk~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_transfer_en~FF (.D(\u_i2c_timing_ctrl_16bit/n139 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_transfer_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/i2c_transfer_en~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_transfer_en~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_transfer_en~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_transfer_en~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_transfer_en~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_transfer_en~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_transfer_en~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \sc130_i2c_config_index[0]~FF (.D(\u_i2c_timing_ctrl_16bit/n198 ), + .CE(\u_i2c_timing_ctrl_16bit/n497 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\sc130_i2c_config_index[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(173) + defparam \sc130_i2c_config_index[0]~FF .CLK_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[0]~FF .CE_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[0]~FF .SR_POLARITY = 1'b0; + defparam \sc130_i2c_config_index[0]~FF .D_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[0]~FF .SR_SYNC = 1'b0; + defparam \sc130_i2c_config_index[0]~FF .SR_VALUE = 1'b0; + defparam \sc130_i2c_config_index[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0]~FF (.D(\u_i2c_timing_ctrl_16bit/n333 ), + .CE(ceg_net2242), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_wdata[0]~FF (.D(\u_i2c_timing_ctrl_16bit/n818 ), + .CE(ceg_net4099), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_wdata[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[0]~FF .CE_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[0]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[0]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[0]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[0]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[0]~FF (.D(\u_i2c_timing_ctrl_16bit/delay_cnt[0] ), + .CE(\u_i2c_timing_ctrl_16bit/n7 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[0]~FF .D_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \csi_sda_o~FF (.D(\u_i2c_timing_ctrl_16bit/n328 ), .CE(ceg_net4409), + .CLK(clk_sys), .SR(rstn_sys), .Q(csi_sda_o)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \csi_sda_o~FF .CLK_POLARITY = 1'b1; + defparam \csi_sda_o~FF .CE_POLARITY = 1'b1; + defparam \csi_sda_o~FF .SR_POLARITY = 1'b0; + defparam \csi_sda_o~FF .D_POLARITY = 1'b1; + defparam \csi_sda_o~FF .SR_SYNC = 1'b0; + defparam \csi_sda_o~FF .SR_VALUE = 1'b1; + defparam \csi_sda_o~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[1]~FF (.D(\u_i2c_timing_ctrl_16bit/n136 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[2]~FF (.D(\u_i2c_timing_ctrl_16bit/n135 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[2]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[3]~FF (.D(\u_i2c_timing_ctrl_16bit/n134 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[3]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[4]~FF (.D(\u_i2c_timing_ctrl_16bit/n133 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[4]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[4]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[4]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[4]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[4]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[5]~FF (.D(\u_i2c_timing_ctrl_16bit/n132 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[5]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[5]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[5]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[5]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[5]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[6]~FF (.D(\u_i2c_timing_ctrl_16bit/n131 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[6]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[6]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[6]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[6]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[6]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[7]~FF (.D(\u_i2c_timing_ctrl_16bit/n130 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[7]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[7]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[7]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[7]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[7]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[8]~FF (.D(\u_i2c_timing_ctrl_16bit/n129 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[8]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[8]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[8]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[8]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[8]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[9]~FF (.D(\u_i2c_timing_ctrl_16bit/n128 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[9]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[9]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[9]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[9]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[9]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[10]~FF (.D(\u_i2c_timing_ctrl_16bit/n127 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[10]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[10]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[10]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[10]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[10]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[11]~FF (.D(\u_i2c_timing_ctrl_16bit/n126 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[11]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[11]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[11]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[11]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[11]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[12]~FF (.D(\u_i2c_timing_ctrl_16bit/n125 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[12]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[12]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[12]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[12]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[12]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[13]~FF (.D(\u_i2c_timing_ctrl_16bit/n124 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[13]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[13]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[13]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[13]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[13]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[14]~FF (.D(\u_i2c_timing_ctrl_16bit/n123 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[14]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[14]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[14]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[14]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[14]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[14]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/clk_cnt[15]~FF (.D(\u_i2c_timing_ctrl_16bit/n122 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/clk_cnt[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(119) + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[15]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[15]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[15]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[15]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[15]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[15]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/clk_cnt[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/current_state[0]~FF (.D(\u_i2c_timing_ctrl_16bit/next_state[0] ), + .CE(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/current_state[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(146) + defparam \u_i2c_timing_ctrl_16bit/current_state[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[0]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[0]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[0]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[0]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[0]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/current_state[1]~FF (.D(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .CE(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/current_state[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(146) + defparam \u_i2c_timing_ctrl_16bit/current_state[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[1]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[1]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[1]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[1]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[1]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/current_state[2]~FF (.D(\u_i2c_timing_ctrl_16bit/next_state[2] ), + .CE(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/current_state[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(146) + defparam \u_i2c_timing_ctrl_16bit/current_state[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[2]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[2]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[2]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[2]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[2]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/current_state[3]~FF (.D(\u_i2c_timing_ctrl_16bit/next_state[3] ), + .CE(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/current_state[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(146) + defparam \u_i2c_timing_ctrl_16bit/current_state[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[3]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[3]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[3]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/current_state[3]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[3]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/current_state[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \sc130_i2c_config_index[1]~FF (.D(\u_i2c_timing_ctrl_16bit/n197 ), + .CE(\u_i2c_timing_ctrl_16bit/n497 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\sc130_i2c_config_index[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(173) + defparam \sc130_i2c_config_index[1]~FF .CLK_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[1]~FF .CE_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[1]~FF .SR_POLARITY = 1'b0; + defparam \sc130_i2c_config_index[1]~FF .D_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[1]~FF .SR_SYNC = 1'b0; + defparam \sc130_i2c_config_index[1]~FF .SR_VALUE = 1'b0; + defparam \sc130_i2c_config_index[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \sc130_i2c_config_index[2]~FF (.D(\u_i2c_timing_ctrl_16bit/n196 ), + .CE(\u_i2c_timing_ctrl_16bit/n497 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\sc130_i2c_config_index[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(173) + defparam \sc130_i2c_config_index[2]~FF .CLK_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[2]~FF .CE_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[2]~FF .SR_POLARITY = 1'b0; + defparam \sc130_i2c_config_index[2]~FF .D_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[2]~FF .SR_SYNC = 1'b0; + defparam \sc130_i2c_config_index[2]~FF .SR_VALUE = 1'b0; + defparam \sc130_i2c_config_index[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \sc130_i2c_config_index[3]~FF (.D(\u_i2c_timing_ctrl_16bit/n195 ), + .CE(\u_i2c_timing_ctrl_16bit/n497 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\sc130_i2c_config_index[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(173) + defparam \sc130_i2c_config_index[3]~FF .CLK_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[3]~FF .CE_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[3]~FF .SR_POLARITY = 1'b0; + defparam \sc130_i2c_config_index[3]~FF .D_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[3]~FF .SR_SYNC = 1'b0; + defparam \sc130_i2c_config_index[3]~FF .SR_VALUE = 1'b0; + defparam \sc130_i2c_config_index[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \sc130_i2c_config_index[4]~FF (.D(\u_i2c_timing_ctrl_16bit/n194 ), + .CE(\u_i2c_timing_ctrl_16bit/n497 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\sc130_i2c_config_index[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(173) + defparam \sc130_i2c_config_index[4]~FF .CLK_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[4]~FF .CE_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[4]~FF .SR_POLARITY = 1'b0; + defparam \sc130_i2c_config_index[4]~FF .D_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[4]~FF .SR_SYNC = 1'b0; + defparam \sc130_i2c_config_index[4]~FF .SR_VALUE = 1'b0; + defparam \sc130_i2c_config_index[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \sc130_i2c_config_index[5]~FF (.D(\u_i2c_timing_ctrl_16bit/n193 ), + .CE(\u_i2c_timing_ctrl_16bit/n497 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\sc130_i2c_config_index[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(173) + defparam \sc130_i2c_config_index[5]~FF .CLK_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[5]~FF .CE_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[5]~FF .SR_POLARITY = 1'b0; + defparam \sc130_i2c_config_index[5]~FF .D_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[5]~FF .SR_SYNC = 1'b0; + defparam \sc130_i2c_config_index[5]~FF .SR_VALUE = 1'b0; + defparam \sc130_i2c_config_index[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \sc130_i2c_config_index[6]~FF (.D(\u_i2c_timing_ctrl_16bit/n192 ), + .CE(\u_i2c_timing_ctrl_16bit/n497 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\sc130_i2c_config_index[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(173) + defparam \sc130_i2c_config_index[6]~FF .CLK_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[6]~FF .CE_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[6]~FF .SR_POLARITY = 1'b0; + defparam \sc130_i2c_config_index[6]~FF .D_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[6]~FF .SR_SYNC = 1'b0; + defparam \sc130_i2c_config_index[6]~FF .SR_VALUE = 1'b0; + defparam \sc130_i2c_config_index[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \sc130_i2c_config_index[7]~FF (.D(\u_i2c_timing_ctrl_16bit/n191 ), + .CE(\u_i2c_timing_ctrl_16bit/n497 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\sc130_i2c_config_index[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(173) + defparam \sc130_i2c_config_index[7]~FF .CLK_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[7]~FF .CE_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[7]~FF .SR_POLARITY = 1'b0; + defparam \sc130_i2c_config_index[7]~FF .D_POLARITY = 1'b1; + defparam \sc130_i2c_config_index[7]~FF .SR_SYNC = 1'b0; + defparam \sc130_i2c_config_index[7]~FF .SR_VALUE = 1'b0; + defparam \sc130_i2c_config_index[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1]~FF (.D(\u_i2c_timing_ctrl_16bit/n332 ), + .CE(ceg_net2242), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2]~FF (.D(\u_i2c_timing_ctrl_16bit/n331 ), + .CE(ceg_net2242), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3]~FF (.D(\u_i2c_timing_ctrl_16bit/n330 ), + .CE(ceg_net2242), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_wdata[1]~FF (.D(\u_i2c_timing_ctrl_16bit/n719 ), + .CE(ceg_net4099), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_wdata[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[1]~FF .CE_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[1]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[1]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[1]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[1]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_wdata[2]~FF (.D(\u_i2c_timing_ctrl_16bit/n727 ), + .CE(ceg_net4099), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_wdata[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[2]~FF .CE_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[2]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[2]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[2]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[2]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_wdata[3]~FF (.D(\u_i2c_timing_ctrl_16bit/n735 ), + .CE(ceg_net4099), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_wdata[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[3]~FF .CE_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[3]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[3]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[3]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[3]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_wdata[4]~FF (.D(\u_i2c_timing_ctrl_16bit/n743 ), + .CE(ceg_net4099), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_wdata[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[4]~FF .CE_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[4]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[4]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[4]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[4]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_wdata[5]~FF (.D(\u_i2c_timing_ctrl_16bit/n751 ), + .CE(ceg_net4099), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_wdata[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[5]~FF .CE_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[5]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[5]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[5]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[5]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_wdata[6]~FF (.D(\u_i2c_timing_ctrl_16bit/n759 ), + .CE(ceg_net4099), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_wdata[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[6]~FF .CE_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[6]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[6]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[6]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[6]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/i2c_wdata[7]~FF (.D(\u_i2c_timing_ctrl_16bit/n767 ), + .CE(ceg_net4099), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/i2c_wdata[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(322) + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[7]~FF .CE_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[7]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[7]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[7]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[7]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/i2c_wdata[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[1]~FF (.D(n2966), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[2]~FF (.D(n5055), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[2]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[3]~FF (.D(n5053), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[3]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[4]~FF (.D(n5051), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[4]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[4]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[4]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[4]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[4]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[5]~FF (.D(n5049), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[5]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[5]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[5]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[5]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[5]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[6]~FF (.D(n5047), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[6]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[6]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[6]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[6]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[6]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[7]~FF (.D(n5045), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[7]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[7]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[7]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[7]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[7]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[8]~FF (.D(n5043), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[8]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[8]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[8]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[8]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[8]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[9]~FF (.D(n5041), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[9]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[9]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[9]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[9]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[9]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[10]~FF (.D(n5039), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[10]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[10]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[10]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[10]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[10]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[11]~FF (.D(n5037), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[11]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[11]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[11]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[11]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[11]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[12]~FF (.D(n5035), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[12]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[12]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[12]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[12]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[12]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[13]~FF (.D(n5033), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[13]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[13]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[13]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[13]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[13]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[14]~FF (.D(n5031), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[14]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[14]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[14]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[14]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[14]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[14]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[15]~FF (.D(n5029), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[15]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[15]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[15]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[15]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[15]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[15]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[16]~FF (.D(n5027), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[16]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[16]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[16]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[16]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[16]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[16]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[17]~FF (.D(n5025), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[17]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[17]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[17]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[17]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[17]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[17]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[18]~FF (.D(n5023), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[18]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[18]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[18]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[18]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[18]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[18]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16bit/delay_cnt[19]~FF (.D(n5022), .CE(\u_i2c_timing_ctrl_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16bit/delay_cnt[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(69) + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[19]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[19]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[19]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[19]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[19]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[19]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16bit/delay_cnt[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i10_rst_7~FF (.D(\u_axi4_ctrl/dff_138/i10_rst_6 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i10_rst_7 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i10_rst_7~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_7~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_7~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_7~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_7~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i10_rst_7~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_7~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n137 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/current_state[0]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(167) + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[0]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[0]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[0]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[0]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[0]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_ctrl_clk~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n138 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_ctrl_clk )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ctrl_clk~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ctrl_clk~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ctrl_clk~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ctrl_clk~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ctrl_clk~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ctrl_clk~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ctrl_clk~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en_2~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n139 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en_2~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en_2~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en_2~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en_2~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en_2~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en_2~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n140 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ar0135_i2c_config_index[0]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n205 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/n846 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\ar0135_i2c_config_index[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(197) + defparam \ar0135_i2c_config_index[0]~FF .CLK_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[0]~FF .CE_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[0]~FF .SR_POLARITY = 1'b0; + defparam \ar0135_i2c_config_index[0]~FF .D_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[0]~FF .SR_SYNC = 1'b0; + defparam \ar0135_i2c_config_index[0]~FF .SR_VALUE = 1'b0; + defparam \ar0135_i2c_config_index[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i10_rst_6_2~FF (.D(\u_axi4_ctrl/dff_138/i10_rst_5 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i10_rst_6 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i10_rst_6_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_6_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_6_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_6_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_6_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i10_rst_6_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_6_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n122 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n123 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n124 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n125 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n126 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n127 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n128 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n129 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n130 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n131 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n132 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n133 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n134 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n135 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n136 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(121) + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i10_rst_5_2~FF (.D(\u_axi4_ctrl/dff_138/i10_rst_4 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i10_rst_5 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i10_rst_5_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_5_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_5_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_5_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_5_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i10_rst_5_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_5_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i10_rst_4_2~FF (.D(\u_axi4_ctrl/dff_138/i10_rst_3 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i10_rst_4 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i10_rst_4_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_4_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_4_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_4_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_4_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i10_rst_4_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_4_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i10_rst_3_2~FF (.D(\u_axi4_ctrl/dff_138/i10_rst_2 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i10_rst_3 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i10_rst_3_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_3_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_3_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_3_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_3_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i10_rst_3_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_3_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i10_rst_2_2~FF (.D(\u_axi4_ctrl/dff_138/i10_rst_1 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i10_rst_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i10_rst_2_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_2_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_2_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_2_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_2_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i10_rst_2_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_rst_2_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_7_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_6 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_7 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_7_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_7_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_7_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_7_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_7_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_7_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_7_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_6_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_5 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_6 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_6_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_6_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_6_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_6_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_6_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_6_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_6_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n500 ), + .CE(ceg_net4141), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n509 ), + .CE(ceg_net4466), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_ack5~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n567 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack5 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(548) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack5~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack5~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack5~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack5~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack5~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack5~FF .SR_VALUE = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack5~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_5_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_4 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_5 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_5_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_5_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_5_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_5_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_5_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_5_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_5_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_4_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_3 ), + .CE(1'b1), .CLK(tac_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/tac_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_4 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_4_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_4_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_4_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_4_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_4_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_4_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_rst_4_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_ack4~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n570 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack4 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(548) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack4~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack4~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack4~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack4~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack4~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack4~FF .SR_VALUE = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack4~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_ack3~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n573 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack3 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(548) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack3~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack3~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack3~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack3~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack3~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack3~FF .SR_VALUE = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack3~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_ack2~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n576 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(548) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack2~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack2~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack2~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack2~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack2~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack2~FF .SR_VALUE = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_ack1~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n579 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack1 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(548) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack1~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack1~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack1~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack1~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack1~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack1~FF .SR_VALUE = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack1~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_ack~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n581 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/i2c_capture_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(548) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack~FF .SR_VALUE = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_ack~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0] ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0]~FF .D_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \cmos_sdat_OUT~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n495 ), .CE(ceg_net4426), + .CLK(clk_sys), .SR(rstn_sys), .Q(cmos_sdat_OUT)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \cmos_sdat_OUT~FF .CLK_POLARITY = 1'b1; + defparam \cmos_sdat_OUT~FF .CE_POLARITY = 1'b1; + defparam \cmos_sdat_OUT~FF .SR_POLARITY = 1'b0; + defparam \cmos_sdat_OUT~FF .D_POLARITY = 1'b1; + defparam \cmos_sdat_OUT~FF .SR_SYNC = 1'b0; + defparam \cmos_sdat_OUT~FF .SR_VALUE = 1'b1; + defparam \cmos_sdat_OUT~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/current_state[1]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(167) + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[1]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[1]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[1]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[1]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[1]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/current_state[2]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(167) + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[2]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[2]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[2]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[2]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[2]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/current_state[3]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(167) + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[3]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[3]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[3]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[3]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[3]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/current_state[4]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(167) + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[4]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[4]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[4]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[4]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[4]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/current_state[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ar0135_i2c_config_index[1]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n204 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/n846 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\ar0135_i2c_config_index[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(197) + defparam \ar0135_i2c_config_index[1]~FF .CLK_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[1]~FF .CE_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[1]~FF .SR_POLARITY = 1'b0; + defparam \ar0135_i2c_config_index[1]~FF .D_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[1]~FF .SR_SYNC = 1'b0; + defparam \ar0135_i2c_config_index[1]~FF .SR_VALUE = 1'b0; + defparam \ar0135_i2c_config_index[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ar0135_i2c_config_index[2]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n203 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/n846 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\ar0135_i2c_config_index[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(197) + defparam \ar0135_i2c_config_index[2]~FF .CLK_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[2]~FF .CE_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[2]~FF .SR_POLARITY = 1'b0; + defparam \ar0135_i2c_config_index[2]~FF .D_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[2]~FF .SR_SYNC = 1'b0; + defparam \ar0135_i2c_config_index[2]~FF .SR_VALUE = 1'b0; + defparam \ar0135_i2c_config_index[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ar0135_i2c_config_index[3]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n202 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/n846 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\ar0135_i2c_config_index[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(197) + defparam \ar0135_i2c_config_index[3]~FF .CLK_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[3]~FF .CE_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[3]~FF .SR_POLARITY = 1'b0; + defparam \ar0135_i2c_config_index[3]~FF .D_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[3]~FF .SR_SYNC = 1'b0; + defparam \ar0135_i2c_config_index[3]~FF .SR_VALUE = 1'b0; + defparam \ar0135_i2c_config_index[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ar0135_i2c_config_index[4]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n201 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/n846 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\ar0135_i2c_config_index[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(197) + defparam \ar0135_i2c_config_index[4]~FF .CLK_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[4]~FF .CE_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[4]~FF .SR_POLARITY = 1'b0; + defparam \ar0135_i2c_config_index[4]~FF .D_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[4]~FF .SR_SYNC = 1'b0; + defparam \ar0135_i2c_config_index[4]~FF .SR_VALUE = 1'b0; + defparam \ar0135_i2c_config_index[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ar0135_i2c_config_index[5]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n200 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/n846 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\ar0135_i2c_config_index[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(197) + defparam \ar0135_i2c_config_index[5]~FF .CLK_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[5]~FF .CE_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[5]~FF .SR_POLARITY = 1'b0; + defparam \ar0135_i2c_config_index[5]~FF .D_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[5]~FF .SR_SYNC = 1'b0; + defparam \ar0135_i2c_config_index[5]~FF .SR_VALUE = 1'b0; + defparam \ar0135_i2c_config_index[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ar0135_i2c_config_index[6]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n199 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/n846 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\ar0135_i2c_config_index[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(197) + defparam \ar0135_i2c_config_index[6]~FF .CLK_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[6]~FF .CE_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[6]~FF .SR_POLARITY = 1'b0; + defparam \ar0135_i2c_config_index[6]~FF .D_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[6]~FF .SR_SYNC = 1'b0; + defparam \ar0135_i2c_config_index[6]~FF .SR_VALUE = 1'b0; + defparam \ar0135_i2c_config_index[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ar0135_i2c_config_index[7]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n198 ), + .CE(\u_i2c_timing_ctrl_16reg_16bit/n846 ), .CLK(clk_sys), .SR(rstn_sys), + .Q(\ar0135_i2c_config_index[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(197) + defparam \ar0135_i2c_config_index[7]~FF .CLK_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[7]~FF .CE_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[7]~FF .SR_POLARITY = 1'b0; + defparam \ar0135_i2c_config_index[7]~FF .D_POLARITY = 1'b1; + defparam \ar0135_i2c_config_index[7]~FF .SR_SYNC = 1'b0; + defparam \ar0135_i2c_config_index[7]~FF .SR_VALUE = 1'b0; + defparam \ar0135_i2c_config_index[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n499 ), + .CE(ceg_net4141), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n498 ), + .CE(ceg_net4141), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n497 ), + .CE(ceg_net4141), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n508 ), + .CE(ceg_net4466), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n507 ), + .CE(ceg_net4466), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n506 ), + .CE(ceg_net4466), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n505 ), + .CE(ceg_net4466), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n504 ), + .CE(ceg_net4466), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n503 ), + .CE(ceg_net4466), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7]~FF (.D(\u_i2c_timing_ctrl_16reg_16bit/n502 ), + .CE(ceg_net4466), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(497) + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1]~FF (.D(n3687), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2]~FF (.D(n4982), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3]~FF (.D(n4980), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4]~FF (.D(n4978), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5]~FF (.D(n4976), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6]~FF (.D(n4974), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7]~FF (.D(n4972), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8]~FF (.D(n4970), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9]~FF (.D(n4968), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10]~FF (.D(n4966), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11]~FF (.D(n4964), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12]~FF (.D(n4962), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13]~FF (.D(n4960), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14]~FF (.D(n4958), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15]~FF (.D(n4956), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16]~FF (.D(n4954), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17]~FF (.D(n4952), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18]~FF (.D(n4950), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19]~FF (.D(n4949), .CE(\u_i2c_timing_ctrl_16reg_16bit/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(71) + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19]~FF .CLK_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19]~FF .CE_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19]~FF .SR_POLARITY = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19]~FF .D_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19]~FF .SR_SYNC = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19]~FF .SR_VALUE = 1'b0; + defparam \u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_cmos_fv_o[0]~FF (.D(n1406_2), .CE(1'b1), .CLK(cmos_pclk), + .SR(1'b0), .Q(\r_cmos_fv_o[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(747) + defparam \r_cmos_fv_o[0]~FF .CLK_POLARITY = 1'b1; + defparam \r_cmos_fv_o[0]~FF .CE_POLARITY = 1'b1; + defparam \r_cmos_fv_o[0]~FF .SR_POLARITY = 1'b1; + defparam \r_cmos_fv_o[0]~FF .D_POLARITY = 1'b1; + defparam \r_cmos_fv_o[0]~FF .SR_SYNC = 1'b1; + defparam \r_cmos_fv_o[0]~FF .SR_VALUE = 1'b0; + defparam \r_cmos_fv_o[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_cmos_fv_o[1]~FF (.D(n1413_2), .CE(1'b1), .CLK(cmos_pclk), + .SR(1'b0), .Q(\r_cmos_fv_o[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(747) + defparam \r_cmos_fv_o[1]~FF .CLK_POLARITY = 1'b1; + defparam \r_cmos_fv_o[1]~FF .CE_POLARITY = 1'b1; + defparam \r_cmos_fv_o[1]~FF .SR_POLARITY = 1'b1; + defparam \r_cmos_fv_o[1]~FF .D_POLARITY = 1'b1; + defparam \r_cmos_fv_o[1]~FF .SR_SYNC = 1'b1; + defparam \r_cmos_fv_o[1]~FF .SR_VALUE = 1'b0; + defparam \r_cmos_fv_o[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_cmos_fv_o[2]~FF (.D(n1418), .CE(1'b1), .CLK(cmos_pclk), + .SR(1'b0), .Q(\r_cmos_fv_o[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(747) + defparam \r_cmos_fv_o[2]~FF .CLK_POLARITY = 1'b1; + defparam \r_cmos_fv_o[2]~FF .CE_POLARITY = 1'b1; + defparam \r_cmos_fv_o[2]~FF .SR_POLARITY = 1'b1; + defparam \r_cmos_fv_o[2]~FF .D_POLARITY = 1'b1; + defparam \r_cmos_fv_o[2]~FF .SR_SYNC = 1'b1; + defparam \r_cmos_fv_o[2]~FF .SR_VALUE = 1'b0; + defparam \r_cmos_fv_o[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \led_o[5]~FF (.D(n1423), .CE(1'b1), .CLK(cmos_pclk), .SR(1'b0), + .Q(led_o[5])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(747) + defparam \led_o[5]~FF .CLK_POLARITY = 1'b1; + defparam \led_o[5]~FF .CE_POLARITY = 1'b1; + defparam \led_o[5]~FF .SR_POLARITY = 1'b1; + defparam \led_o[5]~FF .D_POLARITY = 1'b1; + defparam \led_o[5]~FF .SR_SYNC = 1'b1; + defparam \led_o[5]~FF .SR_VALUE = 1'b0; + defparam \led_o[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \dsi_pwm/rc_pwm[0]~FF (.D(\dsi_pwm/rc_pwm[0] ), .CE(1'b1), .CLK(clk_sys), + .SR(1'b0), .Q(\dsi_pwm/rc_pwm[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(24) + defparam \dsi_pwm/rc_pwm[0]~FF .CLK_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[0]~FF .CE_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[0]~FF .SR_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[0]~FF .D_POLARITY = 1'b0; + defparam \dsi_pwm/rc_pwm[0]~FF .SR_SYNC = 1'b1; + defparam \dsi_pwm/rc_pwm[0]~FF .SR_VALUE = 1'b0; + defparam \dsi_pwm/rc_pwm[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \dsi_pwm_o~FF (.D(\dsi_pwm/n14 ), .CE(1'b1), .CLK(clk_sys), + .SR(1'b0), .Q(dsi_pwm_o)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(24) + defparam \dsi_pwm_o~FF .CLK_POLARITY = 1'b1; + defparam \dsi_pwm_o~FF .CE_POLARITY = 1'b1; + defparam \dsi_pwm_o~FF .SR_POLARITY = 1'b1; + defparam \dsi_pwm_o~FF .D_POLARITY = 1'b1; + defparam \dsi_pwm_o~FF .SR_SYNC = 1'b1; + defparam \dsi_pwm_o~FF .SR_VALUE = 1'b0; + defparam \dsi_pwm_o~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \dsi_pwm/rc_pwm[1]~FF (.D(n3764), .CE(1'b1), .CLK(clk_sys), + .SR(1'b0), .Q(\dsi_pwm/rc_pwm[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(24) + defparam \dsi_pwm/rc_pwm[1]~FF .CLK_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[1]~FF .CE_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[1]~FF .SR_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[1]~FF .D_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[1]~FF .SR_SYNC = 1'b1; + defparam \dsi_pwm/rc_pwm[1]~FF .SR_VALUE = 1'b0; + defparam \dsi_pwm/rc_pwm[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \dsi_pwm/rc_pwm[2]~FF (.D(n4909), .CE(1'b1), .CLK(clk_sys), + .SR(1'b0), .Q(\dsi_pwm/rc_pwm[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(24) + defparam \dsi_pwm/rc_pwm[2]~FF .CLK_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[2]~FF .CE_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[2]~FF .SR_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[2]~FF .D_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[2]~FF .SR_SYNC = 1'b1; + defparam \dsi_pwm/rc_pwm[2]~FF .SR_VALUE = 1'b0; + defparam \dsi_pwm/rc_pwm[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \dsi_pwm/rc_pwm[3]~FF (.D(n4907), .CE(1'b1), .CLK(clk_sys), + .SR(1'b0), .Q(\dsi_pwm/rc_pwm[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(24) + defparam \dsi_pwm/rc_pwm[3]~FF .CLK_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[3]~FF .CE_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[3]~FF .SR_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[3]~FF .D_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[3]~FF .SR_SYNC = 1'b1; + defparam \dsi_pwm/rc_pwm[3]~FF .SR_VALUE = 1'b0; + defparam \dsi_pwm/rc_pwm[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \dsi_pwm/rc_pwm[4]~FF (.D(n4905), .CE(1'b1), .CLK(clk_sys), + .SR(1'b0), .Q(\dsi_pwm/rc_pwm[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(24) + defparam \dsi_pwm/rc_pwm[4]~FF .CLK_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[4]~FF .CE_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[4]~FF .SR_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[4]~FF .D_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[4]~FF .SR_SYNC = 1'b1; + defparam \dsi_pwm/rc_pwm[4]~FF .SR_VALUE = 1'b0; + defparam \dsi_pwm/rc_pwm[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \dsi_pwm/rc_pwm[5]~FF (.D(n4903), .CE(1'b1), .CLK(clk_sys), + .SR(1'b0), .Q(\dsi_pwm/rc_pwm[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(24) + defparam \dsi_pwm/rc_pwm[5]~FF .CLK_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[5]~FF .CE_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[5]~FF .SR_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[5]~FF .D_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[5]~FF .SR_SYNC = 1'b1; + defparam \dsi_pwm/rc_pwm[5]~FF .SR_VALUE = 1'b0; + defparam \dsi_pwm/rc_pwm[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \dsi_pwm/rc_pwm[6]~FF (.D(n4902), .CE(1'b1), .CLK(clk_sys), + .SR(1'b0), .Q(\dsi_pwm/rc_pwm[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(24) + defparam \dsi_pwm/rc_pwm[6]~FF .CLK_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[6]~FF .CE_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[6]~FF .SR_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[6]~FF .D_POLARITY = 1'b1; + defparam \dsi_pwm/rc_pwm[6]~FF .SR_SYNC = 1'b1; + defparam \dsi_pwm/rc_pwm[6]~FF .SR_VALUE = 1'b0; + defparam \dsi_pwm/rc_pwm[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[11]~FF (.D(\u_Sensor_Image_XYCrop/n55 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[11]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[11]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[11]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[11]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[11]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[10]~FF (.D(\u_Sensor_Image_XYCrop/n56 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[10]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[10]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[10]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[10]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[10]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[9]~FF (.D(\u_Sensor_Image_XYCrop/n57 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[9]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[9]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[9]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[9]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[9]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[0]~FF (.D(\u_Sensor_Image_XYCrop/n66 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[0]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[0]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[0]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[0]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[0]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \XYCrop_frame_de_2~FF (.D(cmos_href), .CE(1'b1), .CLK(cmos_pclk), + .SR(rstn_sys), .Q(XYCrop_frame_de)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(79) + defparam \XYCrop_frame_de_2~FF .CLK_POLARITY = 1'b1; + defparam \XYCrop_frame_de_2~FF .CE_POLARITY = 1'b1; + defparam \XYCrop_frame_de_2~FF .SR_POLARITY = 1'b0; + defparam \XYCrop_frame_de_2~FF .D_POLARITY = 1'b1; + defparam \XYCrop_frame_de_2~FF .SR_SYNC = 1'b0; + defparam \XYCrop_frame_de_2~FF .SR_VALUE = 1'b0; + defparam \XYCrop_frame_de_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[8]~FF (.D(\u_Sensor_Image_XYCrop/n58 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[8]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[8]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[8]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[8]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[8]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[7]~FF (.D(\u_Sensor_Image_XYCrop/n59 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[7]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[7]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[7]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[7]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[7]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \XYCrop_frame_Gray[5]~FF (.D(cmos_data[5]), .CE(1'b1), .CLK(cmos_pclk), + .SR(rstn_sys), .Q(\XYCrop_frame_Gray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(79) + defparam \XYCrop_frame_Gray[5]~FF .CLK_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[5]~FF .CE_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[5]~FF .SR_POLARITY = 1'b0; + defparam \XYCrop_frame_Gray[5]~FF .D_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[5]~FF .SR_SYNC = 1'b0; + defparam \XYCrop_frame_Gray[5]~FF .SR_VALUE = 1'b0; + defparam \XYCrop_frame_Gray[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[6]~FF (.D(\u_Sensor_Image_XYCrop/n60 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[6]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[6]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[6]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[6]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[6]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[5]~FF (.D(\u_Sensor_Image_XYCrop/n61 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[5]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[5]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[5]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[5]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[5]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[0]~FF (.D(\u_Sensor_Image_XYCrop/n111 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[0]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[0]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[0]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[0]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[0]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \XYCrop_frame_Gray[3]~FF (.D(cmos_data[3]), .CE(1'b1), .CLK(cmos_pclk), + .SR(rstn_sys), .Q(\XYCrop_frame_Gray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(79) + defparam \XYCrop_frame_Gray[3]~FF .CLK_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[3]~FF .CE_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[3]~FF .SR_POLARITY = 1'b0; + defparam \XYCrop_frame_Gray[3]~FF .D_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[3]~FF .SR_SYNC = 1'b0; + defparam \XYCrop_frame_Gray[3]~FF .SR_VALUE = 1'b0; + defparam \XYCrop_frame_Gray[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[4]~FF (.D(\u_Sensor_Image_XYCrop/n62 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[4]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[4]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[4]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[4]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[4]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[3]~FF (.D(\u_Sensor_Image_XYCrop/n63 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[3]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[3]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[3]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[3]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[3]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \XYCrop_frame_Gray[4]~FF (.D(cmos_data[4]), .CE(1'b1), .CLK(cmos_pclk), + .SR(rstn_sys), .Q(\XYCrop_frame_Gray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(79) + defparam \XYCrop_frame_Gray[4]~FF .CLK_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[4]~FF .CE_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[4]~FF .SR_POLARITY = 1'b0; + defparam \XYCrop_frame_Gray[4]~FF .D_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[4]~FF .SR_SYNC = 1'b0; + defparam \XYCrop_frame_Gray[4]~FF .SR_VALUE = 1'b0; + defparam \XYCrop_frame_Gray[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[2]~FF (.D(\u_Sensor_Image_XYCrop/n64 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[2]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[2]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[2]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[2]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[2]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \XYCrop_frame_href_2~FF (.D(\u_Sensor_Image_XYCrop/w_image_out_href ), + .CE(1'b1), .CLK(cmos_pclk), .SR(1'b0), .Q(XYCrop_frame_href)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(127) + defparam \XYCrop_frame_href_2~FF .CLK_POLARITY = 1'b1; + defparam \XYCrop_frame_href_2~FF .CE_POLARITY = 1'b1; + defparam \XYCrop_frame_href_2~FF .SR_POLARITY = 1'b1; + defparam \XYCrop_frame_href_2~FF .D_POLARITY = 1'b1; + defparam \XYCrop_frame_href_2~FF .SR_SYNC = 1'b1; + defparam \XYCrop_frame_href_2~FF .SR_VALUE = 1'b0; + defparam \XYCrop_frame_href_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_ypos[1]~FF (.D(\u_Sensor_Image_XYCrop/n65 ), + .CE(ceg_net2404), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_ypos[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(99) + defparam \u_Sensor_Image_XYCrop/image_ypos[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[1]~FF .CE_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[1]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[1]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_ypos[1]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[1]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_ypos[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \XYCrop_frame_Gray[6]~FF (.D(cmos_data[6]), .CE(1'b1), .CLK(cmos_pclk), + .SR(rstn_sys), .Q(\XYCrop_frame_Gray[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(79) + defparam \XYCrop_frame_Gray[6]~FF .CLK_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[6]~FF .CE_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[6]~FF .SR_POLARITY = 1'b0; + defparam \XYCrop_frame_Gray[6]~FF .D_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[6]~FF .SR_SYNC = 1'b0; + defparam \XYCrop_frame_Gray[6]~FF .SR_VALUE = 1'b0; + defparam \XYCrop_frame_Gray[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \XYCrop_frame_Gray[7]~FF (.D(cmos_data[7]), .CE(1'b1), .CLK(cmos_pclk), + .SR(rstn_sys), .Q(\XYCrop_frame_Gray[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(79) + defparam \XYCrop_frame_Gray[7]~FF .CLK_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[7]~FF .CE_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[7]~FF .SR_POLARITY = 1'b0; + defparam \XYCrop_frame_Gray[7]~FF .D_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[7]~FF .SR_SYNC = 1'b0; + defparam \XYCrop_frame_Gray[7]~FF .SR_VALUE = 1'b0; + defparam \XYCrop_frame_Gray[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \XYCrop_frame_Gray[2]~FF (.D(cmos_data[2]), .CE(1'b1), .CLK(cmos_pclk), + .SR(rstn_sys), .Q(\XYCrop_frame_Gray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(79) + defparam \XYCrop_frame_Gray[2]~FF .CLK_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[2]~FF .CE_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[2]~FF .SR_POLARITY = 1'b0; + defparam \XYCrop_frame_Gray[2]~FF .D_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[2]~FF .SR_SYNC = 1'b0; + defparam \XYCrop_frame_Gray[2]~FF .SR_VALUE = 1'b0; + defparam \XYCrop_frame_Gray[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \XYCrop_frame_Gray[1]~FF (.D(cmos_data[1]), .CE(1'b1), .CLK(cmos_pclk), + .SR(rstn_sys), .Q(\XYCrop_frame_Gray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(79) + defparam \XYCrop_frame_Gray[1]~FF .CLK_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[1]~FF .CE_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[1]~FF .SR_POLARITY = 1'b0; + defparam \XYCrop_frame_Gray[1]~FF .D_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[1]~FF .SR_SYNC = 1'b0; + defparam \XYCrop_frame_Gray[1]~FF .SR_VALUE = 1'b0; + defparam \XYCrop_frame_Gray[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \XYCrop_frame_Gray[0]_2~FF (.D(cmos_data[0]), .CE(1'b1), .CLK(cmos_pclk), + .SR(rstn_sys), .Q(\XYCrop_frame_Gray[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(79) + defparam \XYCrop_frame_Gray[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[0]_2~FF .CE_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[0]_2~FF .SR_POLARITY = 1'b0; + defparam \XYCrop_frame_Gray[0]_2~FF .D_POLARITY = 1'b1; + defparam \XYCrop_frame_Gray[0]_2~FF .SR_SYNC = 1'b0; + defparam \XYCrop_frame_Gray[0]_2~FF .SR_VALUE = 1'b0; + defparam \XYCrop_frame_Gray[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \XYCrop_frame_vsync_2~FF (.D(cmos_vsync), .CE(1'b1), .CLK(cmos_pclk), + .SR(rstn_sys), .Q(XYCrop_frame_vsync)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(79) + defparam \XYCrop_frame_vsync_2~FF .CLK_POLARITY = 1'b1; + defparam \XYCrop_frame_vsync_2~FF .CE_POLARITY = 1'b1; + defparam \XYCrop_frame_vsync_2~FF .SR_POLARITY = 1'b0; + defparam \XYCrop_frame_vsync_2~FF .D_POLARITY = 1'b1; + defparam \XYCrop_frame_vsync_2~FF .SR_SYNC = 1'b0; + defparam \XYCrop_frame_vsync_2~FF .SR_VALUE = 1'b0; + defparam \XYCrop_frame_vsync_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[1]~FF (.D(\u_Sensor_Image_XYCrop/n110 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[1]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[1]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[1]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[1]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[1]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[2]~FF (.D(\u_Sensor_Image_XYCrop/n109 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[2]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[2]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[2]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[2]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[2]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[3]~FF (.D(\u_Sensor_Image_XYCrop/n108 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[3]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[3]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[3]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[3]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[3]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[4]~FF (.D(\u_Sensor_Image_XYCrop/n107 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[4]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[4]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[4]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[4]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[4]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[5]~FF (.D(\u_Sensor_Image_XYCrop/n106 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[5]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[5]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[5]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[5]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[5]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[6]~FF (.D(\u_Sensor_Image_XYCrop/n105 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[6]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[6]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[6]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[6]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[6]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[7]~FF (.D(\u_Sensor_Image_XYCrop/n104 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[7]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[7]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[7]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[7]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[7]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[8]~FF (.D(\u_Sensor_Image_XYCrop/n103 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[8]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[8]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[8]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[8]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[8]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[9]~FF (.D(\u_Sensor_Image_XYCrop/n102 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[9]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[9]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[9]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[9]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[9]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[10]~FF (.D(\u_Sensor_Image_XYCrop/n101 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[10]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[10]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[10]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[10]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[10]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_Sensor_Image_XYCrop/image_xpos[11]~FF (.D(\u_Sensor_Image_XYCrop/n100 ), + .CE(1'b1), .CLK(cmos_pclk), .SR(rstn_sys), .Q(\u_Sensor_Image_XYCrop/image_xpos[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(115) + defparam \u_Sensor_Image_XYCrop/image_xpos[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[11]~FF .CE_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[11]~FF .SR_POLARITY = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[11]~FF .D_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/image_xpos[11]~FF .SR_SYNC = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[11]~FF .SR_VALUE = 1'b0; + defparam \u_Sensor_Image_XYCrop/image_xpos[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_XYCrop_frame_Gray[1]~FF (.D(\XYCrop_frame_Gray[1] ), .CE(1'b1), + .CLK(cmos_pclk), .SR(1'b0), .Q(\r_XYCrop_frame_Gray[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(911) + defparam \r_XYCrop_frame_Gray[1]~FF .CLK_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[1]~FF .CE_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[1]~FF .SR_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[1]~FF .D_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[1]~FF .SR_SYNC = 1'b1; + defparam \r_XYCrop_frame_Gray[1]~FF .SR_VALUE = 1'b0; + defparam \r_XYCrop_frame_Gray[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_XYCrop_frame_Gray[2]~FF (.D(\XYCrop_frame_Gray[2] ), .CE(1'b1), + .CLK(cmos_pclk), .SR(1'b0), .Q(\r_XYCrop_frame_Gray[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(911) + defparam \r_XYCrop_frame_Gray[2]~FF .CLK_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[2]~FF .CE_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[2]~FF .SR_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[2]~FF .D_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[2]~FF .SR_SYNC = 1'b1; + defparam \r_XYCrop_frame_Gray[2]~FF .SR_VALUE = 1'b0; + defparam \r_XYCrop_frame_Gray[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_XYCrop_frame_Gray[3]~FF (.D(\XYCrop_frame_Gray[3] ), .CE(1'b1), + .CLK(cmos_pclk), .SR(1'b0), .Q(\r_XYCrop_frame_Gray[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(911) + defparam \r_XYCrop_frame_Gray[3]~FF .CLK_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[3]~FF .CE_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[3]~FF .SR_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[3]~FF .D_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[3]~FF .SR_SYNC = 1'b1; + defparam \r_XYCrop_frame_Gray[3]~FF .SR_VALUE = 1'b0; + defparam \r_XYCrop_frame_Gray[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_XYCrop_frame_Gray[4]~FF (.D(\XYCrop_frame_Gray[4] ), .CE(1'b1), + .CLK(cmos_pclk), .SR(1'b0), .Q(\r_XYCrop_frame_Gray[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(911) + defparam \r_XYCrop_frame_Gray[4]~FF .CLK_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[4]~FF .CE_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[4]~FF .SR_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[4]~FF .D_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[4]~FF .SR_SYNC = 1'b1; + defparam \r_XYCrop_frame_Gray[4]~FF .SR_VALUE = 1'b0; + defparam \r_XYCrop_frame_Gray[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_XYCrop_frame_Gray[5]~FF (.D(\XYCrop_frame_Gray[5] ), .CE(1'b1), + .CLK(cmos_pclk), .SR(1'b0), .Q(\r_XYCrop_frame_Gray[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(911) + defparam \r_XYCrop_frame_Gray[5]~FF .CLK_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[5]~FF .CE_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[5]~FF .SR_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[5]~FF .D_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[5]~FF .SR_SYNC = 1'b1; + defparam \r_XYCrop_frame_Gray[5]~FF .SR_VALUE = 1'b0; + defparam \r_XYCrop_frame_Gray[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_XYCrop_frame_Gray[6]~FF (.D(\XYCrop_frame_Gray[6] ), .CE(1'b1), + .CLK(cmos_pclk), .SR(1'b0), .Q(\r_XYCrop_frame_Gray[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(911) + defparam \r_XYCrop_frame_Gray[6]~FF .CLK_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[6]~FF .CE_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[6]~FF .SR_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[6]~FF .D_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[6]~FF .SR_SYNC = 1'b1; + defparam \r_XYCrop_frame_Gray[6]~FF .SR_VALUE = 1'b0; + defparam \r_XYCrop_frame_Gray[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \r_XYCrop_frame_Gray[7]~FF (.D(\XYCrop_frame_Gray[7] ), .CE(1'b1), + .CLK(cmos_pclk), .SR(1'b0), .Q(\r_XYCrop_frame_Gray[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\example_top.v(911) + defparam \r_XYCrop_frame_Gray[7]~FF .CLK_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[7]~FF .CE_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[7]~FF .SR_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[7]~FF .D_POLARITY = 1'b1; + defparam \r_XYCrop_frame_Gray[7]~FF .SR_SYNC = 1'b1; + defparam \r_XYCrop_frame_Gray[7]~FF .SR_VALUE = 1'b0; + defparam \r_XYCrop_frame_Gray[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[22]~FF (.D(\u_axi4_ctrl/n1484 ), .CE(\u_axi4_ctrl/r_rframe_inc ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\w_ddr3_araddr[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(149) + defparam \w_ddr3_araddr[22]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[22]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[22]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_araddr[22]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[22]~FF .SR_SYNC = 1'b1; + defparam \w_ddr3_araddr[22]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/r_wframe_index_last[0]~FF (.D(\w_ddr3_awaddr[22] ), + .CE(\u_axi4_ctrl/n1518 ), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_axi4_ctrl/r_wframe_index_last[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(149) + defparam \u_axi4_ctrl/r_wframe_index_last[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_index_last[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_index_last[0]~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_wframe_index_last[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_index_last[0]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/r_wframe_index_last[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/r_wframe_index_last[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \led_o[0]~FF (.D(\u_axi4_ctrl/n262 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(led_o[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \led_o[0]~FF .CLK_POLARITY = 1'b1; + defparam \led_o[0]~FF .CE_POLARITY = 1'b1; + defparam \led_o[0]~FF .SR_POLARITY = 1'b0; + defparam \led_o[0]~FF .D_POLARITY = 1'b1; + defparam \led_o[0]~FF .SR_SYNC = 1'b0; + defparam \led_o[0]~FF .SR_VALUE = 1'b0; + defparam \led_o[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_LUT4 LUT__19467 (.I0(\u_i2c_timing_ctrl_16bit/current_state[1] ), + .I1(\u_i2c_timing_ctrl_16bit/current_state[2] ), .I2(\u_i2c_timing_ctrl_16bit/current_state[3] ), + .O(n13395)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__19467.LUTMASK = 16'h1e1e; + EFX_FF \led_o[1]~FF (.D(\u_axi4_ctrl/n261 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(led_o[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \led_o[1]~FF .CLK_POLARITY = 1'b1; + defparam \led_o[1]~FF .CE_POLARITY = 1'b1; + defparam \led_o[1]~FF .SR_POLARITY = 1'b0; + defparam \led_o[1]~FF .D_POLARITY = 1'b1; + defparam \led_o[1]~FF .SR_SYNC = 1'b0; + defparam \led_o[1]~FF .SR_VALUE = 1'b0; + defparam \led_o[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/r_wframe_sync[0]~FF (.D(r_XYCrop_frame_vsync), .CE(1'b1), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_axi4_ctrl/r_wframe_sync[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/r_wframe_sync[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_sync[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_sync[0]~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_wframe_sync[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_sync[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/r_wframe_sync[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/r_wframe_sync[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rc_w_eof[0]~FF (.D(\u_axi4_ctrl/n288 ), .CE(1'b1), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_axi4_ctrl/rc_w_eof[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/rc_w_eof[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_w_eof[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_w_eof[0]~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/rc_w_eof[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_w_eof[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/rc_w_eof[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rc_w_eof[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/r_wframe_index_last[1]~FF (.D(\w_ddr3_awaddr[23] ), + .CE(\u_axi4_ctrl/n1518 ), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_axi4_ctrl/r_wframe_index_last[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(149) + defparam \u_axi4_ctrl/r_wframe_index_last[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_index_last[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_index_last[1]~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_wframe_index_last[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_index_last[1]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/r_wframe_index_last[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/r_wframe_index_last[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awvalid~FF (.D(\u_axi4_ctrl/n1315 ), .CE(ceg_net2429), + .CLK(clk_sys), .SR(rstn_sys), .Q(w_ddr3_awvalid)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awvalid~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awvalid~FF .CE_POLARITY = 1'b0; + defparam \w_ddr3_awvalid~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awvalid~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awvalid~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awvalid~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awvalid~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \led_o[2]~FF (.D(\u_axi4_ctrl/n257 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(led_o[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \led_o[2]~FF .CLK_POLARITY = 1'b1; + defparam \led_o[2]~FF .CE_POLARITY = 1'b1; + defparam \led_o[2]~FF .SR_POLARITY = 1'b0; + defparam \led_o[2]~FF .D_POLARITY = 1'b1; + defparam \led_o[2]~FF .SR_SYNC = 1'b0; + defparam \led_o[2]~FF .SR_VALUE = 1'b0; + defparam \led_o[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rc_burst[0]~FF (.D(\u_axi4_ctrl/n251 ), .CE(rstn_sys), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rc_burst[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/rc_burst[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[0]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rc_burst[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rc_burst[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/r_weof_pending~FF (.D(\u_axi4_ctrl/n234 ), .CE(ceg_net2431), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_axi4_ctrl/r_weof_pending )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/r_weof_pending~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_weof_pending~FF .CE_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_weof_pending~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_weof_pending~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_weof_pending~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/r_weof_pending~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/r_weof_pending~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/r_wframe_inc~FF (.D(\u_axi4_ctrl/n263 ), .CE(1'b1), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_axi4_ctrl/r_wframe_inc )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/r_wframe_inc~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_inc~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_inc~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_wframe_inc~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_inc~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/r_wframe_inc~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/r_wframe_inc~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rframe_vsync_dly~FF (.D(lcd_vs), .CE(1'b1), .CLK(clk_pixel), + .SR(rstn_sys), .Q(\u_axi4_ctrl/rframe_vsync_dly )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(351) + defparam \u_axi4_ctrl/rframe_vsync_dly~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rframe_vsync_dly~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rframe_vsync_dly~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/rframe_vsync_dly~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/rframe_vsync_dly~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rframe_vsync_dly~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rframe_vsync_dly~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_cnt[0]~FF (.D(\u_axi4_ctrl/n664 ), .CE(1'b1), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/n1318 ), .Q(\u_axi4_ctrl/rfifo_cnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(371) + defparam \u_axi4_ctrl/rfifo_cnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[0]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[0]~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_rst~FF (.D(\u_axi4_ctrl/equal_129/n9 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_sys), .Q(\u_axi4_ctrl/rfifo_rst )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(386) + defparam \u_axi4_ctrl/rfifo_rst~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_rst~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_rst~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/rfifo_rst~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_rst~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_rst~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/rfifo_rst~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/r_rfifo_rst_2~FF (.D(\u_axi4_ctrl/w_rfifo_rst ), + .CE(1'b1), .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/r_rfifo_rst )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(438) + defparam \u_axi4_ctrl/r_rfifo_rst_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_rfifo_rst_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_rfifo_rst_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_rfifo_rst_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_rfifo_rst_2~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/r_rfifo_rst_2~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/r_rfifo_rst_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wr_rst_busy_dly[0]~FF (.D(1'b1), .CE(1'b1), + .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rd_state[0]~FF (.D(\u_axi4_ctrl/n773 ), .CE(1'b1), + .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/rd_state[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(549) + defparam \u_axi4_ctrl/rd_state[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rd_state[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rd_state[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rd_state[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rd_state[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/rd_state[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rd_state[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/r_rframe_inc_2~FF (.D(\u_axi4_ctrl/equal_139/n3 ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_axi4_ctrl/r_rframe_inc )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(476) + defparam \u_axi4_ctrl/r_rframe_inc_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_rframe_inc_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_rframe_inc_2~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_rframe_inc_2~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_rframe_inc_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/r_rframe_inc_2~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/r_rframe_inc_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_arvalid~FF (.D(\u_axi4_ctrl/n1516 ), .CE(ceg_net2434), + .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(w_ddr3_arvalid)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(549) + defparam \w_ddr3_arvalid~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_arvalid~FF .CE_POLARITY = 1'b0; + defparam \w_ddr3_arvalid~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_arvalid~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_arvalid~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_arvalid~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_arvalid~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/r_rd_pend~FF (.D(\u_axi4_ctrl/n1516 ), .CE(ceg_net2437), + .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/r_rd_pend )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(549) + defparam \u_axi4_ctrl/r_rd_pend~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_rd_pend~FF .CE_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_rd_pend~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_rd_pend~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_rd_pend~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/r_rd_pend~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/r_rd_pend~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wenb~FF (.D(w_ddr3_rvalid), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\u_axi4_ctrl/rfifo_wenb )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(601) + defparam \u_axi4_ctrl/rfifo_wenb~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wenb~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wenb~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/rfifo_wenb~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wenb~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wenb~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wenb~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[23]~FF (.D(\u_axi4_ctrl/n1477 ), .CE(\u_axi4_ctrl/r_rframe_inc ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\w_ddr3_araddr[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(149) + defparam \w_ddr3_araddr[23]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[23]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[23]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_araddr[23]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[23]~FF .SR_SYNC = 1'b1; + defparam \w_ddr3_araddr[23]~FF .SR_VALUE = 1'b1; + defparam \w_ddr3_araddr[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[22]_2~FF (.D(\u_axi4_ctrl/w_wframe_index_next[0] ), + .CE(ceg_net3678), .CLK(clk_sys), .SR(rstn_sys), .Q(\w_ddr3_awaddr[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(149) + defparam \w_ddr3_awaddr[22]_2~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[22]_2~FF .CE_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[22]_2~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[22]_2~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[22]_2~FF .SR_SYNC = 1'b1; + defparam \w_ddr3_awaddr[22]_2~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[22]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/r_w_rst~FF (.D(\u_axi4_ctrl/n189 ), .CE(\u_axi4_ctrl/equal_68/n7 ), + .CLK(clk_sys), .SR(rstn_sys), .Q(\u_axi4_ctrl/r_w_rst )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/r_w_rst~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_w_rst~FF .CE_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_w_rst~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_w_rst~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_w_rst~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/r_w_rst~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/r_w_rst~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[4]~FF (.D(\u_axi4_ctrl/n283 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[4]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[4]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[4]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[4]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[4]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[4]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[5]~FF (.D(\u_axi4_ctrl/n282 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[5]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[5]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[5]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[5]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[5]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[5]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[6]~FF (.D(\u_axi4_ctrl/n281 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[6]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[6]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[6]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[6]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[6]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[6]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[7]~FF (.D(\u_axi4_ctrl/n280 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[7]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[7]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[7]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[7]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[7]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[7]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[8]~FF (.D(\u_axi4_ctrl/n279 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[8]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[8]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[8]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[8]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[8]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[8]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[9]~FF (.D(\u_axi4_ctrl/n278 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[9]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[9]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[9]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[9]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[9]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[9]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[10]~FF (.D(\u_axi4_ctrl/n277 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[10]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[10]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[10]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[10]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[10]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[10]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[11]~FF (.D(\u_axi4_ctrl/n276 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[11]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[11]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[11]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[11]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[11]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[11]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[12]~FF (.D(\u_axi4_ctrl/n275 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[12]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[12]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[12]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[12]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[12]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[12]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[13]~FF (.D(\u_axi4_ctrl/n274 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[13]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[13]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[13]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[13]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[13]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[13]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[14]~FF (.D(\u_axi4_ctrl/n273 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[14]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[14]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[14]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[14]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[14]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[14]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[15]~FF (.D(\u_axi4_ctrl/n272 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[15]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[15]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[15]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[15]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[15]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[15]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[16]~FF (.D(\u_axi4_ctrl/n271 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[16]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[16]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[16]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[16]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[16]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[16]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[17]~FF (.D(\u_axi4_ctrl/n270 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[17]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[17]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[17]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[17]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[17]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[17]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[18]~FF (.D(\u_axi4_ctrl/n269 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[18]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[18]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[18]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[18]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[18]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[18]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[19]~FF (.D(\u_axi4_ctrl/n268 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[19]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[19]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[19]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[19]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[19]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[19]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[20]~FF (.D(\u_axi4_ctrl/n267 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[20]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[20]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[20]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[20]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[20]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[20]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[21]~FF (.D(\u_axi4_ctrl/n266 ), .CE(1'b1), .CLK(clk_sys), + .SR(rstn_sys), .Q(\w_ddr3_awaddr[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \w_ddr3_awaddr[21]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[21]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[21]~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[21]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[21]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_awaddr[21]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/r_wframe_sync[1]~FF (.D(\u_axi4_ctrl/r_wframe_sync[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(rstn_sys), .Q(\u_axi4_ctrl/r_wframe_sync[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/r_wframe_sync[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_sync[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_sync[1]~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/r_wframe_sync[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/r_wframe_sync[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/r_wframe_sync[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/r_wframe_sync[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rc_burst[1]~FF (.D(\u_axi4_ctrl/n250 ), .CE(rstn_sys), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rc_burst[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/rc_burst[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[1]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rc_burst[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rc_burst[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rc_burst[2]~FF (.D(\u_axi4_ctrl/n249 ), .CE(rstn_sys), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rc_burst[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/rc_burst[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[2]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rc_burst[2]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rc_burst[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rc_burst[3]~FF (.D(\u_axi4_ctrl/n248 ), .CE(rstn_sys), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rc_burst[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/rc_burst[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[3]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rc_burst[3]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rc_burst[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rc_burst[4]~FF (.D(\u_axi4_ctrl/n247 ), .CE(rstn_sys), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rc_burst[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/rc_burst[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[4]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rc_burst[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rc_burst[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rc_burst[5]~FF (.D(\u_axi4_ctrl/n246 ), .CE(rstn_sys), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rc_burst[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/rc_burst[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[5]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rc_burst[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rc_burst[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rc_burst[6]~FF (.D(\u_axi4_ctrl/n245 ), .CE(rstn_sys), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rc_burst[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/rc_burst[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[6]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rc_burst[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rc_burst[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rc_burst[7]~FF (.D(\u_axi4_ctrl/n244 ), .CE(rstn_sys), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rc_burst[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(261) + defparam \u_axi4_ctrl/rc_burst[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rc_burst[7]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rc_burst[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rc_burst[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_w_rst ), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0, async_reg="true" */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(511) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF (.D(1'b0), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_w_rst ), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0, async_reg="true" */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(511) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF (.D(1'b0), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/r_w_rst ), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0, async_reg="true" */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(504) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/w_wfifo_empty~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CE(ceg_net2444), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/w_wfifo_empty )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1018) + defparam \u_axi4_ctrl/w_wfifo_empty~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/w_wfifo_empty~FF .CE_POLARITY = 1'b0; + defparam \u_axi4_ctrl/w_wfifo_empty~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/w_wfifo_empty~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/w_wfifo_empty~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/w_wfifo_empty~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/w_wfifo_empty~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[0]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[0]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[0] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[0]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1]~FF (.D(n3918), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2]~FF (.D(n4064), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3]~FF (.D(n4817), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4]~FF (.D(n4815), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5]~FF (.D(n4813), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6]~FF (.D(n4811), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7]~FF (.D(n4809), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8]~FF (.D(n4807), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9]~FF (.D(n4805), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10]~FF (.D(n4803), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11]~FF (.D(n4801), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12]~FF (.D(n4799), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13]~FF (.D(n4798), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1]~FF (.D(n4099), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2]~FF (.D(n4796), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3]~FF (.D(n4794), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4]~FF (.D(n4792), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5]~FF (.D(n4790), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6]~FF (.D(n4788), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7]~FF (.D(n4786), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8]~FF (.D(n4784), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9]~FF (.D(n4783), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[1]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[2]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[2]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[2]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[3]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[3]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[3]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9] ), + .CE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[1]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[1] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[2]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[2] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[2]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[2]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[3]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[3] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[3]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[3]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[4] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[5] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[6] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[7] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[8] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i30_pre ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[7] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[8] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[9] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[10] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[11] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[12] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i42_pre ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13]~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[1]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[2]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[2]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[2]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[3]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[3]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[3]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[7] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[8] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_w[9] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[4] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[5] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[6] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[7] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[8] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[9] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[10]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[10] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[10]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[10]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[10]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[10]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[10]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[11]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[11] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[11]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[11]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[11]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[11]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[11]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[12]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[12] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[12]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[12]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[12]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[12]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[12]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[13]~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[13]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[13]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[13]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[13]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[13]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_6 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_6_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_5 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_6 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_6_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_6_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_6_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_6_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_6_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_6_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_6_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_0~FF (.D(1'b0), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_0 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_0~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_0~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_0~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_0~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_0~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_0~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_0~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_5_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_4 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_5 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_5_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_5_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_5_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_5_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_5_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_5_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_5_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_1~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_0 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_1 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_1~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_1~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_1~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_1~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_1~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_1~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_1~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_1 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_3~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_2 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_3 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_3~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_3~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_3~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_3~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_3~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_3~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_3~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_4_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_3 ), + .CE(1'b1), .CLK(twd_clk), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/twd_clk_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_4 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_4_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_4_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_4_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_4_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_4_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_4_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_4_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0] ), + .CE(1'b1), .CLK(cmos_pclk), .SR(\u_axi4_ctrl/r_w_rst ), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0, async_reg="true" */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(504) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .SR_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_cnt[1]~FF (.D(\u_axi4_ctrl/n663 ), .CE(1'b1), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/n1318 ), .Q(\u_axi4_ctrl/rfifo_cnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(371) + defparam \u_axi4_ctrl/rfifo_cnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[1]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[1]~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_cnt[2]~FF (.D(\u_axi4_ctrl/n662 ), .CE(1'b1), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/n1318 ), .Q(\u_axi4_ctrl/rfifo_cnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(371) + defparam \u_axi4_ctrl/rfifo_cnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[2]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[2]~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_cnt[3]~FF (.D(\u_axi4_ctrl/n661 ), .CE(1'b1), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/n1318 ), .Q(\u_axi4_ctrl/rfifo_cnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(371) + defparam \u_axi4_ctrl/rfifo_cnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[3]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[3]~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_cnt[4]~FF (.D(\u_axi4_ctrl/n660 ), .CE(1'b1), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/n1318 ), .Q(\u_axi4_ctrl/rfifo_cnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(371) + defparam \u_axi4_ctrl/rfifo_cnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[4]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[4]~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/rfifo_cnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/w_rfifo_rst ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1, async_reg="true" */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(511) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF (.D(1'b0), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/w_rfifo_rst ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1, async_reg="true" */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(511) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[0]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF (.D(1'b0), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/w_rfifo_rst ), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1, async_reg="true" */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(504) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/w_rfifo_empty~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CE(ceg_net2451), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/w_rfifo_empty )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1018) + defparam \u_axi4_ctrl/w_rfifo_empty~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/w_rfifo_empty~FF .CE_POLARITY = 1'b0; + defparam \u_axi4_ctrl/w_rfifo_empty~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/w_rfifo_empty~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/w_rfifo_empty~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/w_rfifo_empty~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/w_rfifo_empty~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[0]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[0] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[0]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[0]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1]~FF (.D(n4225), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2]~FF (.D(n4222), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3]~FF (.D(n4744), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4]~FF (.D(n4742), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5]~FF (.D(n4740), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6]~FF (.D(n4738), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7]~FF (.D(n4736), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8]~FF (.D(n4734), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9]~FF (.D(n4733), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1201) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1]~FF (.D(n4230), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2]~FF (.D(n4731), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3]~FF (.D(n4729), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4]~FF (.D(n4727), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5]~FF (.D(n4725), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6]~FF (.D(n4723), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7]~FF (.D(n4721), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8]~FF (.D(n4719), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9]~FF (.D(n4717), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10]~FF (.D(n4715), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11]~FF (.D(n4713), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12]~FF (.D(n4711), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13]~FF (.D(n4710), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[12]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[12]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[12]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[12]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[12]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[12]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[13]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13] ), + .CE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1212) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[13]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[13]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[13]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[13]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[13]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[7] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[8] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[9] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[10] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[11] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[12] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i42_pre ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1244) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13]~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[1]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[1] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[2]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[2] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[2]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[2]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[3]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[3] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[3]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[3]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[4] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[5] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[6] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[7] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[8] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i30_pre ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1253) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .D_POLARITY = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[4] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[5] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[6] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[7] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[8] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[9] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[10]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[10] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[10]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[10]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[10]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[10]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[10]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[11]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[11] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[11]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[11]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[11]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[11]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[11]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[12]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[12] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[12]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[12]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[12]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[12]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[12]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[13]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[13] ), + .CE(1'b1), .CLK(clk_pixel), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.rd_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1267) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[13]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[13]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[13]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[13]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[13]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[1]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[1] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[2]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[2] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[2]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[2]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[3]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[3] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[3]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[3]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[4] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[5] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[6] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[7] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[8] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] ), + .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1279) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF (.D(1'b0), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF (.D(1'b0), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_0 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/logic_rstn ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_1 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_2 ), + .CE(1'b1), .CLK(clk_sys), .SR(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .CE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .SR_POLARITY = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .D_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .SR_SYNC = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .SR_VALUE = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/w_rfifo_rst ), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1, async_reg="true" */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(504) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/genblk2.wr_rst[1]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wr_rst_busy_dly[1]~FF (.D(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[0] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i15_rst_4~FF (.D(\u_axi4_ctrl/dff_138/i15_rst_3 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i15_rst_4 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i15_rst_4~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_4~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_4~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_4~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_4~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i15_rst_4~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_4~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i15_rst_3_2~FF (.D(\u_axi4_ctrl/dff_138/i15_rst_2 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i15_rst_3 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i15_rst_3_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_3_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_3_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_3_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_3_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i15_rst_3_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_3_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i15_rst_2_2~FF (.D(\u_axi4_ctrl/dff_138/i15_rst_1 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i15_rst_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i15_rst_2_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_2_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_2_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_2_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_2_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i15_rst_2_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_2_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i15_rst_1_2~FF (.D(\u_axi4_ctrl/dff_138/i15_rst_0 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i15_rst_1 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i15_rst_1_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_1_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_1_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_1_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_1_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i15_rst_1_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_1_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/dff_138/i15_rst_0_2~FF (.D(\u_axi4_ctrl/dff_138/i10_rst_7 ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/dff_138/i15_rst_0 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/dff_138/i15_rst_0_2~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_0_2~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_0_2~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_0_2~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_0_2~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/dff_138/i15_rst_0_2~FF .SR_VALUE = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_rst_0_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wr_rst_busy_dly[15]~FF (.D(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[14] ), + .CE(1'b1), .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(449) + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[15]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[15]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[15]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[15]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[15]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[15]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wr_rst_busy_dly[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rd_state[1]~FF (.D(\u_axi4_ctrl/n772 ), .CE(1'b1), + .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\u_axi4_ctrl/rd_state[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(549) + defparam \u_axi4_ctrl/rd_state[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rd_state[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rd_state[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rd_state[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rd_state[1]~FF .SR_SYNC = 1'b0; + defparam \u_axi4_ctrl/rd_state[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rd_state[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[11]~FF (.D(\w_ddr3_araddr[11] ), .CE(\u_axi4_ctrl/n785 ), + .CLK(clk_sys), .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\w_ddr3_araddr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(562) + defparam \w_ddr3_araddr[11]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[11]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[11]~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_araddr[11]~FF .D_POLARITY = 1'b0; + defparam \w_ddr3_araddr[11]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_araddr[11]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[12]~FF (.D(n3905), .CE(\u_axi4_ctrl/n785 ), .CLK(clk_sys), + .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\w_ddr3_araddr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(562) + defparam \w_ddr3_araddr[12]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[12]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[12]~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_araddr[12]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[12]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_araddr[12]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[13]~FF (.D(n4847), .CE(\u_axi4_ctrl/n785 ), .CLK(clk_sys), + .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\w_ddr3_araddr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(562) + defparam \w_ddr3_araddr[13]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[13]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[13]~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_araddr[13]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[13]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_araddr[13]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[14]~FF (.D(n4845), .CE(\u_axi4_ctrl/n785 ), .CLK(clk_sys), + .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\w_ddr3_araddr[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(562) + defparam \w_ddr3_araddr[14]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[14]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[14]~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_araddr[14]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[14]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_araddr[14]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[15]~FF (.D(n4843), .CE(\u_axi4_ctrl/n785 ), .CLK(clk_sys), + .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\w_ddr3_araddr[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(562) + defparam \w_ddr3_araddr[15]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[15]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[15]~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_araddr[15]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[15]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_araddr[15]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[16]~FF (.D(n4841), .CE(\u_axi4_ctrl/n785 ), .CLK(clk_sys), + .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\w_ddr3_araddr[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(562) + defparam \w_ddr3_araddr[16]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[16]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[16]~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_araddr[16]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[16]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_araddr[16]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[17]~FF (.D(n4839), .CE(\u_axi4_ctrl/n785 ), .CLK(clk_sys), + .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\w_ddr3_araddr[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(562) + defparam \w_ddr3_araddr[17]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[17]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[17]~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_araddr[17]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[17]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_araddr[17]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[18]~FF (.D(n4837), .CE(\u_axi4_ctrl/n785 ), .CLK(clk_sys), + .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\w_ddr3_araddr[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(562) + defparam \w_ddr3_araddr[18]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[18]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[18]~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_araddr[18]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[18]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_araddr[18]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[19]~FF (.D(n4835), .CE(\u_axi4_ctrl/n785 ), .CLK(clk_sys), + .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\w_ddr3_araddr[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(562) + defparam \w_ddr3_araddr[19]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[19]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[19]~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_araddr[19]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[19]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_araddr[19]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[20]~FF (.D(n4833), .CE(\u_axi4_ctrl/n785 ), .CLK(clk_sys), + .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\w_ddr3_araddr[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(562) + defparam \w_ddr3_araddr[20]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[20]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[20]~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_araddr[20]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[20]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_araddr[20]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_araddr[21]~FF (.D(n4832), .CE(\u_axi4_ctrl/n785 ), .CLK(clk_sys), + .SR(\u_axi4_ctrl/r_rfifo_rst ), .Q(\w_ddr3_araddr[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(562) + defparam \w_ddr3_araddr[21]~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_araddr[21]~FF .CE_POLARITY = 1'b1; + defparam \w_ddr3_araddr[21]~FF .SR_POLARITY = 1'b1; + defparam \w_ddr3_araddr[21]~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_araddr[21]~FF .SR_SYNC = 1'b0; + defparam \w_ddr3_araddr[21]~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_araddr[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[0]~FF (.D(\w_ddr3_rdata[0] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[0]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[0]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[0]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[0]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[0]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[1]~FF (.D(\w_ddr3_rdata[1] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[1]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[1]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[1]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[1]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[1]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[2]~FF (.D(\w_ddr3_rdata[2] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[2]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[2]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[2]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[2]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[2]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[3]~FF (.D(\w_ddr3_rdata[3] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[3]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[3]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[3]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[3]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[3]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[4]~FF (.D(\w_ddr3_rdata[4] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[4]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[4]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[4]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[4]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[4]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[5]~FF (.D(\w_ddr3_rdata[5] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[5]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[5]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[5]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[5]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[5]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[6]~FF (.D(\w_ddr3_rdata[6] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[6]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[6]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[6]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[6]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[6]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[7]~FF (.D(\w_ddr3_rdata[7] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[7]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[7]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[7]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[7]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[7]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[8]~FF (.D(\w_ddr3_rdata[8] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[8]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[8]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[8]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[8]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[8]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[9]~FF (.D(\w_ddr3_rdata[9] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[9]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[9]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[9]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[9]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[9]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[10]~FF (.D(\w_ddr3_rdata[10] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[10]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[10]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[10]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[10]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[10]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[11]~FF (.D(\w_ddr3_rdata[11] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[11]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[11]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[11]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[11]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[11]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[12]~FF (.D(\w_ddr3_rdata[12] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[12]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[12]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[12]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[12]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[12]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[13]~FF (.D(\w_ddr3_rdata[13] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[13]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[13]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[13]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[13]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[13]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[14]~FF (.D(\w_ddr3_rdata[14] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[14]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[14]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[14]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[14]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[14]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[14]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[14]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[15]~FF (.D(\w_ddr3_rdata[15] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[15]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[15]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[15]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[15]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[15]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[15]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[15]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[16]~FF (.D(\w_ddr3_rdata[16] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[16]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[16]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[16]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[16]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[16]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[16]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[16]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[17]~FF (.D(\w_ddr3_rdata[17] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[17]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[17]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[17]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[17]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[17]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[17]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[17]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[18]~FF (.D(\w_ddr3_rdata[18] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[18]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[18]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[18]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[18]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[18]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[18]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[18]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[19]~FF (.D(\w_ddr3_rdata[19] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[19]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[19]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[19]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[19]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[19]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[19]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[19]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[20]~FF (.D(\w_ddr3_rdata[20] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[20]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[20]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[20]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[20]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[20]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[20]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[20]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[21]~FF (.D(\w_ddr3_rdata[21] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[21]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[21]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[21]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[21]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[21]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[21]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[21]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[22]~FF (.D(\w_ddr3_rdata[22] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[22]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[22]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[22]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[22]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[22]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[22]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[22]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[23]~FF (.D(\w_ddr3_rdata[23] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[23]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[23]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[23]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[23]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[23]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[23]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[23]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[24]~FF (.D(\w_ddr3_rdata[24] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[24]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[24]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[24]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[24]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[24]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[24]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[24]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[25]~FF (.D(\w_ddr3_rdata[25] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[25]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[25]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[25]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[25]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[25]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[25]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[25]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[26]~FF (.D(\w_ddr3_rdata[26] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[26]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[26]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[26]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[26]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[26]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[26]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[26]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[27]~FF (.D(\w_ddr3_rdata[27] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[27]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[27]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[27]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[27]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[27]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[27]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[27]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[28]~FF (.D(\w_ddr3_rdata[28] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[28]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[28]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[28]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[28]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[28]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[28]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[28]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[29]~FF (.D(\w_ddr3_rdata[29] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[29]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[29]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[29]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[29]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[29]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[29]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[29]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[30]~FF (.D(\w_ddr3_rdata[30] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[30]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[30]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[30]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[30]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[30]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[30]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[30]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[31]~FF (.D(\w_ddr3_rdata[31] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[31]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[31]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[31]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[31]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[31]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[31]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[31]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[32]~FF (.D(\w_ddr3_rdata[32] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[32] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[32]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[32]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[32]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[32]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[32]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[32]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[32]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[33]~FF (.D(\w_ddr3_rdata[33] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[33] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[33]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[33]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[33]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[33]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[33]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[33]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[33]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[34]~FF (.D(\w_ddr3_rdata[34] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[34] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[34]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[34]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[34]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[34]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[34]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[34]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[34]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[35]~FF (.D(\w_ddr3_rdata[35] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[35] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[35]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[35]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[35]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[35]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[35]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[35]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[35]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[36]~FF (.D(\w_ddr3_rdata[36] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[36] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[36]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[36]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[36]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[36]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[36]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[36]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[36]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[37]~FF (.D(\w_ddr3_rdata[37] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[37] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[37]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[37]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[37]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[37]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[37]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[37]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[37]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[38]~FF (.D(\w_ddr3_rdata[38] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[38] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[38]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[38]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[38]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[38]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[38]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[38]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[38]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[39]~FF (.D(\w_ddr3_rdata[39] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[39] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[39]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[39]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[39]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[39]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[39]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[39]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[39]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[40]~FF (.D(\w_ddr3_rdata[40] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[40] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[40]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[40]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[40]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[40]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[40]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[40]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[40]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[41]~FF (.D(\w_ddr3_rdata[41] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[41] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[41]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[41]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[41]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[41]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[41]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[41]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[41]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[42]~FF (.D(\w_ddr3_rdata[42] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[42] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[42]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[42]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[42]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[42]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[42]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[42]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[42]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[43]~FF (.D(\w_ddr3_rdata[43] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[43] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[43]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[43]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[43]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[43]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[43]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[43]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[43]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[44]~FF (.D(\w_ddr3_rdata[44] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[44] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[44]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[44]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[44]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[44]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[44]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[44]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[44]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[45]~FF (.D(\w_ddr3_rdata[45] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[45] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[45]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[45]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[45]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[45]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[45]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[45]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[45]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[46]~FF (.D(\w_ddr3_rdata[46] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[46] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[46]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[46]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[46]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[46]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[46]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[46]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[46]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[47]~FF (.D(\w_ddr3_rdata[47] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[47] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[47]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[47]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[47]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[47]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[47]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[47]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[47]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[48]~FF (.D(\w_ddr3_rdata[48] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[48] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[48]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[48]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[48]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[48]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[48]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[48]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[48]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[49]~FF (.D(\w_ddr3_rdata[49] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[49] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[49]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[49]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[49]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[49]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[49]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[49]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[49]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[50]~FF (.D(\w_ddr3_rdata[50] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[50] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[50]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[50]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[50]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[50]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[50]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[50]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[50]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[51]~FF (.D(\w_ddr3_rdata[51] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[51] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[51]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[51]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[51]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[51]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[51]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[51]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[51]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[52]~FF (.D(\w_ddr3_rdata[52] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[52] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[52]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[52]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[52]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[52]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[52]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[52]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[52]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[53]~FF (.D(\w_ddr3_rdata[53] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[53] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[53]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[53]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[53]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[53]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[53]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[53]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[53]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[54]~FF (.D(\w_ddr3_rdata[54] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[54] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[54]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[54]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[54]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[54]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[54]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[54]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[54]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[55]~FF (.D(\w_ddr3_rdata[55] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[55] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[55]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[55]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[55]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[55]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[55]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[55]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[55]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[56]~FF (.D(\w_ddr3_rdata[56] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[56] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[56]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[56]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[56]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[56]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[56]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[56]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[56]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[57]~FF (.D(\w_ddr3_rdata[57] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[57] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[57]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[57]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[57]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[57]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[57]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[57]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[57]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[58]~FF (.D(\w_ddr3_rdata[58] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[58] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[58]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[58]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[58]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[58]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[58]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[58]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[58]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[59]~FF (.D(\w_ddr3_rdata[59] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[59] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[59]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[59]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[59]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[59]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[59]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[59]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[59]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[60]~FF (.D(\w_ddr3_rdata[60] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[60] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[60]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[60]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[60]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[60]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[60]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[60]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[60]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[61]~FF (.D(\w_ddr3_rdata[61] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[61] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[61]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[61]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[61]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[61]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[61]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[61]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[61]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[62]~FF (.D(\w_ddr3_rdata[62] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[62] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[62]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[62]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[62]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[62]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[62]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[62]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[62]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[63]~FF (.D(\w_ddr3_rdata[63] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[63] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[63]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[63]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[63]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[63]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[63]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[63]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[63]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[64]~FF (.D(\w_ddr3_rdata[64] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[64] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[64]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[64]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[64]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[64]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[64]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[64]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[64]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[65]~FF (.D(\w_ddr3_rdata[65] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[65] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[65]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[65]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[65]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[65]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[65]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[65]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[65]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[66]~FF (.D(\w_ddr3_rdata[66] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[66] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[66]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[66]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[66]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[66]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[66]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[66]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[66]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[67]~FF (.D(\w_ddr3_rdata[67] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[67] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[67]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[67]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[67]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[67]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[67]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[67]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[67]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[68]~FF (.D(\w_ddr3_rdata[68] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[68] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[68]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[68]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[68]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[68]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[68]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[68]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[68]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[69]~FF (.D(\w_ddr3_rdata[69] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[69] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[69]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[69]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[69]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[69]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[69]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[69]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[69]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[70]~FF (.D(\w_ddr3_rdata[70] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[70] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[70]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[70]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[70]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[70]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[70]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[70]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[70]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[71]~FF (.D(\w_ddr3_rdata[71] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[71] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[71]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[71]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[71]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[71]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[71]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[71]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[71]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[72]~FF (.D(\w_ddr3_rdata[72] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[72] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[72]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[72]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[72]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[72]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[72]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[72]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[72]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[73]~FF (.D(\w_ddr3_rdata[73] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[73] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[73]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[73]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[73]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[73]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[73]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[73]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[73]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[74]~FF (.D(\w_ddr3_rdata[74] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[74] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[74]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[74]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[74]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[74]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[74]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[74]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[74]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[75]~FF (.D(\w_ddr3_rdata[75] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[75] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[75]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[75]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[75]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[75]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[75]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[75]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[75]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[76]~FF (.D(\w_ddr3_rdata[76] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[76] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[76]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[76]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[76]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[76]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[76]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[76]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[76]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[77]~FF (.D(\w_ddr3_rdata[77] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[77] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[77]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[77]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[77]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[77]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[77]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[77]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[77]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[78]~FF (.D(\w_ddr3_rdata[78] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[78] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[78]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[78]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[78]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[78]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[78]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[78]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[78]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[79]~FF (.D(\w_ddr3_rdata[79] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[79] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[79]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[79]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[79]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[79]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[79]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[79]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[79]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[80]~FF (.D(\w_ddr3_rdata[80] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[80] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[80]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[80]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[80]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[80]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[80]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[80]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[80]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[81]~FF (.D(\w_ddr3_rdata[81] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[81] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[81]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[81]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[81]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[81]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[81]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[81]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[81]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[82]~FF (.D(\w_ddr3_rdata[82] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[82] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[82]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[82]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[82]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[82]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[82]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[82]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[82]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[83]~FF (.D(\w_ddr3_rdata[83] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[83] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[83]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[83]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[83]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[83]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[83]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[83]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[83]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[84]~FF (.D(\w_ddr3_rdata[84] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[84] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[84]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[84]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[84]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[84]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[84]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[84]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[84]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[85]~FF (.D(\w_ddr3_rdata[85] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[85] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[85]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[85]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[85]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[85]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[85]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[85]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[85]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[86]~FF (.D(\w_ddr3_rdata[86] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[86] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[86]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[86]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[86]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[86]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[86]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[86]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[86]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[87]~FF (.D(\w_ddr3_rdata[87] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[87] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[87]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[87]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[87]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[87]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[87]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[87]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[87]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[88]~FF (.D(\w_ddr3_rdata[88] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[88] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[88]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[88]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[88]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[88]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[88]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[88]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[88]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[89]~FF (.D(\w_ddr3_rdata[89] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[89] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[89]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[89]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[89]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[89]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[89]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[89]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[89]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[90]~FF (.D(\w_ddr3_rdata[90] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[90] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[90]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[90]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[90]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[90]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[90]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[90]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[90]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[91]~FF (.D(\w_ddr3_rdata[91] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[91] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[91]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[91]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[91]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[91]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[91]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[91]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[91]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[92]~FF (.D(\w_ddr3_rdata[92] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[92] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[92]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[92]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[92]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[92]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[92]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[92]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[92]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[93]~FF (.D(\w_ddr3_rdata[93] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[93] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[93]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[93]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[93]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[93]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[93]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[93]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[93]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[94]~FF (.D(\w_ddr3_rdata[94] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[94] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[94]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[94]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[94]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[94]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[94]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[94]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[94]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[95]~FF (.D(\w_ddr3_rdata[95] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[95] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[95]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[95]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[95]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[95]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[95]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[95]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[95]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[96]~FF (.D(\w_ddr3_rdata[96] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[96] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[96]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[96]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[96]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[96]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[96]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[96]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[96]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[97]~FF (.D(\w_ddr3_rdata[97] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[97] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[97]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[97]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[97]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[97]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[97]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[97]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[97]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[98]~FF (.D(\w_ddr3_rdata[98] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[98] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[98]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[98]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[98]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[98]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[98]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[98]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[98]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[99]~FF (.D(\w_ddr3_rdata[99] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[99] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[99]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[99]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[99]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[99]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[99]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[99]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[99]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[100]~FF (.D(\w_ddr3_rdata[100] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[100] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[100]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[100]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[100]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[100]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[100]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[100]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[100]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[101]~FF (.D(\w_ddr3_rdata[101] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[101] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[101]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[101]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[101]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[101]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[101]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[101]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[101]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[102]~FF (.D(\w_ddr3_rdata[102] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[102] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[102]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[102]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[102]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[102]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[102]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[102]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[102]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[103]~FF (.D(\w_ddr3_rdata[103] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[103] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[103]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[103]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[103]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[103]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[103]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[103]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[103]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[104]~FF (.D(\w_ddr3_rdata[104] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[104] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[104]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[104]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[104]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[104]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[104]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[104]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[104]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[105]~FF (.D(\w_ddr3_rdata[105] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[105] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[105]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[105]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[105]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[105]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[105]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[105]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[105]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[106]~FF (.D(\w_ddr3_rdata[106] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[106] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[106]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[106]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[106]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[106]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[106]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[106]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[106]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[107]~FF (.D(\w_ddr3_rdata[107] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[107] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[107]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[107]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[107]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[107]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[107]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[107]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[107]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[108]~FF (.D(\w_ddr3_rdata[108] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[108] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[108]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[108]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[108]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[108]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[108]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[108]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[108]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[109]~FF (.D(\w_ddr3_rdata[109] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[109] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[109]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[109]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[109]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[109]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[109]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[109]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[109]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[110]~FF (.D(\w_ddr3_rdata[110] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[110] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[110]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[110]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[110]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[110]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[110]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[110]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[110]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[111]~FF (.D(\w_ddr3_rdata[111] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[111] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[111]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[111]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[111]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[111]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[111]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[111]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[111]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[112]~FF (.D(\w_ddr3_rdata[112] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[112] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[112]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[112]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[112]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[112]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[112]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[112]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[112]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[113]~FF (.D(\w_ddr3_rdata[113] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[113] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[113]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[113]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[113]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[113]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[113]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[113]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[113]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[114]~FF (.D(\w_ddr3_rdata[114] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[114] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[114]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[114]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[114]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[114]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[114]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[114]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[114]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[115]~FF (.D(\w_ddr3_rdata[115] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[115] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[115]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[115]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[115]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[115]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[115]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[115]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[115]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[116]~FF (.D(\w_ddr3_rdata[116] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[116] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[116]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[116]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[116]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[116]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[116]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[116]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[116]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[117]~FF (.D(\w_ddr3_rdata[117] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[117] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[117]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[117]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[117]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[117]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[117]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[117]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[117]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[118]~FF (.D(\w_ddr3_rdata[118] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[118] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[118]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[118]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[118]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[118]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[118]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[118]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[118]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[119]~FF (.D(\w_ddr3_rdata[119] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[119] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[119]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[119]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[119]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[119]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[119]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[119]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[119]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[120]~FF (.D(\w_ddr3_rdata[120] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[120] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[120]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[120]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[120]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[120]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[120]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[120]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[120]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[121]~FF (.D(\w_ddr3_rdata[121] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[121] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[121]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[121]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[121]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[121]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[121]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[121]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[121]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[122]~FF (.D(\w_ddr3_rdata[122] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[122] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[122]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[122]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[122]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[122]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[122]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[122]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[122]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[123]~FF (.D(\w_ddr3_rdata[123] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[123] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[123]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[123]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[123]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[123]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[123]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[123]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[123]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[124]~FF (.D(\w_ddr3_rdata[124] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[124] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[124]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[124]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[124]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[124]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[124]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[124]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[124]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[125]~FF (.D(\w_ddr3_rdata[125] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[125] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[125]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[125]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[125]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[125]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[125]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[125]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[125]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[126]~FF (.D(\w_ddr3_rdata[126] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[126] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[126]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[126]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[126]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[126]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[126]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[126]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[126]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_axi4_ctrl/rfifo_wdata[127]~FF (.D(\w_ddr3_rdata[127] ), .CE(1'b1), + .CLK(clk_sys), .SR(1'b0), .Q(\u_axi4_ctrl/rfifo_wdata[127] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(606) + defparam \u_axi4_ctrl/rfifo_wdata[127]~FF .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[127]~FF .CE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[127]~FF .SR_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[127]~FF .D_POLARITY = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[127]~FF .SR_SYNC = 1'b1; + defparam \u_axi4_ctrl/rfifo_wdata[127]~FF .SR_VALUE = 1'b0; + defparam \u_axi4_ctrl/rfifo_wdata[127]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \w_ddr3_awaddr[23]_2~FF (.D(\u_axi4_ctrl/w_wframe_index_next[1] ), + .CE(ceg_net3678), .CLK(clk_sys), .SR(rstn_sys), .Q(\w_ddr3_awaddr[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(149) + defparam \w_ddr3_awaddr[23]_2~FF .CLK_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[23]_2~FF .CE_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[23]_2~FF .SR_POLARITY = 1'b0; + defparam \w_ddr3_awaddr[23]_2~FF .D_POLARITY = 1'b1; + defparam \w_ddr3_awaddr[23]_2~FF .SR_SYNC = 1'b1; + defparam \w_ddr3_awaddr[23]_2~FF .SR_VALUE = 1'b0; + defparam \w_ddr3_awaddr[23]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[0]~FF (.D(\u_lcd_driver/n89 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[0]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[0]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[0]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[0]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[0]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \lcd_hs~FF (.D(\u_lcd_driver/n39 ), .CE(rstn_pixel), .CLK(clk_pixel), + .SR(1'b0), .Q(lcd_hs)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \lcd_hs~FF .CLK_POLARITY = 1'b1; + defparam \lcd_hs~FF .CE_POLARITY = 1'b1; + defparam \lcd_hs~FF .SR_POLARITY = 1'b1; + defparam \lcd_hs~FF .D_POLARITY = 1'b0; + defparam \lcd_hs~FF .SR_SYNC = 1'b1; + defparam \lcd_hs~FF .SR_VALUE = 1'b0; + defparam \lcd_hs~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \lcd_vs_2~FF (.D(\u_lcd_driver/n90 ), .CE(\u_lcd_driver/n434 ), + .CLK(clk_pixel), .SR(1'b0), .Q(lcd_vs)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \lcd_vs_2~FF .CLK_POLARITY = 1'b1; + defparam \lcd_vs_2~FF .CE_POLARITY = 1'b1; + defparam \lcd_vs_2~FF .SR_POLARITY = 1'b1; + defparam \lcd_vs_2~FF .D_POLARITY = 1'b0; + defparam \lcd_vs_2~FF .SR_SYNC = 1'b1; + defparam \lcd_vs_2~FF .SR_VALUE = 1'b0; + defparam \lcd_vs_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \lcd_de~FF (.D(\u_lcd_driver/n132 ), .CE(1'b1), .CLK(clk_pixel), + .SR(1'b0), .Q(lcd_de)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(130) + defparam \lcd_de~FF .CLK_POLARITY = 1'b1; + defparam \lcd_de~FF .CE_POLARITY = 1'b1; + defparam \lcd_de~FF .SR_POLARITY = 1'b1; + defparam \lcd_de~FF .D_POLARITY = 1'b1; + defparam \lcd_de~FF .SR_SYNC = 1'b1; + defparam \lcd_de~FF .SR_VALUE = 1'b0; + defparam \lcd_de~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \lcd_request~FF (.D(\u_lcd_driver/n240 ), .CE(1'b1), .CLK(clk_pixel), + .SR(1'b0), .Q(lcd_request)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(147) + defparam \lcd_request~FF .CLK_POLARITY = 1'b1; + defparam \lcd_request~FF .CE_POLARITY = 1'b1; + defparam \lcd_request~FF .SR_POLARITY = 1'b1; + defparam \lcd_request~FF .D_POLARITY = 1'b1; + defparam \lcd_request~FF .SR_SYNC = 1'b1; + defparam \lcd_request~FF .SR_VALUE = 1'b0; + defparam \lcd_request~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[0]~FF (.D(\u_lcd_driver/n38 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[0]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[0]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[0]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[0]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[0]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[1]~FF (.D(\u_lcd_driver/n88 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[1]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[1]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[1]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[1]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[1]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[2]~FF (.D(\u_lcd_driver/n87 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[2]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[2]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[2]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[2]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[2]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[3]~FF (.D(\u_lcd_driver/n86 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[3]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[3]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[3]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[3]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[3]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[4]~FF (.D(\u_lcd_driver/n85 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[4]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[4]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[4]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[4]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[4]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[5]~FF (.D(\u_lcd_driver/n84 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[5]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[5]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[5]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[5]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[5]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[6]~FF (.D(\u_lcd_driver/n83 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[6]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[6]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[6]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[6]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[6]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[7]~FF (.D(\u_lcd_driver/n82 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[7]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[7]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[7]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[7]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[7]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[8]~FF (.D(\u_lcd_driver/n81 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[8]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[8]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[8]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[8]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[8]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[9]~FF (.D(\u_lcd_driver/n80 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[9]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[9]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[9]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[9]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[9]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[10]~FF (.D(\u_lcd_driver/n79 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[10]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[10]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[10]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[10]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[10]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/vcnt[11]~FF (.D(\u_lcd_driver/n78 ), .CE(\u_lcd_driver/equal_17/n27 ), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/vcnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(112) + defparam \u_lcd_driver/vcnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[11]~FF .CE_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[11]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/vcnt[11]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/vcnt[11]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/vcnt[11]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/vcnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/r_lcd_rgb[0]~FF (.D(\lcd_data[0] ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\u_lcd_driver/r_lcd_rgb[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(130) + defparam \u_lcd_driver/r_lcd_rgb[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[0]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[0]~FF .SR_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[0]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[0]~FF .SR_SYNC = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[0]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/r_lcd_rgb[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/r_lcd_rgb[1]~FF (.D(\lcd_data[1] ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\u_lcd_driver/r_lcd_rgb[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(130) + defparam \u_lcd_driver/r_lcd_rgb[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[1]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[1]~FF .SR_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[1]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[1]~FF .SR_SYNC = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[1]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/r_lcd_rgb[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/r_lcd_rgb[2]~FF (.D(\lcd_data[2] ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\u_lcd_driver/r_lcd_rgb[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(130) + defparam \u_lcd_driver/r_lcd_rgb[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[2]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[2]~FF .SR_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[2]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[2]~FF .SR_SYNC = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[2]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/r_lcd_rgb[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/r_lcd_rgb[3]~FF (.D(\lcd_data[3] ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\u_lcd_driver/r_lcd_rgb[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(130) + defparam \u_lcd_driver/r_lcd_rgb[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[3]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[3]~FF .SR_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[3]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[3]~FF .SR_SYNC = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[3]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/r_lcd_rgb[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/r_lcd_rgb[4]~FF (.D(\lcd_data[4] ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\u_lcd_driver/r_lcd_rgb[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(130) + defparam \u_lcd_driver/r_lcd_rgb[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[4]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[4]~FF .SR_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[4]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[4]~FF .SR_SYNC = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[4]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/r_lcd_rgb[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/r_lcd_rgb[5]~FF (.D(\lcd_data[5] ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\u_lcd_driver/r_lcd_rgb[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(130) + defparam \u_lcd_driver/r_lcd_rgb[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[5]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[5]~FF .SR_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[5]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[5]~FF .SR_SYNC = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[5]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/r_lcd_rgb[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/r_lcd_rgb[6]~FF (.D(\lcd_data[6] ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\u_lcd_driver/r_lcd_rgb[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(130) + defparam \u_lcd_driver/r_lcd_rgb[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[6]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[6]~FF .SR_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[6]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[6]~FF .SR_SYNC = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[6]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/r_lcd_rgb[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/r_lcd_rgb[7]~FF (.D(\lcd_data[7] ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\u_lcd_driver/r_lcd_rgb[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(130) + defparam \u_lcd_driver/r_lcd_rgb[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[7]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[7]~FF .SR_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[7]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[7]~FF .SR_SYNC = 1'b1; + defparam \u_lcd_driver/r_lcd_rgb[7]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/r_lcd_rgb[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[1]~FF (.D(\u_lcd_driver/n37 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[1]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[1]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[1]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[1]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[1]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[2]~FF (.D(\u_lcd_driver/n36 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[2]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[2]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[2]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[2]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[2]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[3]~FF (.D(\u_lcd_driver/n35 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[3]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[3]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[3]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[3]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[3]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[4]~FF (.D(\u_lcd_driver/n34 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[4]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[4]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[4]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[4]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[4]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[5]~FF (.D(\u_lcd_driver/n33 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[5]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[5]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[5]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[5]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[5]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[5]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[6]~FF (.D(\u_lcd_driver/n32 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[6]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[6]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[6]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[6]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[6]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[6]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[6]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[7]~FF (.D(\u_lcd_driver/n31 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[7]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[7]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[7]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[7]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[7]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[7]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[8]~FF (.D(\u_lcd_driver/n30 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[8]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[8]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[8]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[8]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[8]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[8]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[8]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[9]~FF (.D(\u_lcd_driver/n29 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[9]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[9]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[9]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[9]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[9]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[9]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[9]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[10]~FF (.D(\u_lcd_driver/n28 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[10]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[10]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[10]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[10]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[10]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[10]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[10]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[11]~FF (.D(\u_lcd_driver/n27 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[11]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[11]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[11]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[11]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[11]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[11]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[11]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[12]~FF (.D(\u_lcd_driver/n26 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[12]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[12]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[12]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[12]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[12]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[12]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[12]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_lcd_driver/hcnt[13]~FF (.D(\u_lcd_driver/n25 ), .CE(1'b1), + .CLK(clk_pixel), .SR(rstn_pixel), .Q(\u_lcd_driver/hcnt[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(93) + defparam \u_lcd_driver/hcnt[13]~FF .CLK_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[13]~FF .CE_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[13]~FF .SR_POLARITY = 1'b0; + defparam \u_lcd_driver/hcnt[13]~FF .D_POLARITY = 1'b1; + defparam \u_lcd_driver/hcnt[13]~FF .SR_SYNC = 1'b0; + defparam \u_lcd_driver/hcnt[13]~FF .SR_VALUE = 1'b0; + defparam \u_lcd_driver/hcnt[13]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd0_o[0]~FF (.D(\u_rgb2dvi/enc_0/n886 ), .CE(1'b1), .CLK(clk_pixel), + .SR(1'b0), .Q(hdmi_txd0_o[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd0_o[0]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd0_o[0]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd0_o[0]~FF .SR_POLARITY = 1'b1; + defparam \hdmi_txd0_o[0]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd0_o[0]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd0_o[0]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd0_o[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_0/acc[0]~FF (.D(n4543), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_0/acc[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_0/acc[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[0]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[0]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_0/acc[0]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[0]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[0]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_0/acc[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd0_o[1]~FF (.D(\u_rgb2dvi/enc_0/n765 ), .CE(1'b1), .CLK(clk_pixel), + .SR(1'b0), .Q(hdmi_txd0_o[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd0_o[1]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd0_o[1]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd0_o[1]~FF .SR_POLARITY = 1'b1; + defparam \hdmi_txd0_o[1]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd0_o[1]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd0_o[1]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd0_o[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd0_o[2]_2~FF (.D(\u_rgb2dvi/enc_0/n771 ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\hdmi_txd0_o[2]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd0_o[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd0_o[2]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd0_o[2]_2~FF .SR_POLARITY = 1'b1; + defparam \hdmi_txd0_o[2]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd0_o[2]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd0_o[2]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd0_o[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd0_o[3]~FF (.D(\u_rgb2dvi/enc_0/n777 ), .CE(1'b1), .CLK(clk_pixel), + .SR(1'b0), .Q(hdmi_txd0_o[3])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd0_o[3]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd0_o[3]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd0_o[3]~FF .SR_POLARITY = 1'b1; + defparam \hdmi_txd0_o[3]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd0_o[3]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd0_o[3]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd0_o[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd0_o[4]_2~FF (.D(\u_rgb2dvi/enc_0/n783 ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\hdmi_txd0_o[4]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd0_o[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd0_o[4]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd0_o[4]_2~FF .SR_POLARITY = 1'b1; + defparam \hdmi_txd0_o[4]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd0_o[4]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd0_o[4]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd0_o[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd0_o[5]~FF (.D(\u_rgb2dvi/enc_0/n789 ), .CE(1'b1), .CLK(clk_pixel), + .SR(1'b0), .Q(hdmi_txd0_o[5])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd0_o[5]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd0_o[5]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd0_o[5]~FF .SR_POLARITY = 1'b1; + defparam \hdmi_txd0_o[5]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd0_o[5]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd0_o[5]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd0_o[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd0_o[6]_2~FF (.D(\u_rgb2dvi/enc_0/n795 ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\hdmi_txd0_o[6]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd0_o[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd0_o[6]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd0_o[6]_2~FF .SR_POLARITY = 1'b1; + defparam \hdmi_txd0_o[6]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd0_o[6]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd0_o[6]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd0_o[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd0_o[7]~FF (.D(\u_rgb2dvi/enc_0/n801 ), .CE(1'b1), .CLK(clk_pixel), + .SR(1'b0), .Q(hdmi_txd0_o[7])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd0_o[7]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd0_o[7]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd0_o[7]~FF .SR_POLARITY = 1'b1; + defparam \hdmi_txd0_o[7]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd0_o[7]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd0_o[7]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd0_o[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd0_o[8]_2~FF (.D(\u_rgb2dvi/enc_0/n807 ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\hdmi_txd0_o[8]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd0_o[8]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd0_o[8]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd0_o[8]_2~FF .SR_POLARITY = 1'b1; + defparam \hdmi_txd0_o[8]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd0_o[8]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd0_o[8]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd0_o[8]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd0_o[9]_2~FF (.D(\u_rgb2dvi/enc_0/n813 ), .CE(1'b1), + .CLK(clk_pixel), .SR(1'b0), .Q(\hdmi_txd0_o[9]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd0_o[9]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd0_o[9]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd0_o[9]_2~FF .SR_POLARITY = 1'b1; + defparam \hdmi_txd0_o[9]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd0_o[9]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd0_o[9]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd0_o[9]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_0/acc[1]~FF (.D(n4639), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_0/acc[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_0/acc[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[1]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[1]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_0/acc[1]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[1]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[1]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_0/acc[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_0/acc[2]~FF (.D(n4637), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_0/acc[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_0/acc[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[2]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[2]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_0/acc[2]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[2]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[2]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_0/acc[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_0/acc[3]~FF (.D(n4635), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_0/acc[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_0/acc[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[3]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[3]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_0/acc[3]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[3]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[3]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_0/acc[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_0/acc[4]~FF (.D(n4634), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_0/acc[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_0/acc[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[4]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[4]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_0/acc[4]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[4]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_0/acc[4]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_0/acc[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd1_o[0]~FF (.D(\u_rgb2dvi/enc_1/q_out[0] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(hdmi_txd1_o[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd1_o[0]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd1_o[0]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd1_o[0]~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd1_o[0]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd1_o[0]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd1_o[0]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd1_o[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_1/acc[0]~FF (.D(n4560), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_1/acc[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_1/acc[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[0]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[0]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_1/acc[0]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[0]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[0]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_1/acc[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd1_o[1]~FF (.D(\u_rgb2dvi/enc_1/q_out[1] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(hdmi_txd1_o[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd1_o[1]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd1_o[1]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd1_o[1]~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd1_o[1]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd1_o[1]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd1_o[1]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd1_o[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd1_o[2]_2~FF (.D(\u_rgb2dvi/enc_1/q_out[2] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(\hdmi_txd1_o[2]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd1_o[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd1_o[2]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd1_o[2]_2~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd1_o[2]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd1_o[2]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd1_o[2]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd1_o[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd1_o[3]~FF (.D(\u_rgb2dvi/enc_1/q_out[3] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(hdmi_txd1_o[3])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd1_o[3]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd1_o[3]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd1_o[3]~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd1_o[3]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd1_o[3]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd1_o[3]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd1_o[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd1_o[4]_2~FF (.D(\u_rgb2dvi/enc_1/q_out[4] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(\hdmi_txd1_o[4]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd1_o[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd1_o[4]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd1_o[4]_2~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd1_o[4]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd1_o[4]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd1_o[4]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd1_o[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd1_o[5]~FF (.D(\u_rgb2dvi/enc_1/q_out[5] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(hdmi_txd1_o[5])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd1_o[5]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd1_o[5]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd1_o[5]~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd1_o[5]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd1_o[5]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd1_o[5]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd1_o[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd1_o[6]_2~FF (.D(\u_rgb2dvi/enc_1/q_out[6] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(\hdmi_txd1_o[6]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd1_o[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd1_o[6]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd1_o[6]_2~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd1_o[6]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd1_o[6]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd1_o[6]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd1_o[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd1_o[7]~FF (.D(\u_rgb2dvi/enc_1/q_out[7] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(hdmi_txd1_o[7])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd1_o[7]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd1_o[7]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd1_o[7]~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd1_o[7]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd1_o[7]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd1_o[7]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd1_o[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd1_o[8]_2~FF (.D(n12107), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\hdmi_txd1_o[8]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd1_o[8]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd1_o[8]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd1_o[8]_2~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd1_o[8]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd1_o[8]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd1_o[8]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd1_o[8]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd1_o[9]_2~FF (.D(\u_rgb2dvi/enc_1/q_out[9] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(\hdmi_txd1_o[9]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd1_o[9]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd1_o[9]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd1_o[9]_2~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd1_o[9]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd1_o[9]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd1_o[9]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd1_o[9]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_1/acc[1]~FF (.D(n4620), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_1/acc[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_1/acc[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[1]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[1]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_1/acc[1]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[1]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[1]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_1/acc[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_1/acc[2]~FF (.D(n4618), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_1/acc[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_1/acc[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[2]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[2]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_1/acc[2]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[2]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[2]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_1/acc[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_1/acc[3]~FF (.D(n4616), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_1/acc[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_1/acc[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[3]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[3]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_1/acc[3]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[3]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[3]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_1/acc[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_1/acc[4]~FF (.D(n4615), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_1/acc[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_1/acc[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[4]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[4]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_1/acc[4]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[4]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_1/acc[4]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_1/acc[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd2_o[0]~FF (.D(\u_rgb2dvi/enc_2/q_out[0] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(hdmi_txd2_o[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd2_o[0]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd2_o[0]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd2_o[0]~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd2_o[0]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd2_o[0]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd2_o[0]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd2_o[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_2/acc[0]~FF (.D(n4579), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_2/acc[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_2/acc[0]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[0]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[0]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_2/acc[0]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[0]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[0]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_2/acc[0]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd2_o[1]~FF (.D(\u_rgb2dvi/enc_2/q_out[1] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(hdmi_txd2_o[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd2_o[1]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd2_o[1]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd2_o[1]~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd2_o[1]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd2_o[1]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd2_o[1]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd2_o[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd2_o[2]_2~FF (.D(\u_rgb2dvi/enc_2/q_out[2] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(\hdmi_txd2_o[2]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd2_o[2]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd2_o[2]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd2_o[2]_2~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd2_o[2]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd2_o[2]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd2_o[2]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd2_o[2]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd2_o[3]~FF (.D(\u_rgb2dvi/enc_2/q_out[3] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(hdmi_txd2_o[3])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd2_o[3]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd2_o[3]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd2_o[3]~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd2_o[3]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd2_o[3]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd2_o[3]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd2_o[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd2_o[4]_2~FF (.D(\u_rgb2dvi/enc_2/q_out[4] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(\hdmi_txd2_o[4]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd2_o[4]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd2_o[4]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd2_o[4]_2~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd2_o[4]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd2_o[4]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd2_o[4]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd2_o[4]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd2_o[5]~FF (.D(\u_rgb2dvi/enc_2/q_out[5] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(hdmi_txd2_o[5])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd2_o[5]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd2_o[5]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd2_o[5]~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd2_o[5]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd2_o[5]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd2_o[5]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd2_o[5]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd2_o[6]_2~FF (.D(\u_rgb2dvi/enc_2/q_out[6] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(\hdmi_txd2_o[6]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd2_o[6]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd2_o[6]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd2_o[6]_2~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd2_o[6]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd2_o[6]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd2_o[6]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd2_o[6]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd2_o[7]~FF (.D(\u_rgb2dvi/enc_2/q_out[7] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(hdmi_txd2_o[7])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd2_o[7]~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd2_o[7]~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd2_o[7]~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd2_o[7]~FF .D_POLARITY = 1'b1; + defparam \hdmi_txd2_o[7]~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd2_o[7]~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd2_o[7]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \hdmi_txd2_o[9]_2~FF (.D(\u_rgb2dvi/enc_2/q_out[9] ), .CE(1'b1), + .CLK(clk_pixel), .SR(lcd_de), .Q(\hdmi_txd2_o[9]_2 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b0, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(167) + defparam \hdmi_txd2_o[9]_2~FF .CLK_POLARITY = 1'b1; + defparam \hdmi_txd2_o[9]_2~FF .CE_POLARITY = 1'b1; + defparam \hdmi_txd2_o[9]_2~FF .SR_POLARITY = 1'b0; + defparam \hdmi_txd2_o[9]_2~FF .D_POLARITY = 1'b0; + defparam \hdmi_txd2_o[9]_2~FF .SR_SYNC = 1'b1; + defparam \hdmi_txd2_o[9]_2~FF .SR_VALUE = 1'b0; + defparam \hdmi_txd2_o[9]_2~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_2/acc[1]~FF (.D(n4611), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_2/acc[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_2/acc[1]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[1]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[1]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_2/acc[1]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[1]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[1]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_2/acc[1]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_2/acc[2]~FF (.D(n4609), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_2/acc[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_2/acc[2]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[2]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[2]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_2/acc[2]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[2]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[2]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_2/acc[2]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_2/acc[3]~FF (.D(n4607), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_2/acc[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_2/acc[3]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[3]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[3]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_2/acc[3]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[3]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[3]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_2/acc[3]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_FF \u_rgb2dvi/enc_2/acc[4]~FF (.D(n4606), .CE(1'b1), .CLK(clk_pixel), + .SR(lcd_de), .Q(\u_rgb2dvi/enc_2/acc[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b1, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_2/acc[4]~FF .CLK_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[4]~FF .CE_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[4]~FF .SR_POLARITY = 1'b0; + defparam \u_rgb2dvi/enc_2/acc[4]~FF .D_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[4]~FF .SR_SYNC = 1'b1; + defparam \u_rgb2dvi/enc_2/acc[4]~FF .SR_VALUE = 1'b0; + defparam \u_rgb2dvi/enc_2/acc[4]~FF .SR_SYNC_PRIORITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0] ), + .O(n170), .CO(n171)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0] ), + .O(n172), .CO(n173)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0] ), + .O(n176), .CO(n177)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0] ), + .O(n178), .CO(n179)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0] ), + .I1(1'b0), .CI(n15044), .O(n180), .CO(n181)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0] ), + .I1(1'b0), .CI(n15045), .O(n207), .CO(n208)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] ), + .O(n209), .CO(n210)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] ), + .I1(1'b0), .CI(n15046), .O(n515), .CO(n516)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] ), + .O(n532), .CO(n533)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] ), + .I1(1'b0), .CI(n15047), .O(n540), .CO(n541)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] ), + .O(n767), .CO(n768)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] ), + .I1(1'b0), .CI(n15048), .O(n775), .CO(n776)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0] ), + .O(n1016), .CO(n1017)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0] ), + .I1(1'b0), .CI(n15049), .O(n1024), .CO(n1025)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0] ), + .O(n1027), .CO(n1028)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0] ), + .I1(1'b0), .CI(n15050), .O(n1035), .CO(n1036)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0] ), + .O(n1038), .CO(n1039)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0] ), + .I1(1'b0), .CI(n15051), .O(n1046), .CO(n1047)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] ), + .O(n1049), .CO(n1050)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] ), + .I1(1'b0), .CI(n15052), .O(n1057), .CO(n1058)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] ), + .O(n1116), .CO(n1117)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] ), + .I1(1'b0), .CI(n15053), .O(n1124), .CO(n1125)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] ), + .O(n1183), .CO(n1184)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] ), + .I1(1'b0), .CI(n15054), .O(n1191), .CO(n1192)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0] ), + .O(n1250), .CO(n1251)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0] ), + .O(n1259), .CO(n1260)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0] ), + .I1(n8257), .CI(n15055), .CO(n1262)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0] ), + .I1(n8360), .CI(n15056), .CO(n1335)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1] ), + .I1(n8436), .CI(n1335), .CO(n1403)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] ), + .I1(n8472), .CI(n15057), .CO(n1422)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] ), + .I1(n8547), .CI(n1422), .CO(n1490)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i1 (.I0(n8583), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0] ), + .CI(n15058), .O(n1511), .CO(n1512)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i1 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i2 (.I0(n8791), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1] ), + .CI(n1512), .O(n1675), .CO(n1676)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i2 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] ), + .I1(n8862), .CI(n15059), .CO(n1732)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i1 (.I0(n8961), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0] ), + .CI(n15060), .CO(n1804)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i1 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1] ), + .O(n2004), .CO(n2005)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3] ), + .I1(1'b0), .CI(n2005), .O(n2076), .CO(n2077)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0] ), + .I1(1'b0), .CI(n15061), .O(n2115), .CO(n2116)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2] ), + .O(n2603), .CO(n2604)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i1 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0] ), + .I1(1'b1), .O(n2642), .CO(n2643)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i1 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i1 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0] ), + .O(n2646), .CO(n2647)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1] ), + .O(n2660), .CO(n2661)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1] ), + .O(n2662), .CO(n2663)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i2 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[1] ), + .I1(\u_i2c_timing_ctrl_16bit/delay_cnt[0] ), .O(n2966), .CO(n2967)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i2 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i2 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[1] ), + .I1(\u_i2c_timing_ctrl_16bit/clk_cnt[0] ), .O(n3678), .CO(n3679)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i2 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_45/i2 (.I0(\sc130_i2c_config_index[1] ), + .I1(\sc130_i2c_config_index[0] ), .O(n3681), .CO(n3682)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(164) + defparam \u_i2c_timing_ctrl_16bit/add_45/i2 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_45/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i2 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0] ), .O(n3687), + .CO(n3688)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i2 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i2 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0] ), .O(n3754), + .CO(n3755)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i2 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_50/i2 (.I0(\ar0135_i2c_config_index[1] ), + .I1(\ar0135_i2c_config_index[0] ), .O(n3757), .CO(n3758)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(188) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i2 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i2 .I1_POLARITY = 1'b1; + EFX_ADD \dsi_pwm/add_4/i2 (.I0(\dsi_pwm/rc_pwm[1] ), .I1(\dsi_pwm/rc_pwm[0] ), + .O(n3764), .CO(n3765)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(22) + defparam \dsi_pwm/add_4/i2 .I0_POLARITY = 1'b1; + defparam \dsi_pwm/add_4/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_18/i2 (.I0(\u_Sensor_Image_XYCrop/image_ypos[1] ), + .I1(\u_Sensor_Image_XYCrop/image_ypos[0] ), .O(n3844), .CO(n3845)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(94) + defparam \u_Sensor_Image_XYCrop/add_18/i2 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_18/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i1 (.I0(\u_Sensor_Image_XYCrop/image_xpos[0] ), + .I1(cmos_href), .O(n3864), .CO(n3865)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i1 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i1 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_63/i1 (.I0(\u_axi4_ctrl/rc_burst[0] ), .I1(w_ddr3_wready), + .O(n3872), .CO(n3873)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(246) + defparam \u_axi4_ctrl/add_63/i1 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_63/i1 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_177/i2 (.I0(\w_ddr3_araddr[12] ), .I1(\w_ddr3_araddr[11] ), + .O(n3905), .CO(n3906)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(559) + defparam \u_axi4_ctrl/add_177/i2 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_177/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i2 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] ), + .O(n3918), .CO(n3919)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i2 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i3 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2] ), + .I1(1'b0), .CI(n3919), .O(n4064), .CO(n4065)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i3 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i2 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] ), + .O(n4099), .CO(n4100)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i2 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i5 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] ), + .CI(n15062), .O(n4102), .CO(n4103)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i5 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i5 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i1 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4] ), + .I1(n11392), .CI(n15063), .CO(n4122)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1191) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i1 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/sub_122/add_2/i1 (.I0(\u_axi4_ctrl/rfifo_cnt[0] ), + .I1(1'b0), .CI(n15064), .O(n4123), .CO(n4124)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(367) + defparam \u_axi4_ctrl/sub_122/add_2/i1 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/sub_122/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i3 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] ), + .I1(1'b0), .CI(n4226), .O(n4222), .CO(n4223)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i3 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i2 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] ), + .O(n4225), .CO(n4226)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i2 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i2 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] ), + .O(n4230), .CO(n4231)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i2 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i1 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4] ), + .CI(n15065), .CO(n4234)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1184) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i1 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i1 .I1_POLARITY = 1'b0; + EFX_ADD \u_lcd_driver/add_7/i2 (.I0(\u_lcd_driver/hcnt[1] ), .I1(\u_lcd_driver/hcnt[0] ), + .O(n4351), .CO(n4352)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i2 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_19/i2 (.I0(\u_lcd_driver/vcnt[1] ), .I1(\u_lcd_driver/vcnt[0] ), + .O(n4503), .CO(n4504)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(107) + defparam \u_lcd_driver/add_19/i2 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_19/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_0/add_105/i1 (.I0(\u_rgb2dvi/enc_0/acc[0] ), .I1(n4583), + .O(n4543), .CO(n4544)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_0/add_105/i1 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/add_105/i1 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_1/add_105/i1 (.I0(\u_rgb2dvi/enc_1/acc[0] ), .I1(n4583), + .O(n4560), .CO(n4561)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_1/add_105/i1 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/add_105/i1 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_2/add_75/i2 (.I0(n4600), .I1(n12107), .O(n4564), + .CO(n4565)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(88) + defparam \u_rgb2dvi/enc_2/add_75/i2 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/add_75/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_2/add_105/i1 (.I0(\u_rgb2dvi/enc_2/acc[0] ), .I1(n4583), + .O(n4579), .CO(n4580)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_2/add_105/i1 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/add_105/i1 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_2/sub_52/add_2/i1 (.I0(n12124), .I1(n12124), + .CI(n15067), .O(n4583), .CO(n15068)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(79) + defparam \u_rgb2dvi/enc_2/sub_52/add_2/i1 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/sub_52/add_2/i1 .I1_POLARITY = 1'b0; + EFX_ADD \u_rgb2dvi/enc_2/sub_79/add_2/i2 (.I0(n4604), .I1(n12107), + .CI(n15071), .O(n4585), .CO(n4586)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(93) + defparam \u_rgb2dvi/enc_2/sub_79/add_2/i2 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/sub_79/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_2/sub_52/add_2/i5 (.I0(1'b0), .I1(1'b1), .CI(n4628), + .O(n4599)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(79) + defparam \u_rgb2dvi/enc_2/sub_52/add_2/i5 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/sub_52/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_2/sub_52/add_2/i2 (.I0(n12140), .I1(n12146), + .CI(n15070), .O(n4600), .CO(n4601)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(79) + defparam \u_rgb2dvi/enc_2/sub_52/add_2/i2 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/sub_52/add_2/i2 .I1_POLARITY = 1'b0; + EFX_ADD \u_rgb2dvi/enc_2/sub_50/add_2/i3 (.I0(n12143), .I1(n12183), + .CI(n4605), .O(n4602), .CO(n4603)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(74) + defparam \u_rgb2dvi/enc_2/sub_50/add_2/i3 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/sub_50/add_2/i3 .I1_POLARITY = 1'b0; + EFX_ADD \u_rgb2dvi/enc_2/sub_50/add_2/i2 (.I0(n12146), .I1(n12140), + .CI(n15069), .O(n4604), .CO(n4605)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(74) + defparam \u_rgb2dvi/enc_2/sub_50/add_2/i2 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/sub_50/add_2/i2 .I1_POLARITY = 1'b0; + EFX_ADD \u_rgb2dvi/enc_2/add_105/i5 (.I0(\u_rgb2dvi/enc_2/acc[4] ), .I1(n12149), + .CI(n4608), .O(n4606)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_2/add_105/i5 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/add_105/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_2/add_105/i4 (.I0(\u_rgb2dvi/enc_2/acc[3] ), .I1(n12152), + .CI(n4610), .O(n4607), .CO(n4608)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_2/add_105/i4 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/add_105/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_2/add_105/i3 (.I0(\u_rgb2dvi/enc_2/acc[2] ), .I1(n12155), + .CI(n4612), .O(n4609), .CO(n4610)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_2/add_105/i3 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/add_105/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_2/add_105/i2 (.I0(\u_rgb2dvi/enc_2/acc[1] ), .I1(n12158), + .CI(n4580), .O(n4611), .CO(n4612)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_2/add_105/i2 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/add_105/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_2/add_75/i3 (.I0(n4629), .I1(1'b0), .CI(n4565), + .O(n4613), .CO(n4614)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(88) + defparam \u_rgb2dvi/enc_2/add_75/i3 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_2/add_75/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_1/add_105/i5 (.I0(\u_rgb2dvi/enc_1/acc[4] ), .I1(n12163), + .CI(n4617), .O(n4615)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_1/add_105/i5 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/add_105/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_1/add_105/i4 (.I0(\u_rgb2dvi/enc_1/acc[3] ), .I1(n12166), + .CI(n4619), .O(n4616), .CO(n4617)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_1/add_105/i4 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/add_105/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_1/add_105/i3 (.I0(\u_rgb2dvi/enc_1/acc[2] ), .I1(n12169), + .CI(n4621), .O(n4618), .CO(n4619)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_1/add_105/i3 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/add_105/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_1/add_105/i2 (.I0(\u_rgb2dvi/enc_1/acc[1] ), .I1(n12172), + .CI(n4561), .O(n4620), .CO(n4621)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_1/add_105/i2 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_1/add_105/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_0/sub_79/add_2/i5 (.I0(n4631), .I1(1'b1), .CI(n4624), + .O(n4622)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(93) + defparam \u_rgb2dvi/enc_0/sub_79/add_2/i5 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/sub_79/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_0/sub_79/add_2/i4 (.I0(n4632), .I1(1'b1), .CI(n4626), + .O(n4623), .CO(n4624)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(93) + defparam \u_rgb2dvi/enc_0/sub_79/add_2/i4 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/sub_79/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_0/sub_79/add_2/i3 (.I0(n4602), .I1(1'b1), .CI(n4586), + .O(n4625), .CO(n4626)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(93) + defparam \u_rgb2dvi/enc_0/sub_79/add_2/i3 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/sub_79/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_0/sub_52/add_2/i4 (.I0(n12180), .I1(n12187), + .CI(n4630), .O(n4627), .CO(n4628)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(79) + defparam \u_rgb2dvi/enc_0/sub_52/add_2/i4 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/sub_52/add_2/i4 .I1_POLARITY = 1'b0; + EFX_ADD \u_rgb2dvi/enc_0/sub_52/add_2/i3 (.I0(n12183), .I1(n12143), + .CI(n4601), .O(n4629), .CO(n4630)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(79) + defparam \u_rgb2dvi/enc_0/sub_52/add_2/i3 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/sub_52/add_2/i3 .I1_POLARITY = 1'b0; + EFX_ADD \u_rgb2dvi/enc_0/sub_50/add_2/i5 (.I0(1'b0), .I1(1'b1), .CI(n4633), + .O(n4631)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(74) + defparam \u_rgb2dvi/enc_0/sub_50/add_2/i5 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/sub_50/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_0/sub_50/add_2/i4 (.I0(n12187), .I1(n12180), + .CI(n4603), .O(n4632), .CO(n4633)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(74) + defparam \u_rgb2dvi/enc_0/sub_50/add_2/i4 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/sub_50/add_2/i4 .I1_POLARITY = 1'b0; + EFX_ADD \u_rgb2dvi/enc_0/add_105/i5 (.I0(\u_rgb2dvi/enc_0/acc[4] ), .I1(n12191), + .CI(n4636), .O(n4634)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_0/add_105/i5 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/add_105/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_0/add_105/i4 (.I0(\u_rgb2dvi/enc_0/acc[3] ), .I1(n12194), + .CI(n4638), .O(n4635), .CO(n4636)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_0/add_105/i4 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/add_105/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_0/add_105/i3 (.I0(\u_rgb2dvi/enc_0/acc[2] ), .I1(n12197), + .CI(n4640), .O(n4637), .CO(n4638)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_0/add_105/i3 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/add_105/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_0/add_105/i2 (.I0(\u_rgb2dvi/enc_0/acc[1] ), .I1(n12200), + .CI(n4544), .O(n4639), .CO(n4640)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(98) + defparam \u_rgb2dvi/enc_0/add_105/i2 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/add_105/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_0/add_75/i5 (.I0(n4599), .I1(1'b0), .CI(n4643), + .O(n4641)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(88) + defparam \u_rgb2dvi/enc_0/add_75/i5 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/add_75/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_rgb2dvi/enc_0/add_75/i4 (.I0(n4627), .I1(1'b0), .CI(n4614), + .O(n4642), .CO(n4643)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(88) + defparam \u_rgb2dvi/enc_0/add_75/i4 .I0_POLARITY = 1'b1; + defparam \u_rgb2dvi/enc_0/add_75/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_19/i12 (.I0(\u_lcd_driver/vcnt[11] ), .I1(1'b0), + .CI(n4646), .O(n4644)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(107) + defparam \u_lcd_driver/add_19/i12 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_19/i12 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_19/i11 (.I0(\u_lcd_driver/vcnt[10] ), .I1(1'b0), + .CI(n4648), .O(n4645), .CO(n4646)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(107) + defparam \u_lcd_driver/add_19/i11 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_19/i11 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_19/i10 (.I0(\u_lcd_driver/vcnt[9] ), .I1(1'b0), + .CI(n4650), .O(n4647), .CO(n4648)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(107) + defparam \u_lcd_driver/add_19/i10 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_19/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_19/i9 (.I0(\u_lcd_driver/vcnt[8] ), .I1(1'b0), + .CI(n4652), .O(n4649), .CO(n4650)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(107) + defparam \u_lcd_driver/add_19/i9 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_19/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_19/i8 (.I0(\u_lcd_driver/vcnt[7] ), .I1(1'b0), + .CI(n4654), .O(n4651), .CO(n4652)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(107) + defparam \u_lcd_driver/add_19/i8 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_19/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_19/i7 (.I0(\u_lcd_driver/vcnt[6] ), .I1(1'b0), + .CI(n4656), .O(n4653), .CO(n4654)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(107) + defparam \u_lcd_driver/add_19/i7 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_19/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_19/i6 (.I0(\u_lcd_driver/vcnt[5] ), .I1(1'b0), + .CI(n4658), .O(n4655), .CO(n4656)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(107) + defparam \u_lcd_driver/add_19/i6 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_19/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_19/i5 (.I0(\u_lcd_driver/vcnt[4] ), .I1(1'b0), + .CI(n4660), .O(n4657), .CO(n4658)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(107) + defparam \u_lcd_driver/add_19/i5 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_19/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_19/i4 (.I0(\u_lcd_driver/vcnt[3] ), .I1(1'b0), + .CI(n4662), .O(n4659), .CO(n4660)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(107) + defparam \u_lcd_driver/add_19/i4 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_19/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_19/i3 (.I0(\u_lcd_driver/vcnt[2] ), .I1(1'b0), + .CI(n4504), .O(n4661), .CO(n4662)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(107) + defparam \u_lcd_driver/add_19/i3 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_19/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i14 (.I0(\u_lcd_driver/hcnt[13] ), .I1(1'b0), + .CI(n4665), .O(n4663)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i14 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i14 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i13 (.I0(\u_lcd_driver/hcnt[12] ), .I1(1'b0), + .CI(n4667), .O(n4664), .CO(n4665)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i13 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i13 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i12 (.I0(\u_lcd_driver/hcnt[11] ), .I1(1'b0), + .CI(n4669), .O(n4666), .CO(n4667)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i12 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i12 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i11 (.I0(\u_lcd_driver/hcnt[10] ), .I1(1'b0), + .CI(n4671), .O(n4668), .CO(n4669)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i11 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i11 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i10 (.I0(\u_lcd_driver/hcnt[9] ), .I1(1'b0), + .CI(n4673), .O(n4670), .CO(n4671)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i10 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i9 (.I0(\u_lcd_driver/hcnt[8] ), .I1(1'b0), + .CI(n4675), .O(n4672), .CO(n4673)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i9 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i8 (.I0(\u_lcd_driver/hcnt[7] ), .I1(1'b0), + .CI(n4677), .O(n4674), .CO(n4675)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i8 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i7 (.I0(\u_lcd_driver/hcnt[6] ), .I1(1'b0), + .CI(n4679), .O(n4676), .CO(n4677)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i7 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i6 (.I0(\u_lcd_driver/hcnt[5] ), .I1(1'b0), + .CI(n4681), .O(n4678), .CO(n4679)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i6 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i5 (.I0(\u_lcd_driver/hcnt[4] ), .I1(1'b0), + .CI(n4683), .O(n4680), .CO(n4681)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i5 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i4 (.I0(\u_lcd_driver/hcnt[3] ), .I1(1'b0), + .CI(n4685), .O(n4682), .CO(n4683)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i4 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_lcd_driver/add_7/i3 (.I0(\u_lcd_driver/hcnt[2] ), .I1(1'b0), + .CI(n4352), .O(n4684), .CO(n4685)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\lcd_driver.v(88) + defparam \u_lcd_driver/add_7/i3 .I0_POLARITY = 1'b1; + defparam \u_lcd_driver/add_7/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i10 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13] ), + .CI(n4695), .O(n4693)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1184) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i10 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i10 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i9 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12] ), + .CI(n4697), .O(n4694), .CO(n4695)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1184) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i9 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i9 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i8 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11] ), + .CI(n4699), .CO(n4697)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1184) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i8 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i8 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i7 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10] ), + .CI(n4701), .CO(n4699)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1184) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i7 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i7 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i6 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9] ), + .CI(n4703), .CO(n4701)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1184) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i6 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i6 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i5 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8] ), + .CI(n4705), .CO(n4703)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1184) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i5 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i5 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i4 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7] ), + .CI(n4707), .CO(n4705)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1184) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i4 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i4 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i3 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6] ), + .CI(n4709), .CO(n4707)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1184) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i3 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i3 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i2 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5] ), + .CI(n4234), .CO(n4709)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1184) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i2 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i2 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i14 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13] ), + .I1(1'b0), .CI(n4712), .O(n4710)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i14 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i14 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i13 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] ), + .I1(1'b0), .CI(n4714), .O(n4711), .CO(n4712)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i13 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i13 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i12 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] ), + .I1(1'b0), .CI(n4716), .O(n4713), .CO(n4714)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i12 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i12 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i11 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] ), + .I1(1'b0), .CI(n4718), .O(n4715), .CO(n4716)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i11 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i11 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i10 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] ), + .I1(1'b0), .CI(n4720), .O(n4717), .CO(n4718)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i10 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i9 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] ), + .I1(1'b0), .CI(n4722), .O(n4719), .CO(n4720)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i9 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i8 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] ), + .I1(1'b0), .CI(n4724), .O(n4721), .CO(n4722)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i8 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i7 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] ), + .I1(1'b0), .CI(n4726), .O(n4723), .CO(n4724)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i7 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i6 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] ), + .I1(1'b0), .CI(n4728), .O(n4725), .CO(n4726)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i6 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i5 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] ), + .I1(1'b0), .CI(n4730), .O(n4727), .CO(n4728)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i5 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i4 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3] ), + .I1(1'b0), .CI(n4732), .O(n4729), .CO(n4730)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i4 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i3 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2] ), + .I1(1'b0), .CI(n4231), .O(n4731), .CO(n4732)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i3 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_62/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i10 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9] ), + .I1(1'b0), .CI(n4735), .O(n4733)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i10 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i9 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] ), + .I1(1'b0), .CI(n4737), .O(n4734), .CO(n4735)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i9 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i8 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] ), + .I1(1'b0), .CI(n4739), .O(n4736), .CO(n4737)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i8 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i7 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] ), + .I1(1'b0), .CI(n4741), .O(n4738), .CO(n4739)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i7 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i6 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] ), + .I1(1'b0), .CI(n4743), .O(n4740), .CO(n4741)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i6 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i5 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] ), + .I1(1'b0), .CI(n4745), .O(n4742), .CO(n4743)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i5 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i4 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] ), + .I1(1'b0), .CI(n4223), .O(n4744), .CO(n4745)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i4 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_58/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/sub_122/add_2/i5 (.I0(\u_axi4_ctrl/rfifo_cnt[4] ), + .I1(1'b1), .CI(n4748), .O(n4746)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(367) + defparam \u_axi4_ctrl/sub_122/add_2/i5 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/sub_122/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/sub_122/add_2/i4 (.I0(\u_axi4_ctrl/rfifo_cnt[3] ), + .I1(1'b1), .CI(n4750), .O(n4747), .CO(n4748)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(367) + defparam \u_axi4_ctrl/sub_122/add_2/i4 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/sub_122/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/sub_122/add_2/i3 (.I0(\u_axi4_ctrl/rfifo_cnt[2] ), + .I1(1'b1), .CI(n4752), .O(n4749), .CO(n4750)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(367) + defparam \u_axi4_ctrl/sub_122/add_2/i3 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/sub_122/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/sub_122/add_2/i2 (.I0(\u_axi4_ctrl/rfifo_cnt[1] ), + .I1(1'b1), .CI(n4124), .O(n4751), .CO(n4752)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(367) + defparam \u_axi4_ctrl/sub_122/add_2/i2 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/sub_122/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i10 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_w[9] ), + .CI(n4755), .O(n4753)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1191) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i10 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i10 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i9 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12] ), + .I1(n12315), .CI(n4757), .O(n4754), .CO(n4755)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1191) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i9 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i8 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11] ), + .I1(n12318), .CI(n4758), .O(n4756), .CO(n4757)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1191) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i8 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i7 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10] ), + .I1(n12321), .CI(n4759), .CO(n4758)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1191) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i7 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i6 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9] ), + .I1(n12324), .CI(n4760), .CO(n4759)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1191) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i6 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i5 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8] ), + .I1(n12327), .CI(n4761), .CO(n4760)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1191) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i5 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i4 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7] ), + .I1(n12330), .CI(n4762), .CO(n4761)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1191) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i4 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i3 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6] ), + .I1(n12333), .CI(n4763), .CO(n4762)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1191) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i3 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i2 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5] ), + .I1(n12336), .CI(n4122), .CO(n4763)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1191) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i2 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i15 (.I0(1'b0), + .I1(1'b1), .CI(n4766), .O(n4764)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i15 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i15 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i14 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[13] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9] ), + .CI(n4768), .O(n4765), .CO(n4766)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i14 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i14 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i13 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[12] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] ), + .CI(n4770), .O(n4767), .CO(n4768)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i13 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i13 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i12 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[11] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] ), + .CI(n4772), .O(n4769), .CO(n4770)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i12 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i12 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i11 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[10] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] ), + .CI(n4774), .O(n4771), .CO(n4772)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i11 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i11 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i10 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] ), + .CI(n4776), .O(n4773), .CO(n4774)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i10 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i10 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i9 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] ), + .CI(n4778), .O(n4775), .CO(n4776)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i9 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i9 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i8 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] ), + .CI(n4780), .O(n4777), .CO(n4778)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i8 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i8 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i7 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] ), + .CI(n4782), .O(n4779), .CO(n4780)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i7 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i7 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i6 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] ), + .CI(n4103), .O(n4781), .CO(n4782)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i6 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i6 .I1_POLARITY = 1'b0; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i10 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9] ), + .I1(1'b0), .CI(n4785), .O(n4783)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i10 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i9 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] ), + .I1(1'b0), .CI(n4787), .O(n4784), .CO(n4785)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i9 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i8 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] ), + .I1(1'b0), .CI(n4789), .O(n4786), .CO(n4787)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i8 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i7 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] ), + .I1(1'b0), .CI(n4791), .O(n4788), .CO(n4789)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i7 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i6 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] ), + .I1(1'b0), .CI(n4793), .O(n4790), .CO(n4791)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i6 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i5 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] ), + .I1(1'b0), .CI(n4795), .O(n4792), .CO(n4793)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i5 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i4 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] ), + .I1(1'b0), .CI(n4797), .O(n4794), .CO(n4795)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i4 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i3 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] ), + .I1(1'b0), .CI(n4100), .O(n4796), .CO(n4797)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1210) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i3 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_60/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i14 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13] ), + .I1(1'b0), .CI(n4800), .O(n4798)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i14 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i14 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i13 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] ), + .I1(1'b0), .CI(n4802), .O(n4799), .CO(n4800)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i13 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i13 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i12 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] ), + .I1(1'b0), .CI(n4804), .O(n4801), .CO(n4802)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i12 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i12 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i11 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] ), + .I1(1'b0), .CI(n4806), .O(n4803), .CO(n4804)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i11 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i11 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i10 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] ), + .I1(1'b0), .CI(n4808), .O(n4805), .CO(n4806)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i10 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i9 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] ), + .I1(1'b0), .CI(n4810), .O(n4807), .CO(n4808)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i9 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i8 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] ), + .I1(1'b0), .CI(n4812), .O(n4809), .CO(n4810)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i8 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i7 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] ), + .I1(1'b0), .CI(n4814), .O(n4811), .CO(n4812)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i7 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i6 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] ), + .I1(1'b0), .CI(n4816), .O(n4813), .CO(n4814)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i6 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i5 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] ), + .I1(1'b0), .CI(n4818), .O(n4815), .CO(n4816)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i5 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i4 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3] ), + .I1(1'b0), .CI(n4065), .O(n4817), .CO(n4818)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1200) + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i4 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/add_56/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_177/i11 (.I0(\w_ddr3_araddr[21] ), .I1(1'b0), + .CI(n4834), .O(n4832)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(559) + defparam \u_axi4_ctrl/add_177/i11 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_177/i11 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_177/i10 (.I0(\w_ddr3_araddr[20] ), .I1(1'b0), + .CI(n4836), .O(n4833), .CO(n4834)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(559) + defparam \u_axi4_ctrl/add_177/i10 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_177/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_177/i9 (.I0(\w_ddr3_araddr[19] ), .I1(1'b0), + .CI(n4838), .O(n4835), .CO(n4836)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(559) + defparam \u_axi4_ctrl/add_177/i9 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_177/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_177/i8 (.I0(\w_ddr3_araddr[18] ), .I1(1'b0), + .CI(n4840), .O(n4837), .CO(n4838)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(559) + defparam \u_axi4_ctrl/add_177/i8 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_177/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_177/i7 (.I0(\w_ddr3_araddr[17] ), .I1(1'b0), + .CI(n4842), .O(n4839), .CO(n4840)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(559) + defparam \u_axi4_ctrl/add_177/i7 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_177/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_177/i6 (.I0(\w_ddr3_araddr[16] ), .I1(1'b0), + .CI(n4844), .O(n4841), .CO(n4842)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(559) + defparam \u_axi4_ctrl/add_177/i6 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_177/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_177/i5 (.I0(\w_ddr3_araddr[15] ), .I1(1'b0), + .CI(n4846), .O(n4843), .CO(n4844)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(559) + defparam \u_axi4_ctrl/add_177/i5 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_177/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_177/i4 (.I0(\w_ddr3_araddr[14] ), .I1(1'b0), + .CI(n4848), .O(n4845), .CO(n4846)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(559) + defparam \u_axi4_ctrl/add_177/i4 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_177/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_177/i3 (.I0(\w_ddr3_araddr[13] ), .I1(1'b0), + .CI(n3906), .O(n4847), .CO(n4848)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(559) + defparam \u_axi4_ctrl/add_177/i3 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_177/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_63/i8 (.I0(\u_axi4_ctrl/rc_burst[7] ), .I1(1'b0), + .CI(n4851), .O(n4849)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(246) + defparam \u_axi4_ctrl/add_63/i8 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_63/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_63/i7 (.I0(\u_axi4_ctrl/rc_burst[6] ), .I1(1'b0), + .CI(n4853), .O(n4850), .CO(n4851)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(246) + defparam \u_axi4_ctrl/add_63/i7 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_63/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_63/i6 (.I0(\u_axi4_ctrl/rc_burst[5] ), .I1(1'b0), + .CI(n4855), .O(n4852), .CO(n4853)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(246) + defparam \u_axi4_ctrl/add_63/i6 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_63/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_63/i5 (.I0(\u_axi4_ctrl/rc_burst[4] ), .I1(1'b0), + .CI(n4857), .O(n4854), .CO(n4855)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(246) + defparam \u_axi4_ctrl/add_63/i5 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_63/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_63/i4 (.I0(\u_axi4_ctrl/rc_burst[3] ), .I1(1'b0), + .CI(n4859), .O(n4856), .CO(n4857)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(246) + defparam \u_axi4_ctrl/add_63/i4 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_63/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_63/i3 (.I0(\u_axi4_ctrl/rc_burst[2] ), .I1(1'b0), + .CI(n4861), .O(n4858), .CO(n4859)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(246) + defparam \u_axi4_ctrl/add_63/i3 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_63/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_axi4_ctrl/add_63/i2 (.I0(\u_axi4_ctrl/rc_burst[1] ), .I1(1'b0), + .CI(n3873), .O(n4860), .CO(n4861)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(246) + defparam \u_axi4_ctrl/add_63/i2 .I0_POLARITY = 1'b1; + defparam \u_axi4_ctrl/add_63/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i12 (.I0(\u_Sensor_Image_XYCrop/image_xpos[11] ), + .I1(1'b0), .CI(n4864), .O(n4862)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i12 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i12 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i11 (.I0(\u_Sensor_Image_XYCrop/image_xpos[10] ), + .I1(1'b0), .CI(n4866), .O(n4863), .CO(n4864)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i11 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i11 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i10 (.I0(\u_Sensor_Image_XYCrop/image_xpos[9] ), + .I1(1'b0), .CI(n4868), .O(n4865), .CO(n4866)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i10 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i9 (.I0(\u_Sensor_Image_XYCrop/image_xpos[8] ), + .I1(1'b0), .CI(n4870), .O(n4867), .CO(n4868)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i9 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i8 (.I0(\u_Sensor_Image_XYCrop/image_xpos[7] ), + .I1(1'b0), .CI(n4872), .O(n4869), .CO(n4870)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i8 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i7 (.I0(\u_Sensor_Image_XYCrop/image_xpos[6] ), + .I1(1'b0), .CI(n4874), .O(n4871), .CO(n4872)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i7 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i6 (.I0(\u_Sensor_Image_XYCrop/image_xpos[5] ), + .I1(1'b0), .CI(n4876), .O(n4873), .CO(n4874)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i6 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i5 (.I0(\u_Sensor_Image_XYCrop/image_xpos[4] ), + .I1(1'b0), .CI(n4878), .O(n4875), .CO(n4876)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i5 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i4 (.I0(\u_Sensor_Image_XYCrop/image_xpos[3] ), + .I1(1'b0), .CI(n4880), .O(n4877), .CO(n4878)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i4 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i3 (.I0(\u_Sensor_Image_XYCrop/image_xpos[2] ), + .I1(1'b0), .CI(n4882), .O(n4879), .CO(n4880)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i3 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_27/i2 (.I0(\u_Sensor_Image_XYCrop/image_xpos[1] ), + .I1(1'b0), .CI(n3865), .O(n4881), .CO(n4882)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(113) + defparam \u_Sensor_Image_XYCrop/add_27/i2 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_27/i2 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_18/i12 (.I0(\u_Sensor_Image_XYCrop/image_ypos[11] ), + .I1(1'b0), .CI(n4885), .O(n4883)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(94) + defparam \u_Sensor_Image_XYCrop/add_18/i12 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_18/i12 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_18/i11 (.I0(\u_Sensor_Image_XYCrop/image_ypos[10] ), + .I1(1'b0), .CI(n4887), .O(n4884), .CO(n4885)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(94) + defparam \u_Sensor_Image_XYCrop/add_18/i11 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_18/i11 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_18/i10 (.I0(\u_Sensor_Image_XYCrop/image_ypos[9] ), + .I1(1'b0), .CI(n4889), .O(n4886), .CO(n4887)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(94) + defparam \u_Sensor_Image_XYCrop/add_18/i10 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_18/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_18/i9 (.I0(\u_Sensor_Image_XYCrop/image_ypos[8] ), + .I1(1'b0), .CI(n4891), .O(n4888), .CO(n4889)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(94) + defparam \u_Sensor_Image_XYCrop/add_18/i9 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_18/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_18/i8 (.I0(\u_Sensor_Image_XYCrop/image_ypos[7] ), + .I1(1'b0), .CI(n4893), .O(n4890), .CO(n4891)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(94) + defparam \u_Sensor_Image_XYCrop/add_18/i8 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_18/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_18/i7 (.I0(\u_Sensor_Image_XYCrop/image_ypos[6] ), + .I1(1'b0), .CI(n4895), .O(n4892), .CO(n4893)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(94) + defparam \u_Sensor_Image_XYCrop/add_18/i7 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_18/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_18/i6 (.I0(\u_Sensor_Image_XYCrop/image_ypos[5] ), + .I1(1'b0), .CI(n4897), .O(n4894), .CO(n4895)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(94) + defparam \u_Sensor_Image_XYCrop/add_18/i6 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_18/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_18/i5 (.I0(\u_Sensor_Image_XYCrop/image_ypos[4] ), + .I1(1'b0), .CI(n4899), .O(n4896), .CO(n4897)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(94) + defparam \u_Sensor_Image_XYCrop/add_18/i5 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_18/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_18/i4 (.I0(\u_Sensor_Image_XYCrop/image_ypos[3] ), + .I1(1'b0), .CI(n4901), .O(n4898), .CO(n4899)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(94) + defparam \u_Sensor_Image_XYCrop/add_18/i4 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_18/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_Sensor_Image_XYCrop/add_18/i3 (.I0(\u_Sensor_Image_XYCrop/image_ypos[2] ), + .I1(1'b0), .CI(n3845), .O(n4900), .CO(n4901)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\Sensor_Image_XYCrop.v(94) + defparam \u_Sensor_Image_XYCrop/add_18/i3 .I0_POLARITY = 1'b1; + defparam \u_Sensor_Image_XYCrop/add_18/i3 .I1_POLARITY = 1'b1; + EFX_ADD \dsi_pwm/add_4/i7 (.I0(\dsi_pwm/rc_pwm[6] ), .I1(1'b0), .CI(n4904), + .O(n4902)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(22) + defparam \dsi_pwm/add_4/i7 .I0_POLARITY = 1'b1; + defparam \dsi_pwm/add_4/i7 .I1_POLARITY = 1'b1; + EFX_ADD \dsi_pwm/add_4/i6 (.I0(\dsi_pwm/rc_pwm[5] ), .I1(1'b0), .CI(n4906), + .O(n4903), .CO(n4904)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(22) + defparam \dsi_pwm/add_4/i6 .I0_POLARITY = 1'b1; + defparam \dsi_pwm/add_4/i6 .I1_POLARITY = 1'b1; + EFX_ADD \dsi_pwm/add_4/i5 (.I0(\dsi_pwm/rc_pwm[4] ), .I1(1'b0), .CI(n4908), + .O(n4905), .CO(n4906)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(22) + defparam \dsi_pwm/add_4/i5 .I0_POLARITY = 1'b1; + defparam \dsi_pwm/add_4/i5 .I1_POLARITY = 1'b1; + EFX_ADD \dsi_pwm/add_4/i4 (.I0(\dsi_pwm/rc_pwm[3] ), .I1(1'b0), .CI(n4910), + .O(n4907), .CO(n4908)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(22) + defparam \dsi_pwm/add_4/i4 .I0_POLARITY = 1'b1; + defparam \dsi_pwm/add_4/i4 .I1_POLARITY = 1'b1; + EFX_ADD \dsi_pwm/add_4/i3 (.I0(\dsi_pwm/rc_pwm[2] ), .I1(1'b0), .CI(n3765), + .O(n4909), .CO(n4910)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\PWMLite.v(22) + defparam \dsi_pwm/add_4/i3 .I0_POLARITY = 1'b1; + defparam \dsi_pwm/add_4/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_50/i8 (.I0(\ar0135_i2c_config_index[7] ), + .I1(1'b0), .CI(n4913), .O(n4911)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(188) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i8 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_50/i7 (.I0(\ar0135_i2c_config_index[6] ), + .I1(1'b0), .CI(n4915), .O(n4912), .CO(n4913)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(188) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i7 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_50/i6 (.I0(\ar0135_i2c_config_index[5] ), + .I1(1'b0), .CI(n4917), .O(n4914), .CO(n4915)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(188) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i6 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_50/i5 (.I0(\ar0135_i2c_config_index[4] ), + .I1(1'b0), .CI(n4919), .O(n4916), .CO(n4917)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(188) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i5 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_50/i4 (.I0(\ar0135_i2c_config_index[3] ), + .I1(1'b0), .CI(n4921), .O(n4918), .CO(n4919)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(188) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i4 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_50/i3 (.I0(\ar0135_i2c_config_index[2] ), + .I1(1'b0), .CI(n3758), .O(n4920), .CO(n4921)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(188) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i3 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_50/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i16 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15] ), + .I1(1'b0), .CI(n4924), .O(n4922)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i16 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i16 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i15 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14] ), + .I1(1'b0), .CI(n4926), .O(n4923), .CO(n4924)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i15 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i15 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i14 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13] ), + .I1(1'b0), .CI(n4928), .O(n4925), .CO(n4926)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i14 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i14 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i13 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12] ), + .I1(1'b0), .CI(n4930), .O(n4927), .CO(n4928)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i13 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i13 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i12 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11] ), + .I1(1'b0), .CI(n4932), .O(n4929), .CO(n4930)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i12 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i12 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i11 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10] ), + .I1(1'b0), .CI(n4934), .O(n4931), .CO(n4932)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i11 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i11 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i10 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9] ), + .I1(1'b0), .CI(n4936), .O(n4933), .CO(n4934)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i10 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i9 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8] ), + .I1(1'b0), .CI(n4938), .O(n4935), .CO(n4936)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i9 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i8 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7] ), + .I1(1'b0), .CI(n4940), .O(n4937), .CO(n4938)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i8 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i7 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6] ), + .I1(1'b0), .CI(n4942), .O(n4939), .CO(n4940)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i7 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i6 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5] ), + .I1(1'b0), .CI(n4944), .O(n4941), .CO(n4942)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i6 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i5 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4] ), + .I1(1'b0), .CI(n4946), .O(n4943), .CO(n4944)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i5 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i4 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3] ), + .I1(1'b0), .CI(n4948), .O(n4945), .CO(n4946)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i4 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_16/i3 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2] ), + .I1(1'b0), .CI(n3755), .O(n4947), .CO(n4948)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(104) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i3 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_16/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i20 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19] ), + .I1(1'b0), .CI(n4951), .O(n4949)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i20 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i20 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i19 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18] ), + .I1(1'b0), .CI(n4953), .O(n4950), .CO(n4951)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i19 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i19 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i18 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17] ), + .I1(1'b0), .CI(n4955), .O(n4952), .CO(n4953)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i18 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i18 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i17 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16] ), + .I1(1'b0), .CI(n4957), .O(n4954), .CO(n4955)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i17 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i17 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i16 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15] ), + .I1(1'b0), .CI(n4959), .O(n4956), .CO(n4957)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i16 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i16 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i15 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14] ), + .I1(1'b0), .CI(n4961), .O(n4958), .CO(n4959)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i15 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i15 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i14 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13] ), + .I1(1'b0), .CI(n4963), .O(n4960), .CO(n4961)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i14 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i14 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i13 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12] ), + .I1(1'b0), .CI(n4965), .O(n4962), .CO(n4963)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i13 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i13 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i12 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11] ), + .I1(1'b0), .CI(n4967), .O(n4964), .CO(n4965)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i12 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i12 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i11 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10] ), + .I1(1'b0), .CI(n4969), .O(n4966), .CO(n4967)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i11 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i11 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i10 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9] ), + .I1(1'b0), .CI(n4971), .O(n4968), .CO(n4969)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i10 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i9 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8] ), + .I1(1'b0), .CI(n4973), .O(n4970), .CO(n4971)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i9 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i8 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7] ), + .I1(1'b0), .CI(n4975), .O(n4972), .CO(n4973)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i8 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i7 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6] ), + .I1(1'b0), .CI(n4977), .O(n4974), .CO(n4975)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i7 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i6 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5] ), + .I1(1'b0), .CI(n4979), .O(n4976), .CO(n4977)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i6 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i5 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4] ), + .I1(1'b0), .CI(n4981), .O(n4978), .CO(n4979)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i5 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i4 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3] ), + .I1(1'b0), .CI(n4983), .O(n4980), .CO(n4981)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i4 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16reg_16bit/add_7/i3 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2] ), + .I1(1'b0), .CI(n3688), .O(n4982), .CO(n4983)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_reg16_dat16.v(69) + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i3 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16reg_16bit/add_7/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_45/i8 (.I0(\sc130_i2c_config_index[7] ), + .I1(1'b0), .CI(n4986), .O(n4984)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(164) + defparam \u_i2c_timing_ctrl_16bit/add_45/i8 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_45/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_45/i7 (.I0(\sc130_i2c_config_index[6] ), + .I1(1'b0), .CI(n4988), .O(n4985), .CO(n4986)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(164) + defparam \u_i2c_timing_ctrl_16bit/add_45/i7 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_45/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_45/i6 (.I0(\sc130_i2c_config_index[5] ), + .I1(1'b0), .CI(n4990), .O(n4987), .CO(n4988)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(164) + defparam \u_i2c_timing_ctrl_16bit/add_45/i6 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_45/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_45/i5 (.I0(\sc130_i2c_config_index[4] ), + .I1(1'b0), .CI(n4992), .O(n4989), .CO(n4990)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(164) + defparam \u_i2c_timing_ctrl_16bit/add_45/i5 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_45/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_45/i4 (.I0(\sc130_i2c_config_index[3] ), + .I1(1'b0), .CI(n4994), .O(n4991), .CO(n4992)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(164) + defparam \u_i2c_timing_ctrl_16bit/add_45/i4 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_45/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_45/i3 (.I0(\sc130_i2c_config_index[2] ), + .I1(1'b0), .CI(n3682), .O(n4993), .CO(n4994)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(164) + defparam \u_i2c_timing_ctrl_16bit/add_45/i3 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_45/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i16 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[15] ), + .I1(1'b0), .CI(n4997), .O(n4995)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i16 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i16 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i15 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[14] ), + .I1(1'b0), .CI(n4999), .O(n4996), .CO(n4997)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i15 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i15 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i14 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[13] ), + .I1(1'b0), .CI(n5001), .O(n4998), .CO(n4999)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i14 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i14 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i13 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[12] ), + .I1(1'b0), .CI(n5003), .O(n5000), .CO(n5001)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i13 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i13 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i12 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[11] ), + .I1(1'b0), .CI(n5005), .O(n5002), .CO(n5003)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i12 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i12 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i11 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[10] ), + .I1(1'b0), .CI(n5007), .O(n5004), .CO(n5005)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i11 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i11 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i10 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[9] ), + .I1(1'b0), .CI(n5009), .O(n5006), .CO(n5007)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i10 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i9 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[8] ), + .I1(1'b0), .CI(n5011), .O(n5008), .CO(n5009)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i9 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i8 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[7] ), + .I1(1'b0), .CI(n5013), .O(n5010), .CO(n5011)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i8 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i7 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[6] ), + .I1(1'b0), .CI(n5015), .O(n5012), .CO(n5013)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i7 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i6 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[5] ), + .I1(1'b0), .CI(n5017), .O(n5014), .CO(n5015)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i6 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i5 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[4] ), + .I1(1'b0), .CI(n5019), .O(n5016), .CO(n5017)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i5 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i4 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[3] ), + .I1(1'b0), .CI(n5021), .O(n5018), .CO(n5019)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i4 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_16/i3 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[2] ), + .I1(1'b0), .CI(n3679), .O(n5020), .CO(n5021)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(102) + defparam \u_i2c_timing_ctrl_16bit/add_16/i3 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_16/i3 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i20 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[19] ), + .I1(1'b0), .CI(n5024), .O(n5022)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i20 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i20 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i19 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[18] ), + .I1(1'b0), .CI(n5026), .O(n5023), .CO(n5024)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i19 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i19 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i18 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[17] ), + .I1(1'b0), .CI(n5028), .O(n5025), .CO(n5026)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i18 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i18 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i17 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[16] ), + .I1(1'b0), .CI(n5030), .O(n5027), .CO(n5028)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i17 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i17 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i16 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[15] ), + .I1(1'b0), .CI(n5032), .O(n5029), .CO(n5030)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i16 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i16 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i15 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[14] ), + .I1(1'b0), .CI(n5034), .O(n5031), .CO(n5032)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i15 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i15 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i14 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[13] ), + .I1(1'b0), .CI(n5036), .O(n5033), .CO(n5034)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i14 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i14 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i13 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[12] ), + .I1(1'b0), .CI(n5038), .O(n5035), .CO(n5036)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i13 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i13 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i12 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[11] ), + .I1(1'b0), .CI(n5040), .O(n5037), .CO(n5038)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i12 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i12 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i11 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[10] ), + .I1(1'b0), .CI(n5042), .O(n5039), .CO(n5040)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i11 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i11 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i10 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[9] ), + .I1(1'b0), .CI(n5044), .O(n5041), .CO(n5042)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i10 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i10 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i9 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[8] ), + .I1(1'b0), .CI(n5046), .O(n5043), .CO(n5044)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i9 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i9 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i8 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[7] ), + .I1(1'b0), .CI(n5048), .O(n5045), .CO(n5046)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i8 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i8 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i7 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[6] ), + .I1(1'b0), .CI(n5050), .O(n5047), .CO(n5048)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i7 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i7 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i6 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[5] ), + .I1(1'b0), .CI(n5052), .O(n5049), .CO(n5050)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i6 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i6 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i5 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[4] ), + .I1(1'b0), .CI(n5054), .O(n5051), .CO(n5052)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i5 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i5 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i4 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[3] ), + .I1(1'b0), .CI(n5056), .O(n5053), .CO(n5054)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i4 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i4 .I1_POLARITY = 1'b1; + EFX_ADD \u_i2c_timing_ctrl_16bit/add_7/i3 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[2] ), + .I1(1'b0), .CI(n2967), .O(n5055), .CO(n5056)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\cmos_i2c\i2c_timing_ctrl_16bit.v(67) + defparam \u_i2c_timing_ctrl_16bit/add_7/i3 .I0_POLARITY = 1'b1; + defparam \u_i2c_timing_ctrl_16bit/add_7/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15] ), + .I1(1'b0), .CI(n5059), .O(n5057)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14] ), + .I1(1'b0), .CI(n5061), .O(n5058), .CO(n5059)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13] ), + .I1(1'b0), .CI(n5063), .O(n5060), .CO(n5061)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12] ), + .I1(1'b0), .CI(n5065), .O(n5062), .CO(n5063)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11] ), + .I1(1'b0), .CI(n5067), .O(n5064), .CO(n5065)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10] ), + .I1(1'b0), .CI(n5069), .O(n5066), .CO(n5067)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9] ), + .I1(1'b0), .CI(n5071), .O(n5068), .CO(n5069)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[8] ), + .I1(1'b0), .CI(n5073), .O(n5070), .CO(n5071)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[7] ), + .I1(1'b0), .CI(n5075), .O(n5072), .CO(n5073)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[6] ), + .I1(1'b0), .CI(n5077), .O(n5074), .CO(n5075)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[5] ), + .I1(1'b0), .CI(n5079), .O(n5076), .CO(n5077)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[4] ), + .I1(1'b0), .CI(n5081), .O(n5078), .CO(n5079)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[3] ), + .I1(1'b0), .CI(n2663), .O(n5080), .CO(n5081)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2036/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15] ), + .I1(1'b0), .CI(n5084), .O(n5082)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14] ), + .I1(1'b0), .CI(n5086), .O(n5083), .CO(n5084)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13] ), + .I1(1'b0), .CI(n5088), .O(n5085), .CO(n5086)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12] ), + .I1(1'b0), .CI(n5090), .O(n5087), .CO(n5088)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11] ), + .I1(1'b0), .CI(n5092), .O(n5089), .CO(n5090)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10] ), + .I1(1'b0), .CI(n5094), .O(n5091), .CO(n5092)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9] ), + .I1(1'b0), .CI(n5096), .O(n5093), .CO(n5094)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8] ), + .I1(1'b0), .CI(n5098), .O(n5095), .CO(n5096)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7] ), + .I1(1'b0), .CI(n5100), .O(n5097), .CO(n5098)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6] ), + .I1(1'b0), .CI(n5102), .O(n5099), .CO(n5100)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5] ), + .I1(1'b0), .CI(n5104), .O(n5101), .CO(n5102)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4] ), + .I1(1'b0), .CI(n5106), .O(n5103), .CO(n5104)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3] ), + .I1(1'b0), .CI(n2661), .O(n5105), .CO(n5106)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2031/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i16 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15] ), + .I1(1'b0), .CI(n5109), .O(n5107)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i16 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i16 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14] ), + .I1(1'b0), .CI(n5111), .O(n5108), .CO(n5109)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13] ), + .I1(1'b0), .CI(n5113), .O(n5110), .CO(n5111)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12] ), + .I1(1'b0), .CI(n5115), .O(n5112), .CO(n5113)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11] ), + .I1(1'b0), .CI(n5117), .O(n5114), .CO(n5115)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10] ), + .I1(1'b0), .CI(n5119), .O(n5116), .CO(n5117)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9] ), + .I1(1'b0), .CI(n5121), .O(n5118), .CO(n5119)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8] ), + .I1(1'b0), .CI(n5123), .O(n5120), .CO(n5121)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7] ), + .I1(1'b0), .CI(n5125), .O(n5122), .CO(n5123)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6] ), + .I1(1'b0), .CI(n5127), .O(n5124), .CO(n5125)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5] ), + .I1(1'b0), .CI(n5129), .O(n5126), .CO(n5127)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4] ), + .I1(1'b0), .CI(n5131), .O(n5128), .CO(n5129)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3] ), + .I1(1'b0), .CI(n5133), .O(n5130), .CO(n5131)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2] ), + .I1(1'b0), .CI(n2647), .O(n5132), .CO(n5133)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_2030/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i16 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15] ), + .I1(1'b0), .CI(n5136), .O(n5134)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i16 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i16 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14] ), + .I1(1'b0), .CI(n5138), .O(n5135), .CO(n5136)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13] ), + .I1(1'b0), .CI(n5140), .O(n5137), .CO(n5138)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12] ), + .I1(1'b0), .CI(n5142), .O(n5139), .CO(n5140)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11] ), + .I1(1'b0), .CI(n5144), .O(n5141), .CO(n5142)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10] ), + .I1(1'b0), .CI(n5146), .O(n5143), .CO(n5144)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9] ), + .I1(1'b0), .CI(n5148), .O(n5145), .CO(n5146)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8] ), + .I1(1'b0), .CI(n5150), .O(n5147), .CO(n5148)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7] ), + .I1(1'b0), .CI(n5152), .O(n5149), .CO(n5150)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6] ), + .I1(1'b0), .CI(n5154), .O(n5151), .CO(n5152)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5] ), + .I1(1'b0), .CI(n5156), .O(n5153), .CO(n5154)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4] ), + .I1(1'b0), .CI(n5158), .O(n5155), .CO(n5156)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3] ), + .I1(1'b0), .CI(n5160), .O(n5157), .CO(n5158)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2] ), + .I1(1'b0), .CI(n5162), .O(n5159), .CO(n5160)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1] ), + .I1(1'b1), .CI(n2643), .O(n5161), .CO(n5162)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1668/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15] ), + .I1(1'b0), .CI(n5165), .O(n5163)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14] ), + .I1(1'b0), .CI(n5167), .O(n5164), .CO(n5165)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13] ), + .I1(1'b0), .CI(n5169), .O(n5166), .CO(n5167)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12] ), + .I1(1'b0), .CI(n5171), .O(n5168), .CO(n5169)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11] ), + .I1(1'b0), .CI(n5173), .O(n5170), .CO(n5171)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10] ), + .I1(1'b0), .CI(n5175), .O(n5172), .CO(n5173)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9] ), + .I1(1'b0), .CI(n5177), .O(n5174), .CO(n5175)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8] ), + .I1(1'b0), .CI(n5179), .O(n5176), .CO(n5177)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7] ), + .I1(1'b0), .CI(n5181), .O(n5178), .CO(n5179)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6] ), + .I1(1'b0), .CI(n5183), .O(n5180), .CO(n5181)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5] ), + .I1(1'b0), .CI(n5185), .O(n5182), .CO(n5183)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4] ), + .I1(1'b0), .CI(n2604), .O(n5184), .CO(n5185)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_1647/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i16 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15] ), + .I1(1'b1), .CI(n5188), .O(n5186)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i16 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i16 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14] ), + .I1(1'b1), .CI(n5190), .O(n5187), .CO(n5188)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13] ), + .I1(1'b1), .CI(n5192), .O(n5189), .CO(n5190)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12] ), + .I1(1'b1), .CI(n5194), .O(n5191), .CO(n5192)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11] ), + .I1(1'b1), .CI(n5196), .O(n5193), .CO(n5194)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10] ), + .I1(1'b1), .CI(n5198), .O(n5195), .CO(n5196)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9] ), + .I1(1'b1), .CI(n5200), .O(n5197), .CO(n5198)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8] ), + .I1(1'b1), .CI(n5202), .O(n5199), .CO(n5200)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7] ), + .I1(1'b1), .CI(n5204), .O(n5201), .CO(n5202)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6] ), + .I1(1'b1), .CI(n5206), .O(n5203), .CO(n5204)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5] ), + .I1(1'b1), .CI(n5208), .O(n5205), .CO(n5206)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4] ), + .I1(1'b1), .CI(n5210), .O(n5207), .CO(n5208)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3] ), + .I1(1'b1), .CI(n5212), .O(n5209), .CO(n5210)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2] ), + .I1(1'b1), .CI(n5214), .O(n5211), .CO(n5212)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1] ), + .I1(1'b1), .CI(n2116), .O(n5213), .CO(n5214)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15] ), + .I1(1'b0), .CI(n5217), .O(n5215)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14] ), + .I1(1'b0), .CI(n5219), .O(n5216), .CO(n5217)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13] ), + .I1(1'b0), .CI(n5221), .O(n5218), .CO(n5219)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12] ), + .I1(1'b0), .CI(n5223), .O(n5220), .CO(n5221)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11] ), + .I1(1'b0), .CI(n5225), .O(n5222), .CO(n5223)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10] ), + .I1(1'b0), .CI(n5227), .O(n5224), .CO(n5225)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9] ), + .I1(1'b0), .CI(n5229), .O(n5226), .CO(n5227)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8] ), + .I1(1'b0), .CI(n5231), .O(n5228), .CO(n5229)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7] ), + .I1(1'b0), .CI(n5233), .O(n5230), .CO(n5231)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6] ), + .I1(1'b0), .CI(n5235), .O(n5232), .CO(n5233)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5] ), + .I1(1'b0), .CI(n5237), .O(n5234), .CO(n5235)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4] ), + .I1(1'b0), .CI(n2077), .O(n5236), .CO(n5237)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/add_10/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6] ), + .CI(n5240), .O(n5238)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i7 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i6 (.I0(n12798), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5] ), + .CI(n5242), .O(n5239), .CO(n5240)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i6 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i5 (.I0(n12801), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4] ), + .CI(n5244), .O(n5241), .CO(n5242)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i5 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i4 (.I0(n12804), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3] ), + .CI(n5246), .O(n5243), .CO(n5244)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i4 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i3 (.I0(n12807), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2] ), + .CI(n5248), .O(n5245), .CO(n5246)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i3 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i2 (.I0(n12810), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1] ), + .CI(n1804), .CO(n5248)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i2 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6] ), + .CI(n5251), .O(n5249)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i7 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] ), + .I1(n12816), .CI(n5253), .O(n5250), .CO(n5251)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] ), + .I1(n12819), .CI(n5255), .O(n5252), .CO(n5253)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] ), + .I1(n12822), .CI(n5257), .O(n5254), .CO(n5255)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] ), + .I1(n12825), .CI(n5259), .O(n5256), .CO(n5257)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] ), + .I1(n12828), .CI(n1732), .O(n5258), .CO(n5259)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6] ), + .CI(n5262), .O(n5260)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i7 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i6 (.I0(n12833), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5] ), + .CI(n5264), .O(n5261), .CO(n5262)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i6 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i5 (.I0(n12836), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4] ), + .CI(n5266), .O(n5263), .CO(n5264)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i5 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i4 (.I0(n12839), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3] ), + .CI(n5268), .O(n5265), .CO(n5266)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i4 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i3 (.I0(n12842), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2] ), + .CI(n1676), .O(n5267), .CO(n5268)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i3 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6] ), + .CI(n5271), .O(n5269)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i7 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] ), + .I1(n12848), .CI(n5273), .O(n5270), .CO(n5271)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] ), + .I1(n12851), .CI(n5275), .O(n5272), .CO(n5273)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] ), + .I1(n12854), .CI(n5277), .O(n5274), .CO(n5275)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] ), + .I1(n12857), .CI(n1490), .O(n5276), .CO(n5277)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6] ), + .CI(n5280), .O(n5278)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i7 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5] ), + .I1(n12862), .CI(n5282), .O(n5279), .CO(n5280)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4] ), + .I1(n12865), .CI(n5284), .O(n5281), .CO(n5282)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3] ), + .I1(n12868), .CI(n5286), .O(n5283), .CO(n5284)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2] ), + .I1(n12871), .CI(n1403), .O(n5285), .CO(n5286)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6] ), + .CI(n5289), .O(n5287)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b0 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i7 .I1_POLARITY = 1'b0; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5] ), + .I1(n12876), .CI(n5291), .O(n5288), .CO(n5289)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4] ), + .I1(n12879), .CI(n5293), .O(n5290), .CO(n5291)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3] ), + .I1(n12882), .CI(n5295), .O(n5292), .CO(n5293)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2] ), + .I1(n12885), .CI(n5297), .O(n5294), .CO(n5295)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1] ), + .I1(n12888), .CI(n1262), .CO(n5297)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i32 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31] ), + .I1(1'b0), .CI(n5300), .O(n5298)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i32 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i32 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i31 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30] ), + .I1(1'b0), .CI(n5302), .O(n5299), .CO(n5300)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i31 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i31 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i30 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29] ), + .I1(1'b0), .CI(n5304), .O(n5301), .CO(n5302)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i30 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i30 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i29 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28] ), + .I1(1'b0), .CI(n5306), .O(n5303), .CO(n5304)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i29 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i29 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i28 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27] ), + .I1(1'b0), .CI(n5308), .O(n5305), .CO(n5306)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i28 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i28 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i27 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26] ), + .I1(1'b0), .CI(n5310), .O(n5307), .CO(n5308)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i27 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i27 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i26 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25] ), + .I1(1'b0), .CI(n5312), .O(n5309), .CO(n5310)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i26 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i26 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i25 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24] ), + .I1(1'b0), .CI(n5314), .O(n5311), .CO(n5312)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i25 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i25 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i24 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23] ), + .I1(1'b0), .CI(n5316), .O(n5313), .CO(n5314)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i24 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i24 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i23 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22] ), + .I1(1'b0), .CI(n5318), .O(n5315), .CO(n5316)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i23 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i23 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i22 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21] ), + .I1(1'b0), .CI(n5320), .O(n5317), .CO(n5318)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i22 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i22 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i21 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20] ), + .I1(1'b0), .CI(n5322), .O(n5319), .CO(n5320)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i21 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i21 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i20 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19] ), + .I1(1'b0), .CI(n5324), .O(n5321), .CO(n5322)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i20 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i20 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i19 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18] ), + .I1(1'b0), .CI(n5326), .O(n5323), .CO(n5324)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i19 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i19 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i18 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17] ), + .I1(1'b0), .CI(n5328), .O(n5325), .CO(n5326)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i18 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i18 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i17 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16] ), + .I1(1'b0), .CI(n5330), .O(n5327), .CO(n5328)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i17 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i17 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i16 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15] ), + .I1(1'b0), .CI(n5332), .O(n5329), .CO(n5330)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i16 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i16 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14] ), + .I1(1'b0), .CI(n5334), .O(n5331), .CO(n5332)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13] ), + .I1(1'b0), .CI(n5336), .O(n5333), .CO(n5334)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12] ), + .I1(1'b0), .CI(n5338), .O(n5335), .CO(n5336)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11] ), + .I1(1'b0), .CI(n5340), .O(n5337), .CO(n5338)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10] ), + .I1(1'b0), .CI(n5342), .O(n5339), .CO(n5340)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9] ), + .I1(1'b0), .CI(n5344), .O(n5341), .CO(n5342)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8] ), + .I1(1'b0), .CI(n5346), .O(n5343), .CO(n5344)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7] ), + .I1(1'b0), .CI(n5348), .O(n5345), .CO(n5346)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6] ), + .I1(1'b0), .CI(n5350), .O(n5347), .CO(n5348)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5] ), + .I1(1'b0), .CI(n5352), .O(n5349), .CO(n5350)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4] ), + .I1(1'b0), .CI(n5354), .O(n5351), .CO(n5352)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3] ), + .I1(1'b0), .CI(n5356), .O(n5353), .CO(n5354)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2] ), + .I1(1'b0), .CI(n5358), .O(n5355), .CO(n5356)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1] ), + .I1(1'b0), .CI(n1260), .O(n5357), .CO(n5358)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_89/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i32 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31] ), + .I1(1'b0), .CI(n5361), .O(n5359)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i32 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i32 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i31 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30] ), + .I1(1'b0), .CI(n5363), .O(n5360), .CO(n5361)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i31 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i31 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i30 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29] ), + .I1(1'b0), .CI(n5365), .O(n5362), .CO(n5363)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i30 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i30 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i29 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28] ), + .I1(1'b0), .CI(n5367), .O(n5364), .CO(n5365)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i29 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i29 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i28 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27] ), + .I1(1'b0), .CI(n5369), .O(n5366), .CO(n5367)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i28 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i28 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i27 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26] ), + .I1(1'b0), .CI(n5371), .O(n5368), .CO(n5369)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i27 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i27 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i26 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25] ), + .I1(1'b0), .CI(n5373), .O(n5370), .CO(n5371)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i26 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i26 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i25 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24] ), + .I1(1'b0), .CI(n5375), .O(n5372), .CO(n5373)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i25 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i25 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i24 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23] ), + .I1(1'b0), .CI(n5377), .O(n5374), .CO(n5375)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i24 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i24 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i23 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22] ), + .I1(1'b0), .CI(n5379), .O(n5376), .CO(n5377)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i23 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i23 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i22 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21] ), + .I1(1'b0), .CI(n5381), .O(n5378), .CO(n5379)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i22 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i22 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i21 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20] ), + .I1(1'b0), .CI(n5383), .O(n5380), .CO(n5381)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i21 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i21 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i20 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19] ), + .I1(1'b0), .CI(n5385), .O(n5382), .CO(n5383)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i20 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i20 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i19 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18] ), + .I1(1'b0), .CI(n5387), .O(n5384), .CO(n5385)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i19 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i19 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i18 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17] ), + .I1(1'b0), .CI(n5389), .O(n5386), .CO(n5387)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i18 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i18 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i17 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16] ), + .I1(1'b0), .CI(n5391), .O(n5388), .CO(n5389)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i17 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i17 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i16 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15] ), + .I1(1'b0), .CI(n5393), .O(n5390), .CO(n5391)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i16 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i16 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14] ), + .I1(1'b0), .CI(n5395), .O(n5392), .CO(n5393)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13] ), + .I1(1'b0), .CI(n5397), .O(n5394), .CO(n5395)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12] ), + .I1(1'b0), .CI(n5399), .O(n5396), .CO(n5397)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11] ), + .I1(1'b0), .CI(n5401), .O(n5398), .CO(n5399)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10] ), + .I1(1'b0), .CI(n5403), .O(n5400), .CO(n5401)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9] ), + .I1(1'b0), .CI(n5405), .O(n5402), .CO(n5403)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8] ), + .I1(1'b0), .CI(n5407), .O(n5404), .CO(n5405)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7] ), + .I1(1'b0), .CI(n5409), .O(n5406), .CO(n5407)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6] ), + .I1(1'b0), .CI(n5411), .O(n5408), .CO(n5409)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5] ), + .I1(1'b0), .CI(n5413), .O(n5410), .CO(n5411)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4] ), + .I1(1'b0), .CI(n5415), .O(n5412), .CO(n5413)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3] ), + .I1(1'b0), .CI(n5417), .O(n5414), .CO(n5415)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2] ), + .I1(1'b0), .CI(n5419), .O(n5416), .CO(n5417)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1] ), + .I1(1'b0), .CI(n1251), .O(n5418), .CO(n5419)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/add_65/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5] ), + .I1(1'b1), .CI(n5422), .O(n5420)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4] ), + .I1(1'b1), .CI(n5424), .O(n5421), .CO(n5422)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3] ), + .I1(1'b1), .CI(n5426), .O(n5423), .CO(n5424)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2] ), + .I1(1'b1), .CI(n5428), .O(n5425), .CO(n5426)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1] ), + .I1(1'b1), .CI(n1192), .O(n5427), .CO(n5428)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5] ), + .I1(1'b0), .CI(n5431), .O(n5429)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4] ), + .I1(1'b0), .CI(n5433), .O(n5430), .CO(n5431)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3] ), + .I1(1'b0), .CI(n5435), .O(n5432), .CO(n5433)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2] ), + .I1(1'b0), .CI(n1184), .O(n5434), .CO(n5435)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/add_12/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5] ), + .I1(1'b1), .CI(n5438), .O(n5436)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4] ), + .I1(1'b1), .CI(n5440), .O(n5437), .CO(n5438)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3] ), + .I1(1'b1), .CI(n5442), .O(n5439), .CO(n5440)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2] ), + .I1(1'b1), .CI(n5444), .O(n5441), .CO(n5442)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1] ), + .I1(1'b1), .CI(n1125), .O(n5443), .CO(n5444)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5] ), + .I1(1'b0), .CI(n5447), .O(n5445)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4] ), + .I1(1'b0), .CI(n5449), .O(n5446), .CO(n5447)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3] ), + .I1(1'b0), .CI(n5451), .O(n5448), .CO(n5449)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2] ), + .I1(1'b0), .CI(n1117), .O(n5450), .CO(n5451)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/add_12/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5] ), + .I1(1'b1), .CI(n5454), .O(n5452)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4] ), + .I1(1'b1), .CI(n5456), .O(n5453), .CO(n5454)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3] ), + .I1(1'b1), .CI(n5458), .O(n5455), .CO(n5456)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2] ), + .I1(1'b1), .CI(n5460), .O(n5457), .CO(n5458)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1] ), + .I1(1'b1), .CI(n1058), .O(n5459), .CO(n5460)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5] ), + .I1(1'b0), .CI(n5463), .O(n5461)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4] ), + .I1(1'b0), .CI(n5465), .O(n5462), .CO(n5463)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3] ), + .I1(1'b0), .CI(n5467), .O(n5464), .CO(n5465)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2] ), + .I1(1'b0), .CI(n1050), .O(n5466), .CO(n5467)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/add_12/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5] ), + .I1(1'b1), .CI(n5470), .O(n5468)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4] ), + .I1(1'b1), .CI(n5472), .O(n5469), .CO(n5470)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3] ), + .I1(1'b1), .CI(n5474), .O(n5471), .CO(n5472)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2] ), + .I1(1'b1), .CI(n5476), .O(n5473), .CO(n5474)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1] ), + .I1(1'b1), .CI(n1047), .O(n5475), .CO(n5476)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5] ), + .I1(1'b0), .CI(n5479), .O(n5477)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4] ), + .I1(1'b0), .CI(n5481), .O(n5478), .CO(n5479)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3] ), + .I1(1'b0), .CI(n5483), .O(n5480), .CO(n5481)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2] ), + .I1(1'b0), .CI(n1039), .O(n5482), .CO(n5483)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/add_12/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5] ), + .I1(1'b1), .CI(n5486), .O(n5484)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4] ), + .I1(1'b1), .CI(n5488), .O(n5485), .CO(n5486)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3] ), + .I1(1'b1), .CI(n5490), .O(n5487), .CO(n5488)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2] ), + .I1(1'b1), .CI(n5492), .O(n5489), .CO(n5490)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1] ), + .I1(1'b1), .CI(n1036), .O(n5491), .CO(n5492)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5] ), + .I1(1'b0), .CI(n5495), .O(n5493)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4] ), + .I1(1'b0), .CI(n5497), .O(n5494), .CO(n5495)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3] ), + .I1(1'b0), .CI(n5499), .O(n5496), .CO(n5497)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2] ), + .I1(1'b0), .CI(n1028), .O(n5498), .CO(n5499)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/add_12/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5] ), + .I1(1'b1), .CI(n5502), .O(n5500)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4] ), + .I1(1'b1), .CI(n5504), .O(n5501), .CO(n5502)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3] ), + .I1(1'b1), .CI(n5506), .O(n5503), .CO(n5504)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2] ), + .I1(1'b1), .CI(n5508), .O(n5505), .CO(n5506)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1] ), + .I1(1'b1), .CI(n1025), .O(n5507), .CO(n5508)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5] ), + .I1(1'b0), .CI(n5511), .O(n5509)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4] ), + .I1(1'b0), .CI(n5513), .O(n5510), .CO(n5511)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3] ), + .I1(1'b0), .CI(n5515), .O(n5512), .CO(n5513)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2] ), + .I1(1'b0), .CI(n1017), .O(n5514), .CO(n5515)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/add_12/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5] ), + .I1(1'b1), .CI(n5518), .O(n5516)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4] ), + .I1(1'b1), .CI(n5520), .O(n5517), .CO(n5518)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3] ), + .I1(1'b1), .CI(n5522), .O(n5519), .CO(n5520)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2] ), + .I1(1'b1), .CI(n5524), .O(n5521), .CO(n5522)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1] ), + .I1(1'b1), .CI(n776), .O(n5523), .CO(n5524)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5] ), + .I1(1'b0), .CI(n5527), .O(n5525)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4] ), + .I1(1'b0), .CI(n5529), .O(n5526), .CO(n5527)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3] ), + .I1(1'b0), .CI(n5531), .O(n5528), .CO(n5529)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2] ), + .I1(1'b0), .CI(n768), .O(n5530), .CO(n5531)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/add_12/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5] ), + .I1(1'b1), .CI(n5534), .O(n5532)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4] ), + .I1(1'b1), .CI(n5536), .O(n5533), .CO(n5534)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3] ), + .I1(1'b1), .CI(n5538), .O(n5535), .CO(n5536)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2] ), + .I1(1'b1), .CI(n5540), .O(n5537), .CO(n5538)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1] ), + .I1(1'b1), .CI(n541), .O(n5539), .CO(n5540)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5] ), + .I1(1'b0), .CI(n5543), .O(n5541)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4] ), + .I1(1'b0), .CI(n5545), .O(n5542), .CO(n5543)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3] ), + .I1(1'b0), .CI(n5547), .O(n5544), .CO(n5545)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2] ), + .I1(1'b0), .CI(n533), .O(n5546), .CO(n5547)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/add_12/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5] ), + .I1(1'b1), .CI(n5550), .O(n5548)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4] ), + .I1(1'b1), .CI(n5552), .O(n5549), .CO(n5550)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3] ), + .I1(1'b1), .CI(n5554), .O(n5551), .CO(n5552)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2] ), + .I1(1'b1), .CI(n5556), .O(n5553), .CO(n5554)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1] ), + .I1(1'b1), .CI(n516), .O(n5555), .CO(n5556)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5] ), + .I1(1'b0), .CI(n5559), .O(n5557)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4] ), + .I1(1'b0), .CI(n5561), .O(n5558), .CO(n5559)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3] ), + .I1(1'b0), .CI(n5563), .O(n5560), .CO(n5561)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2] ), + .I1(1'b0), .CI(n210), .O(n5562), .CO(n5563)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/add_12/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i16 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15] ), + .I1(1'b1), .CI(n5566), .O(n5564)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i16 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i16 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14] ), + .I1(1'b1), .CI(n5568), .O(n5565), .CO(n5566)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13] ), + .I1(1'b1), .CI(n5570), .O(n5567), .CO(n5568)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12] ), + .I1(1'b1), .CI(n5572), .O(n5569), .CO(n5570)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11] ), + .I1(1'b1), .CI(n5574), .O(n5571), .CO(n5572)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10] ), + .I1(1'b1), .CI(n5576), .O(n5573), .CO(n5574)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9] ), + .I1(1'b1), .CI(n5578), .O(n5575), .CO(n5576)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8] ), + .I1(1'b1), .CI(n5580), .O(n5577), .CO(n5578)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7] ), + .I1(1'b1), .CI(n5582), .O(n5579), .CO(n5580)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6] ), + .I1(1'b1), .CI(n5584), .O(n5581), .CO(n5582)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5] ), + .I1(1'b1), .CI(n5586), .O(n5583), .CO(n5584)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4] ), + .I1(1'b1), .CI(n5588), .O(n5585), .CO(n5586)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3] ), + .I1(1'b1), .CI(n5590), .O(n5587), .CO(n5588)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2] ), + .I1(1'b1), .CI(n5592), .O(n5589), .CO(n5590)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1] ), + .I1(1'b1), .CI(n208), .O(n5591), .CO(n5592)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i16 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15] ), + .I1(1'b1), .CI(n5595), .O(n5593)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i16 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i16 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14] ), + .I1(1'b1), .CI(n5597), .O(n5594), .CO(n5595)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13] ), + .I1(1'b1), .CI(n5599), .O(n5596), .CO(n5597)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12] ), + .I1(1'b1), .CI(n5601), .O(n5598), .CO(n5599)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11] ), + .I1(1'b1), .CI(n5603), .O(n5600), .CO(n5601)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10] ), + .I1(1'b1), .CI(n5605), .O(n5602), .CO(n5603)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9] ), + .I1(1'b1), .CI(n5607), .O(n5604), .CO(n5605)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8] ), + .I1(1'b1), .CI(n5609), .O(n5606), .CO(n5607)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7] ), + .I1(1'b1), .CI(n5611), .O(n5608), .CO(n5609)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6] ), + .I1(1'b1), .CI(n5613), .O(n5610), .CO(n5611)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5] ), + .I1(1'b1), .CI(n5615), .O(n5612), .CO(n5613)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4] ), + .I1(1'b1), .CI(n5617), .O(n5614), .CO(n5615)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3] ), + .I1(1'b1), .CI(n5619), .O(n5616), .CO(n5617)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2] ), + .I1(1'b1), .CI(n5621), .O(n5618), .CO(n5619)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1] ), + .I1(1'b1), .CI(n181), .O(n5620), .CO(n5621)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8] ), + .I1(1'b0), .CI(n5624), .O(n5622)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7] ), + .I1(1'b0), .CI(n5626), .O(n5623), .CO(n5624)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6] ), + .I1(1'b0), .CI(n5628), .O(n5625), .CO(n5626)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5] ), + .I1(1'b0), .CI(n5630), .O(n5627), .CO(n5628)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4] ), + .I1(1'b0), .CI(n5632), .O(n5629), .CO(n5630)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3] ), + .I1(1'b0), .CI(n5634), .O(n5631), .CO(n5632)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2] ), + .I1(1'b0), .CI(n179), .O(n5633), .CO(n5634)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_138/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i16 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15] ), + .I1(1'b0), .CI(n5637), .O(n5635)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i16 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i16 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14] ), + .I1(1'b0), .CI(n5639), .O(n5636), .CO(n5637)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13] ), + .I1(1'b0), .CI(n5641), .O(n5638), .CO(n5639)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12] ), + .I1(1'b0), .CI(n5643), .O(n5640), .CO(n5641)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11] ), + .I1(1'b0), .CI(n5645), .O(n5642), .CO(n5643)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10] ), + .I1(1'b0), .CI(n5647), .O(n5644), .CO(n5645)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9] ), + .I1(1'b0), .CI(n5649), .O(n5646), .CO(n5647)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8] ), + .I1(1'b0), .CI(n5651), .O(n5648), .CO(n5649)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7] ), + .I1(1'b0), .CI(n5653), .O(n5650), .CO(n5651)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6] ), + .I1(1'b0), .CI(n5655), .O(n5652), .CO(n5653)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5] ), + .I1(1'b0), .CI(n5657), .O(n5654), .CO(n5655)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4] ), + .I1(1'b0), .CI(n5659), .O(n5656), .CO(n5657)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3] ), + .I1(1'b0), .CI(n5661), .O(n5658), .CO(n5659)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2] ), + .I1(1'b0), .CI(n177), .O(n5660), .CO(n5661)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_133/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i29 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28] ), + .I1(1'b0), .CI(n5697), .O(n5694)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i29 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i29 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i28 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27] ), + .I1(1'b0), .CI(n5699), .O(n5696), .CO(n5697)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i28 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i28 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i27 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26] ), + .I1(1'b0), .CI(n5701), .O(n5698), .CO(n5699)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i27 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i27 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i26 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25] ), + .I1(1'b0), .CI(n5703), .O(n5700), .CO(n5701)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i26 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i26 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i25 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24] ), + .I1(1'b0), .CI(n5705), .O(n5702), .CO(n5703)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i25 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i25 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i24 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23] ), + .I1(1'b0), .CI(n5707), .O(n5704), .CO(n5705)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i24 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i24 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i23 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22] ), + .I1(1'b0), .CI(n5709), .O(n5706), .CO(n5707)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i23 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i23 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i22 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21] ), + .I1(1'b0), .CI(n5711), .O(n5708), .CO(n5709)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i22 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i22 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i21 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20] ), + .I1(1'b0), .CI(n5713), .O(n5710), .CO(n5711)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i21 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i21 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i20 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19] ), + .I1(1'b0), .CI(n5715), .O(n5712), .CO(n5713)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i20 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i20 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i19 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18] ), + .I1(1'b0), .CI(n5717), .O(n5714), .CO(n5715)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i19 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i19 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i18 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17] ), + .I1(1'b0), .CI(n5719), .O(n5716), .CO(n5717)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i18 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i18 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i17 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16] ), + .I1(1'b0), .CI(n5721), .O(n5718), .CO(n5719)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i17 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i17 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i16 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15] ), + .I1(1'b0), .CI(n5723), .O(n5720), .CO(n5721)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i16 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i16 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14] ), + .I1(1'b0), .CI(n5725), .O(n5722), .CO(n5723)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13] ), + .I1(1'b0), .CI(n5727), .O(n5724), .CO(n5725)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12] ), + .I1(1'b0), .CI(n5729), .O(n5726), .CO(n5727)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11] ), + .I1(1'b0), .CI(n5731), .O(n5728), .CO(n5729)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10] ), + .I1(1'b0), .CI(n5733), .O(n5730), .CO(n5731)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9] ), + .I1(1'b0), .CI(n5735), .O(n5732), .CO(n5733)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8] ), + .I1(1'b0), .CI(n5737), .O(n5734), .CO(n5735)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7] ), + .I1(1'b0), .CI(n5739), .O(n5736), .CO(n5737)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6] ), + .I1(1'b0), .CI(n5741), .O(n5738), .CO(n5739)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5] ), + .I1(1'b0), .CI(n5743), .O(n5740), .CO(n5741)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4] ), + .I1(1'b0), .CI(n5745), .O(n5742), .CO(n5743)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3] ), + .I1(1'b0), .CI(n5747), .O(n5744), .CO(n5745)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2] ), + .I1(1'b0), .CI(n173), .O(n5746), .CO(n5747)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_121/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i29 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28] ), + .I1(1'b0), .CI(n5756), .O(n5753)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i29 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i29 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i28 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27] ), + .I1(1'b0), .CI(n5758), .O(n5755), .CO(n5756)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i28 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i28 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i27 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26] ), + .I1(1'b0), .CI(n5760), .O(n5757), .CO(n5758)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i27 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i27 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i26 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25] ), + .I1(1'b0), .CI(n5762), .O(n5759), .CO(n5760)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i26 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i26 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i25 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24] ), + .I1(1'b0), .CI(n5764), .O(n5761), .CO(n5762)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i25 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i25 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i24 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23] ), + .I1(1'b0), .CI(n5766), .O(n5763), .CO(n5764)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i24 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i24 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i23 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22] ), + .I1(1'b0), .CI(n5768), .O(n5765), .CO(n5766)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i23 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i23 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i22 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21] ), + .I1(1'b0), .CI(n5770), .O(n5767), .CO(n5768)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i22 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i22 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i21 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20] ), + .I1(1'b0), .CI(n5772), .O(n5769), .CO(n5770)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i21 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i21 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i20 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19] ), + .I1(1'b0), .CI(n5774), .O(n5771), .CO(n5772)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i20 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i20 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i19 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18] ), + .I1(1'b0), .CI(n5776), .O(n5773), .CO(n5774)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i19 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i19 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i18 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17] ), + .I1(1'b0), .CI(n5778), .O(n5775), .CO(n5776)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i18 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i18 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i17 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16] ), + .I1(1'b0), .CI(n5780), .O(n5777), .CO(n5778)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i17 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i17 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i16 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15] ), + .I1(1'b0), .CI(n5782), .O(n5779), .CO(n5780)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i16 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i16 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14] ), + .I1(1'b0), .CI(n5784), .O(n5781), .CO(n5782)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13] ), + .I1(1'b0), .CI(n5786), .O(n5783), .CO(n5784)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12] ), + .I1(1'b0), .CI(n5788), .O(n5785), .CO(n5786)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11] ), + .I1(1'b0), .CI(n5790), .O(n5787), .CO(n5788)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10] ), + .I1(1'b0), .CI(n5792), .O(n5789), .CO(n5790)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9] ), + .I1(1'b0), .CI(n5794), .O(n5791), .CO(n5792)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8] ), + .I1(1'b0), .CI(n5796), .O(n5793), .CO(n5794)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7] ), + .I1(1'b0), .CI(n5798), .O(n5795), .CO(n5796)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6] ), + .I1(1'b0), .CI(n5800), .O(n5797), .CO(n5798)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5] ), + .I1(1'b0), .CI(n5802), .O(n5799), .CO(n5800)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4] ), + .I1(1'b0), .CI(n5804), .O(n5801), .CO(n5802)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3] ), + .I1(1'b0), .CI(n5806), .O(n5803), .CO(n5804)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2] ), + .I1(1'b0), .CI(n171), .O(n5805), .CO(n5806)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_81/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i16 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15] ), + .I1(1'b0), .CI(n5809), .O(n5807)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i16 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i16 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i15 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14] ), + .I1(1'b0), .CI(n5811), .O(n5808), .CO(n5809)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i15 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i15 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i14 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13] ), + .I1(1'b0), .CI(n5813), .O(n5810), .CO(n5811)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i14 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i14 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i13 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12] ), + .I1(1'b0), .CI(n5815), .O(n5812), .CO(n5813)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i13 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i13 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i12 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11] ), + .I1(1'b0), .CI(n5817), .O(n5814), .CO(n5815)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i12 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i12 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i11 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10] ), + .I1(1'b0), .CI(n5819), .O(n5816), .CO(n5817)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i11 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i11 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i10 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9] ), + .I1(1'b0), .CI(n5821), .O(n5818), .CO(n5819)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i10 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i10 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i9 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8] ), + .I1(1'b0), .CI(n5823), .O(n5820), .CO(n5821)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i9 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i9 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i8 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7] ), + .I1(1'b0), .CI(n5825), .O(n5822), .CO(n5823)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i8 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i8 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i7 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6] ), + .I1(1'b0), .CI(n5827), .O(n5824), .CO(n5825)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i7 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i7 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i6 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5] ), + .I1(1'b0), .CI(n5829), .O(n5826), .CO(n5827)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i6 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i6 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i5 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4] ), + .I1(1'b0), .CI(n5831), .O(n5828), .CO(n5829)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i5 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i5 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i4 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3] ), + .I1(1'b0), .CI(n5833), .O(n5830), .CO(n5831)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i4 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i4 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i3 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2] ), + .I1(1'b0), .CI(n5835), .O(n5832), .CO(n5833)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i3 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i3 .I1_POLARITY = 1'b1; + EFX_ADD \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i2 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0] ), + .O(n5834), .CO(n5835)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i2 .I0_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/add_69/i2 .I1_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[1][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[0][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[1][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[0][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[2][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[1][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[1][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[2][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[1][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[1][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[3][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[2][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[2][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[3][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[2][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[2][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[3][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[3][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[3][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Q7_Out[3][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[8].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][8] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][8] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[8].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[8].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[8].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[9].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][9] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][9] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[9].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[9].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[9].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[10].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][10] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][10] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[10].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[10].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[10].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[11].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][11] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][11] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[11].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[11].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[11].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[12].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][12] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][12] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[12].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[12].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[12].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[13].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][13] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][13] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[13].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[13].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[13].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[14].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][14] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][14] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[14].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[14].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[14].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[15].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][15] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][15] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[15].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[15].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[15].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[16].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][16] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][16] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[16].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[16].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[16].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[17].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][17] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][17] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[17].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[17].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[17].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[18].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][18] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][18] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[18].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[18].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[18].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[19].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][19] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][19] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[19].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[19].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[19].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[20].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][20] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][20] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[20].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[20].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[20].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[21].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][21] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][21] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[21].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[21].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[21].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[22].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][22] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][22] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[22].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[22].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[22].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[23].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][23] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][23] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[23].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[23].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[23].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[24].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][24] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][24] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[24].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[24].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[24].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[25].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][25] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][25] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[25].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[25].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[25].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[26].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][26] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][26] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[26].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[26].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[26].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[27].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][27] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][27] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[27].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[27].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[27].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[28].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][28] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][28] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[28].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[28].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[0].U_SRL8_W[28].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[8].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][8] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][8] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][8] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[8].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[8].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[8].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[9].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][9] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][9] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][9] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[9].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[9].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[9].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[10].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][10] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][10] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][10] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[10].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[10].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[10].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[11].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][11] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][11] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][11] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[11].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[11].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[11].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[12].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][12] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][12] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][12] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[12].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[12].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[12].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[13].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][13] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][13] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][13] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[13].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[13].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[13].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[14].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][14] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][14] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][14] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[14].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[14].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[14].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[15].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][15] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][15] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][15] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[15].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[15].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[15].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[16].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][16] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][16] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][16] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[16].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[16].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[16].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[17].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][17] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][17] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][17] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[17].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[17].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[17].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[18].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][18] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][18] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][18] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[18].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[18].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[18].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[19].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][19] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][19] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][19] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[19].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[19].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[19].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[20].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][20] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][20] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][20] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[20].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[20].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[20].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[21].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][21] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][21] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][21] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[21].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[21].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[21].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[22].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][22] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][22] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][22] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[22].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[22].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[22].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[23].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][23] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][23] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][23] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[23].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[23].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[23].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[24].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][24] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][24] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][24] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[24].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[24].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[24].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[25].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][25] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][25] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][25] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[25].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[25].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[25].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[26].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][26] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][26] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][26] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[26].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[26].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[26].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[27].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][27] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][27] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][27] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[27].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[27].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[27].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[28].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][28] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][28] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[1][28] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[28].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[28].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[1].U_SRL8_W[28].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[8].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][8] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][8] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][8] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[8].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[8].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[8].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[9].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][9] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][9] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][9] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[9].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[9].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[9].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[10].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][10] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][10] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][10] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[10].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[10].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[10].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[11].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][11] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][11] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][11] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[11].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[11].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[11].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[12].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][12] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][12] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][12] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[12].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[12].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[12].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[13].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][13] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][13] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][13] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[13].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[13].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[13].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[14].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][14] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][14] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][14] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[14].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[14].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[14].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[15].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][15] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][15] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][15] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[15].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[15].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[15].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[16].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][16] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][16] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][16] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[16].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[16].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[16].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[17].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][17] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][17] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][17] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[17].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[17].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[17].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[18].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][18] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][18] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][18] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[18].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[18].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[18].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[19].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][19] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][19] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][19] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[19].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[19].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[19].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[20].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][20] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][20] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][20] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[20].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[20].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[20].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[21].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][21] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][21] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][21] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[21].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[21].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[21].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[22].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][22] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][22] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][22] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[22].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[22].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[22].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[23].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][23] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][23] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][23] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[23].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[23].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[23].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[24].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][24] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][24] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][24] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[24].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[24].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[24].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[25].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][25] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][25] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][25] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[25].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[25].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[25].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[26].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][26] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][26] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][26] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[26].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[26].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[26].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[27].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][27] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][27] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][27] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[27].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[27].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[27].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[28].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][28] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][28] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[2][28] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[28].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[28].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[2].U_SRL8_W[28].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[8].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][8] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][8] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][8] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[8].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[8].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[8].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[9].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][9] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][9] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][9] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[9].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[9].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[9].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[10].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][10] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][10] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][10] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[10].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[10].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[10].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[11].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][11] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][11] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][11] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[11].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[11].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[11].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[12].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][12] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][12] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][12] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[12].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[12].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[12].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[13].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][13] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][13] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][13] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[13].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[13].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[13].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[14].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][14] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][14] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][14] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[14].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[14].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[14].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[15].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][15] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][15] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][15] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[15].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[15].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[15].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[16].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][16] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][16] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][16] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[16].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[16].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[16].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[17].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][17] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][17] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][17] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[17].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[17].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[17].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[18].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][18] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][18] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][18] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[18].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[18].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[18].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[19].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][19] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][19] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][19] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[19].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[19].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[19].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[20].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][20] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][20] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[20].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[20].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[20].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[21].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][21] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][21] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[21].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[21].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[21].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[22].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][22] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][22] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[22].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[22].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[22].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[23].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][23] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][23] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[23].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[23].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[23].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[24].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][24] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][24] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[24].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[24].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[24].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[25].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][25] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][25] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[25].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[25].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[25].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[26].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][26] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][26] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[26].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[26].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[26].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[27].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][27] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][27] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[27].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[27].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[27].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[28].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][28] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Q7_Out[3][28] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[28].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[28].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/U_SRL8_D[3].U_SRL8_W[28].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[8].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][8] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][8] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[8].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[8].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[8].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[9].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][9] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][9] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[9].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[9].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[9].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[10].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][10] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][10] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[10].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[10].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[10].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[11].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][11] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][11] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[11].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[11].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[11].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[12].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][12] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][12] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[12].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[12].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[12].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[13].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][13] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][13] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[13].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[13].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[13].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[14].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][14] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][14] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[14].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[14].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[14].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[15].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][15] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][15] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[15].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[15].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[15].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[16].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][16] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][16] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[16].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[16].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[16].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[17].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][17] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][17] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[17].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[17].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[17].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[18].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][18] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][18] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[18].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[18].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[18].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[19].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][19] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][19] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[19].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[19].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[19].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[20].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][20] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][20] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[20].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[20].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[20].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[21].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][21] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][21] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[21].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[21].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[21].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[22].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][22] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][22] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[22].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[22].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[22].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[23].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][23] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][23] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[23].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[23].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[23].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[24].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][24] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][24] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[24].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[24].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[24].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[25].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][25] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][25] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[25].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[25].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[25].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[26].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][26] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][26] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[26].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[26].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[26].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[27].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][27] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][27] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[27].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[27].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[27].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[28].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][28] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][28] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[28].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[28].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[28].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[40].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][40] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][40] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[40].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[40].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[40].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[41].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][41] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][41] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[41].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[41].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[0].U_SRL8_W[41].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[8].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][8] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][8] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][8] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[8].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[8].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[8].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[9].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][9] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][9] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][9] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[9].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[9].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[9].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[10].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][10] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][10] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][10] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[10].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[10].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[10].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[11].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][11] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][11] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][11] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[11].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[11].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[11].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[12].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][12] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][12] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][12] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[12].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[12].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[12].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[13].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][13] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][13] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][13] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[13].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[13].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[13].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[14].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][14] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][14] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][14] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[14].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[14].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[14].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[15].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][15] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][15] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][15] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[15].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[15].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[15].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[16].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][16] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][16] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][16] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[16].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[16].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[16].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[17].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][17] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][17] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][17] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[17].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[17].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[17].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[18].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][18] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][18] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][18] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[18].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[18].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[18].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[19].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][19] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][19] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][19] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[19].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[19].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[19].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[20].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][20] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][20] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][20] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[20].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[20].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[20].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[21].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][21] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][21] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][21] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[21].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[21].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[21].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[22].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][22] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][22] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][22] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[22].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[22].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[22].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[23].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][23] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][23] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][23] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[23].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[23].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[23].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[24].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][24] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][24] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][24] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[24].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[24].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[24].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[25].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][25] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][25] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][25] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[25].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[25].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[25].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[26].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][26] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][26] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][26] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[26].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[26].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[26].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[27].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][27] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][27] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][27] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[27].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[27].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[27].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[28].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][28] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][28] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][28] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[28].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[28].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[28].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[40].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][40] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][40] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][40] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[40].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[40].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[40].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[41].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][41] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][41] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[1][41] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[41].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[41].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[1].U_SRL8_W[41].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[8].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][8] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][8] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][8] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[8].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[8].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[8].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[9].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][9] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][9] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][9] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[9].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[9].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[9].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[10].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][10] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][10] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][10] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[10].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[10].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[10].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[11].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][11] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][11] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][11] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[11].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[11].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[11].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[12].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][12] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][12] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][12] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[12].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[12].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[12].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[13].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][13] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][13] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][13] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[13].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[13].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[13].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[14].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][14] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][14] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][14] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[14].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[14].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[14].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[15].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][15] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][15] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][15] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[15].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[15].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[15].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[16].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][16] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][16] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][16] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[16].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[16].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[16].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[17].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][17] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][17] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][17] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[17].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[17].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[17].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[18].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][18] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][18] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][18] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[18].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[18].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[18].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[19].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][19] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][19] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][19] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[19].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[19].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[19].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[20].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][20] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][20] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][20] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[20].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[20].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[20].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[21].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][21] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][21] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][21] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[21].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[21].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[21].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[22].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][22] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][22] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][22] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[22].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[22].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[22].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[23].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][23] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][23] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][23] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[23].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[23].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[23].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[24].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][24] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][24] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][24] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[24].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[24].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[24].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[25].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][25] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][25] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][25] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[25].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[25].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[25].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[26].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][26] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][26] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][26] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[26].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[26].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[26].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[27].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][27] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][27] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][27] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[27].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[27].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[27].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[28].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][28] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][28] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][28] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[28].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[28].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[28].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[40].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][40] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][40] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][40] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[40].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[40].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[40].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[41].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][41] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][41] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[2][41] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[41].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[41].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[2].U_SRL8_W[41].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[8].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][8] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][8] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][8] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[8].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[8].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[8].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[9].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][9] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][9] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][9] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[9].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[9].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[9].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[10].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][10] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][10] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][10] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[10].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[10].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[10].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[11].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][11] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][11] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][11] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[11].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[11].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[11].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[12].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][12] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][12] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][12] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[12].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[12].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[12].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[13].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][13] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][13] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][13] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[13].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[13].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[13].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[14].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][14] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][14] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][14] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[14].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[14].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[14].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[15].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][15] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][15] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][15] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[15].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[15].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[15].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[16].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][16] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][16] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][16] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[16].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[16].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[16].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[17].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][17] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][17] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][17] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[17].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[17].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[17].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[18].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][18] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][18] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][18] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[18].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[18].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[18].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[19].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][19] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][19] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][19] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[19].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[19].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[19].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[20].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][20] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][20] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[20].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[20].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[20].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[21].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][21] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][21] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[21].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[21].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[21].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[22].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][22] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][22] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[22].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[22].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[22].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[23].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][23] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][23] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[23].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[23].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[23].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[24].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][24] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][24] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[24].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[24].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[24].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[25].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][25] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][25] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[25].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[25].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[25].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[26].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][26] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][26] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[26].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[26].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[26].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[27].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][27] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][27] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[27].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[27].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[27].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[28].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][28] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][28] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[28].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[28].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[28].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[40].srl8_inst (.D(\axi4_awar_mux/n14 ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][40] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][40] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[40].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[40].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[40].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[41].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][41] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Q7_Out[3][41] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[41].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[41].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/U_SRL8_D[3].U_SRL8_W[41].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[1][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[2][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Q7_Out[3][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[1][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[2][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst (.D(w_ddr3_atype), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Q7_Out[3][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[0].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[1][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[1].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][0] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][1] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][2] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][3] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][4] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][5] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][6] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][7] ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[2][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[2].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst (.D(\axi4_awar_mux/n14 ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][0] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][0] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[0].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst (.D(\axi4_awar_mux/n14 ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][1] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][1] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[1].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst (.D(\axi4_awar_mux/n14 ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][2] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][2] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[2].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst (.D(\axi4_awar_mux/n14 ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][3] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][3] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[3].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst (.D(\axi4_awar_mux/n14 ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][4] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][4] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[4].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst (.D(\axi4_awar_mux/n14 ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][5] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][5] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[5].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst (.D(\axi4_awar_mux/n14 ), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][6] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][6] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[6].srl8_inst .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst (.D(1'b1), + .CLK(clk_sys), .CE(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][7] ), + .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Q7_Out[3][7] ), + .A({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, EFX_ATTRIBUTE_INSTANCE__IS_STF_SRL8=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1, INIT=8'b00000000 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .INIT = 8'b00000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/U_SRL8_D[3].U_SRL8_W[7].srl8_inst .CE_POLARITY = 1'b1; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 (.WCLK(clk_sys), + .RCLK(core_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[13] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[0] }), + .RDATA({Open_0, Open_1, Open_2, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[16] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$1 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 (.WCLK(clk_sys), + .RCLK(core_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[0] , + 3'b000}), .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/ram__D$2 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 (.WCLK(clk_sys), + .RCLK(core_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[16] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[13] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[0] }), + .RDATA({Open_3, Open_4, Open_5, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[16] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$1 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 (.WCLK(clk_sys), + .RCLK(core_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[0] , + 3'b000}), .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/ram__D$2 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 (.WCLK(clk_sys), + .RCLK(twd_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[16] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[16] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 (.WCLK(clk_sys), + .RCLK(twd_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[0] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$2 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 (.WCLK(clk_sys), + .RCLK(twd_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[52] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[48] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[52] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[48] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$c12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 (.WCLK(clk_sys), + .RCLK(twd_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[83] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[82] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[81] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[80] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[79] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[78] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[77] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[76] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[75] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[74] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[73] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[72] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[71] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[70] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[69] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[68] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[65] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[64] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[83] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[82] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[81] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[80] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[79] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[78] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[77] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[76] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[75] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[74] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[73] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[72] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[71] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[70] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[69] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[68] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[65] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[64] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=20, WRITE_WIDTH=20, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .READ_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .WRITE_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$d12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 (.WCLK(clk_sys), + .RCLK(twd_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[103] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[102] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[101] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[100] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[99] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[98] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[97] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[96] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[95] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[94] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[93] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[92] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[91] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[90] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[89] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[88] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[87] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[86] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[85] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[84] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[103] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[102] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[101] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[100] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[99] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[98] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[97] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[96] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[95] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[94] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[93] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[92] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[91] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[90] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[89] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[88] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[87] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[86] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[85] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[84] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=20, WRITE_WIDTH=20, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .READ_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .WRITE_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$e12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 (.WCLK(clk_sys), + .RCLK(twd_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[123] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[122] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[121] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[120] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[119] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[118] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[117] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[116] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[115] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[114] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[113] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[112] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[111] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[110] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[109] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[108] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[107] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[106] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[105] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[104] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[123] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[122] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[121] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[120] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[119] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[118] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[117] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[116] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[115] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[114] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[113] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[112] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[111] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[110] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[109] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[108] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[107] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[106] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[105] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[104] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=20, WRITE_WIDTH=20, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .READ_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .WRITE_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$f12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 (.WCLK(clk_sys), + .RCLK(twd_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 }), + .WDATA({16'b0000000000000000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[127] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[126] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[125] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[124] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[127] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[126] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[125] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[124] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=20, WRITE_WIDTH=20, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .READ_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .WRITE_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$g1 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 (.WCLK(clk_sys), + .RCLK(twd_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[32] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[32] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/ram__D$b12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram (.WCLK(core_clk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({1'b0, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_ack , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_ack }), + .WADDR({6'b000000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0] }), + .RADDR({6'b000000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[0] }), + .RDATA({Open_6, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_data[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=2, WRITE_WIDTH=2, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .READ_WIDTH = 2; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .WRITE_WIDTH = 2; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/ram .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 (.WCLK(tac_clk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[16] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[0] }), + .RDATA({\w_ddr3_rdata[31] , \w_ddr3_rdata[30] , \w_ddr3_rdata[29] , + \w_ddr3_rdata[28] , \w_ddr3_rdata[27] , \w_ddr3_rdata[26] , + \w_ddr3_rdata[25] , \w_ddr3_rdata[24] , \w_ddr3_rdata[23] , + \w_ddr3_rdata[22] , \w_ddr3_rdata[21] , \w_ddr3_rdata[20] , + \w_ddr3_rdata[19] , \w_ddr3_rdata[18] , \w_ddr3_rdata[17] , + \w_ddr3_rdata[16] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 (.WCLK(tac_clk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[0] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[0] }), + .RDATA({\w_ddr3_rdata[15] , \w_ddr3_rdata[14] , \w_ddr3_rdata[13] , + \w_ddr3_rdata[12] , \w_ddr3_rdata[11] , \w_ddr3_rdata[10] , + \w_ddr3_rdata[9] , \w_ddr3_rdata[8] , \w_ddr3_rdata[7] , \w_ddr3_rdata[6] , + \w_ddr3_rdata[5] , \w_ddr3_rdata[4] , \w_ddr3_rdata[3] , \w_ddr3_rdata[2] , + \w_ddr3_rdata[1] , \w_ddr3_rdata[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$2 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 (.WCLK(tac_clk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[65] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[64] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[52] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[48] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[0] }), + .RDATA({\w_ddr3_rdata[67] , \w_ddr3_rdata[66] , \w_ddr3_rdata[65] , + \w_ddr3_rdata[64] , \w_ddr3_rdata[63] , \w_ddr3_rdata[62] , + \w_ddr3_rdata[61] , \w_ddr3_rdata[60] , \w_ddr3_rdata[59] , + \w_ddr3_rdata[58] , \w_ddr3_rdata[57] , \w_ddr3_rdata[56] , + \w_ddr3_rdata[55] , \w_ddr3_rdata[54] , \w_ddr3_rdata[53] , + \w_ddr3_rdata[52] , \w_ddr3_rdata[51] , \w_ddr3_rdata[50] , + \w_ddr3_rdata[49] , \w_ddr3_rdata[48] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=20, WRITE_WIDTH=20, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .READ_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .WRITE_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$c12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 (.WCLK(tac_clk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[87] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[86] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[85] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[84] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[83] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[82] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[81] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[80] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[79] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[78] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[77] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[76] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[75] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[74] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[73] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[72] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[71] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[70] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[69] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[68] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[0] }), + .RDATA({\w_ddr3_rdata[87] , \w_ddr3_rdata[86] , \w_ddr3_rdata[85] , + \w_ddr3_rdata[84] , \w_ddr3_rdata[83] , \w_ddr3_rdata[82] , + \w_ddr3_rdata[81] , \w_ddr3_rdata[80] , \w_ddr3_rdata[79] , + \w_ddr3_rdata[78] , \w_ddr3_rdata[77] , \w_ddr3_rdata[76] , + \w_ddr3_rdata[75] , \w_ddr3_rdata[74] , \w_ddr3_rdata[73] , + \w_ddr3_rdata[72] , \w_ddr3_rdata[71] , \w_ddr3_rdata[70] , + \w_ddr3_rdata[69] , \w_ddr3_rdata[68] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=20, WRITE_WIDTH=20, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .READ_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .WRITE_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$d12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 (.WCLK(tac_clk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[107] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[106] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[105] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[104] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[103] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[102] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[101] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[100] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[99] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[98] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[97] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[96] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[95] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[94] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[93] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[92] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[91] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[90] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[89] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[88] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[0] }), + .RDATA({\w_ddr3_rdata[107] , \w_ddr3_rdata[106] , \w_ddr3_rdata[105] , + \w_ddr3_rdata[104] , \w_ddr3_rdata[103] , \w_ddr3_rdata[102] , + \w_ddr3_rdata[101] , \w_ddr3_rdata[100] , \w_ddr3_rdata[99] , + \w_ddr3_rdata[98] , \w_ddr3_rdata[97] , \w_ddr3_rdata[96] , + \w_ddr3_rdata[95] , \w_ddr3_rdata[94] , \w_ddr3_rdata[93] , + \w_ddr3_rdata[92] , \w_ddr3_rdata[91] , \w_ddr3_rdata[90] , + \w_ddr3_rdata[89] , \w_ddr3_rdata[88] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=20, WRITE_WIDTH=20, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .READ_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .WRITE_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$e12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 (.WCLK(tac_clk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[127] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[126] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[125] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[124] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[123] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[122] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[121] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[120] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[119] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[118] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[117] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[116] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[115] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[114] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[113] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[112] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[111] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[110] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[109] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[108] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[0] }), + .RDATA({\w_ddr3_rdata[127] , \w_ddr3_rdata[126] , \w_ddr3_rdata[125] , + \w_ddr3_rdata[124] , \w_ddr3_rdata[123] , \w_ddr3_rdata[122] , + \w_ddr3_rdata[121] , \w_ddr3_rdata[120] , \w_ddr3_rdata[119] , + \w_ddr3_rdata[118] , \w_ddr3_rdata[117] , \w_ddr3_rdata[116] , + \w_ddr3_rdata[115] , \w_ddr3_rdata[114] , \w_ddr3_rdata[113] , + \w_ddr3_rdata[112] , \w_ddr3_rdata[111] , \w_ddr3_rdata[110] , + \w_ddr3_rdata[109] , \w_ddr3_rdata[108] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=20, WRITE_WIDTH=20, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .READ_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .WRITE_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$f1 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 (.WCLK(tac_clk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_data[32] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[0] }), + .RDATA({\w_ddr3_rdata[47] , \w_ddr3_rdata[46] , \w_ddr3_rdata[45] , + \w_ddr3_rdata[44] , \w_ddr3_rdata[43] , \w_ddr3_rdata[42] , + \w_ddr3_rdata[41] , \w_ddr3_rdata[40] , \w_ddr3_rdata[39] , + \w_ddr3_rdata[38] , \w_ddr3_rdata[37] , \w_ddr3_rdata[36] , + \w_ddr3_rdata[35] , \w_ddr3_rdata[34] , \w_ddr3_rdata[33] , + \w_ddr3_rdata[32] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/ram__D$b12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 (.WCLK(core_clk), + .RCLK(tdqss_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ba[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$2 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 (.WCLK(core_clk), + .RCLK(tdqss_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ba[0] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_odt , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cs , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_ras , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cas , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_we , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_cke , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_addr[12] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[28] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[27] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[26] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[25] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[16] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 (.WCLK(core_clk), + .RCLK(tdqss_clk), .WCLKE(1'b1), .RE(1'b1), .RST(1'b0), .WADDREN(1'b1), + .RADDREN(1'b1), .WE({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 }), + .WDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrB_rstn , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cs , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_ras , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cas , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_we , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_cke , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/i_phy_ddrA_addr[2] }), + .WADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0] }), + .RADDR({3'b000, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[48] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[45] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[44] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[43] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[42] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[41] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[40] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[39] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[38] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[36] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[35] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[34] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[32] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=20, WRITE_WIDTH=20, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .READ_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .WRITE_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/ram__D$b1 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i112_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[111] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i112_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i112_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i112_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i112_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i113_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[112] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i113_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i113_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i113_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i113_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i114_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[113] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i114_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i114_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i114_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i114_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i115_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[114] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i115_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i115_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i115_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i115_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i116_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[115] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i116_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i116_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i116_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i116_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i117_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[116] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i117_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i117_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i117_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i117_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i118_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[117] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i118_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i118_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i118_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i118_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i119_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[118] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i119_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i119_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i119_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i119_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i12_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[11] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i12_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i12_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i12_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i12_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i121_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[120] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i121_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i121_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i121_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i121_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i122_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[121] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i122_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i122_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i122_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i122_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i123_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[122] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i123_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i123_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i123_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i123_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i124_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[123] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i124_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i124_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i124_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i124_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i125_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[124] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i125_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i125_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i125_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i125_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i126_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[125] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i126_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i126_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i126_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i126_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i97_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[96] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i97_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i97_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i97_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i97_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i98_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[97] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i98_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i98_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i98_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i98_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i99_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[98] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i99_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i99_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i99_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i99_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i1_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[0] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i1_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i1_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i1_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i1_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i101_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[100] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i101_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i101_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i101_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i101_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i102_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[101] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i102_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i102_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i102_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i102_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i103_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[102] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i103_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i103_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i103_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i103_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i104_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[103] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i104_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i104_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i104_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i104_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i105_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[104] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i105_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i105_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i105_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i105_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i106_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[105] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i106_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i106_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i106_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i106_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i107_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[106] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i107_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i107_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i107_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i107_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i108_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[107] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i108_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i108_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i108_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i108_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i109_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[108] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i109_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i109_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i109_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i109_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i11_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[10] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i11_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i11_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i11_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i11_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i111_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[110] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i111_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i111_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i111_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i111_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i10_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[9] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i10_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i10_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i10_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i10_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i82_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[81] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i82_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i82_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i82_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i82_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i83_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[82] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i83_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i83_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i83_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i83_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i84_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[83] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i84_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i84_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i84_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i84_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i85_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[84] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i85_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i85_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i85_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i85_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i86_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[85] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i86_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i86_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i86_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i86_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i87_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[86] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i87_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i87_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i87_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i87_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i88_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[87] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i88_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i88_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i88_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i88_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i89_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[88] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i89_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i89_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i89_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i89_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i9_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[8] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i9_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i9_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i9_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i9_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i91_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[90] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i91_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i91_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i91_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i91_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i92_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[91] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i92_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i92_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i92_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i92_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i93_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[92] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i93_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i93_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i93_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i93_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i94_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[93] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i94_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i94_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i94_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i94_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i95_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[94] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i95_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i95_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i95_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i95_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i96_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[95] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i96_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i96_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i96_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i96_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2553 ), + .CLK(tac_clk), .CE(1'b1), .Q7(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_rd_fifo_wr_en_p[7] ), + .A({3'b111})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i8_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i67_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[66] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i67_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i67_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i67_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i67_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i68_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[67] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i68_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i68_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i68_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i68_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i69_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[68] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i69_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i69_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i69_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i69_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i7_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[6] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i7_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i7_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i7_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i7_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i71_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[70] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i71_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i71_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i71_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i71_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i72_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[71] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i72_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i72_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i72_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i72_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i73_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[72] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i73_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i73_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i73_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i73_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i74_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[73] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i74_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i74_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i74_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i74_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i75_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[74] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i75_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i75_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i75_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i75_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i76_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[75] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i76_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i76_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i76_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i76_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i77_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[76] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i77_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i77_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i77_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i77_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i78_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[77] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i78_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i78_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i78_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i78_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i79_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[78] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i79_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i79_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i79_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i79_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i8_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[7] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i8_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i8_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i8_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i8_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i81_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[80] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i81_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i81_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i81_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i81_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_rd_fifo_wr_en_p[7] ), + .CLK(tac_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_pre ), + .A({3'b100})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/dff_138/i10_2 (.D(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[1] ), + .CLK(clk_sys), .CE(1'b1), .Q7(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[9] ), + .A({3'b111})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/dff_138/i10_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/dff_138/i10_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i10_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i52_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[51] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i52_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i52_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i52_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i52_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i53_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[52] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i53_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i53_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i53_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i53_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i54_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[53] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i54_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i54_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i54_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i54_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i55_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[54] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i55_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i55_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i55_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i55_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i56_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[55] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i56_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i56_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i56_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i56_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i57_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[56] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i57_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i57_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i57_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i57_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i58_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[57] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i58_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i58_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i58_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i58_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i59_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[58] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i59_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i59_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i59_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i59_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i6_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[5] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i6_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i6_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i6_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i6_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i61_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[60] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i61_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i61_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i61_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i61_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i62_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[61] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i62_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i62_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i62_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i62_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i63_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[62] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i63_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i63_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i63_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i63_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i64_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[63] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i64_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i64_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i64_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i64_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i65_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[64] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i65_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i65_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i65_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i65_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i66_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[65] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i66_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i66_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i66_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i66_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i37_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[36] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i37_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i37_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i37_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i37_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i38_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[37] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i38_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i38_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i38_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i38_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i39_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[38] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i39_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i39_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i39_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i39_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i4_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[3] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i4_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i4_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i4_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i4_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i41_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[40] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i41_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i41_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i41_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i41_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i42_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[41] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i42_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i42_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i42_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i42_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i43_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[42] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i43_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i43_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i43_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i43_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i44_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[43] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i44_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i44_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i44_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i44_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i45_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[44] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i45_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i45_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i45_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i45_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i46_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[45] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i46_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i46_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i46_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i46_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i47_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[46] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i47_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i47_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i47_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i47_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i48_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[47] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i48_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i48_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i48_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i48_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i49_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[48] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i49_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i49_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i49_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i49_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i5_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[4] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i5_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i5_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i5_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i5_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i51_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[50] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i51_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i51_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i51_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i51_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i22_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[21] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i22_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i22_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i22_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i22_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i23_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[22] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i23_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i23_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i23_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i23_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i24_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[23] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i24_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i24_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i24_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i24_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i25_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[24] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i25_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i25_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i25_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i25_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i26_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[25] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i26_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i26_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i26_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i26_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i27_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[26] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i27_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i27_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i27_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i27_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i28_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[27] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i28_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i28_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i28_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i28_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i29_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[28] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i29_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i29_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i29_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i29_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i3_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[2] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i3_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i3_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i3_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i3_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i31_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[30] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i31_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i31_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i31_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i31_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i32_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[31] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i32_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i32_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i32_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i32_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i33_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[32] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i33_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i33_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i33_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i33_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i34_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[33] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i34_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i34_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i34_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i34_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i35_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[34] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i35_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i35_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i35_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i35_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i36_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[35] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i36_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i36_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i36_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i36_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i80_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[79] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i80_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i80_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i80_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i80_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i90_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[89] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i90_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i90_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i90_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i90_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i100_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[99] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i100_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i100_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i100_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i100_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i110_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[109] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i110_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i110_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i110_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i110_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i120_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[119] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i120_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i120_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i120_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i120_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i128_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[127] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i128_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i128_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i128_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i128_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i13_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[12] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i13_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i13_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i13_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i13_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i14_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[13] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i14_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i14_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i14_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i14_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i15_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[14] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i15_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i15_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i15_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i15_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i16_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[15] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i16_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i16_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i16_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i16_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i17_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[16] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i17_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i17_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i17_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i17_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i18_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[17] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i18_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i18_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i18_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i18_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i19_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[18] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i19_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i19_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i19_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i19_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i2_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[1] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i2_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i2_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i2_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i2_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i21_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[20] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i21_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i21_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i21_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i21_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i15_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[14] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i15_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i15_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i15_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i15_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i20_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[19] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i20_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i20_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i20_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i20_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i30_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[29] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i30_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i30_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i30_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i30_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i40_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[39] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i40_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i40_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i40_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i40_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i50_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[49] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i50_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i50_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i50_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i50_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i60_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[59] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i60_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i60_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i60_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i60_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i70_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[69] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i70_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i70_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i70_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i70_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i127_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[126] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i127_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i127_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i127_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i127_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i16_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[15] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i16_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i16_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i16_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i16_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i2_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[1] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i2_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i2_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i2_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i2_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i3_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[2] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i3_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i3_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i3_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i3_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i4_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[3] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i4_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i4_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i4_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i4_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i5_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[4] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i5_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i5_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i5_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i5_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i6_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[5] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i6_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i6_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i6_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i6_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i7_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[6] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i7_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i7_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i7_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i7_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i8_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[7] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i8_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i8_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i8_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i8_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i9_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[8] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i9_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i9_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i9_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i9_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i1_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[0] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i1_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i1_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i1_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i1_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i11_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[10] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i11_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i11_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i11_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i11_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i12_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[11] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i12_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i12_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i12_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i12_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i13_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[12] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i13_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i13_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i13_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i13_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i14_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_dm_fifo_rd_data[13] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i14_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i14_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i14_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i14_2 .CE_POLARITY = 1'b1; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 (.RCLK(core_clk), + .RE(1'b1), .RST(1'b0), .RADDREN(1'b1), .RADDR({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[15] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[14] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[13] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[12] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[11] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[10] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[9] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] , + Open_7, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] , + Open_8, Open_9, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[1] , + Open_10})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000001000000010000000000010000000040000000000000, INIT_1=256'h0000000000000000000000100000000000000000000000000000000000000010, INIT_2=256'h0000010000200000010000200000000000000000000000100000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0020000000000040000000000000000200000000000000000000000000000000, INIT_9=256'h0020000000000040000000000000000200000000000000000000000000000100, INIT_A=256'h0040000000000000000200000100002000000040000000000000000200000100, INIT_B=256'h0000000000000000000000000000000000000000000000000000010000200000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000010000000000001000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_0 = 256'h0000000000000000000001000000010000000000010000000040000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_1 = 256'h0000000000000000000000100000000000000000000000000000000000000010; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_2 = 256'h0000010000200000010000200000000000000000000000100000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_8 = 256'h0020000000000040000000000000000200000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_9 = 256'h0020000000000040000000000000000200000000000000000000000000000100; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_A = 256'h0040000000000000000200000100002000000040000000000000000200000100; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000010000200000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_15 = 256'h0000000000000000000000000000000000000000010000000000001000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$2 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 (.RCLK(core_clk), + .RE(1'b1), .RST(1'b0), .RADDREN(1'b1), .RADDR({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[31] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[30] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[29] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[28] , + Open_11, Open_12, Open_13, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[24] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[23] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[22] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[21] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[20] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[19] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[18] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[17] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[16] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'hE000E000E0004008E000A000E0009000E000E000E000E0006000E000E000E000, INIT_1=256'hE000E000E000E000E000E000E0004008E000E000E000E000E000E000E000E000, INIT_2=256'hE0009000E000E000A000E000E000E000E000E000E000E000E000E000E0004008, INIT_3=256'hE000E000E000E000E0002000E000E000E0004008E000E000E000E000E000E000, INIT_4=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_5=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_6=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_7=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_8=256'hE000E000E0006000E000E000E0004000E000E000E000E000E000E000E000E000, INIT_9=256'hE000E000E0006000E000E000E0004000E000E000E000E000E000E000E0009000, INIT_A=256'h6000E000E000E0004000E0009000E000E0006000E000E000E0004000E000A000, INIT_B=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000A000E000E000, INIT_C=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_D=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_E=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_F=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_10=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_11=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_12=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_13=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_14=256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000, INIT_15=256'h000000000000000000000000000000000000E000E000E000E000E000E000E000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .READ_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .WRITE_WIDTH = 16; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_0 = 256'hE000E000E0004008E000A000E0009000E000E000E000E0006000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_1 = 256'hE000E000E000E000E000E000E0004008E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_2 = 256'hE0009000E000E000A000E000E000E000E000E000E000E000E000E000E0004008; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_3 = 256'hE000E000E000E000E0002000E000E000E0004008E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_4 = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_5 = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_6 = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_7 = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_8 = 256'hE000E000E0006000E000E000E0004000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_9 = 256'hE000E000E0006000E000E000E0004000E000E000E000E000E000E000E0009000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_A = 256'h6000E000E000E0004000E0009000E000E0006000E000E000E0004000E000A000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_B = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000A000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_C = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_D = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_E = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_F = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_10 = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_11 = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_12 = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_13 = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_14 = 256'hE000E000E000E000E000E000E000E000E000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_15 = 256'h000000000000000000000000000000000000E000E000E000E000E000E000E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 (.RCLK(core_clk), + .RE(1'b1), .RST(1'b0), .RADDREN(1'b1), .RADDR({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] }), + .RDATA({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[51] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[50] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[49] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[48] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[47] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[46] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[45] , + Open_14, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] , + Open_15, Open_16, Open_17, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_ack , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_ack , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[37] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[36] , + Open_18, Open_19, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[33] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[32] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=20, WRITE_WIDTH=20, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0002000030088200003008420000300003000030000300002000030000300003, INIT_1=256'h0030000200003000030000300003000030000300003000030000300003000030, INIT_2=256'h0300003000030000300003000030000200003000030000300003000030000300, INIT_3=256'h3000030000300003000030084200003000030088200003000030000300003000, INIT_4=256'h0000300003000030000300003000020000300003000030000200003000030000, INIT_5=256'h0003000030000300003000030000300003000030000300003000030000300003, INIT_6=256'h0030000300003000030000300003000030000300003000030000300003000030, INIT_7=256'h0300003000030000300003000030000300003000030000300003000030000300, INIT_8=256'h3000030000300003000030000300003000030000300003000030000300003000, INIT_9=256'h0000301003000030000300003000030000300003000030000300003000030000, INIT_A=256'h0002000030000300003000020000300003000030000300003000030000300003, INIT_B=256'h0030000200003000030000300003000030000300003008420000300003000030, INIT_C=256'h0200003000030000300002000030088200003000030000300002000030000300, INIT_D=256'h3008820000300003000020000300003000030000200003008420000300003000, INIT_E=256'h0000300003000030000300003000030000300003000030001100001000010000, INIT_F=256'h0003000030000300003000030000300003000030000300003000030000300003, INIT_10=256'h0030000300003000030000300003000030000300003000030000300003000030, INIT_11=256'h0300003000030000300003000030000300003000030000300003000030000300, INIT_12=256'h3000030000300003000030000300003000030000300003000030000300003000, INIT_13=256'h0000300003000030010300003000030000300003000030000300003000030000, INIT_14=256'h0003000030000300003000030000300003000030000300003000030000300003, INIT_15=256'h0030000300003000030000300003000030000300003000030000300003000030, INIT_16=256'h0300003000030000300003000030000300003000030000300003000030000300, INIT_17=256'h3000030000300003000030000300003000030000300003000030000300003000, INIT_18=256'h0000300003000030000300003000030000300003000030000300003000030000, INIT_19=256'h0003880030000300003000030000300003000030000300003000030000300003, INIT_1A=256'h0000000000000000030000300003000030000300003000030000300003200030, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .READ_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .WRITE_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_0 = 256'h0002000030088200003008420000300003000030000300002000030000300003; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_1 = 256'h0030000200003000030000300003000030000300003000030000300003000030; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_2 = 256'h0300003000030000300003000030000200003000030000300003000030000300; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_3 = 256'h3000030000300003000030084200003000030088200003000030000300003000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_4 = 256'h0000300003000030000300003000020000300003000030000200003000030000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_5 = 256'h0003000030000300003000030000300003000030000300003000030000300003; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_6 = 256'h0030000300003000030000300003000030000300003000030000300003000030; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_7 = 256'h0300003000030000300003000030000300003000030000300003000030000300; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_8 = 256'h3000030000300003000030000300003000030000300003000030000300003000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_9 = 256'h0000301003000030000300003000030000300003000030000300003000030000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_A = 256'h0002000030000300003000020000300003000030000300003000030000300003; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_B = 256'h0030000200003000030000300003000030000300003008420000300003000030; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_C = 256'h0200003000030000300002000030088200003000030000300002000030000300; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_D = 256'h3008820000300003000020000300003000030000200003008420000300003000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_E = 256'h0000300003000030000300003000030000300003000030001100001000010000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_F = 256'h0003000030000300003000030000300003000030000300003000030000300003; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_10 = 256'h0030000300003000030000300003000030000300003000030000300003000030; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_11 = 256'h0300003000030000300003000030000300003000030000300003000030000300; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_12 = 256'h3000030000300003000030000300003000030000300003000030000300003000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_13 = 256'h0000300003000030010300003000030000300003000030000300003000030000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_14 = 256'h0003000030000300003000030000300003000030000300003000030000300003; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_15 = 256'h0030000300003000030000300003000030000300003000030000300003000030; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_16 = 256'h0300003000030000300003000030000300003000030000300003000030000300; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_17 = 256'h3000030000300003000030000300003000030000300003000030000300003000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_18 = 256'h0000300003000030000300003000030000300003000030000300003000030000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_19 = 256'h0003880030000300003000030000300003000030000300003000030000300003; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_1A = 256'h0000000000000000030000300003000030000300003000030000300003200030; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$b12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 (.RCLK(core_clk), + .RE(1'b1), .RST(1'b0), .RADDREN(1'b1), .RADDR({\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] }), + .RDATA({Open_20, Open_21, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[69] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[68] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[67] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[66] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[65] , + Open_22, \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[63] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[62] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[61] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[60] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[59] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[58] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[57] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[56] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[55] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[54] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[53] , + \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[52] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=20, WRITE_WIDTH=20, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'hE0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E000, INIT_1=256'h0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003, INIT_2=256'h003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E, INIT_3=256'h03E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0, INIT_4=256'h3E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E00, INIT_5=256'hE0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E000, INIT_6=256'h0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003, INIT_7=256'h003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E, INIT_8=256'h03E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0, INIT_9=256'h3E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E00, INIT_A=256'hE0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E000, INIT_B=256'h0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003, INIT_C=256'h003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E, INIT_D=256'h03E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0, INIT_E=256'h3E0003E0003E0003E0003E0003E0003E0003E0001E0001E0001E000020003E00, INIT_F=256'hE0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E000, INIT_10=256'h0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003, INIT_11=256'h003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E, INIT_12=256'h03E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0, INIT_13=256'h3E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E00, INIT_14=256'hE0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E000, INIT_15=256'h0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003, INIT_16=256'h003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E, INIT_17=256'h03E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0, INIT_18=256'h3E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E00, INIT_19=256'hE000202003E000206003E000204003E0003E0003E0003E0003E0003E0003E000, INIT_1A=256'h00000000000003E0003E0003E0002C0083E0003E0003E0003E0003E0002002A3, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .READ_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .WRITE_WIDTH = 20; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .WCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .WCLKE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .WE_POLARITY = 2'b11; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .RCLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .RST_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .WADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .RADDREN_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .RESET_RAM = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .RESET_OUTREG = "ASYNC"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .RE_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_0 = 256'hE0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_1 = 256'h0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_2 = 256'h003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_3 = 256'h03E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_4 = 256'h3E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E00; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_5 = 256'hE0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_6 = 256'h0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_7 = 256'h003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_8 = 256'h03E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_9 = 256'h3E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E00; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_A = 256'hE0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_B = 256'h0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_C = 256'h003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_D = 256'h03E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_E = 256'h3E0003E0003E0003E0003E0003E0003E0003E0001E0001E0001E000020003E00; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_F = 256'hE0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_10 = 256'h0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_11 = 256'h003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_12 = 256'h03E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_13 = 256'h3E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E00; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .OUTPUT_REG = 1'b0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .WRITE_MODE = "READ_UNKNOWN"; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_14 = 256'hE0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_15 = 256'h0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_16 = 256'h003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_17 = 256'h03E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_18 = 256'h3E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E0003E00; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_19 = 256'hE000202003E000206003E000204003E0003E0003E0003E0003E0003E0003E000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_1A = 256'h00000000000003E0003E0003E0002C0083E0003E0003E0003E0003E0002002A3; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/map_ram/ram__D$c1 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_2 (.D(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_data[9] ), + .CLK(twd_clk), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_pre ), + .A({3'b000})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_2 (.D(1'b1), + .CLK(clk_sys), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_pre ), + .A({3'b100})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i30_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9] ), + .CLK(cmos_pclk), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i30_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i30_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i30_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i30_2 .CE_POLARITY = 1'b1; + EFX_RAM10 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 (.WCLK(clk_sys), + .RCLK(clk_pixel), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\u_axi4_ctrl/rfifo_wdata[7] , \u_axi4_ctrl/rfifo_wdata[15] , + \u_axi4_ctrl/rfifo_wdata[23] , \u_axi4_ctrl/rfifo_wdata[31] , + \u_axi4_ctrl/rfifo_wdata[39] , \u_axi4_ctrl/rfifo_wdata[47] , + \u_axi4_ctrl/rfifo_wdata[55] , \u_axi4_ctrl/rfifo_wdata[63] , + \u_axi4_ctrl/rfifo_wdata[71] , \u_axi4_ctrl/rfifo_wdata[79] , + \u_axi4_ctrl/rfifo_wdata[87] , \u_axi4_ctrl/rfifo_wdata[95] , + \u_axi4_ctrl/rfifo_wdata[103] , \u_axi4_ctrl/rfifo_wdata[111] , + \u_axi4_ctrl/rfifo_wdata[119] , \u_axi4_ctrl/rfifo_wdata[127] }), + .WADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\lcd_data[7] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=1, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .READ_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WRITE_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 (.WCLK(cmos_pclk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({1'b0, \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\r_XYCrop_frame_Gray[4] }), .WADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\w_ddr3_wdata[4] , \w_ddr3_wdata[12] , \w_ddr3_wdata[20] , + \w_ddr3_wdata[28] , \w_ddr3_wdata[36] , \w_ddr3_wdata[44] , + \w_ddr3_wdata[52] , \w_ddr3_wdata[60] , \w_ddr3_wdata[68] , + \w_ddr3_wdata[76] , \w_ddr3_wdata[84] , \w_ddr3_wdata[92] , + \w_ddr3_wdata[100] , \w_ddr3_wdata[108] , \w_ddr3_wdata[116] , + \w_ddr3_wdata[124] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=1, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .READ_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WRITE_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 (.WCLK(cmos_pclk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({1'b0, \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\r_XYCrop_frame_Gray[1] }), .WADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\w_ddr3_wdata[1] , \w_ddr3_wdata[9] , \w_ddr3_wdata[17] , + \w_ddr3_wdata[25] , \w_ddr3_wdata[33] , \w_ddr3_wdata[41] , + \w_ddr3_wdata[49] , \w_ddr3_wdata[57] , \w_ddr3_wdata[65] , + \w_ddr3_wdata[73] , \w_ddr3_wdata[81] , \w_ddr3_wdata[89] , + \w_ddr3_wdata[97] , \w_ddr3_wdata[105] , \w_ddr3_wdata[113] , + \w_ddr3_wdata[121] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=1, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .READ_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WRITE_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 (.WCLK(cmos_pclk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({1'b0, \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\r_XYCrop_frame_Gray[6] }), .WADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\w_ddr3_wdata[6] , \w_ddr3_wdata[14] , \w_ddr3_wdata[22] , + \w_ddr3_wdata[30] , \w_ddr3_wdata[38] , \w_ddr3_wdata[46] , + \w_ddr3_wdata[54] , \w_ddr3_wdata[62] , \w_ddr3_wdata[70] , + \w_ddr3_wdata[78] , \w_ddr3_wdata[86] , \w_ddr3_wdata[94] , + \w_ddr3_wdata[102] , \w_ddr3_wdata[110] , \w_ddr3_wdata[118] , + \w_ddr3_wdata[126] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=1, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .READ_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WRITE_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 (.WCLK(cmos_pclk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({1'b0, \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\r_XYCrop_frame_Gray[7] }), .WADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\w_ddr3_wdata[7] , \w_ddr3_wdata[15] , \w_ddr3_wdata[23] , + \w_ddr3_wdata[31] , \w_ddr3_wdata[39] , \w_ddr3_wdata[47] , + \w_ddr3_wdata[55] , \w_ddr3_wdata[63] , \w_ddr3_wdata[71] , + \w_ddr3_wdata[79] , \w_ddr3_wdata[87] , \w_ddr3_wdata[95] , + \w_ddr3_wdata[103] , \w_ddr3_wdata[111] , \w_ddr3_wdata[119] , + \w_ddr3_wdata[127] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=1, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .READ_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WRITE_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$g1 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 (.WCLK(cmos_pclk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({1'b0, \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\r_XYCrop_frame_Gray[0] }), .WADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\w_ddr3_wdata[0] , \w_ddr3_wdata[8] , \w_ddr3_wdata[16] , + \w_ddr3_wdata[24] , \w_ddr3_wdata[32] , \w_ddr3_wdata[40] , + \w_ddr3_wdata[48] , \w_ddr3_wdata[56] , \w_ddr3_wdata[64] , + \w_ddr3_wdata[72] , \w_ddr3_wdata[80] , \w_ddr3_wdata[88] , + \w_ddr3_wdata[96] , \w_ddr3_wdata[104] , \w_ddr3_wdata[112] , + \w_ddr3_wdata[120] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=1, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .READ_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WRITE_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 (.WCLK(cmos_pclk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({1'b0, \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\r_XYCrop_frame_Gray[3] }), .WADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\w_ddr3_wdata[3] , \w_ddr3_wdata[11] , \w_ddr3_wdata[19] , + \w_ddr3_wdata[27] , \w_ddr3_wdata[35] , \w_ddr3_wdata[43] , + \w_ddr3_wdata[51] , \w_ddr3_wdata[59] , \w_ddr3_wdata[67] , + \w_ddr3_wdata[75] , \w_ddr3_wdata[83] , \w_ddr3_wdata[91] , + \w_ddr3_wdata[99] , \w_ddr3_wdata[107] , \w_ddr3_wdata[115] , + \w_ddr3_wdata[123] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=1, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .READ_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WRITE_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 (.WCLK(cmos_pclk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({1'b0, \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\r_XYCrop_frame_Gray[2] }), .WADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\w_ddr3_wdata[2] , \w_ddr3_wdata[10] , \w_ddr3_wdata[18] , + \w_ddr3_wdata[26] , \w_ddr3_wdata[34] , \w_ddr3_wdata[42] , + \w_ddr3_wdata[50] , \w_ddr3_wdata[58] , \w_ddr3_wdata[66] , + \w_ddr3_wdata[74] , \w_ddr3_wdata[82] , \w_ddr3_wdata[90] , + \w_ddr3_wdata[98] , \w_ddr3_wdata[106] , \w_ddr3_wdata[114] , + \w_ddr3_wdata[122] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=1, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .READ_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WRITE_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 (.WCLK(cmos_pclk), + .RCLK(clk_sys), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({1'b0, \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\r_XYCrop_frame_Gray[5] }), .WADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\w_ddr3_wdata[5] , \w_ddr3_wdata[13] , \w_ddr3_wdata[21] , + \w_ddr3_wdata[29] , \w_ddr3_wdata[37] , \w_ddr3_wdata[45] , + \w_ddr3_wdata[53] , \w_ddr3_wdata[61] , \w_ddr3_wdata[69] , + \w_ddr3_wdata[77] , \w_ddr3_wdata[85] , \w_ddr3_wdata[93] , + \w_ddr3_wdata[101] , \w_ddr3_wdata[109] , \w_ddr3_wdata[117] , + \w_ddr3_wdata[125] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=16, WRITE_WIDTH=1, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .READ_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WRITE_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i38_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[9] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i38_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i38_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i38_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i38_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i21_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[0] ), + .CLK(cmos_pclk), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i21_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i21_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i21_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i21_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i22_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[1] ), + .CLK(cmos_pclk), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i22_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i22_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i22_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i22_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i23_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[2] ), + .CLK(cmos_pclk), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i23_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i23_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i23_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i23_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i24_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[3] ), + .CLK(cmos_pclk), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i24_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i24_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i24_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i24_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i25_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4] ), + .CLK(cmos_pclk), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i25_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i25_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i25_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i25_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i26_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5] ), + .CLK(cmos_pclk), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i26_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i26_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i26_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i26_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i27_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6] ), + .CLK(cmos_pclk), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i27_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i27_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i27_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i27_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i28_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7] ), + .CLK(cmos_pclk), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i28_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i28_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i28_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i28_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i29_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8] ), + .CLK(cmos_pclk), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i29_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i29_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i29_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i29_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i30_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9] ), + .CLK(clk_pixel), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i30_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i30_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i30_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i30_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i42_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[13] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i42_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i42_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i42_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i42_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i33_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i33_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i33_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i33_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i33_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i34_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i34_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i34_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i34_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i34_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i35_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i35_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i35_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i35_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i35_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i36_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i36_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i36_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i36_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i36_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i37_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i37_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i37_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i37_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i37_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i39_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[10] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i39_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i39_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i39_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i39_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i40_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[11] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i40_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i40_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i40_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i40_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i41_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[12] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i41_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i41_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i41_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i41_2 .CE_POLARITY = 1'b1; + EFX_RAM10 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 (.WCLK(clk_sys), + .RCLK(clk_pixel), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\u_axi4_ctrl/rfifo_wdata[2] , \u_axi4_ctrl/rfifo_wdata[10] , + \u_axi4_ctrl/rfifo_wdata[18] , \u_axi4_ctrl/rfifo_wdata[26] , + \u_axi4_ctrl/rfifo_wdata[34] , \u_axi4_ctrl/rfifo_wdata[42] , + \u_axi4_ctrl/rfifo_wdata[50] , \u_axi4_ctrl/rfifo_wdata[58] , + \u_axi4_ctrl/rfifo_wdata[66] , \u_axi4_ctrl/rfifo_wdata[74] , + \u_axi4_ctrl/rfifo_wdata[82] , \u_axi4_ctrl/rfifo_wdata[90] , + \u_axi4_ctrl/rfifo_wdata[98] , \u_axi4_ctrl/rfifo_wdata[106] , + \u_axi4_ctrl/rfifo_wdata[114] , \u_axi4_ctrl/rfifo_wdata[122] }), + .WADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\lcd_data[2] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=1, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .READ_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WRITE_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$b12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 (.WCLK(clk_sys), + .RCLK(clk_pixel), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\u_axi4_ctrl/rfifo_wdata[1] , \u_axi4_ctrl/rfifo_wdata[9] , + \u_axi4_ctrl/rfifo_wdata[17] , \u_axi4_ctrl/rfifo_wdata[25] , + \u_axi4_ctrl/rfifo_wdata[33] , \u_axi4_ctrl/rfifo_wdata[41] , + \u_axi4_ctrl/rfifo_wdata[49] , \u_axi4_ctrl/rfifo_wdata[57] , + \u_axi4_ctrl/rfifo_wdata[65] , \u_axi4_ctrl/rfifo_wdata[73] , + \u_axi4_ctrl/rfifo_wdata[81] , \u_axi4_ctrl/rfifo_wdata[89] , + \u_axi4_ctrl/rfifo_wdata[97] , \u_axi4_ctrl/rfifo_wdata[105] , + \u_axi4_ctrl/rfifo_wdata[113] , \u_axi4_ctrl/rfifo_wdata[121] }), + .WADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\lcd_data[1] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=1, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .READ_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WRITE_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 (.WCLK(clk_sys), + .RCLK(clk_pixel), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\u_axi4_ctrl/rfifo_wdata[3] , \u_axi4_ctrl/rfifo_wdata[11] , + \u_axi4_ctrl/rfifo_wdata[19] , \u_axi4_ctrl/rfifo_wdata[27] , + \u_axi4_ctrl/rfifo_wdata[35] , \u_axi4_ctrl/rfifo_wdata[43] , + \u_axi4_ctrl/rfifo_wdata[51] , \u_axi4_ctrl/rfifo_wdata[59] , + \u_axi4_ctrl/rfifo_wdata[67] , \u_axi4_ctrl/rfifo_wdata[75] , + \u_axi4_ctrl/rfifo_wdata[83] , \u_axi4_ctrl/rfifo_wdata[91] , + \u_axi4_ctrl/rfifo_wdata[99] , \u_axi4_ctrl/rfifo_wdata[107] , + \u_axi4_ctrl/rfifo_wdata[115] , \u_axi4_ctrl/rfifo_wdata[123] }), + .WADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\lcd_data[3] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=1, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .READ_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WRITE_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$c12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 (.WCLK(clk_sys), + .RCLK(clk_pixel), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\u_axi4_ctrl/rfifo_wdata[4] , \u_axi4_ctrl/rfifo_wdata[12] , + \u_axi4_ctrl/rfifo_wdata[20] , \u_axi4_ctrl/rfifo_wdata[28] , + \u_axi4_ctrl/rfifo_wdata[36] , \u_axi4_ctrl/rfifo_wdata[44] , + \u_axi4_ctrl/rfifo_wdata[52] , \u_axi4_ctrl/rfifo_wdata[60] , + \u_axi4_ctrl/rfifo_wdata[68] , \u_axi4_ctrl/rfifo_wdata[76] , + \u_axi4_ctrl/rfifo_wdata[84] , \u_axi4_ctrl/rfifo_wdata[92] , + \u_axi4_ctrl/rfifo_wdata[100] , \u_axi4_ctrl/rfifo_wdata[108] , + \u_axi4_ctrl/rfifo_wdata[116] , \u_axi4_ctrl/rfifo_wdata[124] }), + .WADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\lcd_data[4] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=1, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .READ_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WRITE_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$d12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 (.WCLK(clk_sys), + .RCLK(clk_pixel), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\u_axi4_ctrl/rfifo_wdata[6] , \u_axi4_ctrl/rfifo_wdata[14] , + \u_axi4_ctrl/rfifo_wdata[22] , \u_axi4_ctrl/rfifo_wdata[30] , + \u_axi4_ctrl/rfifo_wdata[38] , \u_axi4_ctrl/rfifo_wdata[46] , + \u_axi4_ctrl/rfifo_wdata[54] , \u_axi4_ctrl/rfifo_wdata[62] , + \u_axi4_ctrl/rfifo_wdata[70] , \u_axi4_ctrl/rfifo_wdata[78] , + \u_axi4_ctrl/rfifo_wdata[86] , \u_axi4_ctrl/rfifo_wdata[94] , + \u_axi4_ctrl/rfifo_wdata[102] , \u_axi4_ctrl/rfifo_wdata[110] , + \u_axi4_ctrl/rfifo_wdata[118] , \u_axi4_ctrl/rfifo_wdata[126] }), + .WADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\lcd_data[6] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=1, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .READ_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WRITE_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$f12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 (.WCLK(clk_sys), + .RCLK(clk_pixel), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\u_axi4_ctrl/rfifo_wdata[0] , \u_axi4_ctrl/rfifo_wdata[8] , + \u_axi4_ctrl/rfifo_wdata[16] , \u_axi4_ctrl/rfifo_wdata[24] , + \u_axi4_ctrl/rfifo_wdata[32] , \u_axi4_ctrl/rfifo_wdata[40] , + \u_axi4_ctrl/rfifo_wdata[48] , \u_axi4_ctrl/rfifo_wdata[56] , + \u_axi4_ctrl/rfifo_wdata[64] , \u_axi4_ctrl/rfifo_wdata[72] , + \u_axi4_ctrl/rfifo_wdata[80] , \u_axi4_ctrl/rfifo_wdata[88] , + \u_axi4_ctrl/rfifo_wdata[96] , \u_axi4_ctrl/rfifo_wdata[104] , + \u_axi4_ctrl/rfifo_wdata[112] , \u_axi4_ctrl/rfifo_wdata[120] }), + .WADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\lcd_data[0] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=1, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .READ_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WRITE_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$2 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_RAM10 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 (.WCLK(clk_sys), + .RCLK(clk_pixel), .WCLKE(1'b1), .RE(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .RST(1'b0), .WADDREN(1'b1), .RADDREN(1'b1), .WE({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int }), + .WDATA({\u_axi4_ctrl/rfifo_wdata[5] , \u_axi4_ctrl/rfifo_wdata[13] , + \u_axi4_ctrl/rfifo_wdata[21] , \u_axi4_ctrl/rfifo_wdata[29] , + \u_axi4_ctrl/rfifo_wdata[37] , \u_axi4_ctrl/rfifo_wdata[45] , + \u_axi4_ctrl/rfifo_wdata[53] , \u_axi4_ctrl/rfifo_wdata[61] , + \u_axi4_ctrl/rfifo_wdata[69] , \u_axi4_ctrl/rfifo_wdata[77] , + \u_axi4_ctrl/rfifo_wdata[85] , \u_axi4_ctrl/rfifo_wdata[93] , + \u_axi4_ctrl/rfifo_wdata[101] , \u_axi4_ctrl/rfifo_wdata[109] , + \u_axi4_ctrl/rfifo_wdata[117] , \u_axi4_ctrl/rfifo_wdata[125] }), + .WADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] }), + .RADDR({\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[3] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[2] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[1] , + \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[0] }), + .RDATA({\lcd_data[5] })) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_RAM10, READ_WIDTH=1, WRITE_WIDTH=16, WCLK_POLARITY=1'b1, WCLKE_POLARITY=1'b1, WE_POLARITY=2'b11, WADDREN_POLARITY=1'b1, RADDREN_POLARITY=1'b1, RST_POLARITY=1'b1, RCLK_POLARITY=1'b1, RE_POLARITY=1'b1, OUTPUT_REG=1'b0, WRITE_MODE="READ_UNKNOWN", RESET_RAM="ASYNC", RESET_OUTREG="ASYNC", INIT_0=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_2=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_3=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_4=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_5=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_6=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_7=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_8=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_9=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_10=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_11=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_12=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_13=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_14=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_15=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_16=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_17=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_18=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_19=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1A=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1B=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1C=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1D=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1E=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_1F=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_20=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_21=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_22=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_23=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_24=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_25=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_26=256'h0000000000000000000000000000000000000000000000000000000000000000, INIT_27=256'h0000000000000000000000000000000000000000000000000000000000000000, PRESERVE_USER_INIT=1'b0 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .READ_WIDTH = 1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WRITE_WIDTH = 16; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WCLKE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WE_POLARITY = 2'b11; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RCLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RST_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RADDREN_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RESET_RAM = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RESET_OUTREG = "ASYNC"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .RE_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .OUTPUT_REG = 1'b0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .WRITE_MODE = "READ_UNKNOWN"; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ram/ram__D$e12 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i42_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[13] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i42_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i42_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i42_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i42_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i33_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[4] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i33_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i33_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i33_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i33_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i34_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[5] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i34_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i34_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i34_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i34_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i35_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[6] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i35_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i35_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i35_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i35_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i36_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[7] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i36_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i36_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i36_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i36_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i37_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[8] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i37_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i37_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i37_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i37_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i38_2 (.D(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[9] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i38_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i38_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i38_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i38_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i39_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[10] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i39_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i39_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i39_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i39_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i40_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[11] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i40_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i40_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i40_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i40_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i41_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry_r[12] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i41_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i41_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i41_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i41_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_2 (.D(1'b1), + .CLK(clk_sys), .CE(1'b1), .Q(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_pre ), + .A({3'b100})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_2 .INIT = 8'h0; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_2 .CLK_POLARITY = 1'b1; + defparam \ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i21_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[0] ), + .CLK(clk_pixel), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i21_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i21_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i21_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i21_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i22_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[1] ), + .CLK(clk_pixel), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i22_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i22_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i22_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i22_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i23_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[2] ), + .CLK(clk_pixel), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i23_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i23_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i23_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i23_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i24_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[3] ), + .CLK(clk_pixel), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i24_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i24_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i24_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i24_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i25_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[4] ), + .CLK(clk_pixel), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i25_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i25_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i25_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i25_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i26_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[5] ), + .CLK(clk_pixel), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i26_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i26_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i26_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i26_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i27_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[6] ), + .CLK(clk_pixel), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i27_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i27_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i27_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i27_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i28_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[7] ), + .CLK(clk_pixel), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i28_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i28_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i28_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i28_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i29_2 (.D(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry_r[8] ), + .CLK(clk_pixel), .CE(1'b1), .Q(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i29_pre ), + .A({3'b101})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, async_reg=TRUE, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i29_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i29_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i29_2 .CE_POLARITY = 1'b1; + EFX_SRL8 \u_axi4_ctrl/dff_138/i15_2 (.D(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[9] ), + .CLK(clk_sys), .CE(1'b1), .Q(\u_axi4_ctrl/dff_138/i15_pre ), + .A({3'b011})) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_SRL8, INIT=8'h0, CLK_POLARITY=1'b1, CE_POLARITY=1'b1 */ ; + defparam \u_axi4_ctrl/dff_138/i15_2 .INIT = 8'h0; + defparam \u_axi4_ctrl/dff_138/i15_2 .CLK_POLARITY = 1'b1; + defparam \u_axi4_ctrl/dff_138/i15_2 .CE_POLARITY = 1'b1; + EFX_LUT4 LUT__19468 (.I0(\u_i2c_timing_ctrl_16bit/i2c_ctrl_clk ), .I1(n13395), + .O(csi_scl_o)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19468.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19469 (.I0(n13395), .I1(\u_i2c_timing_ctrl_16bit/current_state[0] ), + .O(csi_sda_oe)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19469.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19470 (.I0(r_XYCrop_frame_href), .I1(r_XYCrop_frame_de), + .O(led_o[3])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19470.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19471 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), .O(n13396)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__19471.LUTMASK = 16'h4444; + EFX_LUT4 LUT__19472 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), + .I1(n13396), .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] ), .O(n13397)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4f00 */ ; + defparam LUT__19472.LUTMASK = 16'h4f00; + EFX_LUT4 LUT__19473 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] ), .O(n13398)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f4 */ ; + defparam LUT__19473.LUTMASK = 16'h00f4; + EFX_LUT4 LUT__19474 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), .O(n13399)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf077 */ ; + defparam LUT__19474.LUTMASK = 16'hf077; + EFX_LUT4 LUT__19475 (.I0(n13398), .I1(n13397), .I2(n13399), .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_ctrl_clk ), + .O(cmos_sclk)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff10 */ ; + defparam LUT__19475.LUTMASK = 16'hff10; + EFX_LUT4 LUT__19476 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] ), .O(n13400)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h233f */ ; + defparam LUT__19476.LUTMASK = 16'h233f; + EFX_LUT4 LUT__19477 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), + .I1(n13400), .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), + .I3(n13398), .O(cmos_sdat_OE)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0eee */ ; + defparam LUT__19477.LUTMASK = 16'h0eee; + EFX_LUT4 LUT__19478 (.I0(dsi_pll_rstn_o), .I1(dsi_pll_lock), .I2(ddr_pll_lock), + .I3(lvds_pll_lock), .O(w_pll_lock)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19478.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19479 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3] ), + .O(n13401)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h01fe */ ; + defparam LUT__19479.LUTMASK = 16'h01fe; + EFX_LUT4 LUT__19480 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3] ), + .O(n13402)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19480.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19481 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4] ), + .I1(n13402), .O(n13403)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19481.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19482 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][0] ), + .I2(n13401), .I3(n13403), .O(n13404)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19482.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19483 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][0] ), + .I2(n13401), .I3(n13404), .O(n13405)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19483.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19484 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5] ), + .I2(n13402), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n111 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hefef */ ; + defparam LUT__19484.LUTMASK = 16'hefef; + EFX_LUT4 LUT__19485 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_empty[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n111 ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_awaddr_fifo_rd_en ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf8f8 */ ; + defparam LUT__19485.LUTMASK = 16'hf8f8; + EFX_LUT4 LUT__19486 (.I0(n13405), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1263 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha3a3 */ ; + defparam LUT__19486.LUTMASK = 16'ha3a3; + EFX_LUT4 LUT__19487 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wready ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wvalid ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_i_aburst[0] ), + .O(n13406)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__19487.LUTMASK = 16'h4000; + EFX_LUT4 LUT__19488 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .I1(n13406), .O(ceg_net2)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__19488.LUTMASK = 16'h1111; + EFX_LUT4 LUT__19489 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3] ), + .O(n13407)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h01fe */ ; + defparam LUT__19489.LUTMASK = 16'h01fe; + EFX_LUT4 LUT__19490 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3] ), + .O(n13408)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19490.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19491 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4] ), + .I1(n13408), .O(n13409)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19491.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19492 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][0] ), + .I2(n13407), .I3(n13409), .O(n13410)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19492.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19493 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][0] ), + .I2(n13407), .I3(n13410), .O(n13411)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19493.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19494 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2] ), + .O(n13412)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555 */ ; + defparam LUT__19494.LUTMASK = 16'h5555; + EFX_LUT4 LUT__19495 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0] ), + .I2(n13412), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfbf */ ; + defparam LUT__19495.LUTMASK = 16'hbfbf; + EFX_LUT4 LUT__19496 (.I0(n13411), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1004 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3a3a */ ; + defparam LUT__19496.LUTMASK = 16'h3a3a; + EFX_LUT4 LUT__19497 (.I0(n5288), .I1(n5290), .I2(n5292), .I3(n5294), + .O(n13413)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19497.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19498 (.I0(n5239), .I1(n5241), .I2(n5243), .I3(n5245), + .O(n13414)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19498.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19499 (.I0(n5238), .I1(n5287), .I2(n13413), .I3(n13414), + .O(n13415)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19499.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19500 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1] ), + .I2(n13412), .I3(n13415), .O(n13416)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__19500.LUTMASK = 16'h4000; + EFX_LUT4 LUT__19501 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_i_aburst[0] ), + .I2(n13416), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(ceg_net5)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbf00 */ ; + defparam LUT__19501.LUTMASK = 16'hbf00; + EFX_LUT4 LUT__19502 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[3] ), + .O(n13417)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19502.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19503 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rd_alen[7] ), + .O(n13418)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19503.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19504 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[14] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[15] ), + .O(n13419)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19504.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19505 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[11] ), + .O(n13420)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19505.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19506 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[7] ), + .O(n13421)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19506.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19507 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt_p[3] ), + .O(n13422)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19507.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19508 (.I0(n13419), .I1(n13420), .I2(n13421), .I3(n13422), + .O(n13423)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19508.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19509 (.I0(n13418), .I1(n13417), .I2(n13423), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(n13424)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8f00 */ ; + defparam LUT__19509.LUTMASK = 16'h8f00; + EFX_LUT4 LUT__19510 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13411), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[0] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1037 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19510.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19511 (.I0(n13416), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(ceg_net539)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__19511.LUTMASK = 16'h4444; + EFX_LUT4 LUT__19512 (.I0(n13416), .I1(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1089 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19512.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19513 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3] ), + .O(n13425)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h01fe */ ; + defparam LUT__19513.LUTMASK = 16'h01fe; + EFX_LUT4 LUT__19514 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3] ), + .O(n13426)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19514.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19515 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4] ), + .I1(n13426), .O(n13427)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19515.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19516 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][0] ), + .I2(n13425), .I3(n13427), .O(n13428)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19516.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19517 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][0] ), + .I2(n13425), .I3(n13428), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19517.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19518 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[0] ), + .I1(n207), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1071 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19518.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19519 (.I0(r_ddr_unlock), .I1(w_ddr3_avalid), .I2(w_ddr3_atype), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_i_awvalid )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__19519.LUTMASK = 16'h8080; + EFX_LUT4 LUT__19520 (.I0(n5270), .I1(n5272), .I2(n5274), .I3(n5276), + .O(n13429)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19520.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19521 (.I0(n5279), .I1(n5281), .I2(n5283), .I3(n5285), + .O(n13430)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19521.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19522 (.I0(n5269), .I1(n5278), .I2(n13429), .I3(n13430), + .O(n13431)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19522.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19523 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_awvalid ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_flag ), + .O(n13432)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__19523.LUTMASK = 16'h4444; + EFX_LUT4 LUT__19524 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_i_awvalid ), + .I1(n13431), .I2(w_ddr3_cal_done), .I3(n13432), .O(w_ddr3_wready)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__19524.LUTMASK = 16'h4000; + EFX_LUT4 LUT__19525 (.I0(led_o[2]), .I1(w_ddr3_wready), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1193 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19525.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19526 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][40] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][40] ), + .I2(n13401), .I3(n13403), .O(n13433)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19526.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19527 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][40] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][40] ), + .I2(n13401), .I3(n13433), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_fifo_aw[40] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19527.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19528 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3] ), + .O(n13434)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h01fe */ ; + defparam LUT__19528.LUTMASK = 16'h01fe; + EFX_LUT4 LUT__19529 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[1][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[0][0] ), + .I2(n13434), .O(n13435)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19529.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19530 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[3][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[2][0] ), + .I2(n13434), .O(n13436)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19530.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19531 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3] ), + .O(n13437)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19531.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19532 (.I0(n13435), .I1(n13436), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4] ), + .I3(n13437), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_i_arburst_fifo[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaac */ ; + defparam LUT__19532.LUTMASK = 16'hcaac; + EFX_LUT4 LUT__19533 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3] ), + .O(n13438)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h01fe */ ; + defparam LUT__19533.LUTMASK = 16'h01fe; + EFX_LUT4 LUT__19534 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3] ), + .O(n13439)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19534.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19535 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4] ), + .I1(n13439), .O(n13440)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19535.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19536 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][6] ), + .I2(n13438), .I3(n13440), .O(n13441)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19536.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19537 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][6] ), + .I2(n13438), .I3(n13441), .O(n13442)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19537.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19538 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][5] ), + .I2(n13438), .I3(n13440), .O(n13443)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19538.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19539 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][5] ), + .I2(n13438), .I3(n13443), .O(n13444)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19539.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19540 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][4] ), + .I2(n13438), .I3(n13440), .O(n13445)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19540.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19541 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][4] ), + .I2(n13438), .I3(n13445), .O(n13446)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19541.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19542 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][3] ), + .I2(n13438), .I3(n13440), .O(n13447)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19542.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19543 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][3] ), + .I2(n13438), .I3(n13447), .O(n13448)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19543.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19544 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][2] ), + .I2(n13438), .O(n13449)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19544.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19545 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][2] ), + .I2(n13438), .O(n13450)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19545.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19546 (.I0(n13450), .I1(n13449), .I2(n13440), .O(n13451)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19546.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19547 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][1] ), + .I2(n13438), .O(n13452)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19547.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19548 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][1] ), + .I2(n13438), .O(n13453)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19548.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19549 (.I0(n13453), .I1(n13452), .I2(n13440), .O(n13454)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19549.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19550 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][0] ), + .I2(n13438), .O(n13455)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19550.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19551 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][0] ), + .I2(n13438), .O(n13456)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19551.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19552 (.I0(n13456), .I1(n13455), .I2(n13440), .O(n13457)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19552.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19553 (.I0(n13451), .I1(n13454), .I2(n13457), .O(n13458)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__19553.LUTMASK = 16'h8080; + EFX_LUT4 LUT__19554 (.I0(n13446), .I1(n13448), .I2(n13458), .O(n13459)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__19554.LUTMASK = 16'h8080; + EFX_LUT4 LUT__19555 (.I0(n13442), .I1(n13444), .I2(n13459), .O(n13460)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__19555.LUTMASK = 16'h8080; + EFX_LUT4 LUT__19556 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[2][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[0][7] ), + .I2(n13438), .I3(n13440), .O(n13461)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19556.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19557 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[3][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Shift_Data_Out[1][7] ), + .I2(n13438), .I3(n13461), .O(n13462)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19557.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19558 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[8] ), + .I2(n13460), .I3(n13462), .O(n13463)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbdde */ ; + defparam LUT__19558.LUTMASK = 16'hbdde; + EFX_LUT4 LUT__19559 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[6] ), + .I1(n13442), .O(n13464)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19559.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19560 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[5] ), + .I1(n13464), .I2(n13444), .I3(n13459), .O(n13465)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbdde */ ; + defparam LUT__19560.LUTMASK = 16'hbdde; + EFX_LUT4 LUT__19561 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[4] ), + .I1(n13446), .O(n13466)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19561.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19562 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[3] ), + .I1(n13466), .I2(n13458), .I3(n13448), .O(n13467)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbdde */ ; + defparam LUT__19562.LUTMASK = 16'hbdde; + EFX_LUT4 LUT__19563 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[1] ), + .I2(n13454), .I3(n13457), .O(n13468)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heb7d */ ; + defparam LUT__19563.LUTMASK = 16'heb7d; + EFX_LUT4 LUT__19564 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[2] ), + .I1(n13451), .O(n13469)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19564.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19565 (.I0(n13454), .I1(n13457), .I2(n13468), .I3(n13469), + .O(n13470)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0807 */ ; + defparam LUT__19565.LUTMASK = 16'h0807; + EFX_LUT4 LUT__19566 (.I0(n13463), .I1(n13465), .I2(n13467), .I3(n13470), + .O(n13471)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__19566.LUTMASK = 16'h0100; + EFX_LUT4 LUT__19567 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6] ), + .O(n13472)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19567.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19568 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[1] ), + .O(n13473)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__19568.LUTMASK = 16'h9009; + EFX_LUT4 LUT__19569 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[5] ), + .O(n13474)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__19569.LUTMASK = 16'h9009; + EFX_LUT4 LUT__19570 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushToPopGray_buffercc_io_dataOut[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtrGray[3] ), + .O(n13475)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__19570.LUTMASK = 16'h9009; + EFX_LUT4 LUT__19571 (.I0(n13472), .I1(n13473), .I2(n13474), .I3(n13475), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfff */ ; + defparam LUT__19571.LUTMASK = 16'hbfff; + EFX_LUT4 LUT__19572 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .O(n13476)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19572.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19573 (.I0(n13471), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_wr_b_count[0] ), + .I2(n13476), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1378 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb0b0 */ ; + defparam LUT__19573.LUTMASK = 16'hb0b0; + EFX_LUT4 LUT__19574 (.I0(n13476), .I1(n13471), .O(ceg_net376)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__19574.LUTMASK = 16'h1111; + EFX_LUT4 LUT__19575 (.I0(n13416), .I1(n13423), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1090 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19575.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19576 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1090 ), + .O(n13477)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__19576.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__19577 (.I0(n13477), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1054 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc1c1 */ ; + defparam LUT__19577.LUTMASK = 16'hc1c1; + EFX_LUT4 LUT__19578 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5] ), + .I2(n13408), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n95 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hefef */ ; + defparam LUT__19578.LUTMASK = 16'hefef; + EFX_LUT4 LUT__19581 (.I0(\u_axi4_ctrl/rc_burst[0] ), .I1(\u_axi4_ctrl/rc_burst[1] ), + .I2(\u_axi4_ctrl/rc_burst[2] ), .I3(\u_axi4_ctrl/rc_burst[3] ), + .O(n13478)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19581.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19582 (.I0(\u_axi4_ctrl/rc_burst[4] ), .I1(\u_axi4_ctrl/rc_burst[5] ), + .I2(\u_axi4_ctrl/rc_burst[6] ), .O(n13479)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__19582.LUTMASK = 16'h8080; + EFX_LUT4 LUT__19583 (.I0(n13479), .I1(n13478), .I2(\u_axi4_ctrl/rc_burst[7] ), + .O(n13480)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__19583.LUTMASK = 16'h0707; + EFX_LUT4 LUT__19584 (.I0(n13480), .I1(w_ddr3_wready), .O(n13481)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__19584.LUTMASK = 16'h4444; + EFX_LUT4 LUT__19585 (.I0(led_o[2]), .I1(n13481), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_fifo_rd_en )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19585.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19586 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3] ), + .O(n13482)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h01fe */ ; + defparam LUT__19586.LUTMASK = 16'h01fe; + EFX_LUT4 LUT__19587 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3] ), + .O(n13483)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19587.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19588 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4] ), + .I1(n13483), .O(n13484)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19588.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19589 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][0] ), + .I2(n13482), .I3(n13484), .O(n13485)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19589.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19590 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][0] ), + .I2(n13482), .I3(n13485), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19590.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19591 (.I0(n13480), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1193 ), + .O(n13486)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__19591.LUTMASK = 16'h4444; + EFX_LUT4 LUT__19592 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0] ), + .I1(n180), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n572 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc5c5 */ ; + defparam LUT__19592.LUTMASK = 16'hc5c5; + EFX_LUT4 LUT__19593 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arburst_full ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_araddr_full ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_full ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awid_full ), + .O(n13487)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19593.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19594 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arid_full ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_full ), + .I2(n13487), .O(n13488)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__19594.LUTMASK = 16'h1010; + EFX_LUT4 LUT__19595 (.I0(w_ddr3_cal_done), .I1(n13415), .I2(n13431), + .I3(n13488), .O(n13489)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19595.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19596 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_i_awvalid ), + .I1(n13489), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19596.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19597 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_fifo_rd_en ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(ceg_net2477)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__19597.LUTMASK = 16'h1111; + EFX_LUT4 LUT__19598 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1088 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19598.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19599 (.I0(ceg_net539), .I1(w_ddr3_cal_done), .O(ceg_net541)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__19599.LUTMASK = 16'h4444; + EFX_LUT4 LUT__19600 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[14] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[15] ), + .O(n13490)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19600.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19601 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[11] ), + .O(n13491)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19601.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19602 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[7] ), + .O(n13492)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19602.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19603 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_aw_valid_cnt[3] ), + .O(n13493)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19603.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19604 (.I0(n13490), .I1(n13491), .I2(n13492), .I3(n13493), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/not_equal_72/n31 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7fff */ ; + defparam LUT__19604.LUTMASK = 16'h7fff; + EFX_LUT4 LUT__19605 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6] ), + .O(n13494)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19605.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19606 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[5] ), + .O(n13495)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__19606.LUTMASK = 16'h9009; + EFX_LUT4 LUT__19607 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[3] ), + .O(n13496)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__19607.LUTMASK = 16'h9009; + EFX_LUT4 LUT__19608 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtrGray[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1] ), + .O(n13497)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__19608.LUTMASK = 16'h9009; + EFX_LUT4 LUT__19609 (.I0(n13494), .I1(n13495), .I2(n13496), .I3(n13497), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfff */ ; + defparam LUT__19609.LUTMASK = 16'hbfff; + EFX_LUT4 LUT__19610 (.I0(w_ddr3_cal_done), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .O(w_ddr3_rvalid)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19610.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19611 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[15] ), + .O(n13498)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19611.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19612 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[13] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[14] ), + .O(n13499)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__19612.LUTMASK = 16'h0001; + EFX_LUT4 LUT__19613 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[1] ), + .O(n13500)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__19613.LUTMASK = 16'h9009; + EFX_LUT4 LUT__19614 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[3] ), + .O(n13501)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__19614.LUTMASK = 16'h9009; + EFX_LUT4 LUT__19615 (.I0(n13498), .I1(n13499), .I2(n13500), .I3(n13501), + .O(n13502)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19615.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19616 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[7] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[7] ), + .O(n13503)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__19616.LUTMASK = 16'h9009; + EFX_LUT4 LUT__19617 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arlen_rlast_fifo[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[5] ), + .O(n13504)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__19617.LUTMASK = 16'h9009; + EFX_LUT4 LUT__19618 (.I0(w_ddr3_rvalid), .I1(n13502), .I2(n13503), + .I3(n13504), .O(n13505)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19618.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19619 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_rlast_cnt[0] ), + .I1(n13505), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1337 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__19619.LUTMASK = 16'h1111; + EFX_LUT4 LUT__19620 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][1] ), + .I2(n13401), .I3(n13403), .O(n13506)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19620.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19621 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][1] ), + .I2(n13401), .I3(n13506), .O(n13507)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19621.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19622 (.I0(n13507), .I1(n172), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1262 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19622.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19623 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][2] ), + .I2(n13401), .I3(n13403), .O(n13508)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19623.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19624 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][2] ), + .I2(n13401), .I3(n13508), .O(n13509)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19624.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19625 (.I0(n13509), .I1(n5746), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1261 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19625.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19626 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][3] ), + .I2(n13401), .I3(n13403), .O(n13510)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19626.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19627 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][3] ), + .I2(n13401), .I3(n13510), .O(n13511)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19627.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19628 (.I0(n13511), .I1(n5744), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1260 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19628.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19629 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][4] ), + .I2(n13401), .I3(n13403), .O(n13512)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19629.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19630 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][4] ), + .I2(n13401), .I3(n13512), .O(n13513)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19630.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19631 (.I0(n13513), .I1(n5742), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1259 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19631.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19632 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][5] ), + .I2(n13401), .I3(n13403), .O(n13514)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19632.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19633 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][5] ), + .I2(n13401), .I3(n13514), .O(n13515)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19633.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19634 (.I0(n13515), .I1(n5740), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1258 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19634.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19635 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][6] ), + .I2(n13401), .I3(n13403), .O(n13516)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19635.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19636 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][6] ), + .I2(n13401), .I3(n13516), .O(n13517)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19636.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19637 (.I0(n13517), .I1(n5738), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1257 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19637.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19638 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][7] ), + .I2(n13401), .I3(n13403), .O(n13518)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19638.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19639 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][7] ), + .I2(n13401), .I3(n13518), .O(n13519)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19639.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19640 (.I0(n13519), .I1(n5736), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1256 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19640.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19641 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][8] ), + .I2(n13401), .I3(n13403), .O(n13520)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19641.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19642 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][8] ), + .I2(n13401), .I3(n13520), .O(n13521)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19642.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19643 (.I0(n13521), .I1(n5734), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1255 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19643.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19644 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][9] ), + .I2(n13401), .I3(n13403), .O(n13522)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19644.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19645 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][9] ), + .I2(n13401), .I3(n13522), .O(n13523)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19645.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19646 (.I0(n13523), .I1(n5732), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1254 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19646.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19647 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][10] ), + .I2(n13401), .I3(n13403), .O(n13524)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19647.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19648 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][10] ), + .I2(n13401), .I3(n13524), .O(n13525)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19648.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19649 (.I0(n13525), .I1(n5730), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1253 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19649.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19650 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][11] ), + .I2(n13401), .I3(n13403), .O(n13526)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19650.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19651 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][11] ), + .I2(n13401), .I3(n13526), .O(n13527)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19651.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19652 (.I0(n13527), .I1(n5728), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1252 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19652.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19653 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][12] ), + .I2(n13401), .I3(n13403), .O(n13528)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19653.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19654 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][12] ), + .I2(n13401), .I3(n13528), .O(n13529)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19654.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19655 (.I0(n13529), .I1(n5726), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1251 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19655.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19656 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][13] ), + .I2(n13401), .I3(n13403), .O(n13530)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19656.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19657 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][13] ), + .I2(n13401), .I3(n13530), .O(n13531)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19657.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19658 (.I0(n13531), .I1(n5724), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1250 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19658.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19659 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][14] ), + .I2(n13401), .I3(n13403), .O(n13532)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19659.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19660 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][14] ), + .I2(n13401), .I3(n13532), .O(n13533)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19660.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19661 (.I0(n13533), .I1(n5722), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1249 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19661.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19662 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][15] ), + .I2(n13401), .I3(n13403), .O(n13534)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19662.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19663 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][15] ), + .I2(n13401), .I3(n13534), .O(n13535)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19663.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19664 (.I0(n13535), .I1(n5720), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1248 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19664.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19665 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][16] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][16] ), + .I2(n13401), .I3(n13403), .O(n13536)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19665.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19666 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][16] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][16] ), + .I2(n13401), .I3(n13536), .O(n13537)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19666.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19667 (.I0(n13537), .I1(n5718), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1247 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19667.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19668 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][17] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][17] ), + .I2(n13401), .I3(n13403), .O(n13538)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19668.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19669 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][17] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][17] ), + .I2(n13401), .I3(n13538), .O(n13539)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19669.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19670 (.I0(n13539), .I1(n5716), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1246 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19670.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19671 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][18] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][18] ), + .I2(n13401), .I3(n13403), .O(n13540)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19671.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19672 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][18] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][18] ), + .I2(n13401), .I3(n13540), .O(n13541)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19672.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19673 (.I0(n13541), .I1(n5714), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1245 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19673.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19674 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][19] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][19] ), + .I2(n13401), .I3(n13403), .O(n13542)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19674.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19675 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][19] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][19] ), + .I2(n13401), .I3(n13542), .O(n13543)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19675.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19676 (.I0(n13543), .I1(n5712), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1244 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19676.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19677 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][20] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][20] ), + .I2(n13401), .I3(n13403), .O(n13544)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19677.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19678 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][20] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][20] ), + .I2(n13401), .I3(n13544), .O(n13545)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19678.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19679 (.I0(n13545), .I1(n5710), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1243 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19679.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19680 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][21] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][21] ), + .I2(n13401), .I3(n13403), .O(n13546)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19680.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19681 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][21] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][21] ), + .I2(n13401), .I3(n13546), .O(n13547)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19681.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19682 (.I0(n13547), .I1(n5708), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1242 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19682.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19683 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][22] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][22] ), + .I2(n13401), .I3(n13403), .O(n13548)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19683.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19684 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][22] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][22] ), + .I2(n13401), .I3(n13548), .O(n13549)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19684.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19685 (.I0(n13549), .I1(n5706), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1241 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19685.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19686 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][23] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][23] ), + .I2(n13401), .I3(n13403), .O(n13550)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19686.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19687 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][23] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][23] ), + .I2(n13401), .I3(n13550), .O(n13551)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19687.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19688 (.I0(n13551), .I1(n5704), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1240 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19688.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19689 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][24] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][24] ), + .I2(n13401), .I3(n13403), .O(n13552)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19689.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19690 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][24] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][24] ), + .I2(n13401), .I3(n13552), .O(n13553)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19690.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19691 (.I0(n13553), .I1(n5702), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1239 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19691.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19692 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][25] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][25] ), + .I2(n13401), .I3(n13403), .O(n13554)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19692.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19693 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][25] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][25] ), + .I2(n13401), .I3(n13554), .O(n13555)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19693.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19694 (.I0(n13555), .I1(n5700), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1238 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19694.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19695 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][26] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][26] ), + .I2(n13401), .I3(n13403), .O(n13556)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19695.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19696 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][26] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][26] ), + .I2(n13401), .I3(n13556), .O(n13557)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19696.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19697 (.I0(n13557), .I1(n5698), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1237 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19697.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19698 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][27] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][27] ), + .I2(n13401), .I3(n13403), .O(n13558)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19698.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19699 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][27] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][27] ), + .I2(n13401), .I3(n13558), .O(n13559)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19699.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19700 (.I0(n13559), .I1(n5696), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1236 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19700.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19701 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][28] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][28] ), + .I2(n13401), .I3(n13403), .O(n13560)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19701.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19702 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][28] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][28] ), + .I2(n13401), .I3(n13560), .O(n13561)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19702.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19703 (.I0(n13561), .I1(n5694), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1230 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1235 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19703.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19713 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][1] ), + .I2(n13407), .I3(n13409), .O(n13568)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19713.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19714 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][1] ), + .I2(n13407), .I3(n13568), .O(n13569)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19714.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19715 (.I0(n13569), .I1(n170), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1003 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19715.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19716 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][2] ), + .I2(n13407), .I3(n13409), .O(n13570)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19716.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19717 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][2] ), + .I2(n13407), .I3(n13570), .O(n13571)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19717.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19718 (.I0(n13571), .I1(n5805), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1002 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19718.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19719 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][3] ), + .I2(n13407), .I3(n13409), .O(n13572)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19719.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19720 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][3] ), + .I2(n13407), .I3(n13572), .O(n13573)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19720.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19721 (.I0(n13573), .I1(n5803), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1001 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19721.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19722 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][4] ), + .I2(n13407), .I3(n13409), .O(n13574)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19722.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19723 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][4] ), + .I2(n13407), .I3(n13574), .O(n13575)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19723.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19724 (.I0(n13575), .I1(n5801), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1000 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19724.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19725 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][5] ), + .I2(n13407), .I3(n13409), .O(n13576)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19725.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19726 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][5] ), + .I2(n13407), .I3(n13576), .O(n13577)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19726.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19727 (.I0(n13577), .I1(n5799), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n999 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19727.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19728 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][6] ), + .I2(n13407), .I3(n13409), .O(n13578)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19728.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19729 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][6] ), + .I2(n13407), .I3(n13578), .O(n13579)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19729.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19730 (.I0(n13579), .I1(n5797), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n998 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19730.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19731 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][7] ), + .I2(n13407), .I3(n13409), .O(n13580)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19731.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19732 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][7] ), + .I2(n13407), .I3(n13580), .O(n13581)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19732.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19733 (.I0(n13581), .I1(n5795), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n997 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19733.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19734 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][8] ), + .I2(n13407), .I3(n13409), .O(n13582)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19734.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19735 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][8] ), + .I2(n13407), .I3(n13582), .O(n13583)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19735.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19736 (.I0(n13583), .I1(n5793), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n996 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19736.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19737 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][9] ), + .I2(n13407), .I3(n13409), .O(n13584)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19737.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19738 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][9] ), + .I2(n13407), .I3(n13584), .O(n13585)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19738.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19739 (.I0(n13585), .I1(n5791), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n995 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19739.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19740 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][10] ), + .I2(n13407), .I3(n13409), .O(n13586)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19740.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19741 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][10] ), + .I2(n13407), .I3(n13586), .O(n13587)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19741.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19742 (.I0(n13587), .I1(n5789), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n994 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19742.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19743 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][11] ), + .I2(n13407), .I3(n13409), .O(n13588)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19743.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19744 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][11] ), + .I2(n13407), .I3(n13588), .O(n13589)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19744.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19745 (.I0(n13589), .I1(n5787), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n993 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19745.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19746 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][12] ), + .I2(n13407), .I3(n13409), .O(n13590)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19746.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19747 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][12] ), + .I2(n13407), .I3(n13590), .O(n13591)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19747.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19748 (.I0(n13591), .I1(n5785), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n992 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19748.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19749 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][13] ), + .I2(n13407), .I3(n13409), .O(n13592)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19749.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19750 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][13] ), + .I2(n13407), .I3(n13592), .O(n13593)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19750.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19751 (.I0(n13593), .I1(n5783), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n991 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19751.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19752 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][14] ), + .I2(n13407), .I3(n13409), .O(n13594)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19752.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19753 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][14] ), + .I2(n13407), .I3(n13594), .O(n13595)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19753.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19754 (.I0(n13595), .I1(n5781), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n990 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19754.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19755 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][15] ), + .I2(n13407), .I3(n13409), .O(n13596)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19755.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19756 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][15] ), + .I2(n13407), .I3(n13596), .O(n13597)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19756.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19757 (.I0(n13597), .I1(n5779), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n989 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19757.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19758 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][16] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][16] ), + .I2(n13407), .I3(n13409), .O(n13598)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19758.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19759 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][16] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][16] ), + .I2(n13407), .I3(n13598), .O(n13599)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19759.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19760 (.I0(n13599), .I1(n5777), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n988 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19760.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19761 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][17] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][17] ), + .I2(n13407), .I3(n13409), .O(n13600)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19761.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19762 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][17] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][17] ), + .I2(n13407), .I3(n13600), .O(n13601)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19762.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19763 (.I0(n13601), .I1(n5775), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n987 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19763.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19764 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][18] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][18] ), + .I2(n13407), .I3(n13409), .O(n13602)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19764.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19765 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][18] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][18] ), + .I2(n13407), .I3(n13602), .O(n13603)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19765.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19766 (.I0(n13603), .I1(n5773), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n986 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19766.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19767 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][19] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][19] ), + .I2(n13407), .I3(n13409), .O(n13604)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19767.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19768 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][19] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][19] ), + .I2(n13407), .I3(n13604), .O(n13605)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19768.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19769 (.I0(n13605), .I1(n5771), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n985 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19769.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19770 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][20] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][20] ), + .I2(n13407), .I3(n13409), .O(n13606)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19770.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19771 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][20] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][20] ), + .I2(n13407), .I3(n13606), .O(n13607)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19771.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19772 (.I0(n13607), .I1(n5769), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n984 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19772.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19773 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][21] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][21] ), + .I2(n13407), .I3(n13409), .O(n13608)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19773.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19774 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][21] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][21] ), + .I2(n13407), .I3(n13608), .O(n13609)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19774.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19775 (.I0(n13609), .I1(n5767), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n983 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19775.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19776 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][22] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][22] ), + .I2(n13407), .I3(n13409), .O(n13610)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19776.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19777 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][22] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][22] ), + .I2(n13407), .I3(n13610), .O(n13611)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19777.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19778 (.I0(n13611), .I1(n5765), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n982 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19778.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19779 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][23] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][23] ), + .I2(n13407), .I3(n13409), .O(n13612)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19779.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19780 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][23] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][23] ), + .I2(n13407), .I3(n13612), .O(n13613)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19780.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19781 (.I0(n13613), .I1(n5763), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n981 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19781.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19782 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][24] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][24] ), + .I2(n13407), .I3(n13409), .O(n13614)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19782.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19783 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][24] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][24] ), + .I2(n13407), .I3(n13614), .O(n13615)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19783.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19784 (.I0(n13615), .I1(n5761), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n980 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19784.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19785 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][25] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][25] ), + .I2(n13407), .I3(n13409), .O(n13616)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19785.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19786 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][25] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][25] ), + .I2(n13407), .I3(n13616), .O(n13617)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19786.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19787 (.I0(n13617), .I1(n5759), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n979 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19787.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19788 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][26] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][26] ), + .I2(n13407), .I3(n13409), .O(n13618)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19788.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19789 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][26] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][26] ), + .I2(n13407), .I3(n13618), .O(n13619)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19789.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19790 (.I0(n13619), .I1(n5757), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n978 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19790.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19791 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][27] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][27] ), + .I2(n13407), .I3(n13409), .O(n13620)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19791.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19792 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][27] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][27] ), + .I2(n13407), .I3(n13620), .O(n13621)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19792.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19793 (.I0(n13621), .I1(n5755), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n977 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19793.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19794 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[2][28] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[0][28] ), + .I2(n13407), .I3(n13409), .O(n13622)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__19794.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__19795 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[3][28] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_Out[1][28] ), + .I2(n13407), .I3(n13622), .O(n13623)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__19795.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__19796 (.I0(n13623), .I1(n5753), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n976 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19796.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19806 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13569), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[1] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1036 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19806.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19807 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13571), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[2] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1035 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19807.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19808 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13573), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[3] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1034 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19808.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19809 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13575), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[4] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1033 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19809.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19810 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13577), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[5] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1032 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19810.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19811 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13579), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[6] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1031 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19811.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19812 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13581), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[7] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1030 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19812.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19813 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13583), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[8] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1029 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19813.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19814 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13585), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[9] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1028 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19814.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19815 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13587), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[10] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1027 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19815.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19816 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13589), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[11] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1026 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19816.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19817 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13591), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[12] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1025 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19817.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19818 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13593), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[13] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1024 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19818.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19819 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13595), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[14] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1023 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19819.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19820 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13597), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[15] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1022 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19820.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19821 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13599), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[16] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1021 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19821.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19822 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13601), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[17] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1020 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19822.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19823 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13603), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[18] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1019 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19823.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19824 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13605), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[19] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1018 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19824.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19825 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13607), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[20] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1017 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19825.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19826 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13609), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[21] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1016 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19826.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19827 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13611), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[22] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1015 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19827.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19828 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13613), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[23] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1014 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19828.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19829 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13615), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[24] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1013 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19829.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19830 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13617), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[25] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1012 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19830.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19831 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13619), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[26] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1011 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19831.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19832 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13621), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[27] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1010 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19832.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19833 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .I1(n13623), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr[28] ), + .I3(n13424), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1009 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__19833.LUTMASK = 16'hf444; + EFX_LUT4 LUT__19834 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][1] ), + .I2(n13425), .I3(n13427), .O(n13630)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19834.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19835 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][1] ), + .I2(n13425), .I3(n13630), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19835.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19836 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[1] ), + .I1(n5591), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1070 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19836.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19837 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][2] ), + .I2(n13425), .I3(n13427), .O(n13631)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19837.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19838 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][2] ), + .I2(n13425), .I3(n13631), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19838.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19839 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[2] ), + .I1(n5589), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1069 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19839.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19840 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][3] ), + .I2(n13425), .I3(n13427), .O(n13632)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19840.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19841 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][3] ), + .I2(n13425), .I3(n13632), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19841.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19842 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[3] ), + .I1(n5587), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1068 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19842.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19843 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][4] ), + .I2(n13425), .I3(n13427), .O(n13633)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19843.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19844 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][4] ), + .I2(n13425), .I3(n13633), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19844.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19845 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[4] ), + .I1(n5585), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1067 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19845.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19846 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][5] ), + .I2(n13425), .I3(n13427), .O(n13634)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19846.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19847 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][5] ), + .I2(n13425), .I3(n13634), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19847.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19848 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[5] ), + .I1(n5583), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1066 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19848.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19849 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][6] ), + .I2(n13425), .I3(n13427), .O(n13635)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19849.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19850 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][6] ), + .I2(n13425), .I3(n13635), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19850.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19851 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[6] ), + .I1(n5581), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1065 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19851.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19852 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[2][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[0][7] ), + .I2(n13425), .I3(n13427), .O(n13636)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19852.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19853 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[1][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Shift_Data_Out[3][7] ), + .I2(n13425), .I3(n13636), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19853.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19854 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[7] ), + .I1(n5579), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1064 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19854.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19855 (.I0(n5577), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1063 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19855.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19856 (.I0(n5575), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1062 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19856.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19857 (.I0(n5573), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1061 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19857.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19858 (.I0(n5571), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1060 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19858.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19859 (.I0(n5569), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1059 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19859.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19860 (.I0(n5567), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1058 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19860.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19861 (.I0(n5565), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1057 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19861.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19862 (.I0(n5564), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1056 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19862.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19863 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[2][41] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[0][41] ), + .I2(n13401), .I3(n13403), .O(n13637)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19863.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19864 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[1][41] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_Out[3][41] ), + .I2(n13401), .I3(n13637), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_fifo_aw[41] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19864.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19865 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[1][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[0][1] ), + .I2(n13434), .O(n13638)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19865.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19866 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[3][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Shift_Data_Out[2][1] ), + .I2(n13434), .O(n13639)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19866.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19867 (.I0(n13638), .I1(n13639), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4] ), + .I3(n13437), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_i_arburst_fifo[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaac */ ; + defparam LUT__19867.LUTMASK = 16'hcaac; + EFX_LUT4 LUT__19868 (.I0(n13471), .I1(n13476), .I2(n178), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1377 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__19868.LUTMASK = 16'h4040; + EFX_LUT4 LUT__19869 (.I0(n13471), .I1(n13476), .I2(n5633), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1376 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__19869.LUTMASK = 16'h4040; + EFX_LUT4 LUT__19870 (.I0(n13471), .I1(n13476), .I2(n5631), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1375 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__19870.LUTMASK = 16'h4040; + EFX_LUT4 LUT__19871 (.I0(n13471), .I1(n13476), .I2(n5629), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1374 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__19871.LUTMASK = 16'h4040; + EFX_LUT4 LUT__19872 (.I0(n13471), .I1(n13476), .I2(n5627), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1373 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__19872.LUTMASK = 16'h4040; + EFX_LUT4 LUT__19873 (.I0(n13471), .I1(n13476), .I2(n5625), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1372 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__19873.LUTMASK = 16'h4040; + EFX_LUT4 LUT__19874 (.I0(n13471), .I1(n13476), .I2(n5623), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1371 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__19874.LUTMASK = 16'h4040; + EFX_LUT4 LUT__19875 (.I0(n13471), .I1(n13476), .I2(n5622), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1370 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__19875.LUTMASK = 16'h4040; + EFX_LUT4 LUT__19876 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0] ), + .I1(n13412), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1053 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__19876.LUTMASK = 16'h7878; + EFX_LUT4 LUT__19877 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_state[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1052 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he8e8 */ ; + defparam LUT__19877.LUTMASK = 16'he8e8; + EFX_LUT4 LUT__19893 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][1] ), + .I2(n13482), .I3(n13484), .O(n13640)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19893.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19894 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][1] ), + .I2(n13482), .I3(n13640), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19894.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19895 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][2] ), + .I2(n13482), .I3(n13484), .O(n13641)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19895.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19896 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][2] ), + .I2(n13482), .I3(n13641), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19896.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19897 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][3] ), + .I2(n13482), .I3(n13484), .O(n13642)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19897.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19898 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][3] ), + .I2(n13482), .I3(n13642), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19898.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19899 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][4] ), + .I2(n13482), .I3(n13484), .O(n13643)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19899.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19900 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][4] ), + .I2(n13482), .I3(n13643), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19900.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19901 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][5] ), + .I2(n13482), .I3(n13484), .O(n13644)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19901.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19902 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][5] ), + .I2(n13482), .I3(n13644), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19902.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19903 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][6] ), + .I2(n13482), .I3(n13484), .O(n13645)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19903.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19904 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][6] ), + .I2(n13482), .I3(n13645), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19904.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19905 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[2][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[0][7] ), + .I2(n13482), .I3(n13484), .O(n13646)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf305 */ ; + defparam LUT__19905.LUTMASK = 16'hf305; + EFX_LUT4 LUT__19906 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[1][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Shift_Data_Out[3][7] ), + .I2(n13482), .I3(n13646), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_rlast_fifo[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__19906.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__19907 (.I0(n5834), .I1(n5620), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n571 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19907.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19908 (.I0(n5832), .I1(n5618), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n570 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19908.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19909 (.I0(n5830), .I1(n5616), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n569 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19909.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19910 (.I0(n5828), .I1(n5614), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n568 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19910.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19911 (.I0(n5826), .I1(n5612), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n567 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19911.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19912 (.I0(n5824), .I1(n5610), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n566 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19912.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19913 (.I0(n5822), .I1(n5608), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n565 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19913.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19914 (.I0(n5820), .I1(n5606), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n564 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19914.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19915 (.I0(n5818), .I1(n5604), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n563 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19915.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19916 (.I0(n5816), .I1(n5602), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n562 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19916.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19917 (.I0(n5814), .I1(n5600), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n561 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19917.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19918 (.I0(n5812), .I1(n5598), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n560 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19918.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19919 (.I0(n5810), .I1(n5596), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n559 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19919.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19920 (.I0(n5808), .I1(n5594), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n558 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19920.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19921 (.I0(n5807), .I1(n5593), .I2(n13486), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n557 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19921.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19922 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1087 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19922.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19923 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1086 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19923.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19924 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1085 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19924.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19925 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1084 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19925.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19926 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1083 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19926.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19927 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1082 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19927.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19928 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_arlen_fifo[7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1081 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19928.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19929 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1080 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19929.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19930 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1079 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19930.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19931 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1078 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19931.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19932 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1077 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19932.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19933 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1076 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19933.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19934 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1075 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19934.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19935 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1074 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19935.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19936 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_arvalid_cnt[15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/equal_77/n7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1073 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19936.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19937 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19937.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19938 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Out_Sel[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__19938.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__19939 (.I0(w_ddr3_atype), .I1(w_ddr3_avalid), .I2(r_ddr_unlock), + .I3(n13489), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__19939.LUTMASK = 16'h4000; + EFX_LUT4 LUT__19940 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[3] ), + .O(n13647)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19940.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19941 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4] ), + .I2(n13647), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/equal_40/n11 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfbf */ ; + defparam LUT__19941.LUTMASK = 16'hbfbf; + EFX_LUT4 LUT__19942 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[5] ), + .I2(n13437), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en ), + .O(n13648)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hef00 */ ; + defparam LUT__19942.LUTMASK = 16'hef00; + EFX_LUT4 LUT__19943 (.I0(n13648), .I1(rstn_sys), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19943.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19944 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Data_Num[0] ), + .I1(n515), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n49 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5c5c */ ; + defparam LUT__19944.LUTMASK = 16'h5c5c; + EFX_LUT4 LUT__19945 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .I1(n13648), .O(ceg_net577)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19945.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19946 (.I0(n5555), .I1(n209), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n48 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19946.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19947 (.I0(n5562), .I1(n5553), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n47 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19947.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19948 (.I0(n5560), .I1(n5551), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n46 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19948.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19949 (.I0(n5558), .I1(n5549), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n45 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19949.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19950 (.I0(n5557), .I1(n5548), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/n44 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19950.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19951 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19951.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19952 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Out_Sel[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__19952.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__19953 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[11] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19953.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19954 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[12] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19954.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19955 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[13] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19955.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19956 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[14] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19956.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19957 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[15] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19957.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19958 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[16] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19958.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19959 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[17] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19959.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19960 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[18] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19960.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19961 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[19] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19961.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19962 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[20] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19962.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19963 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[21] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19963.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19964 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[22] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19964.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19965 (.I0(w_ddr3_atype), .I1(\w_ddr3_araddr[23] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Shift_Data_In[3][19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19965.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19966 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[3] ), + .O(n13649)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19966.LUTMASK = 16'h8000; + EFX_LUT4 LUT__19967 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[4] ), + .I2(n13649), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/equal_40/n11 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfbf */ ; + defparam LUT__19967.LUTMASK = 16'hbfbf; + EFX_LUT4 LUT__19968 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n95 ), + .O(n13650)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__19968.LUTMASK = 16'h8888; + EFX_LUT4 LUT__19969 (.I0(n13650), .I1(rstn_sys), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n860 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__19969.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__19970 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/Data_Num[0] ), + .I1(n540), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n73 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5c5c */ ; + defparam LUT__19970.LUTMASK = 16'h5c5c; + EFX_LUT4 LUT__19971 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .I1(n13650), .O(ceg_net595)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19971.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19972 (.I0(n5539), .I1(n532), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n72 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__19972.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__19973 (.I0(n5546), .I1(n5537), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n71 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19973.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19974 (.I0(n5544), .I1(n5535), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n70 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19974.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19975 (.I0(n5542), .I1(n5533), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n69 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19975.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19976 (.I0(n5541), .I1(n5532), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/n68 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__19976.LUTMASK = 16'hacac; + EFX_LUT4 LUT__19977 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__19977.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__19978 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Out_Sel[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__19978.LUTMASK = 16'h6666; + EFX_LUT4 LUT__19979 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[4] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19979.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19980 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[5] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19980.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19981 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[6] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19981.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19982 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[7] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19982.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19983 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[8] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19983.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19984 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[9] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19984.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19985 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[10] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19985.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19986 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[11] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19986.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19987 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[12] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19987.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19988 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[13] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19988.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19989 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[14] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19989.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19990 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[15] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19990.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19991 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[16] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19991.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19992 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[17] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19992.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19993 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[18] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19993.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19994 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[19] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19994.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19995 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[20] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19995.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19996 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[21] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19996.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19997 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[22] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19997.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19998 (.I0(w_ddr3_atype), .I1(\w_ddr3_awaddr[23] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Shift_Data_In[3][19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__19998.LUTMASK = 16'h7777; + EFX_LUT4 LUT__19999 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[3] ), + .O(n13651)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__19999.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20000 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[4] ), + .I2(n13651), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/equal_40/n11 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfbf */ ; + defparam LUT__20000.LUTMASK = 16'hbfbf; + EFX_LUT4 LUT__20001 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n111 ), + .I1(n13486), .I2(rstn_sys), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n1212 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8f8f */ ; + defparam LUT__20001.LUTMASK = 16'h8f8f; + EFX_LUT4 LUT__20002 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Data_Num[0] ), + .I1(n775), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n89 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5c5c */ ; + defparam LUT__20002.LUTMASK = 16'h5c5c; + EFX_LUT4 LUT__20003 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awaddr_fifo_rd_en ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n111 ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(ceg_net649)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf8f8 */ ; + defparam LUT__20003.LUTMASK = 16'hf8f8; + EFX_LUT4 LUT__20004 (.I0(n5523), .I1(n767), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n88 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20004.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20005 (.I0(n5530), .I1(n5521), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n87 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20005.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20006 (.I0(n5528), .I1(n5519), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n86 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20006.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20007 (.I0(n5526), .I1(n5517), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n85 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20007.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20008 (.I0(n5525), .I1(n5516), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/n84 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20008.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20009 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3] ), + .O(n13652)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20009.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20010 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4] ), + .I2(n13652), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/equal_40/n11 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfbf */ ; + defparam LUT__20010.LUTMASK = 16'hbfbf; + EFX_LUT4 LUT__20011 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[3] ), + .O(n13653)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20011.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20012 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3] ), + .O(n13654)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20012.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20013 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5] ), + .I2(n13654), .O(n13655)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__20013.LUTMASK = 16'h1010; + EFX_LUT4 LUT__20014 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[4] ), + .I2(n13653), .I3(n13655), .O(n13656)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00ef */ ; + defparam LUT__20014.LUTMASK = 16'h00ef; + EFX_LUT4 LUT__20015 (.I0(n13656), .I1(rstn_sys), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__20015.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__20016 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/Data_Num[0] ), + .I1(n1024), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n49 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5c5c */ ; + defparam LUT__20016.LUTMASK = 16'h5c5c; + EFX_LUT4 LUT__20017 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .I1(n13656), .O(ceg_net685)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20017.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20018 (.I0(n5507), .I1(n1016), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n48 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20018.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20019 (.I0(n5514), .I1(n5505), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n47 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20019.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20020 (.I0(n5512), .I1(n5503), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n46 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20020.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20021 (.I0(n5510), .I1(n5501), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n45 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20021.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20022 (.I0(n5509), .I1(n5500), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/n44 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20022.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20023 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3] ), + .O(n13657)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20023.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20024 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4] ), + .I2(n13657), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/equal_40/n11 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfbf */ ; + defparam LUT__20024.LUTMASK = 16'hbfbf; + EFX_LUT4 LUT__20025 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[3] ), + .O(n13658)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20025.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20026 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[4] ), + .I2(n13658), .I3(n13505), .O(n13659)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hef00 */ ; + defparam LUT__20026.LUTMASK = 16'hef00; + EFX_LUT4 LUT__20027 (.I0(n13659), .I1(rstn_sys), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__20027.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__20028 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/Data_Num[0] ), + .I1(n1035), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n49 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5c5c */ ; + defparam LUT__20028.LUTMASK = 16'h5c5c; + EFX_LUT4 LUT__20029 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .I1(n13659), .O(ceg_net721)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20029.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20030 (.I0(n5491), .I1(n1027), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n48 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20030.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20031 (.I0(n5498), .I1(n5489), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n47 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20031.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20032 (.I0(n5496), .I1(n5487), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n46 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20032.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20033 (.I0(n5494), .I1(n5485), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n45 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20033.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20034 (.I0(n5493), .I1(n5484), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/n44 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20034.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20035 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[3] ), + .O(n13660)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20035.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20036 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[4] ), + .I2(n13660), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/equal_40/n11 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfbf */ ; + defparam LUT__20036.LUTMASK = 16'hbfbf; + EFX_LUT4 LUT__20037 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full ), + .I1(n13471), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Fifo_Wr_En )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20037.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20038 (.I0(rstn_sys), .I1(n13655), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__20038.LUTMASK = 16'h7777; + EFX_LUT4 LUT__20039 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Data_Num[0] ), + .I1(n1046), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full ), + .I3(n13471), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n49 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc5cc */ ; + defparam LUT__20039.LUTMASK = 16'hc5cc; + EFX_LUT4 LUT__20040 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full ), + .I1(n13471), .I2(n13655), .O(ceg_net739)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4b4b */ ; + defparam LUT__20040.LUTMASK = 16'h4b4b; + EFX_LUT4 LUT__20041 (.I0(n1038), .I1(n5475), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full ), + .I3(n13471), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n48 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcacc */ ; + defparam LUT__20041.LUTMASK = 16'hcacc; + EFX_LUT4 LUT__20042 (.I0(n5482), .I1(n5473), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full ), + .I3(n13471), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n47 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcacc */ ; + defparam LUT__20042.LUTMASK = 16'hcacc; + EFX_LUT4 LUT__20043 (.I0(n5480), .I1(n5471), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full ), + .I3(n13471), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n46 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcacc */ ; + defparam LUT__20043.LUTMASK = 16'hcacc; + EFX_LUT4 LUT__20044 (.I0(n5478), .I1(n5469), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full ), + .I3(n13471), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n45 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcacc */ ; + defparam LUT__20044.LUTMASK = 16'hcacc; + EFX_LUT4 LUT__20045 (.I0(n5477), .I1(n5468), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/Wr_Full ), + .I3(n13471), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/n44 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcacc */ ; + defparam LUT__20045.LUTMASK = 16'hcacc; + EFX_LUT4 LUT__20046 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20046.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20047 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Out_Sel[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20047.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20048 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[3] ), + .O(n13661)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20048.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20049 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4] ), + .I2(n13661), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/equal_40/n11 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfbf */ ; + defparam LUT__20049.LUTMASK = 16'hbfbf; + EFX_LUT4 LUT__20050 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[5] ), + .I2(n13426), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_ar_sample_rd_en ), + .O(n13662)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hef00 */ ; + defparam LUT__20050.LUTMASK = 16'hef00; + EFX_LUT4 LUT__20051 (.I0(n13662), .I1(rstn_sys), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__20051.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__20052 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/Data_Num[0] ), + .I1(n1057), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n49 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5c5c */ ; + defparam LUT__20052.LUTMASK = 16'h5c5c; + EFX_LUT4 LUT__20053 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .I1(n13662), .O(ceg_net793)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20053.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20054 (.I0(n5459), .I1(n1049), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n48 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20054.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20055 (.I0(n5466), .I1(n5457), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n47 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20055.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20056 (.I0(n5464), .I1(n5455), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n46 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20056.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20057 (.I0(n5462), .I1(n5453), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n45 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20057.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20058 (.I0(n5461), .I1(n5452), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/n44 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20058.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20059 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20059.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20060 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Out_Sel[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20060.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20061 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Wr_Full ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20061.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20062 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[3] ), + .O(n13663)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20062.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20063 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4] ), + .I2(n13663), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/equal_40/n11 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfbf */ ; + defparam LUT__20063.LUTMASK = 16'hbfbf; + EFX_LUT4 LUT__20064 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[4] ), + .I2(n13483), .I3(n13505), .O(n13664)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hef00 */ ; + defparam LUT__20064.LUTMASK = 16'hef00; + EFX_LUT4 LUT__20065 (.I0(n13664), .I1(rstn_sys), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__20065.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__20066 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Data_Num[0] ), + .I1(n1124), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n49 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5c5c */ ; + defparam LUT__20066.LUTMASK = 16'h5c5c; + EFX_LUT4 LUT__20067 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .I1(n13664), .O(ceg_net811)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20067.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20068 (.I0(n5443), .I1(n1116), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n48 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20068.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20069 (.I0(n5450), .I1(n5441), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n47 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20069.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20070 (.I0(n5448), .I1(n5439), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n46 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20070.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20071 (.I0(n5446), .I1(n5437), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n45 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20071.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20072 (.I0(n5445), .I1(n5436), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/n44 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20072.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20073 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_awlen_full ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20073.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20074 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20074.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20075 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Out_Sel[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20075.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20076 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[3] ), + .O(n13665)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20076.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20077 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4] ), + .I2(n13665), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/equal_40/n11 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfbf */ ; + defparam LUT__20077.LUTMASK = 16'hbfbf; + EFX_LUT4 LUT__20078 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[5] ), + .O(n13666)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20078.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20079 (.I0(n13439), .I1(n13666), .I2(n13471), .I3(rstn_sys), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h70ff */ ; + defparam LUT__20079.LUTMASK = 16'h70ff; + EFX_LUT4 LUT__20080 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Data_Num[0] ), + .I1(n1191), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n49 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5c5c */ ; + defparam LUT__20080.LUTMASK = 16'h5c5c; + EFX_LUT4 LUT__20081 (.I0(n13439), .I1(n13666), .I2(n13471), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .O(ceg_net847)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8f70 */ ; + defparam LUT__20081.LUTMASK = 16'h8f70; + EFX_LUT4 LUT__20082 (.I0(n5427), .I1(n1183), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n48 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20082.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20083 (.I0(n5434), .I1(n5425), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n47 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20083.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20084 (.I0(n5432), .I1(n5423), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n46 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20084.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20085 (.I0(n5430), .I1(n5421), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n45 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20085.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20086 (.I0(n5429), .I1(n5420), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/Fifo_Wr_En ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/n44 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20086.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20087 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[0].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20087.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20088 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6] ), + .O(n12876)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__20088.LUTMASK = 16'h9999; + EFX_LUT4 LUT__20089 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4] ), + .I1(n12876), .O(n12879)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20089.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20090 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3] ), + .I1(n12879), .O(n12882)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20090.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20091 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2] ), + .I1(n12882), .O(n12885)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20091.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20092 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1] ), + .I1(n12885), .O(n12888)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20092.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20093 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0] ), + .I1(n12888), .O(n8257)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20093.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20094 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11] ), + .O(n13667)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20094.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20095 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7] ), + .O(n13668)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20095.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20096 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3] ), + .O(n13669)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20096.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20097 (.I0(n13667), .I1(n13668), .I2(n13669), .O(n13670)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20097.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20098 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[29] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[30] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[31] ), + .O(n13671)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20098.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20099 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23] ), + .O(n13672)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20099.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20100 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27] ), + .O(n13673)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20100.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20101 (.I0(n13671), .I1(n13672), .I2(n13673), .O(n13674)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20101.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20102 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22] ), + .O(n13675)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20102.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20103 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19] ), + .O(n13676)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20103.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20104 (.I0(n13670), .I1(n13674), .I2(n13675), .I3(n13676), + .O(n13677)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20104.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20105 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I1(n13677), .O(n13678)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20105.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20106 (.I0(n13678), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .O(n13679)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd0d0 */ ; + defparam LUT__20106.LUTMASK = 16'hd0d0; + EFX_LUT4 LUT__20107 (.I0(\ddr3_ctl_axi/cal_shift_val[0] ), .I1(\ddr3_ctl_axi/cal_shift_val[1] ), + .I2(\ddr3_ctl_axi/cal_shift_val[2] ), .O(n13680)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__20107.LUTMASK = 16'h4040; + EFX_LUT4 LUT__20108 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31] ), + .O(n13681)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20108.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20109 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30] ), + .O(n13682)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20109.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20110 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14] ), + .O(n13683)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20110.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20111 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4] ), + .O(n13684)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20111.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20112 (.I0(n13681), .I1(n13682), .I2(n13683), .I3(n13684), + .O(n13685)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20112.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20113 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26] ), + .O(n13686)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20113.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20114 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22] ), + .O(n13687)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20114.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20115 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12] ), + .O(n13688)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__20115.LUTMASK = 16'h0100; + EFX_LUT4 LUT__20116 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13] ), + .I2(n13688), .O(n13689)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__20116.LUTMASK = 16'h1010; + EFX_LUT4 LUT__20117 (.I0(n13685), .I1(n13686), .I2(n13687), .I3(n13689), + .O(n13690)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20117.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20118 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18] ), + .I3(n13690), .O(n13691)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__20118.LUTMASK = 16'h0100; + EFX_LUT4 LUT__20119 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I2(n13680), .I3(n13691), .O(n13692)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20119.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20120 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .O(n13693)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20120.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20121 (.I0(n13692), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I3(n13693), .O(n13694)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f4 */ ; + defparam LUT__20121.LUTMASK = 16'h00f4; + EFX_LUT4 LUT__20122 (.I0(n13694), .I1(n13679), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2698 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc5c5 */ ; + defparam LUT__20122.LUTMASK = 16'hc5c5; + EFX_LUT4 LUT__20123 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5] ), + .O(n13695)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20123.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20124 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0] ), + .O(n13696)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20124.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20125 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11] ), + .I3(n13696), .O(n13697)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20125.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20126 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1] ), + .I2(n13695), .I3(n13697), .O(n13698)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20126.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20127 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24] ), + .O(n13699)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20127.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20128 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28] ), + .O(n13700)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20128.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20129 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22] ), + .O(n13701)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20129.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20130 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20] ), + .O(n13702)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20130.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20131 (.I0(n13699), .I1(n13700), .I2(n13701), .I3(n13702), + .O(n13703)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20131.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20132 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[29] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[30] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[31] ), + .I3(n13703), .O(n13704)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__20132.LUTMASK = 16'h0100; + EFX_LUT4 LUT__20133 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12] ), + .I1(n13698), .I2(n13704), .O(n13705)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__20133.LUTMASK = 16'h1010; + EFX_LUT4 LUT__20134 (.I0(n13705), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_busy ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .O(n13706)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0a0c */ ; + defparam LUT__20134.LUTMASK = 16'h0a0c; + EFX_LUT4 LUT__20135 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23] ), + .O(n13707)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20135.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20136 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20] ), + .O(n13708)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20136.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20137 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31] ), + .O(n13709)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20137.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20138 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28] ), + .O(n13710)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20138.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20139 (.I0(n13707), .I1(n13708), .I2(n13709), .I3(n13710), + .O(n13711)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20139.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20140 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15] ), + .O(n13712)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20140.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20141 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3] ), + .O(n13713)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20141.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20142 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12] ), + .O(n13714)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__20142.LUTMASK = 16'h0100; + EFX_LUT4 LUT__20143 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11] ), + .O(n13715)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20143.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20144 (.I0(n13712), .I1(n13713), .I2(n13714), .I3(n13715), + .O(n13716)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20144.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20145 (.I0(n13711), .I1(n13716), .O(n13717)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20145.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20146 (.I0(n13717), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .O(n13718)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfacf */ ; + defparam LUT__20146.LUTMASK = 16'hfacf; + EFX_LUT4 LUT__20147 (.I0(n13718), .I1(n13706), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(ceg_net4213)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c05 */ ; + defparam LUT__20147.LUTMASK = 16'h0c05; + EFX_LUT4 LUT__20148 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] ), + .I1(n13431), .I2(n13705), .O(n13719)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__20148.LUTMASK = 16'h6060; + EFX_LUT4 LUT__20149 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] ), + .I2(n13719), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(n13720)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0fbb */ ; + defparam LUT__20149.LUTMASK = 16'h0fbb; + EFX_LUT4 LUT__20150 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I1(n13677), .O(n13721)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20150.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20151 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] ), + .I1(n13415), .I2(n13721), .O(n13722)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__20151.LUTMASK = 16'h6060; + EFX_LUT4 LUT__20152 (.I0(n13720), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I2(n13722), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7743 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf1f1 */ ; + defparam LUT__20152.LUTMASK = 16'hf1f1; + EFX_LUT4 LUT__20153 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .O(n13723)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__20153.LUTMASK = 16'h4040; + EFX_LUT4 LUT__20154 (.I0(n13693), .I1(n13723), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .O(ceg_net3077)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf1f1 */ ; + defparam LUT__20154.LUTMASK = 16'hf1f1; + EFX_LUT4 LUT__20155 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .I2(n13691), .O(n13724)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__20155.LUTMASK = 16'h4040; + EFX_LUT4 LUT__20156 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I1(n13724), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20156.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20157 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8147 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20157.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20158 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_start ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_start_p0 ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8147 ), + .O(ceg_net879)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__20158.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__20159 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1742 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20159.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20160 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I2(n13431), .I3(n13693), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9160 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20160.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20161 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I1(n13705), .O(n13725)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20161.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20162 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0] ), + .I1(n1250), .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7719 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20162.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20163 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .O(n13726)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__20163.LUTMASK = 16'h1010; + EFX_LUT4 LUT__20164 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I1(n13717), .I2(n13726), .O(n13727)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__20164.LUTMASK = 16'h4040; + EFX_LUT4 LUT__20165 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .I1(n13727), .O(n13728)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20165.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20166 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I1(n13693), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I3(n13728), .O(ceg_net3886)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbf00 */ ; + defparam LUT__20166.LUTMASK = 16'hbf00; + EFX_LUT4 LUT__20167 (.I0(n13705), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9160 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n3461 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20167.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20168 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I1(n13415), .I2(n13677), .I3(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n3529 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20168.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20169 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run ), + .I1(n13476), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2838 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__20169.LUTMASK = 16'h7800; + EFX_LUT4 LUT__20170 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run ), + .I3(n13693), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8304 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__20170.LUTMASK = 16'h1000; + EFX_LUT4 LUT__20171 (.I0(n13727), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8304 ), + .O(n13729)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20171.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20172 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2896 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__20172.LUTMASK = 16'h6060; + EFX_LUT4 LUT__20173 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I1(n13726), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8144 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__20173.LUTMASK = 16'h7777; + EFX_LUT4 LUT__20174 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2863 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__20174.LUTMASK = 16'h6060; + EFX_LUT4 LUT__20175 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13730)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20175.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20176 (.I0(\w_ddr3_rdata[109] ), .I1(\w_ddr3_rdata[88] ), + .I2(n13730), .O(n13731)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__20176.LUTMASK = 16'h4040; + EFX_LUT4 LUT__20177 (.I0(\w_ddr3_rdata[88] ), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I2(\w_ddr3_rdata[44] ), .O(n13732)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3d3d */ ; + defparam LUT__20177.LUTMASK = 16'h3d3d; + EFX_LUT4 LUT__20178 (.I0(n13732), .I1(\w_ddr3_rdata[88] ), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .I3(\w_ddr3_rdata[109] ), .O(n13733)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1004 */ ; + defparam LUT__20178.LUTMASK = 16'h1004; + EFX_LUT4 LUT__20179 (.I0(\w_ddr3_rdata[44] ), .I1(n13731), .I2(n13733), + .I3(\w_ddr3_rdata[114] ), .O(n13734)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbb0f */ ; + defparam LUT__20179.LUTMASK = 16'hbb0f; + EFX_LUT4 LUT__20180 (.I0(\w_ddr3_rdata[78] ), .I1(\w_ddr3_rdata[24] ), + .I2(\w_ddr3_rdata[23] ), .I3(\w_ddr3_rdata[86] ), .O(n13735)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20180.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20181 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[24] ), .I2(\w_ddr3_rdata[78] ), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13736)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hdff3 */ ; + defparam LUT__20181.LUTMASK = 16'hdff3; + EFX_LUT4 LUT__20182 (.I0(\w_ddr3_rdata[23] ), .I1(\w_ddr3_rdata[86] ), + .I2(n13736), .O(n13737)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__20182.LUTMASK = 16'h0101; + EFX_LUT4 LUT__20183 (.I0(n13735), .I1(n13737), .I2(\w_ddr3_rdata[55] ), + .I3(n13730), .O(n13738)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1ff3 */ ; + defparam LUT__20183.LUTMASK = 16'h1ff3; + EFX_LUT4 LUT__20184 (.I0(\w_ddr3_rdata[97] ), .I1(\w_ddr3_rdata[106] ), + .I2(n13730), .O(n13739)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__20184.LUTMASK = 16'h1010; + EFX_LUT4 LUT__20185 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[97] ), .I2(\w_ddr3_rdata[106] ), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13740)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7ffc */ ; + defparam LUT__20185.LUTMASK = 16'h7ffc; + EFX_LUT4 LUT__20186 (.I0(n13740), .I1(n13739), .I2(\w_ddr3_rdata[92] ), + .I3(\w_ddr3_rdata[95] ), .O(n13741)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3ffa */ ; + defparam LUT__20186.LUTMASK = 16'h3ffa; + EFX_LUT4 LUT__20187 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[83] ), .I2(\w_ddr3_rdata[119] ), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13742)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbffc */ ; + defparam LUT__20187.LUTMASK = 16'hbffc; + EFX_LUT4 LUT__20188 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13743)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20188.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20189 (.I0(\w_ddr3_rdata[83] ), .I1(\w_ddr3_rdata[119] ), + .I2(n13743), .O(n13744)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__20189.LUTMASK = 16'h1010; + EFX_LUT4 LUT__20190 (.I0(n13744), .I1(n13742), .I2(\w_ddr3_rdata[81] ), + .I3(\w_ddr3_rdata[120] ), .O(n13745)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcff5 */ ; + defparam LUT__20190.LUTMASK = 16'hcff5; + EFX_LUT4 LUT__20191 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[53] ), .I2(\w_ddr3_rdata[58] ), .I3(\w_ddr3_rdata[61] ), + .O(n13746)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbffd */ ; + defparam LUT__20191.LUTMASK = 16'hbffd; + EFX_LUT4 LUT__20192 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[22] ), .I2(\w_ddr3_rdata[89] ), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13747)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbffc */ ; + defparam LUT__20192.LUTMASK = 16'hbffc; + EFX_LUT4 LUT__20193 (.I0(\w_ddr3_rdata[22] ), .I1(\w_ddr3_rdata[89] ), + .I2(n13743), .O(n13748)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__20193.LUTMASK = 16'h1010; + EFX_LUT4 LUT__20194 (.I0(n13748), .I1(n13747), .I2(\w_ddr3_rdata[20] ), + .I3(\w_ddr3_rdata[79] ), .O(n13749)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf5cf */ ; + defparam LUT__20194.LUTMASK = 16'hf5cf; + EFX_LUT4 LUT__20195 (.I0(\w_ddr3_rdata[28] ), .I1(\w_ddr3_rdata[37] ), + .I2(\w_ddr3_rdata[41] ), .I3(\w_ddr3_rdata[42] ), .O(n13750)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbffd */ ; + defparam LUT__20195.LUTMASK = 16'hbffd; + EFX_LUT4 LUT__20196 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13751)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20196.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20197 (.I0(n13750), .I1(\w_ddr3_rdata[52] ), .I2(\w_ddr3_rdata[28] ), + .I3(n13751), .O(n13752)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4001 */ ; + defparam LUT__20197.LUTMASK = 16'h4001; + EFX_LUT4 LUT__20198 (.I0(\w_ddr3_rdata[64] ), .I1(\w_ddr3_rdata[70] ), + .I2(\w_ddr3_rdata[71] ), .I3(\w_ddr3_rdata[75] ), .O(n13753)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7ffe */ ; + defparam LUT__20198.LUTMASK = 16'h7ffe; + EFX_LUT4 LUT__20199 (.I0(\w_ddr3_rdata[55] ), .I1(\w_ddr3_rdata[60] ), + .I2(\w_ddr3_rdata[62] ), .I3(\w_ddr3_rdata[63] ), .O(n13754)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7ffe */ ; + defparam LUT__20199.LUTMASK = 16'h7ffe; + EFX_LUT4 LUT__20200 (.I0(\w_ddr3_rdata[64] ), .I1(\w_ddr3_rdata[99] ), + .I2(\w_ddr3_rdata[39] ), .I3(\w_ddr3_rdata[46] ), .O(n13755)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7ffe */ ; + defparam LUT__20200.LUTMASK = 16'h7ffe; + EFX_LUT4 LUT__20201 (.I0(n13755), .I1(\w_ddr3_rdata[96] ), .I2(\w_ddr3_rdata[64] ), + .I3(n13743), .O(n13756)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4001 */ ; + defparam LUT__20201.LUTMASK = 16'h4001; + EFX_LUT4 LUT__20202 (.I0(n13753), .I1(n13754), .I2(n13752), .I3(n13756), + .O(n13757)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__20202.LUTMASK = 16'h1000; + EFX_LUT4 LUT__20203 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[105] ), .I2(\w_ddr3_rdata[116] ), .I3(\w_ddr3_rdata[122] ), + .O(n13758)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heff7 */ ; + defparam LUT__20203.LUTMASK = 16'heff7; + EFX_LUT4 LUT__20204 (.I0(n13758), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I2(\w_ddr3_rdata[50] ), .I3(\w_ddr3_rdata[21] ), .O(n13759)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1004 */ ; + defparam LUT__20204.LUTMASK = 16'h1004; + EFX_LUT4 LUT__20205 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[67] ), .I2(\w_ddr3_rdata[85] ), .I3(\w_ddr3_rdata[115] ), + .O(n13760)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heff7 */ ; + defparam LUT__20205.LUTMASK = 16'heff7; + EFX_LUT4 LUT__20206 (.I0(n13760), .I1(n13759), .O(n13761)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20206.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20207 (.I0(n13746), .I1(n13749), .I2(n13757), .I3(n13761), + .O(n13762)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__20207.LUTMASK = 16'h1000; + EFX_LUT4 LUT__20208 (.I0(n13738), .I1(n13741), .I2(n13745), .I3(n13762), + .O(n13763)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__20208.LUTMASK = 16'h0100; + EFX_LUT4 LUT__20209 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .I2(\w_ddr3_rdata[51] ), .I3(\w_ddr3_rdata[30] ), .O(n13764)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbff4 */ ; + defparam LUT__20209.LUTMASK = 16'hbff4; + EFX_LUT4 LUT__20210 (.I0(n13764), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I2(\w_ddr3_rdata[2] ), .I3(\w_ddr3_rdata[36] ), .O(n13765)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4001 */ ; + defparam LUT__20210.LUTMASK = 16'h4001; + EFX_LUT4 LUT__20211 (.I0(\w_ddr3_rdata[38] ), .I1(\w_ddr3_rdata[47] ), + .I2(n13730), .O(n13766)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__20211.LUTMASK = 16'h1010; + EFX_LUT4 LUT__20212 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[38] ), .I2(\w_ddr3_rdata[47] ), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13767)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7ffc */ ; + defparam LUT__20212.LUTMASK = 16'h7ffc; + EFX_LUT4 LUT__20213 (.I0(n13767), .I1(n13766), .I2(\w_ddr3_rdata[126] ), + .I3(\w_ddr3_rdata[127] ), .O(n13768)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3ffa */ ; + defparam LUT__20213.LUTMASK = 16'h3ffa; + EFX_LUT4 LUT__20214 (.I0(\w_ddr3_rdata[112] ), .I1(\w_ddr3_rdata[104] ), + .I2(n13743), .O(n13769)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__20214.LUTMASK = 16'h4040; + EFX_LUT4 LUT__20215 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[104] ), .I2(\w_ddr3_rdata[112] ), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13770)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heff3 */ ; + defparam LUT__20215.LUTMASK = 16'heff3; + EFX_LUT4 LUT__20216 (.I0(n13770), .I1(n13769), .I2(\w_ddr3_rdata[0] ), + .I3(\w_ddr3_rdata[14] ), .O(n13771)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3ffa */ ; + defparam LUT__20216.LUTMASK = 16'h3ffa; + EFX_LUT4 LUT__20217 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .I2(\w_ddr3_rdata[4] ), .I3(\w_ddr3_rdata[1] ), .O(n13772)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4ffb */ ; + defparam LUT__20217.LUTMASK = 16'h4ffb; + EFX_LUT4 LUT__20218 (.I0(n13772), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I2(\w_ddr3_rdata[98] ), .I3(\w_ddr3_rdata[33] ), .O(n13773)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4001 */ ; + defparam LUT__20218.LUTMASK = 16'h4001; + EFX_LUT4 LUT__20219 (.I0(\w_ddr3_rdata[6] ), .I1(\w_ddr3_rdata[103] ), + .I2(\w_ddr3_rdata[34] ), .I3(\w_ddr3_rdata[43] ), .O(n13774)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7ffe */ ; + defparam LUT__20219.LUTMASK = 16'h7ffe; + EFX_LUT4 LUT__20220 (.I0(n13774), .I1(\w_ddr3_rdata[15] ), .I2(\w_ddr3_rdata[6] ), + .I3(n13743), .O(n13775)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4001 */ ; + defparam LUT__20220.LUTMASK = 16'h4001; + EFX_LUT4 LUT__20221 (.I0(\w_ddr3_rdata[6] ), .I1(\w_ddr3_rdata[76] ), + .I2(\w_ddr3_rdata[100] ), .I3(\w_ddr3_rdata[102] ), .O(n13776)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7ffe */ ; + defparam LUT__20221.LUTMASK = 16'h7ffe; + EFX_LUT4 LUT__20222 (.I0(n13776), .I1(n13775), .O(n13777)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20222.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20223 (.I0(\w_ddr3_rdata[16] ), .I1(\w_ddr3_rdata[91] ), + .I2(\w_ddr3_rdata[117] ), .I3(\w_ddr3_rdata[118] ), .O(n13778)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7ffe */ ; + defparam LUT__20223.LUTMASK = 16'h7ffe; + EFX_LUT4 LUT__20224 (.I0(n13778), .I1(\w_ddr3_rdata[17] ), .I2(\w_ddr3_rdata[16] ), + .I3(n13730), .O(n13779)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4001 */ ; + defparam LUT__20224.LUTMASK = 16'h4001; + EFX_LUT4 LUT__20225 (.I0(\w_ddr3_rdata[16] ), .I1(\w_ddr3_rdata[19] ), + .I2(\w_ddr3_rdata[31] ), .I3(\w_ddr3_rdata[73] ), .O(n13780)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfe7f */ ; + defparam LUT__20225.LUTMASK = 16'hfe7f; + EFX_LUT4 LUT__20226 (.I0(n13780), .I1(n13779), .O(n13781)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20226.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20227 (.I0(n13771), .I1(n13773), .I2(n13777), .I3(n13781), + .O(n13782)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20227.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20228 (.I0(\w_ddr3_rdata[32] ), .I1(\w_ddr3_rdata[56] ), + .I2(\w_ddr3_rdata[57] ), .I3(\w_ddr3_rdata[26] ), .O(n13783)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20228.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20229 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[56] ), .I2(\w_ddr3_rdata[32] ), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13784)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hdff3 */ ; + defparam LUT__20229.LUTMASK = 16'hdff3; + EFX_LUT4 LUT__20230 (.I0(\w_ddr3_rdata[26] ), .I1(\w_ddr3_rdata[57] ), + .I2(n13784), .O(n13785)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__20230.LUTMASK = 16'h0101; + EFX_LUT4 LUT__20231 (.I0(\w_ddr3_rdata[48] ), .I1(\w_ddr3_rdata[40] ), + .I2(n13743), .O(n13786)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__20231.LUTMASK = 16'h4040; + EFX_LUT4 LUT__20232 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[40] ), .I2(\w_ddr3_rdata[48] ), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13787)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heff3 */ ; + defparam LUT__20232.LUTMASK = 16'heff3; + EFX_LUT4 LUT__20233 (.I0(n13787), .I1(n13786), .I2(\w_ddr3_rdata[9] ), + .I3(\w_ddr3_rdata[11] ), .O(n13788)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3ffa */ ; + defparam LUT__20233.LUTMASK = 16'h3ffa; + EFX_LUT4 LUT__20234 (.I0(n13730), .I1(n13783), .I2(n13785), .I3(n13788), + .O(n13789)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f8 */ ; + defparam LUT__20234.LUTMASK = 16'h00f8; + EFX_LUT4 LUT__20235 (.I0(n13768), .I1(n13765), .I2(n13782), .I3(n13789), + .O(n13790)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20235.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20236 (.I0(\w_ddr3_rdata[69] ), .I1(\w_ddr3_rdata[111] ), + .I2(\w_ddr3_rdata[90] ), .I3(n13730), .O(n13791)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__20236.LUTMASK = 16'h1000; + EFX_LUT4 LUT__20237 (.I0(\w_ddr3_rdata[111] ), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I3(\w_ddr3_rdata[69] ), .O(n13792)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7eef */ ; + defparam LUT__20237.LUTMASK = 16'h7eef; + EFX_LUT4 LUT__20238 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(n13792), .I2(\w_ddr3_rdata[69] ), .I3(\w_ddr3_rdata[90] ), + .O(n13793)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0230 */ ; + defparam LUT__20238.LUTMASK = 16'h0230; + EFX_LUT4 LUT__20239 (.I0(\w_ddr3_rdata[68] ), .I1(\w_ddr3_rdata[35] ), + .I2(\w_ddr3_rdata[18] ), .O(n13794)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__20239.LUTMASK = 16'h1010; + EFX_LUT4 LUT__20240 (.I0(\w_ddr3_rdata[18] ), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I3(\w_ddr3_rdata[35] ), .O(n13795)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbedf */ ; + defparam LUT__20240.LUTMASK = 16'hbedf; + EFX_LUT4 LUT__20241 (.I0(n13795), .I1(\w_ddr3_rdata[18] ), .I2(\w_ddr3_rdata[68] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .O(n13796)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1401 */ ; + defparam LUT__20241.LUTMASK = 16'h1401; + EFX_LUT4 LUT__20242 (.I0(n13730), .I1(n13794), .I2(n13796), .I3(\w_ddr3_rdata[72] ), + .O(n13797)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0f77 */ ; + defparam LUT__20242.LUTMASK = 16'h0f77; + EFX_LUT4 LUT__20243 (.I0(n13793), .I1(n13791), .I2(n13797), .I3(\w_ddr3_rdata[94] ), + .O(n13798)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c0a */ ; + defparam LUT__20243.LUTMASK = 16'h0c0a; + EFX_LUT4 LUT__20244 (.I0(\w_ddr3_rdata[77] ), .I1(\w_ddr3_rdata[101] ), + .I2(\w_ddr3_rdata[107] ), .I3(\w_ddr3_rdata[113] ), .O(n13799)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfe7f */ ; + defparam LUT__20244.LUTMASK = 16'hfe7f; + EFX_LUT4 LUT__20245 (.I0(n13799), .I1(\w_ddr3_rdata[77] ), .I2(n13751), + .O(n13800)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1414 */ ; + defparam LUT__20245.LUTMASK = 16'h1414; + EFX_LUT4 LUT__20246 (.I0(\w_ddr3_rdata[54] ), .I1(\w_ddr3_rdata[80] ), + .I2(\w_ddr3_rdata[87] ), .I3(n13730), .O(n13801)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7ffe */ ; + defparam LUT__20246.LUTMASK = 16'h7ffe; + EFX_LUT4 LUT__20247 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[66] ), .I2(\w_ddr3_rdata[84] ), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .O(n13802)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he7f9 */ ; + defparam LUT__20247.LUTMASK = 16'he7f9; + EFX_LUT4 LUT__20248 (.I0(\w_ddr3_rdata[3] ), .I1(\w_ddr3_rdata[7] ), + .I2(\w_ddr3_rdata[65] ), .I3(\w_ddr3_rdata[110] ), .O(n13803)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7ffe */ ; + defparam LUT__20248.LUTMASK = 16'h7ffe; + EFX_LUT4 LUT__20249 (.I0(n13803), .I1(\w_ddr3_rdata[3] ), .I2(n13743), + .O(n13804)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4141 */ ; + defparam LUT__20249.LUTMASK = 16'h4141; + EFX_LUT4 LUT__20250 (.I0(\w_ddr3_rdata[8] ), .I1(\w_ddr3_rdata[12] ), + .I2(\w_ddr3_rdata[123] ), .I3(\w_ddr3_rdata[125] ), .O(n13805)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heff7 */ ; + defparam LUT__20250.LUTMASK = 16'heff7; + EFX_LUT4 LUT__20251 (.I0(n13805), .I1(\w_ddr3_rdata[8] ), .I2(n13730), + .I3(n13804), .O(n13806)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1400 */ ; + defparam LUT__20251.LUTMASK = 16'h1400; + EFX_LUT4 LUT__20252 (.I0(n13801), .I1(n13802), .I2(n13800), .I3(n13806), + .O(n13807)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__20252.LUTMASK = 16'h1000; + EFX_LUT4 LUT__20253 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[74] ), .I2(\w_ddr3_rdata[29] ), .I3(\w_ddr3_rdata[93] ), + .O(n13808)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heff7 */ ; + defparam LUT__20253.LUTMASK = 16'heff7; + EFX_LUT4 LUT__20254 (.I0(n13808), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I2(\w_ddr3_rdata[27] ), .O(n13809)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1414 */ ; + defparam LUT__20254.LUTMASK = 16'h1414; + EFX_LUT4 LUT__20255 (.I0(\w_ddr3_rdata[13] ), .I1(\w_ddr3_rdata[108] ), + .I2(\w_ddr3_rdata[82] ), .I3(\w_ddr3_rdata[59] ), .O(n13810)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heff7 */ ; + defparam LUT__20255.LUTMASK = 16'heff7; + EFX_LUT4 LUT__20256 (.I0(n13810), .I1(\w_ddr3_rdata[13] ), .I2(n13751), + .I3(n13809), .O(n13811)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1400 */ ; + defparam LUT__20256.LUTMASK = 16'h1400; + EFX_LUT4 LUT__20257 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\w_ddr3_rdata[49] ), .I2(\w_ddr3_rdata[121] ), .I3(\w_ddr3_rdata[124] ), + .O(n13812)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbffd */ ; + defparam LUT__20257.LUTMASK = 16'hbffd; + EFX_LUT4 LUT__20258 (.I0(\w_ddr3_rdata[25] ), .I1(n13751), .I2(\w_ddr3_rdata[45] ), + .I3(\w_ddr3_rdata[5] ), .O(n13813)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heff7 */ ; + defparam LUT__20258.LUTMASK = 16'heff7; + EFX_LUT4 LUT__20259 (.I0(n13812), .I1(n13813), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I3(\w_ddr3_rdata[10] ), .O(n13814)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1001 */ ; + defparam LUT__20259.LUTMASK = 16'h1001; + EFX_LUT4 LUT__20260 (.I0(n13798), .I1(n13807), .I2(n13811), .I3(n13814), + .O(n13815)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20260.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20261 (.I0(n13734), .I1(n13763), .I2(n13790), .I3(n13815), + .O(n13816)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20261.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20262 (.I0(n13816), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_read ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8304 ), + .O(ceg_net886)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00bf */ ; + defparam LUT__20262.LUTMASK = 16'h00bf; + EFX_LUT4 LUT__20263 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7076 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfffe */ ; + defparam LUT__20263.LUTMASK = 16'hfffe; + EFX_LUT4 LUT__20264 (.I0(\ddr3_ctl_axi/cal_shift_val[0] ), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail ), + .O(n13817)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20264.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20265 (.I0(\ddr3_ctl_axi/cal_shift_val[1] ), .I1(\ddr3_ctl_axi/cal_shift_val[2] ), + .I2(n13817), .I3(\ddr3_ctl_axi/cal_fail_log[0] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2398 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff10 */ ; + defparam LUT__20265.LUTMASK = 16'hff10; + EFX_LUT4 LUT__20266 (.I0(\ddr3_ctl_axi/cal_fail_log[5] ), .I1(\ddr3_ctl_axi/cal_fail_log[4] ), + .O(n13818)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20266.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20267 (.I0(n13818), .I1(\ddr3_ctl_axi/cal_fail_log[3] ), + .I2(\ddr3_ctl_axi/cal_fail_log[2] ), .O(n13819)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb0b0 */ ; + defparam LUT__20267.LUTMASK = 16'hb0b0; + EFX_LUT4 LUT__20268 (.I0(n13819), .I1(\ddr3_ctl_axi/cal_fail_log[1] ), + .I2(\ddr3_ctl_axi/cal_fail_log[0] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2589 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb0b0 */ ; + defparam LUT__20268.LUTMASK = 16'hb0b0; + EFX_LUT4 LUT__20269 (.I0(\ddr3_ctl_axi/cal_fail_log[4] ), .I1(\ddr3_ctl_axi/cal_fail_log[5] ), + .O(n13820)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20269.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20270 (.I0(\ddr3_ctl_axi/cal_fail_log[6] ), .I1(n13820), + .O(ceg_net2135)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20270.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20271 (.I0(\ddr3_ctl_axi/cal_fail_log[0] ), .I1(\ddr3_ctl_axi/cal_fail_log[1] ), + .I2(\ddr3_ctl_axi/cal_fail_log[2] ), .I3(\ddr3_ctl_axi/cal_fail_log[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5447 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__20271.LUTMASK = 16'h8000; + EFX_LUT4 LUT__20272 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .O(n13821)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__20272.LUTMASK = 16'h1000; + EFX_LUT4 LUT__20273 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5447 ), + .I1(ceg_net2135), .I2(n13821), .O(ceg_net894)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__20273.LUTMASK = 16'h7070; + EFX_LUT4 LUT__20274 (.I0(\ddr3_ctl_axi/cal_fail_log[5] ), .I1(\ddr3_ctl_axi/cal_fail_log[6] ), + .I2(\ddr3_ctl_axi/cal_fail_log[1] ), .I3(\ddr3_ctl_axi/cal_fail_log[2] ), + .O(n13822)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb0bb */ ; + defparam LUT__20274.LUTMASK = 16'hb0bb; + EFX_LUT4 LUT__20275 (.I0(\ddr3_ctl_axi/cal_fail_log[5] ), .I1(\ddr3_ctl_axi/cal_fail_log[3] ), + .I2(n13822), .I3(\ddr3_ctl_axi/cal_fail_log[4] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2631 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3f05 */ ; + defparam LUT__20275.LUTMASK = 16'h3f05; + EFX_LUT4 LUT__20276 (.I0(\ddr3_ctl_axi/cal_fail_log[6] ), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2631 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2554 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20276.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20277 (.I0(\ddr3_ctl_axi/cal_fail_log[6] ), .I1(\ddr3_ctl_axi/cal_fail_log[4] ), + .I2(\ddr3_ctl_axi/cal_fail_log[5] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5457 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3a3a */ ; + defparam LUT__20277.LUTMASK = 16'h3a3a; + EFX_LUT4 LUT__20278 (.I0(\ddr3_ctl_axi/cal_fail_log[2] ), .I1(\ddr3_ctl_axi/cal_fail_log[0] ), + .I2(\ddr3_ctl_axi/cal_fail_log[1] ), .O(n13823)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3a3a */ ; + defparam LUT__20278.LUTMASK = 16'h3a3a; + EFX_LUT4 LUT__20279 (.I0(\ddr3_ctl_axi/cal_fail_log[4] ), .I1(\ddr3_ctl_axi/cal_fail_log[2] ), + .I2(\ddr3_ctl_axi/cal_fail_log[3] ), .O(n13824)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3a3a */ ; + defparam LUT__20279.LUTMASK = 16'h3a3a; + EFX_LUT4 LUT__20280 (.I0(n13823), .I1(n13824), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5457 ), + .I3(n13821), .O(ceg_net917)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfe00 */ ; + defparam LUT__20280.LUTMASK = 16'hfe00; + EFX_LUT4 LUT__20281 (.I0(\ddr3_ctl_axi/cal_fail_log[0] ), .I1(n13818), + .I2(\ddr3_ctl_axi/cal_fail_log[1] ), .I3(n13819), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2673 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff0e */ ; + defparam LUT__20281.LUTMASK = 16'hff0e; + EFX_LUT4 LUT__20282 (.I0(\ddr3_ctl_axi/cal_fail_log[3] ), .I1(\ddr3_ctl_axi/cal_fail_log[0] ), + .I2(\ddr3_ctl_axi/cal_fail_log[2] ), .I3(\ddr3_ctl_axi/cal_fail_log[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5469 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5fdc */ ; + defparam LUT__20282.LUTMASK = 16'h5fdc; + EFX_LUT4 LUT__20283 (.I0(\ddr3_ctl_axi/cal_fail_log[6] ), .I1(\ddr3_ctl_axi/cal_fail_log[3] ), + .I2(\ddr3_ctl_axi/cal_fail_log[4] ), .I3(\ddr3_ctl_axi/cal_fail_log[5] ), + .O(n13825)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5dfc */ ; + defparam LUT__20283.LUTMASK = 16'h5dfc; + EFX_LUT4 LUT__20284 (.I0(n13825), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5469 ), + .I2(n13821), .O(ceg_net930)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__20284.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__20285 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7690 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'haa3c */ ; + defparam LUT__20285.LUTMASK = 16'haa3c; + EFX_LUT4 LUT__20286 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I1(n13693), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8321 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20286.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20287 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7686 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'haa3c */ ; + defparam LUT__20287.LUTMASK = 16'haa3c; + EFX_LUT4 LUT__20288 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I1(n13723), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2839 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf4f4 */ ; + defparam LUT__20288.LUTMASK = 16'hf4f4; + EFX_LUT4 LUT__20289 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[5] ), + .O(n13826)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20289.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20290 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[1] ), + .O(n13827)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20290.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20291 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[2] ), + .O(n13828)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20291.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20292 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtrGray[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushToPopGray_buffercc_io_dataOut[6] ), + .O(n13829)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20292.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20293 (.I0(n13826), .I1(n13827), .I2(n13828), .I3(n13829), + .O(n13830)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20293.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20294 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_addr_re ), + .I3(n13830), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f4 */ ; + defparam LUT__20294.LUTMASK = 16'h00f4; + EFX_LUT4 LUT__20295 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20295.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20296 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20296.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20297 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n482 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20297.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20298 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n482 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20298.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20299 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2] ), + .O(n13831)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20299.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20300 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .I1(n13831), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20300.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20301 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3] ), + .I1(n13831), .O(n13832)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20301.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20302 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .I1(n13832), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20302.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20303 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4] ), + .I1(n13832), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n497 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20303.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20304 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n497 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n212 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_8[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20304.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20305 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20305.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20306 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20306.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20307 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20307.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20308 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[16] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[16] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20308.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20309 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[17] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[17] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20309.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20310 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[18] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[18] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20310.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20311 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[19] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[19] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20311.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20312 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[20] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[20] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20312.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20313 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[21] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[21] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20313.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20314 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[22] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[22] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20314.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20315 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[23] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[23] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20315.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20316 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[24] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[24] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20316.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20317 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[25] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[25] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20317.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20318 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[26] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[26] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20318.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20319 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[27] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[27] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20319.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20320 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[28] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[28] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20320.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20321 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[1] ), + .O(n13833)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20321.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20322 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[4] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[4] ), + .O(n13834)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20322.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20323 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[6] ), + .O(n13835)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1428 */ ; + defparam LUT__20323.LUTMASK = 16'h1428; + EFX_LUT4 LUT__20324 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtrGray[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popToPushGray_buffercc_io_dataOut[2] ), + .O(n13836)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20324.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20325 (.I0(n13833), .I1(n13834), .I2(n13835), .I3(n13836), + .O(n13837)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20325.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20326 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_en ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_en ), + .I2(n13837), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/_zz_16 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c0a */ ; + defparam LUT__20326.LUTMASK = 16'h0c0a; + EFX_LUT4 LUT__20327 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[30] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n735 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20327.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20328 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[24] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[50] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n714 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20328.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20329 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[23] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[49] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n715 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20329.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20330 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[22] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[48] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n716 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20330.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20331 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[21] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[47] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n717 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20331.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20332 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[20] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[46] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n718 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20332.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20333 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[27] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n739 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20333.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20334 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[26] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n740 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20334.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20335 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[25] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[51] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n713 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20335.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20336 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6] ), + .O(n12862)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__20336.LUTMASK = 16'h9999; + EFX_LUT4 LUT__20337 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4] ), + .I1(n12862), .O(n12865)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20337.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20338 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3] ), + .I1(n12865), .O(n12868)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20338.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20339 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2] ), + .I1(n12868), .O(n12871)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20339.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20340 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1] ), + .I1(n12871), .O(n8436)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20340.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20341 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0] ), + .I1(n8436), .O(n8360)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20341.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20342 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n442 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20342.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20343 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[1] ), + .O(n13838)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20343.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20344 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2] ), + .I1(n13838), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n447 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20344.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20345 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2] ), + .I1(n13838), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n452 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20345.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20346 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3] ), + .I2(n13838), .O(n13839)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20346.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20347 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4] ), + .I1(n13839), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n457 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20347.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20348 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4] ), + .I1(n13839), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n462 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20348.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20349 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5] ), + .I2(n13839), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n467 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20349.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20350 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20350.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20351 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20351.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20352 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20352.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20353 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20353.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20354 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20354.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20355 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20355.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20356 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20356.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20357 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20357.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20358 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20358.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20359 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20359.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20360 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20360.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20361 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20361.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20362 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_rd_addr[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_rd_addr_p[12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_rd_addr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20362.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20363 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n442 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n447 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n293 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20363.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20364 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2] ), + .I1(n13838), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n292 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20364.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20365 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[2] ), + .I1(n13838), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n291 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20365.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20366 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[4] ), + .I1(n13839), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n290 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20366.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20367 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n462 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n467 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n289 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20367.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20368 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n477 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20368.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20369 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3] ), + .I1(n13831), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n487 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20369.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20370 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4] ), + .I1(n13832), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n492 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20370.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20371 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5] ), + .I2(n13832), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n502 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20371.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20372 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n482 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n477 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n335 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20372.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20373 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n334 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20373.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20374 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[3] ), + .I1(n13831), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n333 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20374.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20375 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[4] ), + .I1(n13832), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20375.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20376 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n497 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n502 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/n331 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20376.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20377 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[5] ), + .O(n13840)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20377.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20378 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[6] ), + .O(n13841)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20378.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20379 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[1] ), + .O(n13842)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20379.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20380 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushToPopGray_buffercc_io_dataOut[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtrGray[3] ), + .O(n13843)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20380.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20381 (.I0(n13840), .I1(n13841), .I2(n13842), .I3(n13843), + .O(n13844)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20381.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20382 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_addr_re ), + .I3(n13844), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f8 */ ; + defparam LUT__20382.LUTMASK = 16'h00f8; + EFX_LUT4 LUT__20383 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20383.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20384 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20384.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20385 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n482 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20385.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20386 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n482 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20386.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20387 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2] ), + .O(n13845)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20387.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20388 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .I1(n13845), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20388.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20389 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3] ), + .I1(n13845), .O(n13846)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20389.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20390 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .I1(n13846), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20390.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20391 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4] ), + .I1(n13846), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n497 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20391.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20392 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n497 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n212 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_8[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20392.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20393 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20393.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20394 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20394.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20395 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20395.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20396 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[16] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[16] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20396.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20397 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[17] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[17] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20397.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20398 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[18] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[18] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20398.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20399 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[19] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[19] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20399.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20400 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[20] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[20] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20400.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20401 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[21] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[21] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20401.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20402 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[22] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[22] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20402.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20403 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[23] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[23] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20403.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20404 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[24] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[24] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20404.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20405 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[25] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[25] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20405.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20406 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[26] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[26] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20406.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20407 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[27] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[27] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20407.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20408 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[28] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[28] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20408.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20409 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[5] ), + .O(n13847)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0990 */ ; + defparam LUT__20409.LUTMASK = 16'h0990; + EFX_LUT4 LUT__20410 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[3] ), + .O(n13848)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20410.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20411 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[1] ), + .I2(n13848), .O(n13849)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9090 */ ; + defparam LUT__20411.LUTMASK = 16'h9090; + EFX_LUT4 LUT__20412 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popToPushGray_buffercc_io_dataOut[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6] ), + .O(n13850)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0990 */ ; + defparam LUT__20412.LUTMASK = 16'h0990; + EFX_LUT4 LUT__20413 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_en ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_en ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(n13851)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20413.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20414 (.I0(n13849), .I1(n13850), .I2(n13847), .I3(n13851), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/_zz_16 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f00 */ ; + defparam LUT__20414.LUTMASK = 16'h7f00; + EFX_LUT4 LUT__20415 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6] ), + .O(n12848)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__20415.LUTMASK = 16'h9999; + EFX_LUT4 LUT__20416 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4] ), + .I1(n12848), .O(n12851)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20416.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20417 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3] ), + .I1(n12851), .O(n12854)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20417.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20418 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2] ), + .I1(n12854), .O(n12857)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20418.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20419 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1] ), + .I1(n12857), .O(n8547)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20419.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20420 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0] ), + .I1(n8547), .O(n8472)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20420.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20421 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n442 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20421.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20422 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[1] ), + .O(n13852)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20422.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20423 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2] ), + .I1(n13852), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n447 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20423.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20424 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2] ), + .I1(n13852), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n452 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20424.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20425 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3] ), + .I2(n13852), .O(n13853)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20425.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20426 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4] ), + .I1(n13853), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n457 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20426.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20427 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4] ), + .I1(n13853), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n462 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20427.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20428 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20428.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20429 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20429.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20430 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20430.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20431 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20431.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20432 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20432.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20433 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20433.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20434 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20434.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20435 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20435.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20436 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20436.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20437 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20437.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20438 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20438.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20439 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20439.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20440 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_addr[12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_addr[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20440.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20441 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n442 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n447 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n293 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20441.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20442 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2] ), + .I1(n13852), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n292 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20442.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20443 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[2] ), + .I1(n13852), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n291 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20443.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20444 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4] ), + .I1(n13853), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n290 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20444.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20445 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtr[5] ), + .I2(n13853), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/pushCC_pushPtrGray[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n467 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20445.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20446 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n462 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n467 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n289 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20446.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20447 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n477 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20447.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20448 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3] ), + .I1(n13845), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n487 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20448.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20449 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4] ), + .I1(n13846), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n492 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20449.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20450 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5] ), + .I2(n13846), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n502 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20450.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20451 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n482 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n477 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n335 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20451.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20452 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n334 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20452.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20453 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[3] ), + .I1(n13845), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n333 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20453.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20454 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[4] ), + .I1(n13846), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20454.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20455 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n497 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n502 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/n331 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20455.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20456 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[5] ), + .O(n13854)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20456.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20457 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[2] ), + .O(n13855)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20457.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20458 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[6] ), + .O(n13856)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20458.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20459 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtrGray[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushToPopGray_buffercc_io_dataOut[3] ), + .O(n13857)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20459.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20460 (.I0(n13854), .I1(n13855), .I2(n13856), .I3(n13857), + .O(n13858)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20460.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20461 (.I0(n13858), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_fifo_rd_en ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20461.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20462 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20462.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20463 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20463.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20464 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1042 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20464.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20465 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1042 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20465.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20466 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2] ), + .O(n13859)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20466.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20467 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .I1(n13859), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20467.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20468 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3] ), + .I1(n13859), .O(n13860)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20468.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20469 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .I1(n13860), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20469.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20470 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4] ), + .I1(n13860), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1057 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20470.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20471 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1057 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n548 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_8[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20471.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20472 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[16] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20472.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20473 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[17] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20473.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20474 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[18] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20474.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20475 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[19] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20475.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20476 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[20] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20476.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20477 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[21] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20477.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20478 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[22] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20478.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20479 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[23] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20479.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20480 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[24] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20480.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20481 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[25] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20481.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20482 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[26] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20482.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20483 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[27] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20483.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20484 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[28] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20484.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20485 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[29] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20485.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20486 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[30] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20486.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20487 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[31] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20487.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20488 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[5] ), + .O(n13861)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0990 */ ; + defparam LUT__20488.LUTMASK = 16'h0990; + EFX_LUT4 LUT__20489 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[1] ), + .O(n13862)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20489.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20490 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtrGray[3] ), + .O(n13863)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20490.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20491 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popToPushGray_buffercc_io_dataOut[6] ), + .I2(n13863), .O(n13864)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__20491.LUTMASK = 16'h6060; + EFX_LUT4 LUT__20492 (.I0(n13862), .I1(n13864), .I2(n13861), .I3(n13851), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/_zz_16 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f00 */ ; + defparam LUT__20492.LUTMASK = 16'h7f00; + EFX_LUT4 LUT__20493 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6] ), + .O(n12833)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20493.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20494 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4] ), + .I1(n12833), .O(n12836)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20494.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20495 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3] ), + .I1(n12836), .O(n12839)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20495.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20496 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2] ), + .I1(n12839), .O(n12842)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20496.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20497 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1] ), + .I1(n12842), .O(n8791)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20497.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20498 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0] ), + .I1(n8791), .O(n8583)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20498.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20499 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1002 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20499.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20500 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[1] ), + .O(n13865)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20500.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20501 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] ), + .I1(n13865), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1007 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20501.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20502 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] ), + .I1(n13865), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1012 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20502.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20503 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] ), + .I2(n13865), .O(n13866)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20503.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20504 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] ), + .I1(n13866), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1017 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20504.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20505 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] ), + .I1(n13866), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1022 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20505.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20506 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] ), + .I2(n13866), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1027 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20506.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20507 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20507.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20508 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20508.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20509 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20509.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20510 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20510.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20511 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20511.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20512 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20512.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20513 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20513.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20514 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20514.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20515 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20515.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20516 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20516.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20517 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20517.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20518 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20518.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20519 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20519.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20520 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20520.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20521 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20521.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20522 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20522.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20523 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1002 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1007 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n741 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20523.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20524 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] ), + .I1(n13865), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n740 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20524.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20525 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[2] ), + .I1(n13865), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n739 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20525.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20526 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[4] ), + .I1(n13866), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n738 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20526.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20527 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1022 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1027 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n737 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20527.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20528 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1037 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20528.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20529 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3] ), + .I1(n13859), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1047 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20529.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20530 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4] ), + .I1(n13860), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1052 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20530.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20531 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5] ), + .I2(n13860), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1062 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20531.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20532 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1042 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1037 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n783 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20532.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20533 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n782 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20533.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20534 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[3] ), + .I1(n13859), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n781 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20534.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20535 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[4] ), + .I1(n13860), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n780 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20535.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20536 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1057 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n1062 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/n779 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20536.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20537 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[48] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[48] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20537.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20538 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[49] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[49] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20538.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20539 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[50] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[50] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20539.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20540 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[51] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[51] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20540.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20541 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[52] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[52] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20541.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20542 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[53] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[53] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20542.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20543 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[54] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[54] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20543.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20544 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[55] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[55] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20544.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20545 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[56] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[56] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20545.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20546 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[57] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[57] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20546.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20547 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[58] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[58] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20547.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20548 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[59] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[59] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20548.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20549 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[60] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[60] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20549.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20550 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[61] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[61] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20550.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20551 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[62] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[62] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20551.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20552 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[63] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[63] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20552.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20553 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[64] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[64] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20553.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20554 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[65] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[65] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20554.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20555 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[66] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[66] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20555.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20556 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[67] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[67] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20556.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20557 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[68] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[68] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20557.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20558 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[69] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[69] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20558.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20559 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[70] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[70] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20559.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20560 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[71] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[71] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20560.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20561 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[72] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[72] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20561.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20562 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[73] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[73] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20562.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20563 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[74] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[74] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20563.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20564 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[75] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[75] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20564.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20565 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[76] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[76] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20565.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20566 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[77] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[77] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20566.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20567 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[78] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[78] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20567.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20568 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[79] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[79] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20568.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20569 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[80] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[80] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20569.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20570 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[81] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[81] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20570.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20571 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[82] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[82] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20571.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20572 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[83] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[83] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20572.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20573 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[84] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[84] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20573.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20574 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[85] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[85] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20574.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20575 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[86] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[86] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20575.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20576 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[87] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[87] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20576.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20577 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[88] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[88] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20577.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20578 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[89] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[89] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20578.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20579 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[90] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[90] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20579.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20580 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[91] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[91] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20580.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20581 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[92] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[92] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20581.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20582 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[93] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[93] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20582.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20583 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[94] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[94] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20583.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20584 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[95] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[95] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20584.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20585 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[96] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[96] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20585.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20586 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[97] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[97] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20586.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20587 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[98] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[98] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20587.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20588 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[99] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[99] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20588.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20589 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[100] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[100] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20589.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20590 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[101] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[101] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20590.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20591 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[102] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[102] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20591.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20592 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[103] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[103] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20592.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20593 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[104] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[104] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20593.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20594 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[105] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[105] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20594.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20595 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[106] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[106] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20595.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20596 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[107] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[107] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20596.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20597 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[108] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[108] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20597.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20598 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[109] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[109] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20598.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20599 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[110] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[110] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20599.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20600 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[111] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[111] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20600.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20601 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[112] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[112] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20601.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20602 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[90] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[113] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[113] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20602.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20603 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[114] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[114] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20603.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20604 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[115] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[115] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20604.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20605 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[116] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[116] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20605.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20606 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[117] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[117] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20606.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20607 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[118] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[118] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20607.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20608 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[119] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[119] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20608.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20609 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[88] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[120] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[120] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20609.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20610 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[121] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[121] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20610.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20611 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[122] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[122] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20611.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20612 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[123] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[123] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20612.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20613 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[85] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[124] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[124] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20613.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20614 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[125] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[125] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20614.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20615 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[126] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[126] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20615.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20616 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[84] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[127] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[127] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20616.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20617 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[32] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[32] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20617.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20618 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[33] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[33] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20618.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20619 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[34] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[34] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20619.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20620 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[35] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[35] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20620.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20621 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[36] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[36] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20621.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20622 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[37] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[37] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20622.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20623 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[38] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[38] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20623.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20624 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[39] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[39] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20624.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20625 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[40] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[40] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20625.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20626 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[41] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[41] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20626.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20627 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[42] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[42] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20627.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20628 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[43] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[43] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20628.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20629 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[44] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[44] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20629.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20630 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[45] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[45] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20630.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20631 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[46] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[46] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20631.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20632 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/r_i_wr_data[47] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_mux_sel ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_i_wr_data[47] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20632.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20633 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0] ), + .O(n13867)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20633.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20634 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2] ), + .I2(n13867), .O(n13868)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20634.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20635 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4] ), + .I2(n13868), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n308 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20635.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20636 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[5] ), + .O(n13869)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0990 */ ; + defparam LUT__20636.LUTMASK = 16'h0990; + EFX_LUT4 LUT__20637 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[6] ), + .O(n13870)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0990 */ ; + defparam LUT__20637.LUTMASK = 16'h0990; + EFX_LUT4 LUT__20638 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[4] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[4] ), + .O(n13871)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20638.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20639 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popToPushGray_buffercc_io_dataOut[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtrGray[1] ), + .I2(n13871), .O(n13872)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9090 */ ; + defparam LUT__20639.LUTMASK = 16'h9090; + EFX_LUT4 LUT__20640 (.I0(n5254), .I1(n5256), .I2(n5258), .O(n13873)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__20640.LUTMASK = 16'h0101; + EFX_LUT4 LUT__20641 (.I0(n13873), .I1(n5252), .I2(n5250), .I3(n5249), + .O(n13874)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00bf */ ; + defparam LUT__20641.LUTMASK = 16'h00bf; + EFX_LUT4 LUT__20642 (.I0(n13870), .I1(n13872), .I2(n13869), .I3(n13874), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/_zz_16 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h007f */ ; + defparam LUT__20642.LUTMASK = 16'h007f; + EFX_LUT4 LUT__20643 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4] ), + .I1(n13868), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n303 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20643.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20644 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4] ), + .I1(n13868), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n298 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20644.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20645 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2] ), + .I1(n13867), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n293 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20645.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20646 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2] ), + .I1(n13867), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n288 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20646.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20647 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n283 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20647.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20648 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[4] ), + .O(n13875)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20648.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20649 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[5] ), + .O(n13876)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20649.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20650 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[1] ), + .O(n13877)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20650.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20651 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtrGray[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushToPopGray_buffercc_io_dataOut[6] ), + .O(n13878)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20651.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20652 (.I0(n13875), .I1(n13876), .I2(n13877), .I3(n13878), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/io_pop_valid )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfff */ ; + defparam LUT__20652.LUTMASK = 16'hbfff; + EFX_LUT4 LUT__20653 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6] ), + .O(n12816)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__20653.LUTMASK = 16'h9999; + EFX_LUT4 LUT__20654 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4] ), + .I1(n12816), .O(n12819)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20654.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20655 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3] ), + .I1(n12819), .O(n12822)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20655.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20656 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2] ), + .I1(n12822), .O(n12825)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20656.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20657 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1] ), + .I1(n12825), .O(n12828)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20657.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20658 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0] ), + .I1(n12828), .O(n8862)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20658.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20659 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n288 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n283 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n166 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20659.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20660 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2] ), + .I1(n13867), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n165 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20660.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20661 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[2] ), + .I1(n13867), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n164 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20661.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20662 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[4] ), + .I1(n13868), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n163 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20662.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20663 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n308 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n303 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n162 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20663.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20664 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n318 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20664.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20665 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[1] ), + .O(n13879)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20665.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20666 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2] ), + .I1(n13879), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n323 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20666.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20667 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2] ), + .I1(n13879), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n328 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20667.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20668 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3] ), + .I2(n13879), .O(n13880)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20668.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20669 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4] ), + .I1(n13880), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n333 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20669.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20670 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4] ), + .I1(n13880), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n338 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20670.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20671 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5] ), + .I2(n13880), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n343 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20671.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20672 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n318 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n323 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n208 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20672.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20673 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2] ), + .I1(n13879), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n207 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20673.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20674 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[2] ), + .I1(n13879), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n206 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20674.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20675 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[4] ), + .I1(n13880), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n205 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20675.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20676 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n338 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n343 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/n204 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20676.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20677 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20677.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20678 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20678.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20679 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20679.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20680 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2] ), + .O(n13881)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20680.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20681 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .I1(n13881), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20681.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20682 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3] ), + .I1(n13881), .O(n13882)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20682.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20683 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .I1(n13882), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20683.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20684 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4] ), + .I1(n13882), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n347 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20684.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20685 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n347 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_8[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20685.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20686 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[2] ), + .O(n13883)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20686.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20687 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[6] ), + .O(n13884)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1428 */ ; + defparam LUT__20687.LUTMASK = 16'h1428; + EFX_LUT4 LUT__20688 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[1] ), + .O(n13885)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20688.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20689 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popToPushGray_buffercc_io_dataOut[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtrGray[3] ), + .O(n13886)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20689.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20690 (.I0(n13883), .I1(n13884), .I2(n13885), .I3(n13886), + .O(n13887)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20690.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20691 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_ack ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_wr_ack ), + .I2(n13887), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/_zz_16 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0e0e */ ; + defparam LUT__20691.LUTMASK = 16'h0e0e; + EFX_LUT4 LUT__20692 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20692.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20693 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20693.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20694 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20694.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20695 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2] ), + .O(n13888)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20695.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20696 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .I1(n13888), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20696.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20697 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3] ), + .I1(n13888), .O(n13889)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20697.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20698 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .I1(n13889), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20698.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20699 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4] ), + .I1(n13889), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n977 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20699.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20700 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n977 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_8[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20700.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20701 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6] ), + .O(n13890)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0990 */ ; + defparam LUT__20701.LUTMASK = 16'h0990; + EFX_LUT4 LUT__20702 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[5] ), + .O(n13891)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0990 */ ; + defparam LUT__20702.LUTMASK = 16'h0990; + EFX_LUT4 LUT__20703 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[1] ), + .O(n13892)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20703.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20704 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popToPushGray_buffercc_io_dataOut[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[2] ), + .I2(n13892), .O(n13893)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9090 */ ; + defparam LUT__20704.LUTMASK = 16'h9090; + EFX_LUT4 LUT__20705 (.I0(n13891), .I1(n13893), .I2(n13890), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_rd_fifo_wr_en ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/_zz_16 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f00 */ ; + defparam LUT__20705.LUTMASK = 16'h7f00; + EFX_LUT4 LUT__20706 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n922 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20706.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20707 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[1] ), + .O(n13894)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20707.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20708 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] ), + .I1(n13894), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n927 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20708.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20709 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] ), + .I1(n13894), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n932 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20709.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20710 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] ), + .I2(n13894), .O(n13895)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20710.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20711 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] ), + .I1(n13895), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n937 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20711.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20712 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] ), + .I1(n13895), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n942 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20712.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20713 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[6] ), + .O(n12798)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20713.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20714 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[4] ), + .I1(n12798), .O(n12801)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20714.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20715 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[3] ), + .I1(n12801), .O(n12804)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20715.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20716 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[2] ), + .I1(n12804), .O(n12807)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20716.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20717 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[1] ), + .I1(n12807), .O(n12810)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20717.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20718 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushToPopGray_buffercc_io_dataOut[0] ), + .I1(n12810), .O(n8961)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20718.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20719 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n922 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n927 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n677 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20719.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20720 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] ), + .I1(n13894), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n676 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20720.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20721 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[2] ), + .I1(n13894), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n675 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20721.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20722 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] ), + .I1(n13895), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n674 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20722.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20723 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtr[5] ), + .I2(n13895), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/pushCC_pushPtrGray[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n947 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20723.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20724 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n942 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n947 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n673 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20724.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20725 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n957 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20725.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20726 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n962 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20726.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20727 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3] ), + .I1(n13888), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n967 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20727.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20728 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4] ), + .I1(n13889), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n972 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20728.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20729 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5] ), + .I2(n13889), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n982 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20729.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20730 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n957 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n962 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n719 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20730.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20731 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n718 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20731.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20732 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[3] ), + .I1(n13888), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n717 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20732.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20733 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[4] ), + .I1(n13889), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n716 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20733.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20734 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n977 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n982 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/n715 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20734.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20735 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1] ), + .O(n13896)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20735.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20736 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2] ), + .I2(n13896), .O(n13897)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20736.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20737 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4] ), + .I2(n13897), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n317 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20737.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20738 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[0] ), + .O(n13898)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20738.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20739 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[6] ), + .O(n13899)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20739.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20740 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[5] ), + .O(n13900)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20740.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20741 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtrGray[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushToPopGray_buffercc_io_dataOut[1] ), + .O(n13901)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20741.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20742 (.I0(n13898), .I1(n13899), .I2(n13900), .I3(n13901), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfff */ ; + defparam LUT__20742.LUTMASK = 16'hbfff; + EFX_LUT4 LUT__20743 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20743.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20744 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20744.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20745 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20745.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20746 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2] ), + .O(n13902)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20746.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20747 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .I1(n13902), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20747.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20748 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3] ), + .I1(n13902), .O(n13903)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20748.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20749 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .I1(n13903), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20749.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20750 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4] ), + .I1(n13903), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n597 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20750.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20751 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n597 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n272 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_8[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20751.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20752 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[2] ), + .O(n13904)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__20752.LUTMASK = 16'h9009; + EFX_LUT4 LUT__20753 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[6] ), + .O(n13905)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0990 */ ; + defparam LUT__20753.LUTMASK = 16'h0990; + EFX_LUT4 LUT__20754 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[5] ), + .O(n13906)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0990 */ ; + defparam LUT__20754.LUTMASK = 16'h0990; + EFX_LUT4 LUT__20755 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popToPushGray_buffercc_io_dataOut[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtrGray[4] ), + .I2(n13906), .O(n13907)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9090 */ ; + defparam LUT__20755.LUTMASK = 16'h9090; + EFX_LUT4 LUT__20756 (.I0(n13905), .I1(n13907), .I2(n13904), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_push ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/_zz_16 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f00 */ ; + defparam LUT__20756.LUTMASK = 16'h7f00; + EFX_LUT4 LUT__20757 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4] ), + .I1(n13897), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n312 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20757.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20758 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[4] ), + .I1(n13897), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n307 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20758.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20759 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2] ), + .I1(n13896), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n302 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20759.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20760 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2] ), + .I1(n13896), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n297 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20760.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20761 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n292 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20761.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20762 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n297 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n292 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n173 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20762.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20763 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[2] ), + .I1(n13896), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n172 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20763.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20764 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n307 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n302 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n171 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20764.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20765 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n312 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n307 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n170 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20765.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20766 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n317 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n312 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n169 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20766.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20767 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n327 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20767.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20768 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20768.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20769 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3] ), + .I1(n13881), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n337 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20769.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20770 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4] ), + .I1(n13882), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n342 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20770.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20771 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5] ), + .I2(n13882), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n352 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20771.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20772 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n327 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n332 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n215 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20772.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20773 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n214 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20773.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20774 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[3] ), + .I1(n13881), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n213 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20774.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20775 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[4] ), + .I1(n13882), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n212 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20775.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20776 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n347 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n352 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ack/n211 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20776.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20777 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n542 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20777.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20778 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[1] ), + .O(n13908)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20778.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20779 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2] ), + .I1(n13908), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n547 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20779.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20780 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2] ), + .I1(n13908), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n552 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20780.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20781 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3] ), + .I2(n13908), .O(n13909)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__20781.LUTMASK = 16'h8080; + EFX_LUT4 LUT__20782 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4] ), + .I1(n13909), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n557 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20782.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20783 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4] ), + .I1(n13909), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n562 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20783.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20784 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5] ), + .I2(n13909), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n567 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20784.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20785 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n542 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n547 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n373 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20785.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20786 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2] ), + .I1(n13908), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n372 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20786.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20787 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[2] ), + .I1(n13908), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n371 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20787.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20788 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[4] ), + .I1(n13909), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/pushCC_pushPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n370 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20788.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20789 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n562 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n567 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n369 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20789.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20790 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n577 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20790.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20791 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n582 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__20791.LUTMASK = 16'h7878; + EFX_LUT4 LUT__20792 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3] ), + .I1(n13902), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n587 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20792.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20793 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4] ), + .I1(n13903), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n592 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20793.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20794 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5] ), + .I2(n13903), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n602 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__20794.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__20795 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n577 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n582 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n415 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20795.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20796 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n414 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f8 */ ; + defparam LUT__20796.LUTMASK = 16'h07f8; + EFX_LUT4 LUT__20797 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[3] ), + .I1(n13902), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n413 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20797.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20798 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[4] ), + .I1(n13903), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/popCC_popPtr[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n412 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__20798.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__20799 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n597 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n602 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/ac_fifo/n411 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__20799.LUTMASK = 16'h6666; + EFX_LUT4 LUT__20800 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[31] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n734 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20800.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20801 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[32] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n733 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20801.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20802 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[33] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n732 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20802.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20803 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[34] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n731 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20803.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20804 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[35] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n730 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20804.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20805 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[36] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n729 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20805.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20806 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[37] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n728 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20806.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20807 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[38] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n727 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20807.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20808 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[39] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n726 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20808.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20809 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[40] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n725 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20809.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20810 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[41] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n724 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20810.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20811 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[16] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[42] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n723 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20811.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20812 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[17] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[43] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n722 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20812.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20813 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[18] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[44] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n721 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20813.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20814 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[19] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[45] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n720 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20814.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20815 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[28] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n738 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20815.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20816 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/o_ac_bus[29] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/r_ac_re ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/n737 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20816.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20817 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[3] ), + .O(n13910)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20817.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20818 (.I0(n13910), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[6] ), + .O(n13911)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00bf */ ; + defparam LUT__20818.LUTMASK = 16'h00bf; + EFX_LUT4 LUT__20819 (.I0(n13911), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[9] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[7] ), + .O(n13912)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__20819.LUTMASK = 16'h4000; + EFX_LUT4 LUT__20820 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[14] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[15] ), + .O(n13913)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__20820.LUTMASK = 16'h0001; + EFX_LUT4 LUT__20821 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n13913), .O(n13914)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__20821.LUTMASK = 16'h8888; + EFX_LUT4 LUT__20822 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[10] ), + .I1(n13912), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[11] ), + .I3(n13914), .O(ceg_net932)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__20822.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__20823 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][81] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][113] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13915)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20823.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20824 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][49] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][17] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13916)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20824.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20825 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0] ), + .O(n13917)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20825.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20826 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3] ), + .I2(n13917), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hefef */ ; + defparam LUT__20826.LUTMASK = 16'hefef; + EFX_LUT4 LUT__20827 (.I0(n13916), .I1(n13915), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1626 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20827.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20828 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][114] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][82] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13918)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20828.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20829 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][50] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][18] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13919)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20829.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20830 (.I0(n13919), .I1(n13918), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1625 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20830.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20831 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][115] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][83] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13920)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20831.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20832 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][51] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][19] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13921)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20832.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20833 (.I0(n13921), .I1(n13920), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1624 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20833.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20834 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][116] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][84] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13922)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20834.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20835 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][52] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][20] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13923)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20835.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20836 (.I0(n13923), .I1(n13922), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1623 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20836.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20837 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][117] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][85] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13924)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20837.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20838 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][53] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][21] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13925)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20838.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20839 (.I0(n13925), .I1(n13924), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1622 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20839.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20840 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][118] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][86] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13926)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20840.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20841 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][54] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][22] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13927)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20841.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20842 (.I0(n13927), .I1(n13926), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1621 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20842.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20843 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][119] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][87] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13928)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20843.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20844 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][55] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][23] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13929)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20844.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20845 (.I0(n13929), .I1(n13928), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1620 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20845.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20846 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][120] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][88] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13930)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20846.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20847 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][56] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][24] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13931)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20847.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20848 (.I0(n13931), .I1(n13930), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1619 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20848.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20849 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][121] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][89] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13932)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20849.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20850 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][57] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][25] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13933)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20850.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20851 (.I0(n13933), .I1(n13932), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1618 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20851.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20852 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][122] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][90] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13934)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20852.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20853 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][58] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][26] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13935)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20853.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20854 (.I0(n13935), .I1(n13934), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1617 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20854.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20855 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][123] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][91] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13936)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20855.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20856 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][59] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][27] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13937)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20856.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20857 (.I0(n13937), .I1(n13936), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1616 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20857.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20858 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][124] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][92] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13938)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20858.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20859 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][60] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][28] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13939)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20859.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20860 (.I0(n13939), .I1(n13938), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1615 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20860.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20861 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][125] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][93] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13940)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20861.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20862 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][61] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][29] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13941)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20862.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20863 (.I0(n13941), .I1(n13940), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1614 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20863.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20864 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][126] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][94] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13942)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20864.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20865 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][62] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][30] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13943)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20865.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20866 (.I0(n13943), .I1(n13942), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1613 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20866.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20867 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][127] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][95] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13944)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20867.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20868 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][63] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][31] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13945)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20868.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20869 (.I0(n13945), .I1(n13944), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1612 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20869.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20870 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1646 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__20870.LUTMASK = 16'h6060; + EFX_LUT4 LUT__20871 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8136 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__20871.LUTMASK = 16'h9999; + EFX_LUT4 LUT__20872 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8] ), + .I3(n13917), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1650 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd33c */ ; + defparam LUT__20872.LUTMASK = 16'hd33c; + EFX_LUT4 LUT__20873 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(ceg_net938)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20873.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20874 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dq_pipe_ap[8] ), + .I2(n13917), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_cnt[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1649 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he708 */ ; + defparam LUT__20874.LUTMASK = 16'he708; + EFX_LUT4 LUT__20875 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_rd_ack_ap[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2553 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20875.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20876 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][65] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][97] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13946)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20876.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20877 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][33] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13947)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20877.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20878 (.I0(n13947), .I1(n13946), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1643 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20878.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20879 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][66] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][98] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13948)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20879.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20880 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][34] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13949)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20880.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20881 (.I0(n13949), .I1(n13948), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1642 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20881.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20882 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][67] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][99] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13950)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20882.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20883 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][35] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13951)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20883.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20884 (.I0(n13951), .I1(n13950), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1641 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20884.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20885 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][68] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][100] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13952)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20885.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20886 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][36] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13953)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20886.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20887 (.I0(n13953), .I1(n13952), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1640 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20887.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20888 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][69] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][101] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13954)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20888.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20889 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][37] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13955)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20889.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20890 (.I0(n13955), .I1(n13954), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1639 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20890.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20891 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][70] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][102] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13956)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20891.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20892 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][38] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13957)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20892.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20893 (.I0(n13957), .I1(n13956), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1638 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20893.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20894 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][71] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][103] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13958)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20894.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20895 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][39] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13959)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20895.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20896 (.I0(n13959), .I1(n13958), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1637 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20896.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20897 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][72] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][104] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13960)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20897.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20898 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][40] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13961)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20898.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20899 (.I0(n13961), .I1(n13960), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1636 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20899.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20900 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][73] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][105] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13962)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20900.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20901 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][41] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13963)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20901.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20902 (.I0(n13963), .I1(n13962), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1635 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20902.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20903 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][74] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][106] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13964)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20903.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20904 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][42] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13965)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20904.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20905 (.I0(n13965), .I1(n13964), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1634 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20905.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20906 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][75] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][107] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13966)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20906.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20907 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][43] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13967)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20907.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20908 (.I0(n13967), .I1(n13966), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1633 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20908.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20909 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][76] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][108] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13968)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20909.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20910 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][44] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13969)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20910.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20911 (.I0(n13969), .I1(n13968), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1632 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20911.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20912 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][77] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][109] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13970)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20912.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20913 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][45] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13971)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20913.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20914 (.I0(n13971), .I1(n13970), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1631 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20914.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20915 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][78] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][110] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13972)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20915.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20916 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][46] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13973)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20916.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20917 (.I0(n13973), .I1(n13972), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1630 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20917.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20918 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][79] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][111] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13974)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__20918.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__20919 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][47] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13975)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20919.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20920 (.I0(n13975), .I1(n13974), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1629 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20920.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20921 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_wr_ack[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1521 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__20921.LUTMASK = 16'h4444; + EFX_LUT4 LUT__20922 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_rst_3 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3997/i12_pre ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_rd_fifo_wr_en_p[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20922.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20923 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13976)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20923.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20924 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13977)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__20924.LUTMASK = 16'hacac; + EFX_LUT4 LUT__20925 (.I0(n13977), .I1(n13976), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1512 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__20925.LUTMASK = 16'hca00; + EFX_LUT4 LUT__20926 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i98_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][97] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20926.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20927 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i99_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][98] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20927.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20928 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i100_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][99] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20928.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20929 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i101_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][100] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20929.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20930 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i102_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][101] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20930.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20931 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i103_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][102] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20931.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20932 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i104_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][103] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20932.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20933 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i105_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][104] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20933.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20934 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i106_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][105] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20934.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20935 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i107_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][106] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20935.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20936 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i108_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][107] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20936.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20937 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i109_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][108] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20937.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20938 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i110_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][109] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20938.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20939 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i111_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][110] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20939.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20940 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i112_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][111] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20940.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20941 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i113_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][112] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20941.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20942 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i114_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][113] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20942.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20943 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i115_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][114] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20943.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20944 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i116_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][115] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20944.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20945 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i117_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][116] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20945.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20946 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i118_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][117] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20946.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20947 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i119_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][118] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20947.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20948 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i120_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][119] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20948.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20949 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i121_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][120] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20949.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20950 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i122_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][121] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20950.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20951 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i123_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][122] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20951.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20952 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i124_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][123] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20952.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20953 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i125_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][124] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20953.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20954 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i126_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][125] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20954.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20955 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i127_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][126] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20955.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20956 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i128_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][127] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20956.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20957 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i2_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20957.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20958 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i3_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20958.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20959 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i4_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20959.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20960 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i5_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20960.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20961 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i6_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20961.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20962 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i7_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20962.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20963 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i8_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20963.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20964 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i9_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20964.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20965 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i10_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20965.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20966 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i11_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20966.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20967 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i12_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20967.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20968 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i13_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20968.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20969 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i14_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20969.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20970 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i15_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20970.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20971 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i16_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20971.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20972 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i1_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20972.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20973 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3986/i1_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[7][0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20973.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20974 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i2_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20974.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20975 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i3_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20975.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20976 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i4_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20976.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20977 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i5_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20977.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20978 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i6_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20978.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20979 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i7_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20979.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20980 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i8_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20980.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20981 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i9_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20981.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20982 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20982.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20983 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i11_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20983.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20984 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i12_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20984.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20985 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i13_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20985.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20986 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i14_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20986.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20987 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i15_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20987.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20988 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i16_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][15] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20988.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20989 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i17_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][16] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20989.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20990 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i18_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][17] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20990.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20991 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i19_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][18] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20991.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20992 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i20_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][19] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20992.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20993 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i21_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][20] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20993.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20994 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i22_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][21] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20994.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20995 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i23_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][22] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20995.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20996 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i24_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][23] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20996.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20997 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i25_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][24] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20997.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20998 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i26_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][25] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20998.LUTMASK = 16'h1111; + EFX_LUT4 LUT__20999 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i27_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][26] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__20999.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21000 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i28_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][27] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21000.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21001 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i29_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][28] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21001.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21002 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i30_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][29] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21002.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21003 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i31_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][30] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21003.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21004 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i32_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][31] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21004.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21005 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i33_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][32] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21005.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21006 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i34_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][33] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21006.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21007 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i35_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][34] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21007.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21008 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i36_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][35] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21008.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21009 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i37_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][36] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21009.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21010 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i38_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][37] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21010.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21011 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i39_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][38] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21011.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21012 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i40_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][39] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21012.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21013 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i41_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][40] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21013.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21014 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i42_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][41] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21014.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21015 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i43_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][42] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21015.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21016 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i44_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][43] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21016.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21017 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i45_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][44] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21017.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21018 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i46_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][45] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21018.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21019 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i47_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][46] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21019.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21020 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i48_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][47] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21020.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21021 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i49_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][48] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21021.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21022 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i50_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][49] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21022.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21023 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i51_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][50] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21023.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21024 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i52_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][51] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21024.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21025 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i53_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][52] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21025.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21026 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i54_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][53] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21026.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21027 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i55_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][54] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21027.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21028 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i56_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][55] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21028.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21029 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i57_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][56] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21029.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21030 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i58_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][57] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21030.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21031 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i59_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][58] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21031.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21032 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i60_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][59] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21032.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21033 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i61_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][60] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21033.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21034 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i62_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][61] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21034.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21035 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i63_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][62] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21035.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21036 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i64_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][63] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21036.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21037 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i65_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][64] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21037.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21038 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i66_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][65] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21038.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21039 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i67_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][66] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21039.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21040 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i68_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][67] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21040.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21041 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i69_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][68] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21041.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21042 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i70_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][69] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21042.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21043 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i71_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][70] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21043.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21044 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i72_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][71] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21044.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21045 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i73_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][72] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21045.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21046 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i74_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][73] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21046.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21047 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i75_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][74] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21047.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21048 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i76_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][75] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21048.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21049 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i77_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][76] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21049.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21050 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i78_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][77] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21050.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21051 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i79_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][78] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21051.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21052 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i80_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][79] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21052.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21053 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i81_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][80] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21053.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21054 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i82_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][81] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21054.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21055 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i83_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][82] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21055.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21056 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i84_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][83] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21056.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21057 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i85_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][84] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21057.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21058 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i86_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][85] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21058.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21059 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i87_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][86] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21059.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21060 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i88_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][87] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21060.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21061 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i89_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][88] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21061.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21062 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i90_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][89] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21062.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21063 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i91_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][90] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21063.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21064 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i92_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][91] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21064.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21065 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i93_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][92] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21065.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21066 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i94_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][93] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21066.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21067 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i95_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][94] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21067.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21068 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i96_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][95] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21068.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21069 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i97_pre ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dffrs_3976/i10_rst_7 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[7][96] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21069.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21070 (.I0(i_dqs_hi[0]), .I1(i_dqs_lo[0]), .O(n13978)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21070.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21071 (.I0(i_dqs_lo[0]), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[0] ), + .O(n13979)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21071.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21072 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[5] ), + .I1(n13979), .I2(i_dq_lo[5]), .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2471 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21072.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21073 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13980)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21073.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21074 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13981)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21074.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21075 (.I0(n13981), .I1(n13980), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1502 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21075.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21076 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[4] ), + .I1(n13979), .I2(i_dq_lo[4]), .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2472 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21076.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21077 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][64] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][96] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13982)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21077.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21078 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][32] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13983)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21078.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21079 (.I0(n13983), .I1(n13982), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1644 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21079.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21080 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][80] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][112] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13984)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21080.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21081 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][48] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_data_buf_p[9][16] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n13985)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21081.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21082 (.I0(n13985), .I1(n13984), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1627 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21082.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21083 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1647 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21083.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21084 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8010 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555 */ ; + defparam LUT__21084.LUTMASK = 16'h5555; + EFX_LUT4 LUT__21085 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8010 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/equal_1648/n7 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__21085.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__21086 (.I0(n5213), .I1(n5161), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2072 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21086.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21087 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21087.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21088 (.I0(n5211), .I1(n5159), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13986)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21088.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21089 (.I0(n13986), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2185 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha3a3 */ ; + defparam LUT__21089.LUTMASK = 16'ha3a3; + EFX_LUT4 LUT__21090 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(ceg_net947)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21090.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21091 (.I0(n5209), .I1(n5157), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13987)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21091.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21092 (.I0(n13987), .I1(n2603), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2184 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21092.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21093 (.I0(n5207), .I1(n5155), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13988)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21093.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21094 (.I0(n13988), .I1(n5184), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2183 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21094.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21095 (.I0(n5205), .I1(n5153), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13989)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21095.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21096 (.I0(n13989), .I1(n5182), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2182 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21096.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21097 (.I0(n5203), .I1(n5151), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13990)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21097.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21098 (.I0(n13990), .I1(n5180), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2181 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21098.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21099 (.I0(n5201), .I1(n5149), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13991)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21099.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21100 (.I0(n13991), .I1(n5178), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2180 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21100.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21101 (.I0(n5199), .I1(n5147), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13992)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21101.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21102 (.I0(n13992), .I1(n5176), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2179 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21102.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21103 (.I0(n5197), .I1(n5145), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13993)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21103.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21104 (.I0(n13993), .I1(n5174), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2178 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21104.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21105 (.I0(n5195), .I1(n5143), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13994)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21105.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21106 (.I0(n13994), .I1(n5172), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2177 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21106.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21107 (.I0(n5193), .I1(n5141), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13995)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21107.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21108 (.I0(n13995), .I1(n5170), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2176 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21108.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21109 (.I0(n5191), .I1(n5139), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13996)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21109.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21110 (.I0(n13996), .I1(n5168), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2175 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21110.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21111 (.I0(n5189), .I1(n5137), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13997)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21111.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21112 (.I0(n13997), .I1(n5166), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2174 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21112.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21113 (.I0(n5187), .I1(n5135), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13998)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21113.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21114 (.I0(n13998), .I1(n5164), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2173 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21114.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21115 (.I0(n5186), .I1(n5134), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(n13999)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21115.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21116 (.I0(n13999), .I1(n5163), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8015 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2172 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21116.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21117 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2169 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__21117.LUTMASK = 16'h6666; + EFX_LUT4 LUT__21118 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[1] ), + .I1(n13979), .I2(i_dq_lo[1]), .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2475 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21118.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21119 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[2] ), + .I1(n13979), .I2(i_dq_lo[2]), .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2474 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21119.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21120 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[3] ), + .I1(n13979), .I2(i_dq_lo[3]), .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2473 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21120.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21121 (.I0(n2642), .I1(n2115), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2073 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21121.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21122 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[15] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[0] ), + .O(n14000)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__21122.LUTMASK = 16'h0100; + EFX_LUT4 LUT__21123 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[11] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[12] ), + .O(n14001)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21123.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21124 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[7] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[8] ), + .O(n14002)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21124.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21125 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_dqs_cnt[4] ), + .O(n14003)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21125.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21126 (.I0(n14000), .I1(n14001), .I2(n14002), .I3(n14003), + .O(n14004)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21126.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21127 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_wr_start_p[7] ), + .I1(n14004), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[1] ), + .O(n14005)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21127.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21128 (.I0(n14005), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dqs_state[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2170 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h2222 */ ; + defparam LUT__21128.LUTMASK = 16'h2222; + EFX_LUT4 LUT__21129 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[0] ), + .I1(n13979), .I2(i_dq_lo[0]), .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2476 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21129.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21130 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/get_dqs_wr_start_p[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1977 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21130.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21131 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6] ), + .O(n14006)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21131.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21132 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7] ), + .I3(n14006), .O(n14007)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__21132.LUTMASK = 16'h1000; + EFX_LUT4 LUT__21133 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2] ), + .I2(n14007), .O(n14008)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__21133.LUTMASK = 16'h1010; + EFX_LUT4 LUT__21134 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref ), + .I1(n14008), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4141 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__21134.LUTMASK = 16'h7777; + EFX_LUT4 LUT__21135 (.I0(i_dqs_hi[1]), .I1(i_dqs_lo[1]), .O(n14009)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21135.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21136 (.I0(i_dqs_lo[1]), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dqs_p_IN_HI_p[1] ), + .O(n14010)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21136.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21137 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[10] ), + .I1(n14010), .I2(i_dq_lo[10]), .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2529 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21137.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21138 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n14011)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21138.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21139 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n14012)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21139.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21140 (.I0(n14012), .I1(n14011), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1503 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21140.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21141 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[6] ), + .I1(n13979), .I2(i_dq_lo[6]), .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2470 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21141.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21142 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[7] ), + .I1(n13979), .I2(i_dq_lo[7]), .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2469 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21142.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21143 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[8] ), + .I1(n14010), .I2(i_dq_lo[8]), .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2531 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21143.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21144 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[9] ), + .I1(n14010), .I2(i_dq_lo[9]), .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2530 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21144.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21145 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[36] ), + .I1(n14008), .O(n14013)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21145.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21146 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(n14014)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__21146.LUTMASK = 16'h1010; + EFX_LUT4 LUT__21147 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2] ), + .O(n14015)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__21147.LUTMASK = 16'h0707; + EFX_LUT4 LUT__21148 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5] ), + .O(n14016)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21148.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21149 (.I0(n14015), .I1(n14016), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7] ), + .O(n14017)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf400 */ ; + defparam LUT__21149.LUTMASK = 16'hf400; + EFX_LUT4 LUT__21150 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[13] ), + .O(n14018)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21150.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21151 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[15] ), + .I2(n14018), .O(n14019)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__21151.LUTMASK = 16'h1010; + EFX_LUT4 LUT__21152 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8] ), + .I1(n14017), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9] ), + .I3(n14019), .O(n14020)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__21152.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__21153 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(n14020), .O(ceg_net1036)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21153.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21154 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] ), + .I1(n14008), .I2(ceg_net1036), .O(n14021)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__21154.LUTMASK = 16'h1010; + EFX_LUT4 LUT__21155 (.I0(n14014), .I1(n14013), .I2(n14021), .O(n14022)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__21155.LUTMASK = 16'h0707; + EFX_LUT4 LUT__21156 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14023)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21156.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21157 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14023), .O(n14024)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21157.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21158 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14025)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21158.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21159 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14025), .O(n14026)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21159.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21160 (.I0(n14024), .I1(n14026), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[15] ), + .O(n14027)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21160.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21161 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14028)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21161.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21162 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14028), .O(n14029)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21162.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21163 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14030)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21163.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21164 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14030), .O(n14031)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21164.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21165 (.I0(n14029), .I1(n14031), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[25] ), + .O(n14032)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21165.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21166 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14033)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21166.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21167 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14033), .O(n14034)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21167.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21168 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14035)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21168.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21169 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14035), .O(n14036)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21169.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21170 (.I0(n14034), .I1(n14036), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[26] ), + .O(n14037)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21170.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21171 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14038)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21171.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21172 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14038), .O(n14039)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21172.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21173 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14040)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21173.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21174 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14040), .O(n14041)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21174.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21175 (.I0(n14039), .I1(n14041), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[14] ), + .O(n14042)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21175.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21176 (.I0(n14027), .I1(n14032), .I2(n14037), .I3(n14042), + .O(n14043)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21176.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21177 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14044)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21177.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21178 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14044), .O(n14045)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21178.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21179 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14046)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21179.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21180 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14046), .O(n14047)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21180.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21181 (.I0(n14045), .I1(n14047), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[17] ), + .O(n14048)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21181.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21182 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14049)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21182.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21183 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14049), .O(n14050)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21183.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21184 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14051)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21184.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21185 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14051), .O(n14052)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21185.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21186 (.I0(n14050), .I1(n14052), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[16] ), + .O(n14053)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21186.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21187 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14054)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21187.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21188 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14054), .O(n14055)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21188.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21189 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14056)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21189.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21190 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14056), .O(n14057)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21190.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21191 (.I0(n14055), .I1(n14057), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[20] ), + .O(n14058)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21191.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21192 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14059)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21192.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21193 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14059), .O(n14060)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21193.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21194 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14061)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21194.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21195 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14061), .O(n14062)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21195.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21196 (.I0(n14060), .I1(n14062), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[19] ), + .O(n14063)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21196.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21197 (.I0(n14048), .I1(n14053), .I2(n14058), .I3(n14063), + .O(n14064)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21197.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21198 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14065)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21198.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21199 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14065), .O(n14066)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21199.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21200 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14067)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21200.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21201 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14067), .O(n14068)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21201.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21202 (.I0(n14066), .I1(n14068), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[23] ), + .O(n14069)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21202.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21203 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14070)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21203.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21204 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14070), .O(n14071)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21204.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21205 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14072)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21205.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21206 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14072), .O(n14073)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21206.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21207 (.I0(n14071), .I1(n14073), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[18] ), + .O(n14074)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21207.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21208 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14075)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21208.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21209 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14075), .O(n14076)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21209.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21210 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14077)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21210.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21211 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14077), .O(n14078)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21211.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21212 (.I0(n14076), .I1(n14078), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[22] ), + .O(n14079)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21212.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21213 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14080)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21213.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21214 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14080), .O(n14081)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21214.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21215 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14082)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21215.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21216 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14082), .O(n14083)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21216.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21217 (.I0(n14081), .I1(n14083), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[27] ), + .O(n14084)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21217.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21218 (.I0(n14069), .I1(n14074), .I2(n14079), .I3(n14084), + .O(n14085)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21218.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21219 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14086)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21219.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21220 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14086), .O(n14087)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21220.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21221 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14088)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21221.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21222 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14088), .O(n14089)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21222.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21223 (.I0(n14087), .I1(n14089), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[13] ), + .O(n14090)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21223.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21224 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14091)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21224.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21225 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14091), .O(n14092)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21225.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21226 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14093)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21226.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21227 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14093), .O(n14094)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21227.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21228 (.I0(n14092), .I1(n14094), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[21] ), + .O(n14095)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21228.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21229 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14096)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21229.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21230 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14096), .O(n14097)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21230.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21231 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14098)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21231.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21232 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14098), .O(n14099)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21232.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21233 (.I0(n14097), .I1(n14099), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[24] ), + .O(n14100)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21233.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21234 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14101)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21234.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21235 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14101), .O(n14102)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21235.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21236 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14103)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21236.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21237 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I3(n14103), .O(n14104)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21237.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21238 (.I0(n14102), .I1(n14104), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[28] ), + .O(n14105)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21238.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21239 (.I0(n14090), .I1(n14095), .I2(n14100), .I3(n14105), + .O(n14106)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21239.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21240 (.I0(n14043), .I1(n14064), .I2(n14085), .I3(n14106), + .O(n14107)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21240.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21241 (.I0(n13844), .I1(n13858), .O(n14108)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21241.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21242 (.I0(n1675), .I1(n5260), .O(n14109)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21242.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21243 (.I0(n5263), .I1(n5265), .I2(n5267), .I3(n14109), + .O(n14110)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__21243.LUTMASK = 16'h0100; + EFX_LUT4 LUT__21244 (.I0(n1511), .I1(n5261), .I2(n13830), .I3(n14110), + .O(n14111)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__21244.LUTMASK = 16'h0100; + EFX_LUT4 LUT__21245 (.I0(n14108), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter ), + .I2(n14111), .O(n14112)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd0d0 */ ; + defparam LUT__21245.LUTMASK = 16'hd0d0; + EFX_LUT4 LUT__21246 (.I0(n14107), .I1(n14112), .O(n14113)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21246.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21247 (.I0(n14111), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter ), + .I2(n14108), .O(n14114)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__21247.LUTMASK = 16'h7070; + EFX_LUT4 LUT__21248 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14115)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21248.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21249 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14115), .O(n14116)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21249.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21250 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14117)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21250.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21251 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14117), .O(n14118)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21251.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21252 (.I0(n14116), .I1(n14118), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[20] ), + .O(n14119)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21252.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21253 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14120)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21253.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21254 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14120), .O(n14121)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21254.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21255 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14122)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21255.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21256 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14122), .O(n14123)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21256.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21257 (.I0(n14121), .I1(n14123), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[14] ), + .O(n14124)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21257.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21258 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14125)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21258.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21259 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14125), .O(n14126)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21259.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21260 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14127)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21260.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21261 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14127), .O(n14128)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21261.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21262 (.I0(n14126), .I1(n14128), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[13] ), + .O(n14129)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21262.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21263 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14130)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21263.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21264 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14130), .O(n14131)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21264.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21265 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14132)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21265.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21266 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14132), .O(n14133)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21266.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21267 (.I0(n14131), .I1(n14133), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[23] ), + .O(n14134)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21267.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21268 (.I0(n14119), .I1(n14124), .I2(n14129), .I3(n14134), + .O(n14135)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21268.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21269 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14136)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21269.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21270 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14136), .O(n14137)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21270.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21271 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14138)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21271.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21272 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14138), .O(n14139)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21272.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21273 (.I0(n14137), .I1(n14139), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[25] ), + .O(n14140)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21273.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21274 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14141)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21274.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21275 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14141), .O(n14142)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21275.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21276 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14143)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21276.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21277 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14143), .O(n14144)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21277.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21278 (.I0(n14142), .I1(n14144), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[19] ), + .O(n14145)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21278.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21279 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14146)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21279.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21280 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14146), .O(n14147)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21280.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21281 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14148)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21281.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21282 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14148), .O(n14149)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21282.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21283 (.I0(n14147), .I1(n14149), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[27] ), + .O(n14150)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21283.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21284 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14151)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21284.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21285 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14151), .O(n14152)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21285.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21286 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14153)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21286.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21287 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14153), .O(n14154)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21287.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21288 (.I0(n14152), .I1(n14154), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[22] ), + .O(n14155)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21288.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21289 (.I0(n14140), .I1(n14145), .I2(n14150), .I3(n14155), + .O(n14156)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21289.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21290 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14157)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21290.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21291 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14157), .O(n14158)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21291.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21292 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14159)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21292.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21293 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14159), .O(n14160)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21293.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21294 (.I0(n14158), .I1(n14160), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[17] ), + .O(n14161)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21294.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21295 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14162)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21295.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21296 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14162), .O(n14163)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21296.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21297 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14164)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21297.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21298 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14164), .O(n14165)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21298.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21299 (.I0(n14163), .I1(n14165), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[21] ), + .O(n14166)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21299.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21300 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14167)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21300.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21301 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14167), .O(n14168)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21301.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21302 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14169)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21302.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21303 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14169), .O(n14170)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21303.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21304 (.I0(n14168), .I1(n14170), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[26] ), + .O(n14171)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21304.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21305 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14172)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21305.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21306 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14172), .O(n14173)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21306.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21307 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14174)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21307.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21308 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14174), .O(n14175)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21308.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21309 (.I0(n14173), .I1(n14175), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[15] ), + .O(n14176)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21309.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21310 (.I0(n14161), .I1(n14166), .I2(n14171), .I3(n14176), + .O(n14177)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21310.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21311 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14178)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21311.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21312 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14178), .O(n14179)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21312.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21313 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14180)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21313.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21314 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14180), .O(n14181)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21314.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21315 (.I0(n14179), .I1(n14181), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[28] ), + .O(n14182)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21315.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21316 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14183)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21316.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21317 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14183), .O(n14184)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21317.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21318 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14185)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21318.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21319 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14185), .O(n14186)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21319.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21320 (.I0(n14184), .I1(n14186), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[24] ), + .O(n14187)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21320.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21321 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14188)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21321.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21322 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14188), .O(n14189)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21322.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21323 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14190)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21323.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21324 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14190), .O(n14191)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21324.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21325 (.I0(n14189), .I1(n14191), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[16] ), + .O(n14192)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21325.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21326 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[7][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[5][5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14193)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21326.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21327 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[6][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[4][5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14193), .O(n14194)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21327.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21328 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[3][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[1][5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14195)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21328.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21329 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[2][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/row_activated_p0[0][5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I3(n14195), .O(n14196)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21329.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21330 (.I0(n14194), .I1(n14196), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[18] ), + .O(n14197)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__21330.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__21331 (.I0(n14182), .I1(n14187), .I2(n14192), .I3(n14197), + .O(n14198)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21331.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21332 (.I0(n14135), .I1(n14156), .I2(n14177), .I3(n14198), + .O(n14199)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21332.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21333 (.I0(n14114), .I1(n14199), .O(n14200)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21333.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21334 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .O(n14201)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21334.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21335 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5] ), + .I2(n14201), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14202)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0f77 */ ; + defparam LUT__21335.LUTMASK = 16'h0f77; + EFX_LUT4 LUT__21336 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .O(n14203)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21336.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21337 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .I3(n14203), .O(n14204)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21337.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21338 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .O(n14205)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__21338.LUTMASK = 16'h1010; + EFX_LUT4 LUT__21339 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1] ), + .I1(n14205), .O(n14206)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21339.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21340 (.I0(n14204), .I1(n14202), .I2(n14206), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .O(n14207)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c05 */ ; + defparam LUT__21340.LUTMASK = 16'h0c05; + EFX_LUT4 LUT__21341 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .O(n14208)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21341.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21342 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .I3(n14208), .O(n14209)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21342.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21343 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .O(n14210)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__21343.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__21344 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .I3(n14210), .O(n14211)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__21344.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__21345 (.I0(n14211), .I1(n14209), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .O(n14212)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21345.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21346 (.I0(n14212), .I1(n14112), .I2(n14114), .I3(n14207), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4602 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf444 */ ; + defparam LUT__21346.LUTMASK = 16'hf444; + EFX_LUT4 LUT__21347 (.I0(n14200), .I1(n14113), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4602 ), + .O(n14213)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f1 */ ; + defparam LUT__21347.LUTMASK = 16'h00f1; + EFX_LUT4 LUT__21348 (.I0(n14108), .I1(n14111), .O(n14214)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21348.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21349 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref ), + .I1(n14214), .O(n14215)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21349.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21350 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .I1(n14215), .O(n14216)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21350.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21351 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] ), + .I1(n14213), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I3(n14216), .O(n14217)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__21351.LUTMASK = 16'h1000; + EFX_LUT4 LUT__21352 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op ), + .I1(n14008), .I2(n14215), .O(n14218)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21352.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21353 (.I0(n14014), .I1(n14218), .O(n14219)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21353.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21354 (.I0(n14022), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] ), + .I2(n14217), .I3(n14219), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4694 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff1 */ ; + defparam LUT__21354.LUTMASK = 16'hfff1; + EFX_LUT4 LUT__21355 (.I0(n14008), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .I2(n14215), .O(n14220)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__21355.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__21356 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[2] ), + .O(n14221)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555 */ ; + defparam LUT__21356.LUTMASK = 16'h5555; + EFX_LUT4 LUT__21357 (.I0(n14216), .I1(n14220), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0] ), + .I3(n14221), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4684 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3a00 */ ; + defparam LUT__21357.LUTMASK = 16'h3a00; + EFX_LUT4 LUT__21358 (.I0(n14221), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4602 ), + .I2(n14216), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(ceg_net4223)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f00 */ ; + defparam LUT__21358.LUTMASK = 16'h7f00; + EFX_LUT4 LUT__21359 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I1(n14112), .I2(n14216), .I3(n14218), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4658 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h333a */ ; + defparam LUT__21359.LUTMASK = 16'h333a; + EFX_LUT4 LUT__21360 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8097 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfbf */ ; + defparam LUT__21360.LUTMASK = 16'hbfbf; + EFX_LUT4 LUT__21361 (.I0(n14221), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4679 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__21361.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__21362 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(n14008), .I2(n14215), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8096 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21362.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21363 (.I0(n14221), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8096 ), + .O(ceg_net1009)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf4f4 */ ; + defparam LUT__21363.LUTMASK = 16'hf4f4; + EFX_LUT4 LUT__21364 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14222)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21364.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21365 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .O(n14223)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__21365.LUTMASK = 16'h0101; + EFX_LUT4 LUT__21366 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I1(n14222), .I2(n14223), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14224)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0fbb */ ; + defparam LUT__21366.LUTMASK = 16'h0fbb; + EFX_LUT4 LUT__21367 (.I0(n14008), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref ), + .O(n14225)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__21367.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__21368 (.I0(n14224), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0] ), + .I2(n14225), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4651 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__21368.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__21369 (.I0(n14225), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[37] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(ceg_net1122)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfe00 */ ; + defparam LUT__21369.LUTMASK = 16'hfe00; + EFX_LUT4 LUT__21370 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out ), + .O(n14226)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__21370.LUTMASK = 16'h1000; + EFX_LUT4 LUT__21371 (.I0(n14226), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[28] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(ceg_net1019)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__21371.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__21372 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[14] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[15] ), + .O(n14227)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21372.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21373 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[11] ), + .I3(n14227), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3413 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfeff */ ; + defparam LUT__21373.LUTMASK = 16'hfeff; + EFX_LUT4 LUT__21374 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3413 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8092 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21374.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21375 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(n14020), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8089 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21375.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21376 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3413 ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(ceg_net1023)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf1f1 */ ; + defparam LUT__21376.LUTMASK = 16'hf1f1; + EFX_LUT4 LUT__21377 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3858 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21377.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21378 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14228)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21378.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21379 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .O(n14229)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21379.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21380 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I1(n14228), .I2(n14229), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14230)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0f77 */ ; + defparam LUT__21380.LUTMASK = 16'h0f77; + EFX_LUT4 LUT__21381 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(n14231)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21381.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21382 (.I0(n14230), .I1(n14231), .O(ceg_net2599)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21382.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21383 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8089 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_start_count ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21383.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21384 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[5] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[6] ), + .O(n14232)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21384.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21385 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[2] ), + .I3(n14232), .O(n14233)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__21385.LUTMASK = 16'h0100; + EFX_LUT4 LUT__21386 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[14] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[15] ), + .O(n14234)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21386.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21387 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[12] ), + .I3(n14234), .O(n14235)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__21387.LUTMASK = 16'h0100; + EFX_LUT4 LUT__21388 (.I0(n14233), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[7] ), + .I3(n14235), .O(n14236)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbf00 */ ; + defparam LUT__21388.LUTMASK = 16'hbf00; + EFX_LUT4 LUT__21389 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .I1(n14236), .O(ceg_net1030)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21389.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21390 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4712 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21390.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21391 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3139 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21391.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21392 (.I0(n14207), .I1(n14199), .O(n14237)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21392.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21393 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8097 ), + .I1(n14114), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(n14237), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4892 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__21393.LUTMASK = 16'h4000; + EFX_LUT4 LUT__21394 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I1(n14212), .I2(n14112), .O(n14238)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__21394.LUTMASK = 16'h4040; + EFX_LUT4 LUT__21395 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8097 ), + .I1(n14107), .I2(n14238), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4893 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__21395.LUTMASK = 16'h4040; + EFX_LUT4 LUT__21396 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[69] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3146 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__21396.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__21397 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3143 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21397.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21398 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3164 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21398.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21399 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[2] ), + .O(n14239)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21399.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21400 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[5] ), + .O(n14240)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__21400.LUTMASK = 16'h0101; + EFX_LUT4 LUT__21401 (.I0(n14240), .I1(n14239), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[7] ), + .O(n14241)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd000 */ ; + defparam LUT__21401.LUTMASK = 16'hd000; + EFX_LUT4 LUT__21402 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/us_counter[9] ), + .O(n14242)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21402.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21403 (.I0(n14241), .I1(n14019), .I2(n14242), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8016 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00bf */ ; + defparam LUT__21403.LUTMASK = 16'h00bf; + EFX_LUT4 LUT__21404 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[33] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3147 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__21404.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__21405 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3185 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21405.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21406 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[28] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_out ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3190 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__21406.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__21407 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .O(n14243)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21407.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21408 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] ), + .O(n14244)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21408.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21409 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(n14244), .O(n14245)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21409.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21410 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .O(n14246)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21410.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21411 (.I0(n14243), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[9] ), + .I2(n14245), .I3(n14246), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3091 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff8 */ ; + defparam LUT__21411.LUTMASK = 16'hfff8; + EFX_LUT4 LUT__21412 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[1] ), + .I1(n14243), .O(n14247)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21412.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21413 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[0] ), + .I2(n14247), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3101 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c0a */ ; + defparam LUT__21413.LUTMASK = 16'h0c0a; + EFX_LUT4 LUT__21414 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[11] ), + .I1(n14010), .I2(i_dq_lo[11]), .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2528 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21414.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21415 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[12] ), + .I1(n14010), .I2(i_dq_lo[12]), .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2527 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21415.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21416 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[13] ), + .I1(n14010), .I2(i_dq_lo[13]), .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2526 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21416.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21417 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[14] ), + .I1(n14010), .I2(i_dq_lo[14]), .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2525 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21417.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21418 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/phy_ddr_dq_IN_HI_p0[15] ), + .I1(n14010), .I2(i_dq_lo[15]), .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2524 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21418.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21419 (.I0(i_dq_lo[0]), .I1(n13979), .I2(i_dq_hi[0]), + .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2468 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21419.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21420 (.I0(i_dq_lo[1]), .I1(n13979), .I2(i_dq_hi[1]), + .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2467 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21420.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21421 (.I0(i_dq_lo[2]), .I1(n13979), .I2(i_dq_hi[2]), + .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2466 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21421.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21422 (.I0(i_dq_lo[3]), .I1(n13979), .I2(i_dq_hi[3]), + .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2465 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21422.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21423 (.I0(i_dq_lo[4]), .I1(n13979), .I2(i_dq_hi[4]), + .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2464 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21423.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21424 (.I0(i_dq_lo[5]), .I1(n13979), .I2(i_dq_hi[5]), + .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2463 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21424.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21425 (.I0(i_dq_lo[6]), .I1(n13979), .I2(i_dq_hi[6]), + .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2462 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21425.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21426 (.I0(i_dq_lo[7]), .I1(n13979), .I2(i_dq_hi[7]), + .I3(n13978), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2461 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21426.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21427 (.I0(i_dq_lo[8]), .I1(n14010), .I2(i_dq_hi[8]), + .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2523 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21427.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21428 (.I0(i_dq_lo[9]), .I1(n14010), .I2(i_dq_hi[9]), + .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2522 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21428.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21429 (.I0(i_dq_lo[10]), .I1(n14010), .I2(i_dq_hi[10]), + .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2521 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21429.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21430 (.I0(i_dq_lo[11]), .I1(n14010), .I2(i_dq_hi[11]), + .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2520 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21430.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21431 (.I0(i_dq_lo[12]), .I1(n14010), .I2(i_dq_hi[12]), + .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2519 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21431.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21432 (.I0(i_dq_lo[13]), .I1(n14010), .I2(i_dq_hi[13]), + .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2518 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21432.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21433 (.I0(i_dq_lo[14]), .I1(n14010), .I2(i_dq_hi[14]), + .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2517 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21433.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21434 (.I0(i_dq_lo[15]), .I1(n14010), .I2(i_dq_hi[15]), + .I3(n14009), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n2516 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf888 */ ; + defparam LUT__21434.LUTMASK = 16'hf888; + EFX_LUT4 LUT__21435 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n14248)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21435.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21436 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/dm_data_buf_p[9][1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[0] ), + .O(n14249)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21436.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21437 (.I0(n14249), .I1(n14248), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_shift_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1528 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n1513 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21437.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21438 (.I0(n14237), .I1(n14108), .I2(n14112), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref ), + .O(n14250)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h000b */ ; + defparam LUT__21438.LUTMASK = 16'h000b; + EFX_LUT4 LUT__21439 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .O(n14251)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4f00 */ ; + defparam LUT__21439.LUTMASK = 16'h4f00; + EFX_LUT4 LUT__21440 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7] ), + .O(n14252)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21440.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21441 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3] ), + .O(n14253)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21441.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21442 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4141 ), + .I1(n14252), .I2(n14253), .O(n14254)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__21442.LUTMASK = 16'h4040; + EFX_LUT4 LUT__21443 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] ), + .O(n14255)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__21443.LUTMASK = 16'h6666; + EFX_LUT4 LUT__21444 (.I0(n14255), .I1(n14214), .I2(n14008), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[36] ), + .O(n14256)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c0a */ ; + defparam LUT__21444.LUTMASK = 16'h0c0a; + EFX_LUT4 LUT__21445 (.I0(n14256), .I1(n14254), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(n14257)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf100 */ ; + defparam LUT__21445.LUTMASK = 16'hf100; + EFX_LUT4 LUT__21446 (.I0(n14255), .I1(ceg_net1036), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] ), + .O(n14258)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__21446.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__21447 (.I0(n14250), .I1(n14251), .I2(n14257), .I3(n14258), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4693 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4f00 */ ; + defparam LUT__21447.LUTMASK = 16'h4f00; + EFX_LUT4 LUT__21448 (.I0(n14212), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14259)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21448.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21449 (.I0(n14259), .I1(n14107), .I2(n14112), .O(n14260)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__21449.LUTMASK = 16'h7070; + EFX_LUT4 LUT__21450 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I1(n14207), .O(n14261)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21450.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21451 (.I0(n14199), .I1(n14261), .I2(n14114), .I3(n14215), + .O(n14262)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8f00 */ ; + defparam LUT__21451.LUTMASK = 16'h8f00; + EFX_LUT4 LUT__21452 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] ), + .I1(n14007), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[36] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] ), + .O(n14263)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfa30 */ ; + defparam LUT__21452.LUTMASK = 16'hfa30; + EFX_LUT4 LUT__21453 (.I0(n14214), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[36] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2] ), + .I3(n14263), .O(n14264)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8bb0 */ ; + defparam LUT__21453.LUTMASK = 16'h8bb0; + EFX_LUT4 LUT__21454 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .I1(n14264), .I2(n14218), .O(n14265)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__21454.LUTMASK = 16'h0101; + EFX_LUT4 LUT__21455 (.I0(n14260), .I1(n14262), .I2(n14251), .I3(n14265), + .O(n14266)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h004f */ ; + defparam LUT__21455.LUTMASK = 16'h004f; + EFX_LUT4 LUT__21456 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2] ), + .I3(ceg_net1036), .O(n14267)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8700 */ ; + defparam LUT__21456.LUTMASK = 16'h8700; + EFX_LUT4 LUT__21457 (.I0(n14266), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I2(n14267), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4692 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h000b */ ; + defparam LUT__21457.LUTMASK = 16'h000b; + EFX_LUT4 LUT__21458 (.I0(n14237), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref ), + .I2(n14238), .I3(n14114), .O(n14268)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5d0f */ ; + defparam LUT__21458.LUTMASK = 16'h5d0f; + EFX_LUT4 LUT__21459 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3] ), + .O(n14269)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__21459.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__21460 (.I0(n14269), .I1(n14214), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[36] ), + .O(n14270)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3a3a */ ; + defparam LUT__21460.LUTMASK = 16'h3a3a; + EFX_LUT4 LUT__21461 (.I0(n14270), .I1(n14008), .I2(n14254), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .O(n14271)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h000d */ ; + defparam LUT__21461.LUTMASK = 16'h000d; + EFX_LUT4 LUT__21462 (.I0(n14268), .I1(n14251), .I2(n14271), .O(n14272)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__21462.LUTMASK = 16'h0707; + EFX_LUT4 LUT__21463 (.I0(n14269), .I1(n14020), .O(n14273)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21463.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21464 (.I0(n14273), .I1(n14272), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4691 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c05 */ ; + defparam LUT__21464.LUTMASK = 16'h0c05; + EFX_LUT4 LUT__21465 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[3] ), + .O(n14274)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21465.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21466 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4] ), + .I1(n14274), .O(n14275)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__21466.LUTMASK = 16'h6666; + EFX_LUT4 LUT__21467 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_act ), + .O(n14276)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21467.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21468 (.I0(n14113), .I1(n14259), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref ), + .I3(n14276), .O(n14277)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f8 */ ; + defparam LUT__21468.LUTMASK = 16'h00f8; + EFX_LUT4 LUT__21469 (.I0(n14214), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_op ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref ), + .O(n14278)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__21469.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__21470 (.I0(n14275), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[36] ), + .I2(n14278), .I3(n14008), .O(n14279)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0fee */ ; + defparam LUT__21470.LUTMASK = 16'h0fee; + EFX_LUT4 LUT__21471 (.I0(n14279), .I1(n14277), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(n14280)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3500 */ ; + defparam LUT__21471.LUTMASK = 16'h3500; + EFX_LUT4 LUT__21472 (.I0(n14275), .I1(ceg_net1036), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] ), + .I3(n14280), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4690 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h000b */ ; + defparam LUT__21472.LUTMASK = 16'h000b; + EFX_LUT4 LUT__21473 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4] ), + .I1(n14274), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5] ), + .O(n14281)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__21473.LUTMASK = 16'h7878; + EFX_LUT4 LUT__21474 (.I0(n14281), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[36] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref ), + .I3(n14008), .O(n14282)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf0ee */ ; + defparam LUT__21474.LUTMASK = 16'hf0ee; + EFX_LUT4 LUT__21475 (.I0(n14212), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I2(n14107), .I3(n14112), .O(n14283)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7d00 */ ; + defparam LUT__21475.LUTMASK = 16'h7d00; + EFX_LUT4 LUT__21476 (.I0(n14261), .I1(n14114), .I2(n14283), .I3(n14216), + .O(n14284)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b00 */ ; + defparam LUT__21476.LUTMASK = 16'h0b00; + EFX_LUT4 LUT__21477 (.I0(n14282), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .I2(n14284), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(n14285)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d00 */ ; + defparam LUT__21477.LUTMASK = 16'h0d00; + EFX_LUT4 LUT__21478 (.I0(n14281), .I1(ceg_net1036), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] ), + .I3(n14285), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4689 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h000b */ ; + defparam LUT__21478.LUTMASK = 16'h000b; + EFX_LUT4 LUT__21479 (.I0(n14013), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .O(n14286)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd0d0 */ ; + defparam LUT__21479.LUTMASK = 16'hd0d0; + EFX_LUT4 LUT__21480 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[5] ), + .I2(n14274), .O(n14287)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21480.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21481 (.I0(n14286), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6] ), + .I2(n14287), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8089 ), + .O(n14288)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00eb */ ; + defparam LUT__21481.LUTMASK = 16'h00eb; + EFX_LUT4 LUT__21482 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] ), + .I1(n14288), .I2(n14219), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4688 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf1f1 */ ; + defparam LUT__21482.LUTMASK = 16'hf1f1; + EFX_LUT4 LUT__21483 (.I0(n14112), .I1(n14107), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4602 ), + .O(n14289)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0007 */ ; + defparam LUT__21483.LUTMASK = 16'h0007; + EFX_LUT4 LUT__21484 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6] ), + .I1(n14287), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[36] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7] ), + .O(n14290)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0807 */ ; + defparam LUT__21484.LUTMASK = 16'h0807; + EFX_LUT4 LUT__21485 (.I0(n14278), .I1(n14008), .I2(n14290), .O(n14291)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__21485.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__21486 (.I0(n14200), .I1(n14289), .I2(n14291), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[8] ), + .O(n14292)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbb0f */ ; + defparam LUT__21486.LUTMASK = 16'hbb0f; + EFX_LUT4 LUT__21487 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6] ), + .I1(n14287), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7] ), + .I3(n14021), .O(n14293)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8700 */ ; + defparam LUT__21487.LUTMASK = 16'h8700; + EFX_LUT4 LUT__21488 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I2(n14292), .I3(n14293), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4687 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00bf */ ; + defparam LUT__21488.LUTMASK = 16'h00bf; + EFX_LUT4 LUT__21489 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[7] ), + .I2(n14287), .O(n14294)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21489.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21490 (.I0(n14219), .I1(n14022), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_raddr[8] ), + .I3(n14294), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4686 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'habba */ ; + defparam LUT__21490.LUTMASK = 16'habba; + EFX_LUT4 LUT__21491 (.I0(n14220), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0] ), + .I2(n14216), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1] ), + .O(n14295)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8a3f */ ; + defparam LUT__21491.LUTMASK = 16'h8a3f; + EFX_LUT4 LUT__21492 (.I0(n14295), .I1(n14221), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4683 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21492.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21493 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/arbiter_counter[1] ), + .I2(n14216), .I3(n14221), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4682 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21493.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21494 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[28] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3438 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff0b */ ; + defparam LUT__21494.LUTMASK = 16'hff0b; + EFX_LUT4 LUT__21495 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[28] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3437 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0230 */ ; + defparam LUT__21495.LUTMASK = 16'h0230; + EFX_LUT4 LUT__21496 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[28] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/odt_cnt[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3436 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0708 */ ; + defparam LUT__21496.LUTMASK = 16'h0708; + EFX_LUT4 LUT__21497 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .O(n14296)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21497.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21498 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I1(n14296), .I2(n14205), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14297)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0fbb */ ; + defparam LUT__21498.LUTMASK = 16'h0fbb; + EFX_LUT4 LUT__21499 (.I0(n14297), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[1] ), + .I2(n14225), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4650 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__21499.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__21500 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[11] ), + .O(n14298)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21500.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21501 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .O(n14299)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21501.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21502 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I1(n14299), .O(n14300)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21502.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21503 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I1(n14298), .I2(n14300), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14301)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0fbb */ ; + defparam LUT__21503.LUTMASK = 16'h0fbb; + EFX_LUT4 LUT__21504 (.I0(n14301), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[2] ), + .I2(n14225), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4649 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__21504.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__21505 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I1(n14299), .O(n14302)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21505.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21506 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I1(n14228), .I2(n14302), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14303)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0fbb */ ; + defparam LUT__21506.LUTMASK = 16'h0fbb; + EFX_LUT4 LUT__21507 (.I0(n14303), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[3] ), + .I2(n14225), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4648 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__21507.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__21508 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .O(n14304)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__21508.LUTMASK = 16'h1010; + EFX_LUT4 LUT__21509 (.I0(n14222), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I2(n14304), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14305)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0f77 */ ; + defparam LUT__21509.LUTMASK = 16'h0f77; + EFX_LUT4 LUT__21510 (.I0(n14305), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[4] ), + .I2(n14225), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4647 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__21510.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__21511 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .O(n14306)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__21511.LUTMASK = 16'h4040; + EFX_LUT4 LUT__21512 (.I0(n14296), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I2(n14306), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14307)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0f77 */ ; + defparam LUT__21512.LUTMASK = 16'h0f77; + EFX_LUT4 LUT__21513 (.I0(n14307), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[5] ), + .I2(n14225), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4646 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__21513.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__21514 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_aw_fifo_rd_data[12] ), + .O(n14308)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__21514.LUTMASK = 16'h4040; + EFX_LUT4 LUT__21515 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ar_fifo_rd_data[12] ), + .I1(n14298), .I2(n14308), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14309)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0f77 */ ; + defparam LUT__21515.LUTMASK = 16'h0f77; + EFX_LUT4 LUT__21516 (.I0(n14309), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[6] ), + .I2(n14225), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4645 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__21516.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__21517 (.I0(n14230), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/bank_activated[7] ), + .I2(n14225), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4644 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__21517.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__21518 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3857 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21518.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21519 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3856 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21519.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21520 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3855 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21520.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21521 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3854 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21521.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21522 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3853 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21522.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21523 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3852 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21523.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21524 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3851 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21524.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21525 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3850 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21525.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21526 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3849 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21526.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21527 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3848 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21527.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21528 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3847 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21528.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21529 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3846 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21529.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21530 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3845 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21530.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21531 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3844 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21531.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21532 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p0[15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p0[15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3843 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21532.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21533 (.I0(n14309), .I1(n14231), .O(ceg_net2663)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21533.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21534 (.I0(n14307), .I1(n14231), .O(ceg_net2727)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21534.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21535 (.I0(n14305), .I1(n14231), .O(ceg_net2791)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21535.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21536 (.I0(n14303), .I1(n14231), .O(ceg_net2855)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21536.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21537 (.I0(n14301), .I1(n14231), .O(ceg_net2919)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21537.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21538 (.I0(n14297), .I1(n14231), .O(ceg_net2983)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21538.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21539 (.I0(n14224), .I1(n14231), .O(ceg_net3047)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21539.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21540 (.I0(n14236), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/counter[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4728 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__21540.LUTMASK = 16'h7070; + EFX_LUT4 LUT__21541 (.I0(n2660), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4727 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21541.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21542 (.I0(n5105), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4726 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21542.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21543 (.I0(n5103), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4725 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21543.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21544 (.I0(n5101), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4724 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21544.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21545 (.I0(n5099), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4723 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21545.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21546 (.I0(n5097), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4722 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21546.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21547 (.I0(n5095), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4721 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21547.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21548 (.I0(n5093), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4720 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21548.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21549 (.I0(n5091), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4719 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21549.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21550 (.I0(n5089), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4718 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21550.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21551 (.I0(n5087), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4717 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21551.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21552 (.I0(n5085), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4716 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21552.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21553 (.I0(n5083), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4715 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21553.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21554 (.I0(n5082), .I1(ceg_net1030), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4714 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21554.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21555 (.I0(n2646), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4711 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21555.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21556 (.I0(n5132), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4710 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21556.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21557 (.I0(n5130), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4709 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21557.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21558 (.I0(n5128), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4708 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21558.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21559 (.I0(n5126), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4707 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21559.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21560 (.I0(n5124), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4706 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21560.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21561 (.I0(n5122), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4705 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21561.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21562 (.I0(n5120), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4704 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21562.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21563 (.I0(n5118), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4703 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21563.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21564 (.I0(n5116), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4702 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21564.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21565 (.I0(n5114), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4701 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21565.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21566 (.I0(n5112), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4700 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21566.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21567 (.I0(n5110), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4699 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21567.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21568 (.I0(n5108), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4698 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21568.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21569 (.I0(n5107), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n8102 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n4697 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21569.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21570 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/Latency_counter[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3331 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21570.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21571 (.I0(n2662), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3330 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21571.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21572 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5080), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3329 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21572.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21573 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5078), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3328 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21573.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21574 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5076), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3327 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21574.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21575 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5074), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3326 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21575.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21576 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5072), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3325 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21576.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21577 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5070), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3324 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21577.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21578 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5068), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3323 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21578.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21579 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5066), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3322 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21579.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21580 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5064), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3321 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21580.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21581 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5062), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3320 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21581.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21582 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5060), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3319 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21582.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21583 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5058), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3318 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21583.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21584 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/lat_start_count ), + .I1(n5057), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3317 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21584.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21585 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3138 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21585.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21586 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3137 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21586.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21587 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3136 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21587.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21588 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3135 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21588.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21589 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3134 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21589.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21590 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3133 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21590.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21591 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[7] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3132 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21591.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21592 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[8] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3131 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21592.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21593 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[9] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3130 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21593.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21594 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[10] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3129 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21594.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21595 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[11] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3128 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21595.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21596 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[12] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3127 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21596.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21597 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[13] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3126 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21597.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21598 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[14] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3125 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21598.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21599 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_addr_p[15] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3124 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21599.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21600 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3142 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21600.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21601 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrA_ba_p[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3141 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21601.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21602 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3163 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21602.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21603 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3162 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21603.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21604 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3161 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21604.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21605 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[4] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3160 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21605.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21606 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[5] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3159 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21606.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21607 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3158 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21607.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21608 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[7] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3157 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21608.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21609 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[8] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3156 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21609.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21610 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[9] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3155 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21610.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21611 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[10] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3154 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21611.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21612 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[11] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3153 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21612.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21613 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[12] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3152 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21613.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21614 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[13] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3151 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21614.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21615 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[14] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3150 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21615.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21616 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_addr_p[15] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3149 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21616.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21617 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3184 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21617.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21618 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/w_init_done ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ddrB_ba_p[2] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3183 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21618.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21619 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .O(n14310)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21619.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21620 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(n14244), .O(n14311)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21620.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21621 (.I0(n14243), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[10] ), + .I2(n14310), .I3(n14311), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3090 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff8 */ ; + defparam LUT__21621.LUTMASK = 16'hfff8; + EFX_LUT4 LUT__21622 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .O(n14312)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21622.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21623 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(n14244), .O(n14313)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21623.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21624 (.I0(n14243), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[11] ), + .I2(n14312), .I3(n14313), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3089 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff8 */ ; + defparam LUT__21624.LUTMASK = 16'hfff8; + EFX_LUT4 LUT__21625 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .O(n14314)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21625.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21626 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(n14244), .O(n14315)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21626.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21627 (.I0(n14243), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[12] ), + .I2(n14314), .I3(n14315), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3088 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff8 */ ; + defparam LUT__21627.LUTMASK = 16'hfff8; + EFX_LUT4 LUT__21628 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .O(n14316)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21628.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21629 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(n14244), .O(n14317)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21629.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21630 (.I0(n14243), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[13] ), + .I2(n14316), .I3(n14317), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3087 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff8 */ ; + defparam LUT__21630.LUTMASK = 16'hfff8; + EFX_LUT4 LUT__21631 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .O(n14318)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21631.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21632 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(n14244), .O(n14319)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21632.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21633 (.I0(n14243), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[14] ), + .I2(n14318), .I3(n14319), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3086 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff8 */ ; + defparam LUT__21633.LUTMASK = 16'hfff8; + EFX_LUT4 LUT__21634 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .O(n14320)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21634.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21635 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[6] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[6] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(n14244), .O(n14321)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21635.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21636 (.I0(n14243), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[15] ), + .I2(n14320), .I3(n14321), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3085 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff8 */ ; + defparam LUT__21636.LUTMASK = 16'hfff8; + EFX_LUT4 LUT__21637 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .O(n14322)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21637.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21638 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[7] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[7] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(n14244), .O(n14323)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21638.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21639 (.I0(n14243), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[16] ), + .I2(n14322), .I3(n14323), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3084 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff8 */ ; + defparam LUT__21639.LUTMASK = 16'hfff8; + EFX_LUT4 LUT__21640 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .O(n14324)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21640.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21641 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[8] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(n14244), .O(n14325)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21641.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21642 (.I0(n14243), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[17] ), + .I2(n14324), .I3(n14325), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3083 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff8 */ ; + defparam LUT__21642.LUTMASK = 16'hfff8; + EFX_LUT4 LUT__21643 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_col_p1[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_col_p1[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[43] ), + .O(n14326)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21643.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21644 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .I3(n14244), .O(n14327)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21644.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21645 (.I0(n14243), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[18] ), + .I2(n14326), .I3(n14327), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3082 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff8 */ ; + defparam LUT__21645.LUTMASK = 16'hfff8; + EFX_LUT4 LUT__21646 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[10] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[10] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14328)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21646.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21647 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[19] ), + .I1(n14328), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3061 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21647.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21648 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[11] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[11] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14329)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21648.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21649 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[20] ), + .I1(n14329), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3060 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21649.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21650 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[12] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14330)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21650.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21651 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[21] ), + .I1(n14330), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3059 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21651.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21652 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[13] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14331)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21652.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21653 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[22] ), + .I1(n14331), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3058 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21653.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21654 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[14] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14332)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21654.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21655 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[23] ), + .I1(n14332), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3057 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21655.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21656 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_row_p1[15] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_row_p1[15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(n14333)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21656.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21657 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[24] ), + .I1(n14333), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ram_bus[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3056 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21657.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21658 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[1] ), + .I2(n14247), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3100 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c0a */ ; + defparam LUT__21658.LUTMASK = 16'h0c0a; + EFX_LUT4 LUT__21659 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/rd_bank_p1[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/wr_bank_p1[2] ), + .I2(n14247), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/cur_rdwr ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n3099 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c0a */ ; + defparam LUT__21659.LUTMASK = 16'h0c0a; + EFX_LUT4 LUT__21660 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/ref_counter[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n45 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__21660.LUTMASK = 16'h7777; + EFX_LUT4 LUT__21661 (.I0(n2004), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n44 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21661.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21662 (.I0(n2076), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n43 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21662.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21663 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5236), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n42 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21663.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21664 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5234), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n41 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21664.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21665 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5232), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n40 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21665.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21666 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5230), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n39 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21666.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21667 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5228), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n38 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21667.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21668 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5226), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n37 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21668.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21669 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5224), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n36 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21669.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21670 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5222), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n35 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21670.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21671 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5220), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n34 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21671.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21672 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5218), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n33 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21672.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21673 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5216), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n32 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21673.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21674 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/r_ref_rst ), + .I1(n5215), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/n31 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21674.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21675 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_rst_3 ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/dffrs_29/i4_pre ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/rst_top0/genblk1[1].genblk1.genblk1.inst_sysclk_rstn/r_srst_1P[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21675.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21676 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n55 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21676.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21677 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n50 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0700 */ ; + defparam LUT__21677.LUTMASK = 16'h0700; + EFX_LUT4 LUT__21678 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start ), + .I1(\ddr3_ctl_axi/cal_shift_val[0] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n43 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21678.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21679 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n55 ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n97 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__21679.LUTMASK = 16'h1000; + EFX_LUT4 LUT__21680 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/ena_p ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_shift_ena ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n97 ), + .O(ceg_net1790)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__21680.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__21681 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n54 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21681.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21682 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[1] ), + .O(n14334)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21682.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21683 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2] ), + .I1(n14334), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n53 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21683.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21684 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[2] ), + .I1(n14334), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter[3] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n52 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21684.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21685 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start ), + .I1(\ddr3_ctl_axi/cal_shift_val[1] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n42 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21685.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21686 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/counter_start ), + .I1(\ddr3_ctl_axi/cal_shift_val[2] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/phase_u0/n41 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21686.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21687 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .O(n14335)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21687.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21688 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I1(n13693), .O(n14336)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21688.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21689 (.I0(n13678), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .O(n14337)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h004f */ ; + defparam LUT__21689.LUTMASK = 16'h004f; + EFX_LUT4 LUT__21690 (.I0(n13724), .I1(n14335), .I2(n14336), .I3(n14337), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2697 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0007 */ ; + defparam LUT__21690.LUTMASK = 16'h0007; + EFX_LUT4 LUT__21691 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .O(n14338)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfcc4 */ ; + defparam LUT__21691.LUTMASK = 16'hfcc4; + EFX_LUT4 LUT__21692 (.I0(n13724), .I1(n14338), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2696 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21692.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21693 (.I0(n13692), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I2(n13726), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2695 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0e0e */ ; + defparam LUT__21693.LUTMASK = 16'h0e0e; + EFX_LUT4 LUT__21694 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] ), + .I1(n13431), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1] ), + .I3(n13705), .O(n14339)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21694.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21695 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1] ), + .I2(n14339), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(n14340)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0fbb */ ; + defparam LUT__21695.LUTMASK = 16'h0fbb; + EFX_LUT4 LUT__21696 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] ), + .I1(n13415), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1] ), + .O(n14341)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__21696.LUTMASK = 16'h7878; + EFX_LUT4 LUT__21697 (.I0(n14341), .I1(n13721), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I3(n14340), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6308 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h888f */ ; + defparam LUT__21697.LUTMASK = 16'h888f; + EFX_LUT4 LUT__21698 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1658 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21698.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21699 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/loop_cnt[1] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n1652 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__21699.LUTMASK = 16'h6666; + EFX_LUT4 LUT__21700 (.I0(n5418), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[1] ), + .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5630 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__21700.LUTMASK = 16'hac00; + EFX_LUT4 LUT__21701 (.I0(n5416), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[2] ), + .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5637 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__21701.LUTMASK = 16'hac00; + EFX_LUT4 LUT__21702 (.I0(n5414), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[3] ), + .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5644 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__21702.LUTMASK = 16'hac00; + EFX_LUT4 LUT__21703 (.I0(n5412), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[4] ), + .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5651 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__21703.LUTMASK = 16'hac00; + EFX_LUT4 LUT__21704 (.I0(n5410), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[5] ), + .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5658 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__21704.LUTMASK = 16'hac00; + EFX_LUT4 LUT__21705 (.I0(n5408), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[6] ), + .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5665 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__21705.LUTMASK = 16'hac00; + EFX_LUT4 LUT__21706 (.I0(n5406), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[7] ), + .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5672 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__21706.LUTMASK = 16'hac00; + EFX_LUT4 LUT__21707 (.I0(n5404), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[8] ), + .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5679 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__21707.LUTMASK = 16'hac00; + EFX_LUT4 LUT__21708 (.I0(n5402), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[9] ), + .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5686 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__21708.LUTMASK = 16'hac00; + EFX_LUT4 LUT__21709 (.I0(n5400), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[10] ), + .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5693 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__21709.LUTMASK = 16'hac00; + EFX_LUT4 LUT__21710 (.I0(n5398), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_wr_addr[11] ), + .I2(n13431), .I3(n13725), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5700 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__21710.LUTMASK = 16'hac00; + EFX_LUT4 LUT__21711 (.I0(n13431), .I1(n13725), .O(n14342)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21711.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21712 (.I0(n5396), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5707 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21712.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21713 (.I0(n5394), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5714 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21713.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21714 (.I0(n5392), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5721 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21714.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21715 (.I0(n5390), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5728 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21715.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21716 (.I0(n5388), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5735 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21716.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21717 (.I0(n5386), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5742 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21717.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21718 (.I0(n5384), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5749 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21718.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21719 (.I0(n5382), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5756 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21719.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21720 (.I0(n5380), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5763 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21720.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21721 (.I0(n5378), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5770 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21721.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21722 (.I0(n5376), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5777 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21722.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21723 (.I0(n5374), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5784 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21723.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21724 (.I0(n5372), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5791 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21724.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21725 (.I0(n5370), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5798 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21725.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21726 (.I0(n5368), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5805 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21726.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21727 (.I0(n5366), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5812 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21727.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21728 (.I0(n5364), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5819 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21728.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21729 (.I0(n5362), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5826 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21729.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21730 (.I0(n5360), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5833 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21730.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21731 (.I0(n5359), .I1(n14342), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5840 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21731.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21732 (.I0(n1259), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7726 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21732.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21733 (.I0(n13717), .I1(n13415), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(n14343)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21733.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21734 (.I0(n14343), .I1(n13691), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .O(n14344)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__21734.LUTMASK = 16'hca00; + EFX_LUT4 LUT__21735 (.I0(n13705), .I1(n14336), .I2(n14344), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .O(ceg_net4402)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff0b */ ; + defparam LUT__21735.LUTMASK = 16'hff0b; + EFX_LUT4 LUT__21736 (.I0(n5357), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5847 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21736.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21737 (.I0(n5355), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5854 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21737.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21738 (.I0(n5353), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5861 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21738.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21739 (.I0(n5351), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5868 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21739.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21740 (.I0(n5349), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5875 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21740.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21741 (.I0(n5347), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5882 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21741.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21742 (.I0(n5345), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5889 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21742.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21743 (.I0(n5343), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5896 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21743.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21744 (.I0(n5341), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5903 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21744.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21745 (.I0(n5339), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5910 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21745.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21746 (.I0(n5337), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5917 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21746.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21747 (.I0(n5335), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5924 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21747.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21748 (.I0(n5333), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5931 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21748.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21749 (.I0(n5331), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5938 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21749.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21750 (.I0(n5329), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5945 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21750.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21751 (.I0(n5327), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5952 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21751.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21752 (.I0(n5325), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5959 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21752.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21753 (.I0(n5323), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5966 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21753.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21754 (.I0(n5321), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5973 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21754.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21755 (.I0(n5319), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5980 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21755.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21756 (.I0(n5317), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5987 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21756.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21757 (.I0(n5315), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5994 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21757.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21758 (.I0(n5313), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6001 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21758.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21759 (.I0(n5311), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6008 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21759.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21760 (.I0(n5309), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6015 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21760.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21761 (.I0(n5307), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6022 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21761.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21762 (.I0(n5305), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6029 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21762.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21763 (.I0(n5303), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6036 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21763.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21764 (.I0(n5301), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6043 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21764.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21765 (.I0(n5299), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6050 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21765.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21766 (.I0(n5298), .I1(n13723), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n6057 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21766.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21767 (.I0(n13415), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0] ), + .I2(n13721), .O(n14345)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__21767.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__21768 (.I0(n13431), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/inc_addr_p[0] ), + .I2(n13725), .I3(n14345), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n7737 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hffe0 */ ; + defparam LUT__21768.LUTMASK = 16'hffe0; + EFX_LUT4 LUT__21769 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(ceg_net3459)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hebff */ ; + defparam LUT__21769.LUTMASK = 16'hebff; + EFX_LUT4 LUT__21770 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_run ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[0] ), + .O(n14346)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21770.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21771 (.I0(n13476), .I1(n14346), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2837 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21771.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21772 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_data[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/w_ack_rd_valid ), + .I3(n14346), .O(n14347)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21772.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21773 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2] ), + .I1(n14347), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2836 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21773.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21774 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2] ), + .I1(n14347), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2835 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21774.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21775 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3] ), + .I2(n14347), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4] ), + .O(n14348)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__21775.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__21776 (.I0(n14348), .I1(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2834 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21776.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21777 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4] ), + .I3(n14347), .O(n14349)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21777.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21778 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5] ), + .I1(n14349), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2833 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21778.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21779 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5] ), + .I1(n14349), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2832 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21779.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21780 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[5] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[6] ), + .O(n14350)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21780.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21781 (.I0(n14349), .I1(n14350), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2831 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21781.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21782 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[7] ), + .I1(n14350), .O(n14351)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21782.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21783 (.I0(n14349), .I1(n14351), .O(n14352)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21783.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21784 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8] ), + .I1(n14352), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2830 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21784.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21785 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8] ), + .I1(n14352), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2829 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21785.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21786 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9] ), + .I2(n14352), .O(n14353)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21786.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21787 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10] ), + .I1(n14353), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2828 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21787.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21788 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10] ), + .I1(n14353), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2827 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21788.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21789 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[9] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[10] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[11] ), + .O(n14354)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21789.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21790 (.I0(n14352), .I1(n14354), .O(n14355)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21790.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21791 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12] ), + .I1(n14355), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2826 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21791.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21792 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12] ), + .I1(n14355), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2825 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21792.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21793 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13] ), + .I2(n14354), .O(n14356)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21793.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21794 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[3] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[4] ), + .I3(n14351), .O(n14357)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21794.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21795 (.I0(n14347), .I1(n14356), .I2(n14357), .O(n14358)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21795.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21796 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14] ), + .I1(n14358), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2824 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21796.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21797 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[13] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14] ), + .I3(n14355), .O(n14359)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21797.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21798 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15] ), + .I1(n14359), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2823 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21798.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21799 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15] ), + .I1(n14359), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2822 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21799.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21800 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[15] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[16] ), + .O(n14360)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21800.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21801 (.I0(n14347), .I1(n14356), .I2(n14357), .I3(n14360), + .O(n14361)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21801.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21802 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17] ), + .I1(n14361), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2821 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21802.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21803 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[17] ), + .I1(n14361), .O(n14362)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21803.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21804 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18] ), + .I1(n14362), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2820 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21804.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21805 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18] ), + .I1(n14362), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2819 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21805.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21806 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[18] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[19] ), + .I2(n14362), .O(n14363)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21806.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21807 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20] ), + .I1(n14363), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2818 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21807.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21808 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20] ), + .I1(n14363), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2817 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21808.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21809 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[20] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[21] ), + .O(n14364)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21809.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21810 (.I0(n14363), .I1(n14364), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2816 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21810.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21811 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[22] ), + .I1(n14364), .O(n14365)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21811.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21812 (.I0(n14363), .I1(n14365), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2815 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21812.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21813 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[23] ), + .I1(n14365), .O(n14366)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21813.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21814 (.I0(n14363), .I1(n14366), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2814 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21814.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21815 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24] ), + .I1(n14363), .I2(n14366), .O(n14367)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21815.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21816 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25] ), + .I1(n14367), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2813 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21816.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21817 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[24] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[25] ), + .I2(n14363), .I3(n14366), .O(n14368)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21817.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21818 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26] ), + .I1(n14368), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2812 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21818.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21819 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26] ), + .I1(n14368), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2811 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21819.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21820 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[26] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[27] ), + .O(n14369)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21820.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21821 (.I0(n14368), .I1(n14369), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2810 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21821.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21822 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[28] ), + .I1(n14369), .O(n14370)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21822.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21823 (.I0(n14368), .I1(n14370), .O(n14371)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21823.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21824 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29] ), + .I1(n14371), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2809 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21824.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21825 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[29] ), + .I1(n14368), .I2(n14370), .O(n14372)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21825.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21826 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30] ), + .I1(n14372), .I2(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2808 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21826.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21827 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[30] ), + .I1(n14372), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/ack_cnt[31] ), + .I3(n13728), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2807 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21827.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21828 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .O(n14373)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21828.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21829 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1] ), + .I1(n14373), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2895 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21829.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21830 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1] ), + .I1(n14373), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2894 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21830.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21831 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2] ), + .I2(n14373), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3] ), + .O(n14374)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ; + defparam LUT__21831.LUTMASK = 16'h7f80; + EFX_LUT4 LUT__21832 (.I0(n14374), .I1(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2893 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21832.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21833 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[3] ), + .O(n14375)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21833.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21834 (.I0(n14373), .I1(n14375), .O(n14376)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21834.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21835 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4] ), + .I1(n14376), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2892 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21835.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21836 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4] ), + .I1(n14376), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2891 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21836.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21837 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5] ), + .I2(n14376), .O(n14377)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21837.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21838 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6] ), + .I1(n14377), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2890 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21838.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21839 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6] ), + .I1(n14377), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2889 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21839.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21840 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[4] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[5] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[6] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[7] ), + .O(n14378)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21840.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21841 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .I2(n14375), .I3(n14378), .O(n14379)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21841.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21842 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8] ), + .I1(n14379), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2888 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21842.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21843 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8] ), + .I1(n14379), .O(n14380)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21843.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21844 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9] ), + .I1(n14380), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2887 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21844.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21845 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9] ), + .I1(n14380), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2886 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21845.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21846 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[9] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[10] ), + .O(n14381)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21846.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21847 (.I0(n14380), .I1(n14381), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2885 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21847.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21848 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[8] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[11] ), + .I2(n14379), .I3(n14381), .O(n14382)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21848.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21849 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12] ), + .I1(n14382), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2884 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21849.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21850 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12] ), + .I1(n14382), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2883 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21850.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21851 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[12] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[13] ), + .I2(n14382), .O(n14383)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21851.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21852 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14] ), + .I1(n14383), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2882 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21852.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21853 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14] ), + .I1(n14383), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2881 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21853.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21854 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[14] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[15] ), + .O(n14384)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21854.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21855 (.I0(n14383), .I1(n14384), .O(n14385)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21855.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21856 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16] ), + .I1(n14385), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2880 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21856.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21857 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16] ), + .I1(n14385), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2879 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21857.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21858 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[16] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[17] ), + .I2(n14384), .O(n14386)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21858.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21859 (.I0(n14383), .I1(n14386), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2878 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21859.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21860 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[18] ), + .I1(n14386), .O(n14387)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21860.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21861 (.I0(n14383), .I1(n14387), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2877 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21861.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21862 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[19] ), + .I1(n14383), .I2(n14387), .O(n14388)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21862.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21863 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20] ), + .I1(n14388), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2876 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21863.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21864 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20] ), + .I1(n14388), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2875 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21864.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21865 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[20] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[21] ), + .O(n14389)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21865.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21866 (.I0(n14388), .I1(n14389), .O(n14390)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21866.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21867 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22] ), + .I1(n14390), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2874 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21867.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21868 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22] ), + .I1(n14390), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2873 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21868.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21869 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[22] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[23] ), + .I2(n14389), .O(n14391)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21869.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21870 (.I0(n14388), .I1(n14391), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2872 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21870.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21871 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[24] ), + .I1(n14391), .O(n14392)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21871.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21872 (.I0(n14388), .I1(n14392), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2871 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21872.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21873 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25] ), + .I1(n14388), .I2(n14392), .O(n14393)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21873.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21874 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26] ), + .I1(n14393), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2870 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21874.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21875 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[25] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[26] ), + .I2(n14388), .I3(n14392), .O(n14394)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21875.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21876 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27] ), + .I1(n14394), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2869 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21876.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21877 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27] ), + .I1(n14394), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2868 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21877.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21878 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[27] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[28] ), + .O(n14395)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21878.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21879 (.I0(n14394), .I1(n14395), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2867 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21879.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21880 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[29] ), + .I1(n14394), .I2(n14395), .O(n14396)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21880.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21881 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30] ), + .I1(n14396), .I2(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2866 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__21881.LUTMASK = 16'h6060; + EFX_LUT4 LUT__21882 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[30] ), + .I1(n14396), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_sub_cnt[31] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2865 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21882.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21883 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/w_o_rd_valid ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cmp_cnt[1] ), + .I3(n13729), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2862 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__21883.LUTMASK = 16'h7800; + EFX_LUT4 LUT__21884 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7] ), + .I1(\ddr3_ctl_axi/cal_fail_log[5] ), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1] ), + .O(n14397)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21884.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21885 (.I0(\ddr3_ctl_axi/cal_fail_log[6] ), .I1(\ddr3_ctl_axi/cal_fail_log[4] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1] ), + .O(n14398)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21885.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21886 (.I0(n14398), .I1(n14397), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2] ), + .O(n14399)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3500 */ ; + defparam LUT__21886.LUTMASK = 16'h3500; + EFX_LUT4 LUT__21887 (.I0(\ddr3_ctl_axi/cal_fail_log[3] ), .I1(\ddr3_ctl_axi/cal_fail_log[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1] ), + .O(n14400)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21887.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21888 (.I0(\ddr3_ctl_axi/cal_fail_log[2] ), .I1(\ddr3_ctl_axi/cal_fail_log[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1] ), + .O(n14401)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__21888.LUTMASK = 16'hacac; + EFX_LUT4 LUT__21889 (.I0(n14401), .I1(n14400), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0] ), + .O(n14402)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0305 */ ; + defparam LUT__21889.LUTMASK = 16'h0305; + EFX_LUT4 LUT__21890 (.I0(n14399), .I1(n14402), .O(n14403)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21890.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21891 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[0] ), + .I2(n14403), .O(n14404)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21891.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21892 (.I0(\ddr3_ctl_axi/cal_shift_val[0] ), .I1(n14404), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2693 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc5c5 */ ; + defparam LUT__21892.LUTMASK = 16'hc5c5; + EFX_LUT4 LUT__21893 (.I0(n13680), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_cal_end ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n9138 ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n8144 ), + .O(ceg_net3510)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hef00 */ ; + defparam LUT__21893.LUTMASK = 16'hef00; + EFX_LUT4 LUT__21894 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[1] ), + .I2(n14403), .O(n14405)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21894.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21895 (.I0(n14405), .I1(\ddr3_ctl_axi/cal_shift_val[0] ), + .I2(\ddr3_ctl_axi/cal_shift_val[1] ), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2692 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'haa3c */ ; + defparam LUT__21895.LUTMASK = 16'haa3c; + EFX_LUT4 LUT__21896 (.I0(n14402), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2] ), + .I2(n14399), .O(n14406)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__21896.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__21897 (.I0(\ddr3_ctl_axi/cal_shift_val[0] ), .I1(\ddr3_ctl_axi/cal_shift_val[1] ), + .I2(\ddr3_ctl_axi/cal_shift_val[2] ), .O(n14407)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__21897.LUTMASK = 16'h7878; + EFX_LUT4 LUT__21898 (.I0(n14407), .I1(n14406), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[3] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2691 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3a3a */ ; + defparam LUT__21898.LUTMASK = 16'h3a3a; + EFX_LUT4 LUT__21899 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/bFail ), + .I1(\ddr3_ctl_axi/cal_shift_val[0] ), .O(n14408)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21899.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21900 (.I0(\ddr3_ctl_axi/cal_shift_val[2] ), .I1(\ddr3_ctl_axi/cal_shift_val[1] ), + .I2(n14408), .I3(\ddr3_ctl_axi/cal_fail_log[1] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2397 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff10 */ ; + defparam LUT__21900.LUTMASK = 16'hff10; + EFX_LUT4 LUT__21901 (.I0(\ddr3_ctl_axi/cal_shift_val[2] ), .I1(\ddr3_ctl_axi/cal_shift_val[1] ), + .I2(n13817), .I3(\ddr3_ctl_axi/cal_fail_log[2] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2396 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff40 */ ; + defparam LUT__21901.LUTMASK = 16'hff40; + EFX_LUT4 LUT__21902 (.I0(\ddr3_ctl_axi/cal_shift_val[2] ), .I1(\ddr3_ctl_axi/cal_shift_val[1] ), + .I2(n14408), .I3(\ddr3_ctl_axi/cal_fail_log[3] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2395 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff40 */ ; + defparam LUT__21902.LUTMASK = 16'hff40; + EFX_LUT4 LUT__21903 (.I0(\ddr3_ctl_axi/cal_shift_val[1] ), .I1(\ddr3_ctl_axi/cal_shift_val[2] ), + .I2(n13817), .I3(\ddr3_ctl_axi/cal_fail_log[4] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2394 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff40 */ ; + defparam LUT__21903.LUTMASK = 16'hff40; + EFX_LUT4 LUT__21904 (.I0(\ddr3_ctl_axi/cal_shift_val[1] ), .I1(\ddr3_ctl_axi/cal_shift_val[2] ), + .I2(n14408), .I3(\ddr3_ctl_axi/cal_fail_log[5] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2393 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff40 */ ; + defparam LUT__21904.LUTMASK = 16'hff40; + EFX_LUT4 LUT__21905 (.I0(n13817), .I1(\ddr3_ctl_axi/cal_shift_val[2] ), + .I2(\ddr3_ctl_axi/cal_shift_val[1] ), .I3(\ddr3_ctl_axi/cal_fail_log[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2392 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff80 */ ; + defparam LUT__21905.LUTMASK = 16'hff80; + EFX_LUT4 LUT__21906 (.I0(n14408), .I1(\ddr3_ctl_axi/cal_shift_val[2] ), + .I2(\ddr3_ctl_axi/cal_shift_val[1] ), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/Fail_log[7] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2391 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff80 */ ; + defparam LUT__21906.LUTMASK = 16'hff80; + EFX_LUT4 LUT__21907 (.I0(\ddr3_ctl_axi/cal_fail_log[2] ), .I1(\ddr3_ctl_axi/cal_fail_log[3] ), + .O(n14409)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21907.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21908 (.I0(n14409), .I1(n13820), .I2(\ddr3_ctl_axi/cal_fail_log[0] ), + .I3(\ddr3_ctl_axi/cal_fail_log[1] ), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2588 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd000 */ ; + defparam LUT__21908.LUTMASK = 16'hd000; + EFX_LUT4 LUT__21909 (.I0(n14409), .I1(n13820), .I2(\ddr3_ctl_axi/cal_fail_log[6] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2553 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4f4f */ ; + defparam LUT__21909.LUTMASK = 16'h4f4f; + EFX_LUT4 LUT__21910 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5457 ), + .I1(n13824), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2630 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21910.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21911 (.I0(\ddr3_ctl_axi/cal_fail_log[5] ), .I1(\ddr3_ctl_axi/cal_fail_log[3] ), + .I2(\ddr3_ctl_axi/cal_fail_log[4] ), .O(n14410)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5c5c */ ; + defparam LUT__21911.LUTMASK = 16'h5c5c; + EFX_LUT4 LUT__21912 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5469 ), + .I1(n14410), .I2(\ddr3_ctl_axi/cal_fail_log[1] ), .I3(\ddr3_ctl_axi/cal_fail_log[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n2672 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb0bb */ ; + defparam LUT__21912.LUTMASK = 16'hb0bb; + EFX_LUT4 LUT__21913 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1] ), + .O(n14411)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8778 */ ; + defparam LUT__21913.LUTMASK = 16'h8778; + EFX_LUT4 LUT__21914 (.I0(n14411), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5542 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21914.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21915 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[0] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[0] ), + .O(n14412)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1777 */ ; + defparam LUT__21915.LUTMASK = 16'h1777; + EFX_LUT4 LUT__21916 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2] ), + .O(n14413)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__21916.LUTMASK = 16'h6666; + EFX_LUT4 LUT__21917 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val_round[3] ), + .I1(n14412), .I2(n14413), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5546 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'haac3 */ ; + defparam LUT__21917.LUTMASK = 16'haac3; + EFX_LUT4 LUT__21918 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass_round[2] ), + .I2(n14412), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass_round[3] ), + .O(n14414)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h718e */ ; + defparam LUT__21918.LUTMASK = 16'h718e; + EFX_LUT4 LUT__21919 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .I1(n14414), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5550 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21919.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21920 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1] ), + .O(n14415)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8778 */ ; + defparam LUT__21920.LUTMASK = 16'h8778; + EFX_LUT4 LUT__21921 (.I0(n14415), .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[2] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5530 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21921.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21922 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[1] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[1] ), + .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[0] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[0] ), + .O(n14416)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1777 */ ; + defparam LUT__21922.LUTMASK = 16'h1777; + EFX_LUT4 LUT__21923 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2] ), + .I1(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2] ), + .O(n14417)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__21923.LUTMASK = 16'h6666; + EFX_LUT4 LUT__21924 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/cal_val[3] ), + .I1(n14416), .I2(n14417), .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5534 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'haac3 */ ; + defparam LUT__21924.LUTMASK = 16'haac3; + EFX_LUT4 LUT__21925 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_first_pass[2] ), + .I1(n14416), .I2(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/r_last_pass[2] ), + .I3(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/test_state[0] ), + .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/n5538 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00b2 */ ; + defparam LUT__21925.LUTMASK = 16'h00b2; + EFX_LUT4 LUT__21926 (.I0(n13505), .I1(n176), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1336 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21926.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21927 (.I0(n13505), .I1(n5660), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1335 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21927.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21928 (.I0(n13505), .I1(n5658), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1334 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21928.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21929 (.I0(n13505), .I1(n5656), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1333 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21929.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21930 (.I0(n13505), .I1(n5654), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21930.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21931 (.I0(n13505), .I1(n5652), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1331 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21931.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21932 (.I0(n13505), .I1(n5650), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1330 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21932.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21933 (.I0(n13505), .I1(n5648), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1329 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21933.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21934 (.I0(n13505), .I1(n5646), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1328 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21934.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21935 (.I0(n13505), .I1(n5644), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1327 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21935.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21936 (.I0(n13505), .I1(n5642), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1326 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21936.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21937 (.I0(n13505), .I1(n5640), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1325 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21937.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21938 (.I0(n13505), .I1(n5638), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1324 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21938.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21939 (.I0(n13505), .I1(n5636), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1323 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21939.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21940 (.I0(n13505), .I1(n5635), .O(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1322 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21940.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21941 (.I0(w_ddr3_arvalid), .I1(w_ddr3_awvalid), .I2(w_ddr3_atype), + .O(n14418)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__21941.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__21942 (.I0(\axi4_awar_mux/rs_req[1] ), .I1(n14418), .O(n14419)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21942.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21943 (.I0(\axi4_awar_mux/rs_req[1] ), .I1(\axi4_awar_mux/rs_req[0] ), + .I2(n13489), .O(\axi4_awar_mux/n129 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__21943.LUTMASK = 16'h4040; + EFX_LUT4 LUT__21944 (.I0(n14419), .I1(\axi4_awar_mux/rs_req[0] ), .I2(\axi4_awar_mux/n129 ), + .O(\axi4_awar_mux/n50 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0e0e */ ; + defparam LUT__21944.LUTMASK = 16'h0e0e; + EFX_LUT4 LUT__21945 (.I0(\axi4_awar_mux/rs_req[0] ), .I1(n14419), .I2(w_ddr3_avalid), + .I3(\axi4_awar_mux/n129 ), .O(\axi4_awar_mux/n52 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f4 */ ; + defparam LUT__21945.LUTMASK = 16'h00f4; + EFX_LUT4 LUT__21946 (.I0(\axi4_awar_mux/rs_req[0] ), .I1(\axi4_awar_mux/rs_req[1] ), + .O(\axi4_awar_mux/n45 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21946.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21947 (.I0(n14418), .I1(n13489), .I2(\axi4_awar_mux/rs_req[1] ), + .I3(\axi4_awar_mux/rs_req[0] ), .O(\axi4_awar_mux/n49 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc05 */ ; + defparam LUT__21947.LUTMASK = 16'hfc05; + EFX_LUT4 LUT__21948 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[0] ), .I1(\u_i2c_timing_ctrl_16bit/clk_cnt[1] ), + .I2(\u_i2c_timing_ctrl_16bit/clk_cnt[2] ), .I3(\u_i2c_timing_ctrl_16bit/clk_cnt[3] ), + .O(n14420)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21948.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21949 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[4] ), .I1(\u_i2c_timing_ctrl_16bit/clk_cnt[5] ), + .I2(n14420), .O(n14421)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21949.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21950 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[8] ), .I1(\u_i2c_timing_ctrl_16bit/clk_cnt[9] ), + .I2(\u_i2c_timing_ctrl_16bit/clk_cnt[10] ), .O(n14422)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21950.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21951 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[6] ), .I1(n14421), + .I2(\u_i2c_timing_ctrl_16bit/clk_cnt[7] ), .I3(n14422), .O(n14423)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__21951.LUTMASK = 16'hf800; + EFX_LUT4 LUT__21952 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[8] ), .I1(\u_i2c_timing_ctrl_16bit/delay_cnt[9] ), + .I2(\u_i2c_timing_ctrl_16bit/delay_cnt[10] ), .I3(\u_i2c_timing_ctrl_16bit/delay_cnt[11] ), + .O(n14424)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h007f */ ; + defparam LUT__21952.LUTMASK = 16'h007f; + EFX_LUT4 LUT__21953 (.I0(n14424), .I1(\u_i2c_timing_ctrl_16bit/delay_cnt[13] ), + .I2(\u_i2c_timing_ctrl_16bit/delay_cnt[14] ), .I3(\u_i2c_timing_ctrl_16bit/delay_cnt[12] ), + .O(n14425)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__21953.LUTMASK = 16'h4000; + EFX_LUT4 LUT__21954 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[2] ), .I1(\u_i2c_timing_ctrl_16bit/delay_cnt[3] ), + .I2(\u_i2c_timing_ctrl_16bit/delay_cnt[4] ), .I3(\u_i2c_timing_ctrl_16bit/delay_cnt[6] ), + .O(n14426)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21954.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21955 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[1] ), .I1(\u_i2c_timing_ctrl_16bit/delay_cnt[5] ), + .I2(\u_i2c_timing_ctrl_16bit/delay_cnt[7] ), .I3(\u_i2c_timing_ctrl_16bit/delay_cnt[11] ), + .O(n14427)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21955.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21956 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[17] ), .I1(\u_i2c_timing_ctrl_16bit/delay_cnt[18] ), + .I2(\u_i2c_timing_ctrl_16bit/delay_cnt[19] ), .O(n14428)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__21956.LUTMASK = 16'h0101; + EFX_LUT4 LUT__21957 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[0] ), .I1(\u_i2c_timing_ctrl_16bit/delay_cnt[15] ), + .I2(\u_i2c_timing_ctrl_16bit/delay_cnt[16] ), .I3(n14428), .O(n14429)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__21957.LUTMASK = 16'h1000; + EFX_LUT4 LUT__21958 (.I0(n14425), .I1(n14426), .I2(n14427), .I3(n14429), + .O(n14430)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__21958.LUTMASK = 16'h8000; + EFX_LUT4 LUT__21959 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[12] ), .I1(\u_i2c_timing_ctrl_16bit/clk_cnt[13] ), + .I2(\u_i2c_timing_ctrl_16bit/clk_cnt[14] ), .I3(\u_i2c_timing_ctrl_16bit/clk_cnt[15] ), + .O(n14431)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21959.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21960 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[11] ), .I1(n14430), + .I2(n14431), .O(n14432)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__21960.LUTMASK = 16'h4040; + EFX_LUT4 LUT__21961 (.I0(n14423), .I1(n14432), .O(n14433)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21961.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21962 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[0] ), .I1(n14433), + .O(\u_i2c_timing_ctrl_16bit/n137 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21962.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21963 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[0] ), .I1(\u_i2c_timing_ctrl_16bit/clk_cnt[1] ), + .I2(\u_i2c_timing_ctrl_16bit/clk_cnt[2] ), .I3(\u_i2c_timing_ctrl_16bit/clk_cnt[3] ), + .O(n14434)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21963.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21964 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[4] ), .I1(n14434), + .O(n14435)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21964.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21965 (.I0(n14435), .I1(\u_i2c_timing_ctrl_16bit/clk_cnt[5] ), + .O(n14436)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21965.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21966 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[7] ), .I1(\u_i2c_timing_ctrl_16bit/clk_cnt[8] ), + .O(n14437)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21966.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21967 (.I0(n14437), .I1(n14436), .I2(\u_i2c_timing_ctrl_16bit/clk_cnt[6] ), + .I3(\u_i2c_timing_ctrl_16bit/clk_cnt[10] ), .O(n14438)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha87f */ ; + defparam LUT__21967.LUTMASK = 16'ha87f; + EFX_LUT4 LUT__21968 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[10] ), .I1(n14438), + .I2(\u_i2c_timing_ctrl_16bit/clk_cnt[9] ), .O(n14439)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5353 */ ; + defparam LUT__21968.LUTMASK = 16'h5353; + EFX_LUT4 LUT__21969 (.I0(n14439), .I1(n14432), .O(\u_i2c_timing_ctrl_16bit/n138 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21969.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21970 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[6] ), .I1(\u_i2c_timing_ctrl_16bit/clk_cnt[10] ), + .I2(n14432), .O(n14440)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__21970.LUTMASK = 16'h1010; + EFX_LUT4 LUT__21971 (.I0(\u_i2c_timing_ctrl_16bit/clk_cnt[5] ), .I1(\u_i2c_timing_ctrl_16bit/clk_cnt[7] ), + .I2(\u_i2c_timing_ctrl_16bit/clk_cnt[8] ), .I3(\u_i2c_timing_ctrl_16bit/clk_cnt[9] ), + .O(n14441)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21971.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21972 (.I0(n14435), .I1(n14440), .I2(n14441), .O(\u_i2c_timing_ctrl_16bit/n139 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21972.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21974 (.I0(\sc130_i2c_config_index[2] ), .I1(\sc130_i2c_config_index[3] ), + .O(n14442)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21974.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21975 (.I0(\sc130_i2c_config_index[0] ), .I1(\sc130_i2c_config_index[1] ), + .O(n14443)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21975.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21976 (.I0(\sc130_i2c_config_index[2] ), .I1(\sc130_i2c_config_index[3] ), + .O(n14444)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21976.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21977 (.I0(n14443), .I1(n14444), .O(n14445)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21977.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21978 (.I0(\sc130_i2c_config_index[4] ), .I1(n14442), + .I2(n14445), .O(n14446)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__21978.LUTMASK = 16'h0101; + EFX_LUT4 LUT__21979 (.I0(n14446), .I1(\sc130_i2c_config_index[5] ), + .I2(\sc130_i2c_config_index[6] ), .I3(\sc130_i2c_config_index[7] ), + .O(n14447)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00bf */ ; + defparam LUT__21979.LUTMASK = 16'h00bf; + EFX_LUT4 LUT__21980 (.I0(\sc130_i2c_config_index[0] ), .I1(n14447), + .O(\u_i2c_timing_ctrl_16bit/n198 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7777 */ ; + defparam LUT__21980.LUTMASK = 16'h7777; + EFX_LUT4 LUT__21981 (.I0(\u_i2c_timing_ctrl_16bit/current_state[2] ), + .I1(\u_i2c_timing_ctrl_16bit/current_state[3] ), .O(n14448)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21981.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21982 (.I0(\u_i2c_timing_ctrl_16bit/current_state[0] ), + .I1(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), .I2(\u_i2c_timing_ctrl_16bit/current_state[1] ), + .I3(n14448), .O(\u_i2c_timing_ctrl_16bit/n497 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__21982.LUTMASK = 16'h4000; + EFX_LUT4 LUT__21983 (.I0(n14430), .I1(n14447), .I2(\u_i2c_timing_ctrl_16bit/current_state[0] ), + .I3(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), .O(n14449)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf70f */ ; + defparam LUT__21983.LUTMASK = 16'hf70f; + EFX_LUT4 LUT__21984 (.I0(\u_i2c_timing_ctrl_16bit/current_state[1] ), + .I1(\u_i2c_timing_ctrl_16bit/current_state[2] ), .I2(\u_i2c_timing_ctrl_16bit/current_state[3] ), + .I3(n14449), .O(n14450)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__21984.LUTMASK = 16'h0001; + EFX_LUT4 LUT__21985 (.I0(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0] ), + .I1(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1] ), .I2(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2] ), + .I3(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3] ), .O(n14451)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__21985.LUTMASK = 16'h0100; + EFX_LUT4 LUT__21986 (.I0(n14451), .I1(\u_i2c_timing_ctrl_16bit/current_state[0] ), + .I2(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), .I3(n13395), + .O(n14452)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h2c00 */ ; + defparam LUT__21986.LUTMASK = 16'h2c00; + EFX_LUT4 LUT__21987 (.I0(n14450), .I1(n14452), .O(\u_i2c_timing_ctrl_16bit/next_state[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heeee */ ; + defparam LUT__21987.LUTMASK = 16'heeee; + EFX_LUT4 LUT__21988 (.I0(\u_i2c_timing_ctrl_16bit/current_state[0] ), + .I1(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), .I2(\u_i2c_timing_ctrl_16bit/current_state[1] ), + .O(n14453)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__21988.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__21989 (.I0(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), .I1(\u_i2c_timing_ctrl_16bit/current_state[0] ), + .I2(\u_i2c_timing_ctrl_16bit/current_state[1] ), .O(n14454)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__21989.LUTMASK = 16'h8080; + EFX_LUT4 LUT__21990 (.I0(n14453), .I1(\u_i2c_timing_ctrl_16bit/current_state[2] ), + .I2(n14454), .I3(\u_i2c_timing_ctrl_16bit/current_state[3] ), + .O(n14455)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heef0 */ ; + defparam LUT__21990.LUTMASK = 16'heef0; + EFX_LUT4 LUT__21991 (.I0(\u_i2c_timing_ctrl_16bit/current_state[0] ), + .I1(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), .I2(\u_i2c_timing_ctrl_16bit/current_state[1] ), + .I3(n14455), .O(\u_i2c_timing_ctrl_16bit/next_state[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f8 */ ; + defparam LUT__21991.LUTMASK = 16'h00f8; + EFX_LUT4 LUT__21992 (.I0(\u_i2c_timing_ctrl_16bit/current_state[3] ), + .I1(\u_i2c_timing_ctrl_16bit/current_state[2] ), .I2(n14454), + .O(\u_i2c_timing_ctrl_16bit/next_state[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1414 */ ; + defparam LUT__21992.LUTMASK = 16'h1414; + EFX_LUT4 LUT__21993 (.I0(n14453), .I1(n14454), .I2(\u_i2c_timing_ctrl_16bit/current_state[2] ), + .I3(\u_i2c_timing_ctrl_16bit/current_state[3] ), .O(\u_i2c_timing_ctrl_16bit/next_state[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h05c0 */ ; + defparam LUT__21993.LUTMASK = 16'h05c0; + EFX_LUT4 LUT__21994 (.I0(\u_i2c_timing_ctrl_16bit/next_state[2] ), .I1(\u_i2c_timing_ctrl_16bit/next_state[3] ), + .O(n14456)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21994.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21995 (.I0(\u_i2c_timing_ctrl_16bit/next_state[1] ), .I1(n14456), + .O(n14457)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21995.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21996 (.I0(\u_i2c_timing_ctrl_16bit/next_state[0] ), .I1(n14457), + .O(n14458)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__21996.LUTMASK = 16'h1111; + EFX_LUT4 LUT__21997 (.I0(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0] ), + .I1(n14458), .O(\u_i2c_timing_ctrl_16bit/n333 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21997.LUTMASK = 16'h4444; + EFX_LUT4 LUT__21998 (.I0(\u_i2c_timing_ctrl_16bit/next_state[1] ), .I1(\u_i2c_timing_ctrl_16bit/next_state[3] ), + .O(n14459)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__21998.LUTMASK = 16'h8888; + EFX_LUT4 LUT__21999 (.I0(n14459), .I1(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), + .O(ceg_net2242)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__21999.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22000 (.I0(\sc130_i2c_config_index[0] ), .I1(\sc130_i2c_config_index[1] ), + .O(n14460)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22000.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22001 (.I0(n14444), .I1(n14460), .O(n14461)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22001.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22002 (.I0(\sc130_i2c_config_index[2] ), .I1(\sc130_i2c_config_index[3] ), + .O(n14462)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22002.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22003 (.I0(\sc130_i2c_config_index[0] ), .I1(\sc130_i2c_config_index[1] ), + .I2(n14462), .O(n14463)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__22003.LUTMASK = 16'h6060; + EFX_LUT4 LUT__22004 (.I0(\sc130_i2c_config_index[4] ), .I1(\sc130_i2c_config_index[7] ), + .I2(\sc130_i2c_config_index[6] ), .I3(\sc130_i2c_config_index[5] ), + .O(n14464)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22004.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22005 (.I0(n14463), .I1(n14461), .I2(n14464), .O(n14465)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__22005.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__22006 (.I0(\sc130_i2c_config_index[3] ), .I1(\sc130_i2c_config_index[2] ), + .O(n14466)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22006.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22007 (.I0(\sc130_i2c_config_index[1] ), .I1(n14466), + .O(n14467)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22007.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22008 (.I0(\sc130_i2c_config_index[6] ), .I1(\sc130_i2c_config_index[7] ), + .I2(\sc130_i2c_config_index[4] ), .I3(\sc130_i2c_config_index[5] ), + .O(n14468)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22008.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22009 (.I0(\sc130_i2c_config_index[3] ), .I1(n14468), + .O(n14469)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22009.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22010 (.I0(\sc130_i2c_config_index[1] ), .I1(n14462), + .O(n14470)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22010.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22011 (.I0(\sc130_i2c_config_index[4] ), .I1(\sc130_i2c_config_index[6] ), + .I2(\sc130_i2c_config_index[7] ), .O(n14471)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__22011.LUTMASK = 16'h0101; + EFX_LUT4 LUT__22012 (.I0(\sc130_i2c_config_index[5] ), .I1(n14471), + .O(n14472)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22012.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22013 (.I0(n14470), .I1(n14472), .I2(n14467), .I3(n14469), + .O(n14473)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb0bb */ ; + defparam LUT__22013.LUTMASK = 16'hb0bb; + EFX_LUT4 LUT__22014 (.I0(\sc130_i2c_config_index[5] ), .I1(n14471), + .O(n14474)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22014.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22015 (.I0(\sc130_i2c_config_index[2] ), .I1(\sc130_i2c_config_index[3] ), + .I2(n14468), .I3(n14460), .O(n14475)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6000 */ ; + defparam LUT__22015.LUTMASK = 16'h6000; + EFX_LUT4 LUT__22016 (.I0(\sc130_i2c_config_index[0] ), .I1(\sc130_i2c_config_index[1] ), + .O(n14476)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22016.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22017 (.I0(n14442), .I1(n14476), .O(n14477)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22017.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22018 (.I0(\sc130_i2c_config_index[5] ), .I1(\sc130_i2c_config_index[7] ), + .I2(\sc130_i2c_config_index[6] ), .I3(\sc130_i2c_config_index[4] ), + .O(n14478)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22018.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22019 (.I0(\sc130_i2c_config_index[1] ), .I1(\sc130_i2c_config_index[0] ), + .O(n14479)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22019.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22020 (.I0(n14444), .I1(n14479), .O(n14480)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22020.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22021 (.I0(n14468), .I1(n14480), .I2(n14477), .I3(n14478), + .O(n14481)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22021.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22022 (.I0(n14443), .I1(n14442), .O(n14482)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22022.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22023 (.I0(\sc130_i2c_config_index[0] ), .I1(n14470), + .O(n14483)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22023.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22024 (.I0(n14483), .I1(n14464), .I2(n14478), .I3(n14482), + .O(n14484)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22024.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22025 (.I0(n14481), .I1(n14484), .O(n14485)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22025.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22026 (.I0(n14470), .I1(n14474), .I2(n14475), .I3(n14485), + .O(n14486)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0700 */ ; + defparam LUT__22026.LUTMASK = 16'h0700; + EFX_LUT4 LUT__22027 (.I0(\sc130_i2c_config_index[0] ), .I1(\sc130_i2c_config_index[1] ), + .I2(\sc130_i2c_config_index[3] ), .O(n14487)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbdbd */ ; + defparam LUT__22027.LUTMASK = 16'hbdbd; + EFX_LUT4 LUT__22028 (.I0(n14474), .I1(n14483), .I2(n14445), .I3(n14478), + .O(n14488)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22028.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22029 (.I0(\sc130_i2c_config_index[2] ), .I1(n14487), + .I2(n14478), .I3(n14488), .O(n14489)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hef00 */ ; + defparam LUT__22029.LUTMASK = 16'hef00; + EFX_LUT4 LUT__22030 (.I0(n14465), .I1(n14473), .I2(n14486), .I3(n14489), + .O(n14490)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__22030.LUTMASK = 16'h4000; + EFX_LUT4 LUT__22031 (.I0(\sc130_i2c_config_index[3] ), .I1(n14478), + .O(n14491)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22031.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22032 (.I0(\sc130_i2c_config_index[5] ), .I1(\sc130_i2c_config_index[6] ), + .I2(\sc130_i2c_config_index[7] ), .I3(\sc130_i2c_config_index[4] ), + .O(n14492)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22032.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22033 (.I0(n14482), .I1(n14461), .I2(n14470), .I3(n14492), + .O(n14493)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfe00 */ ; + defparam LUT__22033.LUTMASK = 16'hfe00; + EFX_LUT4 LUT__22034 (.I0(n14476), .I1(n14491), .I2(n14493), .I3(\sc130_i2c_config_index[2] ), + .O(n14494)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__22034.LUTMASK = 16'hf800; + EFX_LUT4 LUT__22035 (.I0(n14472), .I1(n14492), .I2(\sc130_i2c_config_index[0] ), + .I3(n14470), .O(n14495)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__22035.LUTMASK = 16'hca00; + EFX_LUT4 LUT__22036 (.I0(n14442), .I1(n14479), .O(n14496)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22036.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22037 (.I0(n14492), .I1(n14496), .O(n14497)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22037.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22038 (.I0(n14472), .I1(n14482), .I2(n14468), .I3(n14461), + .O(n14498)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22038.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22039 (.I0(n14494), .I1(n14495), .I2(n14497), .I3(n14498), + .O(n14499)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22039.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22040 (.I0(n14443), .I1(n14462), .O(n14500)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22040.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22041 (.I0(n14443), .I1(n14466), .O(n14501)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22041.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22042 (.I0(n14460), .I1(n14462), .O(n14502)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22042.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22043 (.I0(n14502), .I1(n14501), .I2(n14474), .O(n14503)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__22043.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__22044 (.I0(\sc130_i2c_config_index[4] ), .I1(\sc130_i2c_config_index[5] ), + .I2(\sc130_i2c_config_index[7] ), .I3(\sc130_i2c_config_index[6] ), + .O(n14504)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22044.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22045 (.I0(n14504), .I1(n14445), .I2(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .O(n14505)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__22045.LUTMASK = 16'h0707; + EFX_LUT4 LUT__22046 (.I0(n14500), .I1(n14464), .I2(n14503), .I3(n14505), + .O(n14506)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0700 */ ; + defparam LUT__22046.LUTMASK = 16'h0700; + EFX_LUT4 LUT__22047 (.I0(n14504), .I1(n14464), .I2(\sc130_i2c_config_index[1] ), + .I3(\sc130_i2c_config_index[3] ), .O(n14507)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf331 */ ; + defparam LUT__22047.LUTMASK = 16'hf331; + EFX_LUT4 LUT__22048 (.I0(n14507), .I1(\sc130_i2c_config_index[2] ), + .I2(\sc130_i2c_config_index[0] ), .I3(n14488), .O(n14508)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfe00 */ ; + defparam LUT__22048.LUTMASK = 16'hfe00; + EFX_LUT4 LUT__22049 (.I0(n14442), .I1(n14460), .O(n14509)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22049.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22050 (.I0(n14501), .I1(n14492), .I2(n14504), .I3(n14509), + .O(n14510)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22050.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22051 (.I0(n14477), .I1(n14445), .I2(n14472), .I3(n14510), + .O(n14511)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__22051.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__22052 (.I0(n14499), .I1(n14506), .I2(n14508), .I3(n14511), + .O(n14512)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22052.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22053 (.I0(\sc130_i2c_config_index[3] ), .I1(n14479), + .O(n14513)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22053.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22054 (.I0(n14478), .I1(n14472), .I2(\sc130_i2c_config_index[3] ), + .I3(n14460), .O(n14514)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__22054.LUTMASK = 16'hca00; + EFX_LUT4 LUT__22055 (.I0(n14472), .I1(n14513), .I2(n14514), .I3(\sc130_i2c_config_index[2] ), + .O(n14515)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f8 */ ; + defparam LUT__22055.LUTMASK = 16'h00f8; + EFX_LUT4 LUT__22056 (.I0(\sc130_i2c_config_index[1] ), .I1(n14442), + .O(n14516)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22056.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22057 (.I0(\sc130_i2c_config_index[0] ), .I1(n14466), + .I2(n14516), .I3(n14471), .O(n14517)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf400 */ ; + defparam LUT__22057.LUTMASK = 16'hf400; + EFX_LUT4 LUT__22058 (.I0(\sc130_i2c_config_index[6] ), .I1(\sc130_i2c_config_index[4] ), + .I2(\sc130_i2c_config_index[5] ), .I3(\sc130_i2c_config_index[7] ), + .O(n14518)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0007 */ ; + defparam LUT__22058.LUTMASK = 16'h0007; + EFX_LUT4 LUT__22059 (.I0(n14517), .I1(n14480), .I2(n14518), .O(n14519)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__22059.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__22060 (.I0(n14460), .I1(n14466), .O(n14520)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22060.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22061 (.I0(n14520), .I1(n14478), .I2(n14472), .I3(n14501), + .O(n14521)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22061.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22062 (.I0(n14445), .I1(n14520), .I2(n14492), .I3(n14521), + .O(n14522)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__22062.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__22063 (.I0(n14468), .I1(\sc130_i2c_config_index[1] ), + .I2(n14504), .O(n14523)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__22063.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__22064 (.I0(\sc130_i2c_config_index[0] ), .I1(n14442), + .I2(n14463), .I3(n14468), .O(n14524)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf400 */ ; + defparam LUT__22064.LUTMASK = 16'hf400; + EFX_LUT4 LUT__22065 (.I0(n14523), .I1(\sc130_i2c_config_index[0] ), + .I2(n14466), .I3(n14524), .O(n14525)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00bf */ ; + defparam LUT__22065.LUTMASK = 16'h00bf; + EFX_LUT4 LUT__22066 (.I0(n14515), .I1(n14519), .I2(n14522), .I3(n14525), + .O(n14526)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22066.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22067 (.I0(n14478), .I1(n14474), .I2(\sc130_i2c_config_index[2] ), + .I3(n14464), .O(n14527)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f1 */ ; + defparam LUT__22067.LUTMASK = 16'h00f1; + EFX_LUT4 LUT__22068 (.I0(\sc130_i2c_config_index[3] ), .I1(n14527), + .I2(n14476), .O(n14528)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22068.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22069 (.I0(\sc130_i2c_config_index[0] ), .I1(\sc130_i2c_config_index[1] ), + .I2(\sc130_i2c_config_index[3] ), .I3(\sc130_i2c_config_index[2] ), + .O(n14529)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he9f7 */ ; + defparam LUT__22069.LUTMASK = 16'he9f7; + EFX_LUT4 LUT__22070 (.I0(n14529), .I1(n14504), .O(n14530)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22070.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22071 (.I0(n14464), .I1(n14520), .O(n14531)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22071.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22072 (.I0(n14469), .I1(n14443), .I2(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .O(n14532)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__22072.LUTMASK = 16'h7070; + EFX_LUT4 LUT__22073 (.I0(n14530), .I1(n14494), .I2(n14531), .I3(n14532), + .O(n14533)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22073.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22074 (.I0(n14443), .I1(n14444), .I2(n14468), .O(n14534)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22074.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22075 (.I0(n14534), .I1(n14474), .I2(n14461), .I3(n14501), + .O(n14535)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hccca */ ; + defparam LUT__22075.LUTMASK = 16'hccca; + EFX_LUT4 LUT__22076 (.I0(n14477), .I1(n14483), .I2(n14492), .I3(n14465), + .O(n14536)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h001f */ ; + defparam LUT__22076.LUTMASK = 16'h001f; + EFX_LUT4 LUT__22077 (.I0(n14478), .I1(n14496), .I2(n14472), .I3(n14520), + .O(n14537)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22077.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22078 (.I0(n14474), .I1(n14482), .I2(n14492), .I3(n14501), + .O(n14538)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22078.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22079 (.I0(n14536), .I1(n14537), .I2(n14538), .O(n14539)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22079.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22080 (.I0(n14528), .I1(n14535), .I2(n14533), .I3(n14539), + .O(n14540)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22080.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22081 (.I0(n14466), .I1(n14476), .I2(n14500), .O(n14541)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__22081.LUTMASK = 16'h0707; + EFX_LUT4 LUT__22082 (.I0(n14444), .I1(n14476), .O(n14542)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22082.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22083 (.I0(n14478), .I1(n14542), .I2(n14504), .I3(n14502), + .O(n14543)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22083.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22084 (.I0(n14541), .I1(n14492), .I2(n14543), .O(n14544)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb0b0 */ ; + defparam LUT__22084.LUTMASK = 16'hb0b0; + EFX_LUT4 LUT__22085 (.I0(n14526), .I1(n14512), .I2(n14540), .I3(n14544), + .O(n14545)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__22085.LUTMASK = 16'hf800; + EFX_LUT4 LUT__22086 (.I0(n14490), .I1(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .I2(n14545), .I3(\u_i2c_timing_ctrl_16bit/next_state[2] ), .O(\u_i2c_timing_ctrl_16bit/n818 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0f44 */ ; + defparam LUT__22086.LUTMASK = 16'h0f44; + EFX_LUT4 LUT__22087 (.I0(\u_i2c_timing_ctrl_16bit/next_state[3] ), .I1(n14458), + .I2(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), .O(ceg_net4099)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hefef */ ; + defparam LUT__22087.LUTMASK = 16'hefef; + EFX_LUT4 LUT__22100 (.I0(\u_i2c_timing_ctrl_16bit/delay_cnt[15] ), .I1(n14425), + .I2(\u_i2c_timing_ctrl_16bit/delay_cnt[16] ), .I3(n14428), .O(\u_i2c_timing_ctrl_16bit/n7 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__22100.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__22101 (.I0(\u_i2c_timing_ctrl_16bit/i2c_wdata[0] ), .I1(\u_i2c_timing_ctrl_16bit/i2c_wdata[2] ), + .I2(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0] ), .I3(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1] ), + .O(n14553)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__22101.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__22102 (.I0(\u_i2c_timing_ctrl_16bit/i2c_wdata[1] ), .I1(\u_i2c_timing_ctrl_16bit/i2c_wdata[3] ), + .I2(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0] ), .I3(n14553), + .O(n14554)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__22102.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__22103 (.I0(\u_i2c_timing_ctrl_16bit/i2c_wdata[4] ), .I1(\u_i2c_timing_ctrl_16bit/i2c_wdata[6] ), + .I2(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0] ), .I3(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1] ), + .O(n14555)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__22103.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__22104 (.I0(\u_i2c_timing_ctrl_16bit/i2c_wdata[5] ), .I1(\u_i2c_timing_ctrl_16bit/i2c_wdata[7] ), + .I2(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0] ), .I3(n14555), + .O(n14556)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__22104.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__22105 (.I0(n14556), .I1(n14554), .I2(n14459), .I3(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2] ), + .O(n14557)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c0a */ ; + defparam LUT__22105.LUTMASK = 16'h0c0a; + EFX_LUT4 LUT__22106 (.I0(n14557), .I1(n14457), .I2(n14450), .O(\u_i2c_timing_ctrl_16bit/n328 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0e0e */ ; + defparam LUT__22106.LUTMASK = 16'h0e0e; + EFX_LUT4 LUT__22107 (.I0(n14452), .I1(\u_i2c_timing_ctrl_16bit/i2c_transfer_en ), + .O(ceg_net4409)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22107.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22108 (.I0(n3678), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n136 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22108.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22109 (.I0(n5020), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n135 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22109.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22110 (.I0(n5018), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n134 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22110.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22111 (.I0(n5016), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n133 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22111.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22112 (.I0(n5014), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n132 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22112.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22113 (.I0(n5012), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n131 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22113.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22114 (.I0(n5010), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n130 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22114.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22115 (.I0(n5008), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n129 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22115.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22116 (.I0(n5006), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n128 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22116.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22117 (.I0(n5004), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n127 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22117.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22118 (.I0(n5002), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n126 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22118.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22119 (.I0(n5000), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n125 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22119.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22120 (.I0(n4998), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n124 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22120.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22121 (.I0(n4996), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n123 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22121.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22122 (.I0(n4995), .I1(n14433), .O(\u_i2c_timing_ctrl_16bit/n122 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22122.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22123 (.I0(n3681), .I1(n14447), .O(\u_i2c_timing_ctrl_16bit/n197 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__22123.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__22124 (.I0(n4993), .I1(n14447), .O(\u_i2c_timing_ctrl_16bit/n196 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22124.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22125 (.I0(n4991), .I1(n14447), .O(\u_i2c_timing_ctrl_16bit/n195 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__22125.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__22126 (.I0(n4989), .I1(n14447), .O(\u_i2c_timing_ctrl_16bit/n194 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22126.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22127 (.I0(n4987), .I1(n14447), .O(\u_i2c_timing_ctrl_16bit/n193 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__22127.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__22128 (.I0(n4985), .I1(n14447), .O(\u_i2c_timing_ctrl_16bit/n192 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__22128.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__22129 (.I0(n4984), .I1(n14447), .O(\u_i2c_timing_ctrl_16bit/n191 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22129.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22130 (.I0(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0] ), + .I1(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1] ), .I2(n14458), + .O(\u_i2c_timing_ctrl_16bit/n332 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__22130.LUTMASK = 16'h6060; + EFX_LUT4 LUT__22131 (.I0(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[0] ), + .I1(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[1] ), .O(n14558)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22131.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22132 (.I0(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2] ), + .I1(n14558), .I2(n14458), .O(\u_i2c_timing_ctrl_16bit/n331 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__22132.LUTMASK = 16'h6060; + EFX_LUT4 LUT__22133 (.I0(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[2] ), + .I1(n14558), .I2(\u_i2c_timing_ctrl_16bit/i2c_stream_cnt[3] ), + .I3(n14458), .O(\u_i2c_timing_ctrl_16bit/n330 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__22133.LUTMASK = 16'h7800; + EFX_LUT4 LUT__22134 (.I0(\sc130_i2c_config_index[1] ), .I1(\sc130_i2c_config_index[0] ), + .I2(n14464), .I3(n14466), .O(n14559)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__22134.LUTMASK = 16'h4000; + EFX_LUT4 LUT__22135 (.I0(n14460), .I1(n14559), .I2(n14478), .O(n14560)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22135.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22136 (.I0(n14476), .I1(\sc130_i2c_config_index[2] ), + .I2(\sc130_i2c_config_index[3] ), .O(n14561)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__22136.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__22137 (.I0(n14444), .I1(n14466), .I2(\sc130_i2c_config_index[1] ), + .I3(n14464), .O(n14562)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__22137.LUTMASK = 16'hca00; + EFX_LUT4 LUT__22138 (.I0(n14470), .I1(n14472), .I2(n14562), .O(n14563)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__22138.LUTMASK = 16'h0707; + EFX_LUT4 LUT__22139 (.I0(n14561), .I1(n14492), .I2(n14563), .I3(n14473), + .O(n14564)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb000 */ ; + defparam LUT__22139.LUTMASK = 16'hb000; + EFX_LUT4 LUT__22140 (.I0(\sc130_i2c_config_index[2] ), .I1(n14443), + .O(n14565)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22140.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22141 (.I0(n14466), .I1(n14478), .I2(n14504), .O(n14566)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__22141.LUTMASK = 16'h0707; + EFX_LUT4 LUT__22142 (.I0(n14565), .I1(n14468), .I2(\sc130_i2c_config_index[3] ), + .I3(n14566), .O(n14567)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbf00 */ ; + defparam LUT__22142.LUTMASK = 16'hbf00; + EFX_LUT4 LUT__22143 (.I0(\sc130_i2c_config_index[0] ), .I1(\sc130_i2c_config_index[2] ), + .I2(n14469), .O(n14568)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__22143.LUTMASK = 16'h6060; + EFX_LUT4 LUT__22144 (.I0(n14443), .I1(n14444), .I2(n14478), .O(n14569)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22144.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22145 (.I0(n14568), .I1(n14569), .O(n14570)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22145.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22146 (.I0(n14484), .I1(n14564), .I2(n14567), .I3(n14570), + .O(n14571)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22146.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22147 (.I0(n14463), .I1(n14464), .I2(n14541), .I3(n14478), + .O(n14572)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7077 */ ; + defparam LUT__22147.LUTMASK = 16'h7077; + EFX_LUT4 LUT__22148 (.I0(n14560), .I1(\sc130_i2c_config_index[3] ), + .I2(n14571), .I3(n14572), .O(n14573)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd000 */ ; + defparam LUT__22148.LUTMASK = 16'hd000; + EFX_LUT4 LUT__22149 (.I0(n14504), .I1(n14483), .I2(n14468), .I3(n14496), + .O(n14574)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfac0 */ ; + defparam LUT__22149.LUTMASK = 16'hfac0; + EFX_LUT4 LUT__22150 (.I0(n14466), .I1(n14479), .O(n14575)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22150.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22151 (.I0(n14477), .I1(n14575), .I2(n14468), .I3(n14538), + .O(n14576)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__22151.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__22152 (.I0(n14492), .I1(n14478), .I2(\sc130_i2c_config_index[2] ), + .I3(n14513), .O(n14577)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__22152.LUTMASK = 16'hca00; + EFX_LUT4 LUT__22153 (.I0(\sc130_i2c_config_index[2] ), .I1(\sc130_i2c_config_index[0] ), + .I2(\sc130_i2c_config_index[3] ), .I3(\sc130_i2c_config_index[1] ), + .O(n14578)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfacf */ ; + defparam LUT__22153.LUTMASK = 16'hfacf; + EFX_LUT4 LUT__22154 (.I0(n14504), .I1(n14542), .I2(n14492), .I3(n14578), + .O(n14579)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f8 */ ; + defparam LUT__22154.LUTMASK = 16'h00f8; + EFX_LUT4 LUT__22155 (.I0(n14472), .I1(n14542), .I2(n14504), .I3(n14482), + .O(n14580)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22155.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22156 (.I0(\sc130_i2c_config_index[1] ), .I1(n14442), + .I2(n14472), .O(n14581)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22156.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22157 (.I0(n14501), .I1(n14496), .I2(n14474), .O(n14582)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__22157.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__22158 (.I0(n14579), .I1(n14581), .I2(n14582), .I3(n14580), + .O(n14583)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22158.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22159 (.I0(n14574), .I1(n14577), .I2(n14576), .I3(n14583), + .O(n14584)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22159.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22160 (.I0(n14509), .I1(n14492), .I2(n14584), .I3(n14485), + .O(n14585)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7000 */ ; + defparam LUT__22160.LUTMASK = 16'h7000; + EFX_LUT4 LUT__22161 (.I0(n14474), .I1(n14464), .I2(n14508), .I3(\sc130_i2c_config_index[3] ), + .O(n14586)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c0a */ ; + defparam LUT__22161.LUTMASK = 16'h0c0a; + EFX_LUT4 LUT__22162 (.I0(n14542), .I1(n14478), .I2(n14493), .I3(n14559), + .O(n14587)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0007 */ ; + defparam LUT__22162.LUTMASK = 16'h0007; + EFX_LUT4 LUT__22163 (.I0(n14542), .I1(n14467), .I2(n14472), .I3(n14587), + .O(n14588)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__22163.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__22164 (.I0(n14504), .I1(n14468), .O(n14589)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22164.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22165 (.I0(n14464), .I1(\sc130_i2c_config_index[0] ), + .I2(n14589), .I3(\sc130_i2c_config_index[1] ), .O(n14590)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h77f0 */ ; + defparam LUT__22165.LUTMASK = 16'h77f0; + EFX_LUT4 LUT__22166 (.I0(n14590), .I1(n14466), .I2(n14505), .O(n14591)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb0b0 */ ; + defparam LUT__22166.LUTMASK = 16'hb0b0; + EFX_LUT4 LUT__22167 (.I0(\sc130_i2c_config_index[1] ), .I1(\sc130_i2c_config_index[3] ), + .I2(\sc130_i2c_config_index[0] ), .I3(\sc130_i2c_config_index[2] ), + .O(n14592)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hed3f */ ; + defparam LUT__22167.LUTMASK = 16'hed3f; + EFX_LUT4 LUT__22168 (.I0(n14474), .I1(\sc130_i2c_config_index[3] ), + .I2(n14469), .O(n14593)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__22168.LUTMASK = 16'h0707; + EFX_LUT4 LUT__22169 (.I0(\sc130_i2c_config_index[1] ), .I1(\sc130_i2c_config_index[2] ), + .I2(n14593), .O(n14594)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__22169.LUTMASK = 16'h0101; + EFX_LUT4 LUT__22170 (.I0(n14468), .I1(n14542), .I2(n14504), .I3(n14461), + .O(n14595)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22170.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22171 (.I0(n14592), .I1(n14492), .I2(n14594), .I3(n14595), + .O(n14596)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b00 */ ; + defparam LUT__22171.LUTMASK = 16'h0b00; + EFX_LUT4 LUT__22172 (.I0(n14586), .I1(n14588), .I2(n14591), .I3(n14596), + .O(n14597)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__22172.LUTMASK = 16'h4000; + EFX_LUT4 LUT__22173 (.I0(n14541), .I1(n14472), .I2(n14504), .I3(n14509), + .O(n14598)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0bbb */ ; + defparam LUT__22173.LUTMASK = 16'h0bbb; + EFX_LUT4 LUT__22174 (.I0(n14472), .I1(n14478), .O(n14599)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22174.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22175 (.I0(n14466), .I1(n14492), .I2(n14444), .I3(n14474), + .O(n14600)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22175.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22176 (.I0(n14599), .I1(n14442), .I2(n14600), .I3(n14476), + .O(n14601)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4f00 */ ; + defparam LUT__22176.LUTMASK = 16'h4f00; + EFX_LUT4 LUT__22177 (.I0(n14468), .I1(n14442), .I2(\sc130_i2c_config_index[1] ), + .O(n14602)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__22177.LUTMASK = 16'h0707; + EFX_LUT4 LUT__22178 (.I0(n14466), .I1(n14474), .I2(n14443), .I3(n14602), + .O(n14603)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h008f */ ; + defparam LUT__22178.LUTMASK = 16'h008f; + EFX_LUT4 LUT__22179 (.I0(n14468), .I1(\sc130_i2c_config_index[1] ), + .I2(n14442), .I3(\sc130_i2c_config_index[0] ), .O(n14604)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h007f */ ; + defparam LUT__22179.LUTMASK = 16'h007f; + EFX_LUT4 LUT__22180 (.I0(n14470), .I1(n14472), .I2(n14603), .I3(n14604), + .O(n14605)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f8 */ ; + defparam LUT__22180.LUTMASK = 16'h00f8; + EFX_LUT4 LUT__22181 (.I0(n14474), .I1(n14492), .I2(n14509), .O(n14606)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__22181.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__22182 (.I0(n14492), .I1(n14542), .I2(n14504), .I3(n14463), + .O(n14607)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22182.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22183 (.I0(n14501), .I1(n14478), .I2(n14606), .I3(n14607), + .O(n14608)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0700 */ ; + defparam LUT__22183.LUTMASK = 16'h0700; + EFX_LUT4 LUT__22184 (.I0(n14601), .I1(n14605), .I2(n14608), .O(n14609)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22184.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22185 (.I0(n14572), .I1(n14598), .I2(n14609), .O(n14610)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22185.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22186 (.I0(n14597), .I1(n14610), .I2(n14533), .I3(n14585), + .O(n14611)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22186.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22187 (.I0(n14573), .I1(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .I2(n14611), .I3(\u_i2c_timing_ctrl_16bit/next_state[2] ), .O(\u_i2c_timing_ctrl_16bit/n719 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf044 */ ; + defparam LUT__22187.LUTMASK = 16'hf044; + EFX_LUT4 LUT__22188 (.I0(n14468), .I1(\sc130_i2c_config_index[3] ), + .I2(n14504), .I3(n14559), .O(n14612)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0007 */ ; + defparam LUT__22188.LUTMASK = 16'h0007; + EFX_LUT4 LUT__22189 (.I0(n14476), .I1(n14442), .I2(n14478), .O(n14613)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22189.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22190 (.I0(n14445), .I1(n14478), .O(n14614)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22190.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22191 (.I0(n14501), .I1(n14468), .I2(n14614), .I3(n14562), + .O(n14615)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0007 */ ; + defparam LUT__22191.LUTMASK = 16'h0007; + EFX_LUT4 LUT__22192 (.I0(n14478), .I1(n14612), .I2(n14613), .I3(n14615), + .O(n14616)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf400 */ ; + defparam LUT__22192.LUTMASK = 16'hf400; + EFX_LUT4 LUT__22193 (.I0(n14492), .I1(n14589), .I2(n14482), .I3(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .O(n14617)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h004f */ ; + defparam LUT__22193.LUTMASK = 16'h004f; + EFX_LUT4 LUT__22194 (.I0(n14468), .I1(n14472), .I2(\sc130_i2c_config_index[0] ), + .I3(n14478), .O(n14618)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f1 */ ; + defparam LUT__22194.LUTMASK = 16'h00f1; + EFX_LUT4 LUT__22195 (.I0(\sc130_i2c_config_index[1] ), .I1(n14618), + .I2(n14444), .O(n14619)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22195.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22196 (.I0(n14466), .I1(n14476), .I2(n14480), .I3(n14464), + .O(n14620)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__22196.LUTMASK = 16'hf800; + EFX_LUT4 LUT__22197 (.I0(n14466), .I1(n14476), .I2(n14496), .I3(n14472), + .O(n14621)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__22197.LUTMASK = 16'hf800; + EFX_LUT4 LUT__22198 (.I0(n14483), .I1(n14504), .I2(n14620), .I3(n14621), + .O(n14622)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0007 */ ; + defparam LUT__22198.LUTMASK = 16'h0007; + EFX_LUT4 LUT__22199 (.I0(\sc130_i2c_config_index[2] ), .I1(\sc130_i2c_config_index[3] ), + .I2(\sc130_i2c_config_index[0] ), .I3(\sc130_i2c_config_index[1] ), + .O(n14623)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hce35 */ ; + defparam LUT__22199.LUTMASK = 16'hce35; + EFX_LUT4 LUT__22200 (.I0(n14467), .I1(n14504), .I2(n14582), .O(n14624)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__22200.LUTMASK = 16'h0707; + EFX_LUT4 LUT__22201 (.I0(n14474), .I1(n14500), .I2(n14469), .I3(n14460), + .O(n14625)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22201.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22202 (.I0(n14623), .I1(n14492), .I2(n14624), .I3(n14625), + .O(n14626)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb000 */ ; + defparam LUT__22202.LUTMASK = 16'hb000; + EFX_LUT4 LUT__22203 (.I0(n14619), .I1(n14622), .I2(n14626), .O(n14627)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22203.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22204 (.I0(n14464), .I1(n14472), .I2(n14500), .O(n14628)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__22204.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__22205 (.I0(\sc130_i2c_config_index[5] ), .I1(\sc130_i2c_config_index[7] ), + .I2(\sc130_i2c_config_index[6] ), .I3(n14461), .O(n14629)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22205.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22206 (.I0(n14482), .I1(n14480), .I2(n14504), .I3(n14629), + .O(n14630)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h001f */ ; + defparam LUT__22206.LUTMASK = 16'h001f; + EFX_LUT4 LUT__22207 (.I0(\sc130_i2c_config_index[3] ), .I1(n14479), + .O(n14631)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22207.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22208 (.I0(\sc130_i2c_config_index[2] ), .I1(n14443), + .I2(n14468), .O(n14632)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22208.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22209 (.I0(n14631), .I1(n14502), .I2(n14492), .I3(n14632), + .O(n14633)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h001f */ ; + defparam LUT__22209.LUTMASK = 16'h001f; + EFX_LUT4 LUT__22210 (.I0(n14628), .I1(n14630), .I2(n14633), .I3(n14587), + .O(n14634)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__22210.LUTMASK = 16'h4000; + EFX_LUT4 LUT__22211 (.I0(n14478), .I1(n14464), .I2(\sc130_i2c_config_index[0] ), + .I3(\sc130_i2c_config_index[3] ), .O(n14635)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf53f */ ; + defparam LUT__22211.LUTMASK = 16'hf53f; + EFX_LUT4 LUT__22212 (.I0(n14635), .I1(\sc130_i2c_config_index[1] ), + .I2(n14562), .I3(\sc130_i2c_config_index[2] ), .O(n14636)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbb0f */ ; + defparam LUT__22212.LUTMASK = 16'hbb0f; + EFX_LUT4 LUT__22213 (.I0(n14468), .I1(n14504), .I2(\sc130_i2c_config_index[0] ), + .I3(\sc130_i2c_config_index[1] ), .O(n14637)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h31f3 */ ; + defparam LUT__22213.LUTMASK = 16'h31f3; + EFX_LUT4 LUT__22214 (.I0(n14482), .I1(n14472), .I2(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .O(n14638)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__22214.LUTMASK = 16'h7070; + EFX_LUT4 LUT__22215 (.I0(n14637), .I1(n14466), .I2(n14638), .I3(n14481), + .O(n14639)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb000 */ ; + defparam LUT__22215.LUTMASK = 16'hb000; + EFX_LUT4 LUT__22216 (.I0(n14605), .I1(n14634), .I2(n14636), .I3(n14639), + .O(n14640)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__22216.LUTMASK = 16'h4000; + EFX_LUT4 LUT__22217 (.I0(n14608), .I1(n14627), .I2(n14617), .I3(n14640), + .O(n14641)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h007f */ ; + defparam LUT__22217.LUTMASK = 16'h007f; + EFX_LUT4 LUT__22218 (.I0(n14616), .I1(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .I2(n14641), .I3(\u_i2c_timing_ctrl_16bit/next_state[2] ), .O(\u_i2c_timing_ctrl_16bit/n727 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf044 */ ; + defparam LUT__22218.LUTMASK = 16'hf044; + EFX_LUT4 LUT__22219 (.I0(\sc130_i2c_config_index[5] ), .I1(\sc130_i2c_config_index[3] ), + .I2(\sc130_i2c_config_index[0] ), .I3(\sc130_i2c_config_index[2] ), + .O(n14642)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbe7f */ ; + defparam LUT__22219.LUTMASK = 16'hbe7f; + EFX_LUT4 LUT__22220 (.I0(n14480), .I1(\sc130_i2c_config_index[1] ), + .I2(n14642), .I3(n14471), .O(n14643)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hac00 */ ; + defparam LUT__22220.LUTMASK = 16'hac00; + EFX_LUT4 LUT__22221 (.I0(n14491), .I1(\sc130_i2c_config_index[2] ), + .I2(n14534), .I3(n14476), .O(n14644)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f8 */ ; + defparam LUT__22221.LUTMASK = 16'h00f8; + EFX_LUT4 LUT__22222 (.I0(\sc130_i2c_config_index[2] ), .I1(n14471), + .I2(n14504), .I3(\sc130_i2c_config_index[3] ), .O(n14645)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0f77 */ ; + defparam LUT__22222.LUTMASK = 16'h0f77; + EFX_LUT4 LUT__22223 (.I0(\sc130_i2c_config_index[2] ), .I1(n14487), + .I2(n14478), .O(n14646)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22223.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22224 (.I0(n14469), .I1(n14565), .I2(n14581), .O(n14647)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__22224.LUTMASK = 16'h0707; + EFX_LUT4 LUT__22225 (.I0(n14645), .I1(n14479), .I2(n14646), .I3(n14647), + .O(n14648)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b00 */ ; + defparam LUT__22225.LUTMASK = 16'h0b00; + EFX_LUT4 LUT__22226 (.I0(n14442), .I1(n14502), .I2(n14541), .O(n14649)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22226.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22227 (.I0(n14443), .I1(n14492), .I2(n14504), .I3(n14444), + .O(n14650)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__22227.LUTMASK = 16'hf800; + EFX_LUT4 LUT__22228 (.I0(n14649), .I1(n14492), .I2(n14650), .O(n14651)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__22228.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__22229 (.I0(n14643), .I1(n14644), .I2(n14648), .I3(n14651), + .O(n14652)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22229.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22230 (.I0(n14478), .I1(n14509), .I2(n14504), .I3(n14496), + .O(n14653)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22230.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22231 (.I0(\sc130_i2c_config_index[0] ), .I1(\sc130_i2c_config_index[1] ), + .I2(\sc130_i2c_config_index[2] ), .I3(\sc130_i2c_config_index[5] ), + .O(n14654)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf6ef */ ; + defparam LUT__22231.LUTMASK = 16'hf6ef; + EFX_LUT4 LUT__22232 (.I0(n14468), .I1(n14500), .I2(n14504), .I3(n14520), + .O(n14655)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22232.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22233 (.I0(n14654), .I1(n14471), .I2(\sc130_i2c_config_index[3] ), + .I3(n14655), .O(n14656)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbf00 */ ; + defparam LUT__22233.LUTMASK = 16'hbf00; + EFX_LUT4 LUT__22234 (.I0(\u_i2c_timing_ctrl_16bit/next_state[1] ), .I1(n14576), + .I2(n14653), .I3(n14656), .O(n14657)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22234.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22235 (.I0(n14499), .I1(n14598), .I2(n14657), .O(n14658)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22235.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22236 (.I0(n14506), .I1(n14588), .I2(n14652), .I3(n14658), + .O(n14659)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h007f */ ; + defparam LUT__22236.LUTMASK = 16'h007f; + EFX_LUT4 LUT__22237 (.I0(n14463), .I1(n14464), .I2(n14491), .I3(n14569), + .O(n14660)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0007 */ ; + defparam LUT__22237.LUTMASK = 16'h0007; + EFX_LUT4 LUT__22238 (.I0(n14660), .I1(n14484), .I2(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .O(n14661)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__22238.LUTMASK = 16'h7070; + EFX_LUT4 LUT__22239 (.I0(n14661), .I1(n14659), .I2(\u_i2c_timing_ctrl_16bit/next_state[2] ), + .O(\u_i2c_timing_ctrl_16bit/n735 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22239.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22240 (.I0(\sc130_i2c_config_index[1] ), .I1(n14466), + .I2(n14500), .I3(n14464), .O(n14662)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf400 */ ; + defparam LUT__22240.LUTMASK = 16'hf400; + EFX_LUT4 LUT__22241 (.I0(\sc130_i2c_config_index[1] ), .I1(n14474), + .I2(n14492), .I3(n14561), .O(n14663)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__22241.LUTMASK = 16'hf800; + EFX_LUT4 LUT__22242 (.I0(n14474), .I1(n14442), .I2(n14662), .I3(n14663), + .O(n14664)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0007 */ ; + defparam LUT__22242.LUTMASK = 16'h0007; + EFX_LUT4 LUT__22243 (.I0(n14472), .I1(n14516), .I2(n14505), .I3(n14664), + .O(n14665)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7000 */ ; + defparam LUT__22243.LUTMASK = 16'h7000; + EFX_LUT4 LUT__22244 (.I0(\sc130_i2c_config_index[1] ), .I1(n14472), + .I2(n14504), .I3(n14444), .O(n14666)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__22244.LUTMASK = 16'hf800; + EFX_LUT4 LUT__22245 (.I0(n14474), .I1(n14575), .I2(n14504), .I3(n14500), + .O(n14667)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22245.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22246 (.I0(n14480), .I1(n14478), .I2(n14667), .O(n14668)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__22246.LUTMASK = 16'h7070; + EFX_LUT4 LUT__22247 (.I0(\sc130_i2c_config_index[2] ), .I1(n14468), + .I2(n14460), .O(n14669)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22247.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22248 (.I0(n14474), .I1(n14520), .I2(n14472), .I3(n14631), + .O(n14670)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22248.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22249 (.I0(n14466), .I1(n14504), .I2(n14669), .I3(n14670), + .O(n14671)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0700 */ ; + defparam LUT__22249.LUTMASK = 16'h0700; + EFX_LUT4 LUT__22250 (.I0(n14666), .I1(n14535), .I2(n14668), .I3(n14671), + .O(n14672)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22250.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22251 (.I0(n14563), .I1(n14653), .I2(n14665), .I3(n14672), + .O(n14673)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22251.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22252 (.I0(\sc130_i2c_config_index[0] ), .I1(n14466), + .O(n14674)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22252.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22253 (.I0(n14496), .I1(n14474), .I2(n14674), .I3(n14504), + .O(n14675)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22253.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22254 (.I0(n14444), .I1(n14472), .I2(n14469), .I3(\sc130_i2c_config_index[0] ), + .O(n14676)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0f77 */ ; + defparam LUT__22254.LUTMASK = 16'h0f77; + EFX_LUT4 LUT__22255 (.I0(n14645), .I1(\sc130_i2c_config_index[0] ), + .I2(n14676), .I3(\sc130_i2c_config_index[1] ), .O(n14677)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf0bb */ ; + defparam LUT__22255.LUTMASK = 16'hf0bb; + EFX_LUT4 LUT__22256 (.I0(n14478), .I1(n14500), .O(n14678)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22256.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22257 (.I0(n14483), .I1(n14492), .I2(n14472), .I3(n14631), + .O(n14679)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22257.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22258 (.I0(n14678), .I1(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .I2(n14679), .O(n14680)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22258.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22259 (.I0(n14677), .I1(n14468), .I2(n14509), .I3(n14680), + .O(n14681)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3a00 */ ; + defparam LUT__22259.LUTMASK = 16'h3a00; + EFX_LUT4 LUT__22260 (.I0(n14601), .I1(n14619), .I2(n14675), .I3(n14681), + .O(n14682)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22260.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22261 (.I0(n14476), .I1(n14442), .I2(n14565), .O(n14683)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__22261.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__22262 (.I0(n14464), .I1(n14478), .I2(\sc130_i2c_config_index[3] ), + .O(n14684)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22262.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22263 (.I0(n14462), .I1(n14474), .I2(n14491), .I3(n14589), + .O(n14685)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b00 */ ; + defparam LUT__22263.LUTMASK = 16'h0b00; + EFX_LUT4 LUT__22264 (.I0(n14564), .I1(n14664), .I2(n14685), .O(n14686)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22264.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22265 (.I0(n14683), .I1(n14684), .I2(n14686), .I3(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .O(n14687)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4f00 */ ; + defparam LUT__22265.LUTMASK = 16'h4f00; + EFX_LUT4 LUT__22266 (.I0(n14682), .I1(n14673), .I2(n14687), .I3(\u_i2c_timing_ctrl_16bit/next_state[2] ), + .O(\u_i2c_timing_ctrl_16bit/n743 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h11f0 */ ; + defparam LUT__22266.LUTMASK = 16'h11f0; + EFX_LUT4 LUT__22267 (.I0(n14474), .I1(n14468), .I2(n14443), .I3(n14444), + .O(n14688)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__22267.LUTMASK = 16'hca00; + EFX_LUT4 LUT__22268 (.I0(n14468), .I1(\sc130_i2c_config_index[1] ), + .I2(n14504), .I3(n14442), .O(n14689)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heaf0 */ ; + defparam LUT__22268.LUTMASK = 16'heaf0; + EFX_LUT4 LUT__22269 (.I0(n14531), .I1(n14688), .I2(n14689), .I3(n14665), + .O(n14690)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22269.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22270 (.I0(n14445), .I1(n14502), .I2(n14472), .I3(n14521), + .O(n14691)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__22270.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__22271 (.I0(n14466), .I1(\sc130_i2c_config_index[1] ), + .I2(n14480), .O(n14692)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__22271.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__22272 (.I0(\sc130_i2c_config_index[3] ), .I1(n14443), + .I2(n14468), .I3(n14531), .O(n14693)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h007f */ ; + defparam LUT__22272.LUTMASK = 16'h007f; + EFX_LUT4 LUT__22273 (.I0(n14692), .I1(n14504), .I2(n14693), .I3(n14595), + .O(n14694)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb000 */ ; + defparam LUT__22273.LUTMASK = 16'hb000; + EFX_LUT4 LUT__22274 (.I0(n14520), .I1(n14504), .I2(n14568), .I3(n14638), + .O(n14695)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0700 */ ; + defparam LUT__22274.LUTMASK = 16'h0700; + EFX_LUT4 LUT__22275 (.I0(n14560), .I1(\sc130_i2c_config_index[3] ), + .I2(n14679), .I3(n14695), .O(n14696)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd000 */ ; + defparam LUT__22275.LUTMASK = 16'hd000; + EFX_LUT4 LUT__22276 (.I0(n14668), .I1(n14691), .I2(n14694), .I3(n14696), + .O(n14697)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22276.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22277 (.I0(n14569), .I1(n14686), .I2(\u_i2c_timing_ctrl_16bit/next_state[0] ), + .I3(\u_i2c_timing_ctrl_16bit/next_state[1] ), .O(n14698)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbf0 */ ; + defparam LUT__22277.LUTMASK = 16'hbbf0; + EFX_LUT4 LUT__22278 (.I0(n14697), .I1(n14690), .I2(n14698), .I3(\u_i2c_timing_ctrl_16bit/next_state[2] ), + .O(\u_i2c_timing_ctrl_16bit/n751 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h11f0 */ ; + defparam LUT__22278.LUTMASK = 16'h11f0; + EFX_LUT4 LUT__22279 (.I0(n14504), .I1(n14442), .I2(n14636), .I3(n14647), + .O(n14699)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7000 */ ; + defparam LUT__22279.LUTMASK = 16'h7000; + EFX_LUT4 LUT__22280 (.I0(\u_i2c_timing_ctrl_16bit/next_state[0] ), .I1(n14699), + .I2(\u_i2c_timing_ctrl_16bit/next_state[1] ), .I3(\u_i2c_timing_ctrl_16bit/next_state[2] ), + .O(n14700)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc05 */ ; + defparam LUT__22280.LUTMASK = 16'hfc05; + EFX_LUT4 LUT__22281 (.I0(\sc130_i2c_config_index[3] ), .I1(n14565), + .I2(n14684), .O(n14701)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__22281.LUTMASK = 16'h6060; + EFX_LUT4 LUT__22282 (.I0(\u_i2c_timing_ctrl_16bit/next_state[2] ), .I1(n14498), + .I2(n14615), .I3(n14667), .O(n14702)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22282.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22283 (.I0(n14482), .I1(n14474), .I2(n14464), .I3(n14500), + .O(n14703)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0777 */ ; + defparam LUT__22283.LUTMASK = 16'h0777; + EFX_LUT4 LUT__22284 (.I0(n14483), .I1(n14478), .I2(n14568), .O(n14704)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0707 */ ; + defparam LUT__22284.LUTMASK = 16'h0707; + EFX_LUT4 LUT__22285 (.I0(\sc130_i2c_config_index[1] ), .I1(\sc130_i2c_config_index[0] ), + .I2(\sc130_i2c_config_index[3] ), .I3(\sc130_i2c_config_index[2] ), + .O(n14705)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfa3f */ ; + defparam LUT__22285.LUTMASK = 16'hfa3f; + EFX_LUT4 LUT__22286 (.I0(\sc130_i2c_config_index[1] ), .I1(n14504), + .I2(n14472), .I3(n14705), .O(n14706)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f4 */ ; + defparam LUT__22286.LUTMASK = 16'h00f4; + EFX_LUT4 LUT__22287 (.I0(n14678), .I1(n14706), .I2(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .I3(n14624), .O(n14707)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22287.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22288 (.I0(n14702), .I1(n14703), .I2(n14704), .I3(n14707), + .O(n14708)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22288.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22289 (.I0(n14701), .I1(n14700), .I2(n14708), .I3(\u_i2c_timing_ctrl_16bit/next_state[1] ), + .O(\u_i2c_timing_ctrl_16bit/n759 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0e03 */ ; + defparam LUT__22289.LUTMASK = 16'h0e03; + EFX_LUT4 LUT__22290 (.I0(n14474), .I1(\sc130_i2c_config_index[2] ), + .I2(n14504), .I3(\sc130_i2c_config_index[0] ), .O(n14709)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h15cf */ ; + defparam LUT__22290.LUTMASK = 16'h15cf; + EFX_LUT4 LUT__22291 (.I0(n14474), .I1(n14462), .O(n14710)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22291.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22292 (.I0(n14709), .I1(\sc130_i2c_config_index[3] ), + .I2(n14710), .I3(\sc130_i2c_config_index[1] ), .O(n14711)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0fbb */ ; + defparam LUT__22292.LUTMASK = 16'h0fbb; + EFX_LUT4 LUT__22293 (.I0(n14460), .I1(n14468), .I2(n14599), .I3(\sc130_i2c_config_index[0] ), + .O(n14712)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7077 */ ; + defparam LUT__22293.LUTMASK = 16'h7077; + EFX_LUT4 LUT__22294 (.I0(n14712), .I1(n14444), .I2(n14695), .I3(n14511), + .O(n14713)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb000 */ ; + defparam LUT__22294.LUTMASK = 16'hb000; + EFX_LUT4 LUT__22295 (.I0(n14469), .I1(n14443), .I2(\sc130_i2c_config_index[2] ), + .I3(\u_i2c_timing_ctrl_16bit/next_state[1] ), .O(n14714)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00d7 */ ; + defparam LUT__22295.LUTMASK = 16'h00d7; + EFX_LUT4 LUT__22296 (.I0(n14713), .I1(n14711), .I2(n14714), .I3(\u_i2c_timing_ctrl_16bit/next_state[2] ), + .O(\u_i2c_timing_ctrl_16bit/n767 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0700 */ ; + defparam LUT__22296.LUTMASK = 16'h0700; + EFX_LUT4 LUT__22297 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3] ), .O(n14715)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22297.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22298 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1] ), .I2(n14715), + .O(n14716)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22298.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22299 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8] ), + .O(n14717)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22299.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22300 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6] ), + .I1(n14716), .I2(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7] ), + .I3(n14717), .O(n14718)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__22300.LUTMASK = 16'hf800; + EFX_LUT4 LUT__22301 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[6] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[7] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15] ), .O(n14719)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22301.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22302 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[2] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[3] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[4] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[5] ), .O(n14720)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22302.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22303 (.I0(n14719), .I1(n14720), .O(n14721)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22303.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22304 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[17] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[18] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[19] ), + .O(n14722)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__22304.LUTMASK = 16'h0101; + EFX_LUT4 LUT__22305 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[1] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16] ), + .O(n14723)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22305.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22306 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[12] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[13] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[14] ), + .O(n14724)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22306.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22307 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[8] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[9] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[10] ), + .O(n14725)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22307.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22308 (.I0(n14722), .I1(n14723), .I2(n14724), .I3(n14725), + .O(n14726)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22308.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22309 (.I0(n14721), .I1(n14726), .O(n14727)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22309.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22310 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[14] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[13] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[12] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[11] ), .O(n14728)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22310.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22311 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[15] ), + .I1(n14727), .I2(n14728), .O(n14729)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22311.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22312 (.I0(n14718), .I1(n14729), .O(n14730)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22312.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22313 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0] ), + .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n137 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22313.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22314 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), + .O(n14731)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4141 */ ; + defparam LUT__22314.LUTMASK = 16'h4141; + EFX_LUT4 LUT__22315 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3] ), .O(n14732)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22315.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22316 (.I0(n14731), .I1(n14732), .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), .O(n14733)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfb0f */ ; + defparam LUT__22316.LUTMASK = 16'hfb0f; + EFX_LUT4 LUT__22317 (.I0(\ar0135_i2c_config_index[5] ), .I1(\ar0135_i2c_config_index[6] ), + .I2(\ar0135_i2c_config_index[7] ), .O(n14734)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__22317.LUTMASK = 16'h0101; + EFX_LUT4 LUT__22318 (.I0(\ar0135_i2c_config_index[4] ), .I1(\ar0135_i2c_config_index[3] ), + .I2(n14734), .O(n14735)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__22318.LUTMASK = 16'h7070; + EFX_LUT4 LUT__22319 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), .O(n14736)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22319.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22320 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), + .O(n14737)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22320.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22321 (.I0(n14736), .I1(n14737), .O(n14738)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22321.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22322 (.I0(n14721), .I1(n14735), .I2(n14726), .I3(n14738), + .O(n14739)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22322.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22323 (.I0(n14739), .I1(n14733), .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] ), + .O(n14740)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__22323.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__22324 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), .O(n14741)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22324.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22325 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), .I2(n14732), + .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), .O(n14742)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c0a */ ; + defparam LUT__22325.LUTMASK = 16'h0c0a; + EFX_LUT4 LUT__22326 (.I0(n14732), .I1(n14736), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), .O(n14743)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h004f */ ; + defparam LUT__22326.LUTMASK = 16'h004f; + EFX_LUT4 LUT__22327 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), .O(n14744)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22327.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22328 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), + .I1(n14741), .I2(n14744), .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] ), + .O(n14745)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__22328.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__22329 (.I0(n14742), .I1(n14741), .I2(n14743), .I3(n14745), + .O(n14746)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b00 */ ; + defparam LUT__22329.LUTMASK = 16'h0b00; + EFX_LUT4 LUT__22330 (.I0(n14740), .I1(n14746), .O(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heeee */ ; + defparam LUT__22330.LUTMASK = 16'heeee; + EFX_LUT4 LUT__22331 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[4] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[3] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[2] ), .O(n14747)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22331.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22332 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[1] ), + .I1(n14747), .O(n14748)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22332.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22333 (.I0(n14748), .I1(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5] ), + .O(n14749)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22333.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22334 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7] ), .O(n14750)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22334.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22335 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6] ), + .I1(n14749), .I2(n14750), .I3(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9] ), + .O(n14751)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h001f */ ; + defparam LUT__22335.LUTMASK = 16'h001f; + EFX_LUT4 LUT__22336 (.I0(n14749), .I1(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6] ), + .I2(n14750), .I3(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9] ), + .O(n14752)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h007f */ ; + defparam LUT__22336.LUTMASK = 16'h007f; + EFX_LUT4 LUT__22337 (.I0(n14752), .I1(n14751), .I2(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10] ), + .I3(n14729), .O(\u_i2c_timing_ctrl_16reg_16bit/n138 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc500 */ ; + defparam LUT__22337.LUTMASK = 16'hc500; + EFX_LUT4 LUT__22338 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[10] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[6] ), .I2(n14729), + .O(n14753)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22338.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22339 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[8] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[7] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[5] ), .O(n14754)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22339.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22340 (.I0(n14748), .I1(n14753), .I2(n14754), .O(\u_i2c_timing_ctrl_16reg_16bit/n139 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22340.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22341 (.I0(\u_i2c_timing_ctrl_16reg_16bit/clk_cnt[9] ), + .I1(n14716), .I2(n14750), .I3(n14753), .O(\u_i2c_timing_ctrl_16reg_16bit/n140 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22341.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22342 (.I0(\ar0135_i2c_config_index[0] ), .I1(n14735), + .O(\u_i2c_timing_ctrl_16reg_16bit/n205 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22342.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22343 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack ), .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), + .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] ), .O(n14755)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4141 */ ; + defparam LUT__22343.LUTMASK = 16'h4141; + EFX_LUT4 LUT__22344 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), .I2(n14744), + .I3(n14755), .O(\u_i2c_timing_ctrl_16reg_16bit/n846 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__22344.LUTMASK = 16'h4000; + EFX_LUT4 LUT__22345 (.I0(n4922), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n122 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22345.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22346 (.I0(n4923), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n123 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22346.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22347 (.I0(n4925), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n124 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22347.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22348 (.I0(n4927), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n125 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22348.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22349 (.I0(n4929), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n126 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22349.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22350 (.I0(n4931), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n127 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22350.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22351 (.I0(n4933), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n128 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22351.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22352 (.I0(n4935), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n129 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22352.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22353 (.I0(n4937), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n130 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22353.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22354 (.I0(n4939), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n131 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22354.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22355 (.I0(n4941), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n132 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22355.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22356 (.I0(n4943), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n133 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22356.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22357 (.I0(n4945), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n134 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22357.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22358 (.I0(n4947), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n135 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22358.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22359 (.I0(n3754), .I1(n14730), .O(\u_i2c_timing_ctrl_16reg_16bit/n136 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22359.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22360 (.I0(n14744), .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), + .I2(n14741), .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] ), + .O(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5780 */ ; + defparam LUT__22360.LUTMASK = 16'h5780; + EFX_LUT4 LUT__22361 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] ), + .I1(n14744), .O(n14756)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22361.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22362 (.I0(n14746), .I1(n14741), .I2(n14756), .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), + .O(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b04 */ ; + defparam LUT__22362.LUTMASK = 16'h0b04; + EFX_LUT4 LUT__22363 (.I0(\ar0135_i2c_config_index[1] ), .I1(\ar0135_i2c_config_index[3] ), + .I2(\ar0135_i2c_config_index[2] ), .I3(\ar0135_i2c_config_index[0] ), + .O(n14757)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3ffa */ ; + defparam LUT__22363.LUTMASK = 16'h3ffa; + EFX_LUT4 LUT__22364 (.I0(\ar0135_i2c_config_index[2] ), .I1(\ar0135_i2c_config_index[3] ), + .O(n14758)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22364.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22365 (.I0(\ar0135_i2c_config_index[4] ), .I1(n14757), + .I2(n14758), .I3(n14734), .O(n14759)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22365.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22366 (.I0(n14719), .I1(n14720), .I2(n14737), .O(n14760)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22366.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22367 (.I0(n14760), .I1(n14726), .I2(n14759), .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), + .O(n14761)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h007f */ ; + defparam LUT__22367.LUTMASK = 16'h007f; + EFX_LUT4 LUT__22368 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), + .I1(n13396), .O(n14762)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22368.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22369 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), .O(n14763)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8a7f */ ; + defparam LUT__22369.LUTMASK = 16'h8a7f; + EFX_LUT4 LUT__22370 (.I0(n14761), .I1(n14762), .I2(n14763), .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] ), + .O(n14764)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h004f */ ; + defparam LUT__22370.LUTMASK = 16'h004f; + EFX_LUT4 LUT__22371 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), + .I1(n14741), .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), + .I3(n14732), .O(n14765)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h570f */ ; + defparam LUT__22371.LUTMASK = 16'h570f; + EFX_LUT4 LUT__22372 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), + .I3(n14741), .O(n14766)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbaf0 */ ; + defparam LUT__22372.LUTMASK = 16'hbaf0; + EFX_LUT4 LUT__22373 (.I0(n14765), .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), + .I2(n14766), .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] ), + .O(n14767)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb000 */ ; + defparam LUT__22373.LUTMASK = 16'hb000; + EFX_LUT4 LUT__22374 (.I0(n14764), .I1(n14767), .O(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heeee */ ; + defparam LUT__22374.LUTMASK = 16'heeee; + EFX_LUT4 LUT__22375 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), + .I1(n14726), .I2(n14759), .I3(n14760), .O(n14768)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__22375.LUTMASK = 16'h4000; + EFX_LUT4 LUT__22376 (.I0(n14741), .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[2] ), + .I2(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), + .O(n14769)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h007f */ ; + defparam LUT__22376.LUTMASK = 16'h007f; + EFX_LUT4 LUT__22377 (.I0(\u_i2c_timing_ctrl_16reg_16bit/current_state[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[1] ), .O(n14770)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22377.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22378 (.I0(n14770), .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), + .I2(n14744), .I3(\u_i2c_timing_ctrl_16reg_16bit/current_state[4] ), + .O(n14771)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00bf */ ; + defparam LUT__22378.LUTMASK = 16'h00bf; + EFX_LUT4 LUT__22379 (.I0(n14732), .I1(\u_i2c_timing_ctrl_16reg_16bit/current_state[3] ), + .I2(n14769), .I3(n14745), .O(n14772)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0e00 */ ; + defparam LUT__22379.LUTMASK = 16'h0e00; + EFX_LUT4 LUT__22380 (.I0(n14768), .I1(n14769), .I2(n14771), .I3(n14772), + .O(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hffb0 */ ; + defparam LUT__22380.LUTMASK = 16'hffb0; + EFX_LUT4 LUT__22381 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), .O(n14773)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h57bc */ ; + defparam LUT__22381.LUTMASK = 16'h57bc; + EFX_LUT4 LUT__22382 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I3(n14773), .O(n14774)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h03ce */ ; + defparam LUT__22382.LUTMASK = 16'h03ce; + EFX_LUT4 LUT__22383 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0] ), + .I1(n14774), .O(\u_i2c_timing_ctrl_16reg_16bit/n500 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22383.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22384 (.I0(n14769), .I1(n14771), .O(n14775)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22384.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22385 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I1(n14775), .O(n14776)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22385.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22386 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), .O(n14777)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22386.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22387 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .I1(n14776), .I2(n14777), .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), + .O(ceg_net4141)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__22387.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__22388 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), .O(n14778)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1004 */ ; + defparam LUT__22388.LUTMASK = 16'h1004; + EFX_LUT4 LUT__22389 (.I0(\ar0135_i2c_config_index[0] ), .I1(\ar0135_i2c_config_index[4] ), + .I2(\ar0135_i2c_config_index[3] ), .I3(\ar0135_i2c_config_index[2] ), + .O(n14779)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he7fe */ ; + defparam LUT__22389.LUTMASK = 16'he7fe; + EFX_LUT4 LUT__22390 (.I0(\ar0135_i2c_config_index[1] ), .I1(n14779), + .I2(n14734), .O(n14780)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22390.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22391 (.I0(\ar0135_i2c_config_index[0] ), .I1(\ar0135_i2c_config_index[1] ), + .I2(\ar0135_i2c_config_index[4] ), .I3(n14734), .O(n14781)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__22391.LUTMASK = 16'h4000; + EFX_LUT4 LUT__22392 (.I0(\ar0135_i2c_config_index[3] ), .I1(\ar0135_i2c_config_index[2] ), + .I2(n14781), .O(n14782)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22392.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22393 (.I0(n14782), .I1(n14780), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .O(n14783)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22393.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22394 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .I1(n14782), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), .O(n14784)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h770f */ ; + defparam LUT__22394.LUTMASK = 16'h770f; + EFX_LUT4 LUT__22395 (.I0(\ar0135_i2c_config_index[3] ), .I1(\ar0135_i2c_config_index[4] ), + .I2(\ar0135_i2c_config_index[0] ), .I3(\ar0135_i2c_config_index[2] ), + .O(n14785)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hdcab */ ; + defparam LUT__22395.LUTMASK = 16'hdcab; + EFX_LUT4 LUT__22396 (.I0(\ar0135_i2c_config_index[1] ), .I1(\ar0135_i2c_config_index[3] ), + .I2(\ar0135_i2c_config_index[4] ), .O(n14786)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd3d3 */ ; + defparam LUT__22396.LUTMASK = 16'hd3d3; + EFX_LUT4 LUT__22397 (.I0(\ar0135_i2c_config_index[0] ), .I1(n14786), + .I2(\ar0135_i2c_config_index[2] ), .O(n14787)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22397.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22398 (.I0(n14785), .I1(\ar0135_i2c_config_index[1] ), + .I2(n14787), .I3(n14734), .O(n14788)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf100 */ ; + defparam LUT__22398.LUTMASK = 16'hf100; + EFX_LUT4 LUT__22399 (.I0(n14788), .I1(n14784), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .O(n14789)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3a3a */ ; + defparam LUT__22399.LUTMASK = 16'h3a3a; + EFX_LUT4 LUT__22400 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .I1(n14783), .I2(n14789), .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .O(n14790)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0f77 */ ; + defparam LUT__22400.LUTMASK = 16'h0f77; + EFX_LUT4 LUT__22401 (.I0(n14778), .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0] ), + .I2(n14790), .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .O(\u_i2c_timing_ctrl_16reg_16bit/n509 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h440f */ ; + defparam LUT__22401.LUTMASK = 16'h440f; + EFX_LUT4 LUT__22402 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), .O(n14791)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f1 */ ; + defparam LUT__22402.LUTMASK = 16'h00f1; + EFX_LUT4 LUT__22403 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), .O(n14792)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0503 */ ; + defparam LUT__22403.LUTMASK = 16'h0503; + EFX_LUT4 LUT__22404 (.I0(n14792), .I1(n14791), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), + .O(ceg_net4466)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd0d0 */ ; + defparam LUT__22404.LUTMASK = 16'hd0d0; + EFX_LUT4 LUT__22405 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), .O(n14793)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22405.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22406 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I3(n14793), .O(n14794)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22406.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22407 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), .O(n14795)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22407.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22408 (.I0(n14792), .I1(n14795), .O(n14796)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22408.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22409 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack5 ), .I1(cmos_sdat_IN), + .I2(n14794), .I3(n14796), .O(\u_i2c_timing_ctrl_16reg_16bit/n567 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfcfa */ ; + defparam LUT__22409.LUTMASK = 16'hfcfa; + EFX_LUT4 LUT__22410 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .I1(n14746), .I2(n14740), .O(n14797)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__22410.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__22411 (.I0(n14797), .I1(n14793), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .O(n14798)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22411.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22412 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack4 ), .I1(cmos_sdat_IN), + .I2(n14794), .I3(n14798), .O(\u_i2c_timing_ctrl_16reg_16bit/n570 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfcfa */ ; + defparam LUT__22412.LUTMASK = 16'hfcfa; + EFX_LUT4 LUT__22413 (.I0(n14797), .I1(n14740), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), .O(n14799)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0c0a */ ; + defparam LUT__22413.LUTMASK = 16'h0c0a; + EFX_LUT4 LUT__22414 (.I0(cmos_sdat_IN), .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack3 ), + .I2(n14795), .I3(n14799), .O(n14800)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'haccc */ ; + defparam LUT__22414.LUTMASK = 16'haccc; + EFX_LUT4 LUT__22415 (.I0(n14794), .I1(n14800), .O(\u_i2c_timing_ctrl_16reg_16bit/n573 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heeee */ ; + defparam LUT__22415.LUTMASK = 16'heeee; + EFX_LUT4 LUT__22416 (.I0(cmos_sdat_IN), .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack2 ), + .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), .I3(n14799), + .O(n14801)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcacc */ ; + defparam LUT__22416.LUTMASK = 16'hcacc; + EFX_LUT4 LUT__22417 (.I0(n14794), .I1(n14801), .O(\u_i2c_timing_ctrl_16reg_16bit/n576 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heeee */ ; + defparam LUT__22417.LUTMASK = 16'heeee; + EFX_LUT4 LUT__22418 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .I3(n14795), .O(n14802)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4100 */ ; + defparam LUT__22418.LUTMASK = 16'h4100; + EFX_LUT4 LUT__22419 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack1 ), .I1(cmos_sdat_IN), + .I2(n14794), .I3(n14802), .O(\u_i2c_timing_ctrl_16reg_16bit/n579 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfcfa */ ; + defparam LUT__22419.LUTMASK = 16'hfcfa; + EFX_LUT4 LUT__22420 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack4 ), .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack3 ), + .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack2 ), .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack1 ), + .O(n14803)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22420.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22421 (.I0(n14803), .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack5 ), + .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), .I3(n14775), + .O(n14804)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d00 */ ; + defparam LUT__22421.LUTMASK = 16'h0d00; + EFX_LUT4 LUT__22422 (.I0(n14803), .I1(n14772), .I2(n14804), .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .O(n14805)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbb0f */ ; + defparam LUT__22422.LUTMASK = 16'hbb0f; + EFX_LUT4 LUT__22423 (.I0(n14797), .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I2(n14777), .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_ack ), .O(n14806)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f00 */ ; + defparam LUT__22423.LUTMASK = 16'h7f00; + EFX_LUT4 LUT__22424 (.I0(n14805), .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .I2(n14806), .I3(n14794), .O(\u_i2c_timing_ctrl_16reg_16bit/n581 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff4 */ ; + defparam LUT__22424.LUTMASK = 16'hfff4; + EFX_LUT4 LUT__22425 (.I0(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[11] ), + .I1(n14725), .I2(n14724), .I3(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[15] ), + .O(n14807)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h001f */ ; + defparam LUT__22425.LUTMASK = 16'h001f; + EFX_LUT4 LUT__22426 (.I0(n14807), .I1(\u_i2c_timing_ctrl_16reg_16bit/delay_cnt[16] ), + .I2(n14722), .O(\u_i2c_timing_ctrl_16reg_16bit/n7 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hb0b0 */ ; + defparam LUT__22426.LUTMASK = 16'hb0b0; + EFX_LUT4 LUT__22427 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1] ), .O(n14808)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__22427.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__22428 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0] ), + .I3(n14808), .O(n14809)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__22428.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__22429 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1] ), .O(n14810)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha0cf */ ; + defparam LUT__22429.LUTMASK = 16'ha0cf; + EFX_LUT4 LUT__22430 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0] ), + .I3(n14810), .O(n14811)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc0a */ ; + defparam LUT__22430.LUTMASK = 16'hfc0a; + EFX_LUT4 LUT__22431 (.I0(n14811), .I1(n14809), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2] ), + .O(n14812)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22431.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22432 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), .I2(n14812), + .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), .O(n14813)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0fee */ ; + defparam LUT__22432.LUTMASK = 16'h0fee; + EFX_LUT4 LUT__22433 (.I0(n14795), .I1(cmos_sdat_OUT), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), .O(n14814)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h007f */ ; + defparam LUT__22433.LUTMASK = 16'h007f; + EFX_LUT4 LUT__22434 (.I0(n14812), .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I2(n14793), .I3(n14814), .O(n14815)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7d00 */ ; + defparam LUT__22434.LUTMASK = 16'h7d00; + EFX_LUT4 LUT__22435 (.I0(cmos_sdat_OUT), .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .O(n14816)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h57c5 */ ; + defparam LUT__22435.LUTMASK = 16'h57c5; + EFX_LUT4 LUT__22436 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2] ), + .O(n14817)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22436.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22437 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3] ), + .I1(n14817), .O(n14818)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22437.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22438 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .I1(n14818), .I2(n14812), .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .O(n14819)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf70f */ ; + defparam LUT__22438.LUTMASK = 16'hf70f; + EFX_LUT4 LUT__22439 (.I0(cmos_sdat_OUT), .I1(n14819), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), .O(n14820)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca03 */ ; + defparam LUT__22439.LUTMASK = 16'hca03; + EFX_LUT4 LUT__22440 (.I0(n14820), .I1(n14816), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), .O(n14821)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc500 */ ; + defparam LUT__22440.LUTMASK = 16'hc500; + EFX_LUT4 LUT__22441 (.I0(n14813), .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I2(n14815), .I3(n14821), .O(\u_i2c_timing_ctrl_16reg_16bit/n495 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h001f */ ; + defparam LUT__22441.LUTMASK = 16'h001f; + EFX_LUT4 LUT__22442 (.I0(n14740), .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I2(n14793), .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_transfer_en ), + .O(ceg_net4426)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7d00 */ ; + defparam LUT__22442.LUTMASK = 16'h7d00; + EFX_LUT4 LUT__22443 (.I0(n3757), .I1(n14735), .O(\u_i2c_timing_ctrl_16reg_16bit/n204 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22443.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22444 (.I0(n4920), .I1(n14735), .O(\u_i2c_timing_ctrl_16reg_16bit/n203 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22444.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22445 (.I0(n4918), .I1(n14735), .O(\u_i2c_timing_ctrl_16reg_16bit/n202 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__22445.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__22446 (.I0(n4916), .I1(n14735), .O(\u_i2c_timing_ctrl_16reg_16bit/n201 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__22446.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__22447 (.I0(n4914), .I1(n14735), .O(\u_i2c_timing_ctrl_16reg_16bit/n200 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22447.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22448 (.I0(n4912), .I1(n14735), .O(\u_i2c_timing_ctrl_16reg_16bit/n199 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22448.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22449 (.I0(n4911), .I1(n14735), .O(\u_i2c_timing_ctrl_16reg_16bit/n198 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22449.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22450 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1] ), .I2(n14774), + .O(\u_i2c_timing_ctrl_16reg_16bit/n499 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__22450.LUTMASK = 16'h6060; + EFX_LUT4 LUT__22451 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[1] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[2] ), + .I3(n14774), .O(\u_i2c_timing_ctrl_16reg_16bit/n498 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7800 */ ; + defparam LUT__22451.LUTMASK = 16'h7800; + EFX_LUT4 LUT__22452 (.I0(\u_i2c_timing_ctrl_16reg_16bit/i2c_stream_cnt[3] ), + .I1(n14817), .I2(n14774), .O(\u_i2c_timing_ctrl_16reg_16bit/n497 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__22452.LUTMASK = 16'h6060; + EFX_LUT4 LUT__22453 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .O(n14822)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__22453.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__22454 (.I0(n14778), .I1(n14822), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1] ), + .O(n14823)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22454.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22455 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), .O(n14824)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22455.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22456 (.I0(\ar0135_i2c_config_index[2] ), .I1(\ar0135_i2c_config_index[1] ), + .I2(\ar0135_i2c_config_index[0] ), .I3(\ar0135_i2c_config_index[4] ), + .O(n14825)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4ccf */ ; + defparam LUT__22456.LUTMASK = 16'h4ccf; + EFX_LUT4 LUT__22457 (.I0(\ar0135_i2c_config_index[1] ), .I1(\ar0135_i2c_config_index[2] ), + .I2(\ar0135_i2c_config_index[3] ), .I3(\ar0135_i2c_config_index[0] ), + .O(n14826)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfc17 */ ; + defparam LUT__22457.LUTMASK = 16'hfc17; + EFX_LUT4 LUT__22458 (.I0(n14826), .I1(\ar0135_i2c_config_index[4] ), + .I2(\ar0135_i2c_config_index[3] ), .I3(n14825), .O(n14827)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heee0 */ ; + defparam LUT__22458.LUTMASK = 16'heee0; + EFX_LUT4 LUT__22459 (.I0(n14827), .I1(n14734), .O(n14828)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22459.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22460 (.I0(\ar0135_i2c_config_index[1] ), .I1(\ar0135_i2c_config_index[0] ), + .I2(\ar0135_i2c_config_index[3] ), .I3(\ar0135_i2c_config_index[4] ), + .O(n14829)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfb4f */ ; + defparam LUT__22460.LUTMASK = 16'hfb4f; + EFX_LUT4 LUT__22461 (.I0(n14829), .I1(n14734), .I2(\ar0135_i2c_config_index[2] ), + .O(n14830)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22461.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22462 (.I0(n14828), .I1(n14830), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .I3(n14764), .O(n14831)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__22462.LUTMASK = 16'hca00; + EFX_LUT4 LUT__22463 (.I0(n14824), .I1(n14828), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .I3(n14831), .O(n14832)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h007f */ ; + defparam LUT__22463.LUTMASK = 16'h007f; + EFX_LUT4 LUT__22464 (.I0(\ar0135_i2c_config_index[0] ), .I1(\ar0135_i2c_config_index[1] ), + .I2(\ar0135_i2c_config_index[4] ), .I3(\ar0135_i2c_config_index[3] ), + .O(n14833)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf0bb */ ; + defparam LUT__22464.LUTMASK = 16'hf0bb; + EFX_LUT4 LUT__22465 (.I0(n14833), .I1(n14734), .I2(\ar0135_i2c_config_index[2] ), + .O(n14834)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22465.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22466 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[1] ), .I2(n14834), + .I3(n14822), .O(n14835)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbb0f */ ; + defparam LUT__22466.LUTMASK = 16'hbb0f; + EFX_LUT4 LUT__22467 (.I0(n14823), .I1(n14832), .I2(n14835), .I3(n14775), + .O(\u_i2c_timing_ctrl_16reg_16bit/n508 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0fbb */ ; + defparam LUT__22467.LUTMASK = 16'h0fbb; + EFX_LUT4 LUT__22468 (.I0(n14778), .I1(n14822), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2] ), + .O(n14836)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22468.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22469 (.I0(\ar0135_i2c_config_index[4] ), .I1(n14757), + .I2(n14734), .O(n14837)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22469.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22470 (.I0(\ar0135_i2c_config_index[1] ), .I1(\ar0135_i2c_config_index[3] ), + .I2(\ar0135_i2c_config_index[4] ), .I3(\ar0135_i2c_config_index[2] ), + .O(n14838)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1700 */ ; + defparam LUT__22470.LUTMASK = 16'h1700; + EFX_LUT4 LUT__22471 (.I0(n14829), .I1(n14838), .I2(\ar0135_i2c_config_index[0] ), + .I3(n14734), .O(n14839)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1c00 */ ; + defparam LUT__22471.LUTMASK = 16'h1c00; + EFX_LUT4 LUT__22472 (.I0(n14839), .I1(n14837), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .O(n14840)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22472.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22473 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .I1(n14824), .I2(n14764), .I3(n14840), .O(n14841)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__22473.LUTMASK = 16'hf800; + EFX_LUT4 LUT__22474 (.I0(\ar0135_i2c_config_index[3] ), .I1(\ar0135_i2c_config_index[0] ), + .O(n14842)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22474.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22475 (.I0(\ar0135_i2c_config_index[2] ), .I1(n14842), + .O(n14843)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22475.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22476 (.I0(\ar0135_i2c_config_index[0] ), .I1(\ar0135_i2c_config_index[4] ), + .I2(\ar0135_i2c_config_index[3] ), .I3(\ar0135_i2c_config_index[2] ), + .O(n14844)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3001 */ ; + defparam LUT__22476.LUTMASK = 16'h3001; + EFX_LUT4 LUT__22477 (.I0(n14844), .I1(n14843), .I2(\ar0135_i2c_config_index[1] ), + .I3(n14734), .O(n14845)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hca00 */ ; + defparam LUT__22477.LUTMASK = 16'hca00; + EFX_LUT4 LUT__22478 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[2] ), .I2(n14845), + .I3(n14822), .O(n14846)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbb0f */ ; + defparam LUT__22478.LUTMASK = 16'hbb0f; + EFX_LUT4 LUT__22479 (.I0(n14841), .I1(n14836), .I2(n14846), .I3(n14775), + .O(\u_i2c_timing_ctrl_16reg_16bit/n507 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0fee */ ; + defparam LUT__22479.LUTMASK = 16'h0fee; + EFX_LUT4 LUT__22480 (.I0(n14776), .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .I2(n14778), .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .O(n14847)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7077 */ ; + defparam LUT__22480.LUTMASK = 16'h7077; + EFX_LUT4 LUT__22481 (.I0(\ar0135_i2c_config_index[1] ), .I1(\ar0135_i2c_config_index[0] ), + .I2(\ar0135_i2c_config_index[2] ), .I3(\ar0135_i2c_config_index[3] ), + .O(n14848)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9ef3 */ ; + defparam LUT__22481.LUTMASK = 16'h9ef3; + EFX_LUT4 LUT__22482 (.I0(\ar0135_i2c_config_index[4] ), .I1(\ar0135_i2c_config_index[0] ), + .O(n14849)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22482.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22483 (.I0(\ar0135_i2c_config_index[4] ), .I1(\ar0135_i2c_config_index[2] ), + .I2(\ar0135_i2c_config_index[0] ), .I3(\ar0135_i2c_config_index[3] ), + .O(n14850)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfa3f */ ; + defparam LUT__22483.LUTMASK = 16'hfa3f; + EFX_LUT4 LUT__22484 (.I0(\ar0135_i2c_config_index[1] ), .I1(n14848), + .I2(n14850), .I3(n14849), .O(n14851)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3f0a */ ; + defparam LUT__22484.LUTMASK = 16'h3f0a; + EFX_LUT4 LUT__22485 (.I0(\ar0135_i2c_config_index[1] ), .I1(\ar0135_i2c_config_index[4] ), + .I2(\ar0135_i2c_config_index[0] ), .I3(\ar0135_i2c_config_index[3] ), + .O(n14852)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3207 */ ; + defparam LUT__22485.LUTMASK = 16'h3207; + EFX_LUT4 LUT__22486 (.I0(\ar0135_i2c_config_index[2] ), .I1(\ar0135_i2c_config_index[1] ), + .I2(\ar0135_i2c_config_index[4] ), .I3(n14842), .O(n14853)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc700 */ ; + defparam LUT__22486.LUTMASK = 16'hc700; + EFX_LUT4 LUT__22487 (.I0(n14767), .I1(n14746), .O(n14854)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22487.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22488 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .I1(n14854), .I2(n14764), .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .O(n14855)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00f4 */ ; + defparam LUT__22488.LUTMASK = 16'h00f4; + EFX_LUT4 LUT__22489 (.I0(\ar0135_i2c_config_index[2] ), .I1(n14852), + .I2(n14853), .I3(n14855), .O(n14856)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__22489.LUTMASK = 16'hf800; + EFX_LUT4 LUT__22490 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .I1(n14851), .I2(n14856), .I3(n14775), .O(n14857)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbb0f */ ; + defparam LUT__22490.LUTMASK = 16'hbb0f; + EFX_LUT4 LUT__22491 (.I0(n14857), .I1(n14734), .I2(n14847), .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[3] ), + .O(\u_i2c_timing_ctrl_16reg_16bit/n506 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4f44 */ ; + defparam LUT__22491.LUTMASK = 16'h4f44; + EFX_LUT4 LUT__22492 (.I0(\ar0135_i2c_config_index[1] ), .I1(\ar0135_i2c_config_index[0] ), + .I2(\ar0135_i2c_config_index[2] ), .I3(\ar0135_i2c_config_index[4] ), + .O(n14858)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3ff2 */ ; + defparam LUT__22492.LUTMASK = 16'h3ff2; + EFX_LUT4 LUT__22493 (.I0(\ar0135_i2c_config_index[1] ), .I1(\ar0135_i2c_config_index[0] ), + .I2(\ar0135_i2c_config_index[2] ), .I3(\ar0135_i2c_config_index[4] ), + .O(n14859)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd08c */ ; + defparam LUT__22493.LUTMASK = 16'hd08c; + EFX_LUT4 LUT__22494 (.I0(n14858), .I1(n14859), .I2(\ar0135_i2c_config_index[3] ), + .I3(n14734), .O(n14860)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1c00 */ ; + defparam LUT__22494.LUTMASK = 16'h1c00; + EFX_LUT4 LUT__22495 (.I0(n14824), .I1(n14860), .I2(n14778), .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4] ), + .O(n14861)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7077 */ ; + defparam LUT__22495.LUTMASK = 16'h7077; + EFX_LUT4 LUT__22496 (.I0(\ar0135_i2c_config_index[4] ), .I1(\ar0135_i2c_config_index[3] ), + .I2(\ar0135_i2c_config_index[0] ), .I3(\ar0135_i2c_config_index[1] ), + .O(n14862)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfe3f */ ; + defparam LUT__22496.LUTMASK = 16'hfe3f; + EFX_LUT4 LUT__22497 (.I0(n14862), .I1(\ar0135_i2c_config_index[2] ), + .I2(n14735), .O(n14863)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0e0 */ ; + defparam LUT__22497.LUTMASK = 16'he0e0; + EFX_LUT4 LUT__22498 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .I1(n14863), .O(n14864)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22498.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22499 (.I0(n14864), .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[4] ), + .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), .O(n14865)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22499.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22500 (.I0(\ar0135_i2c_config_index[0] ), .I1(\ar0135_i2c_config_index[4] ), + .I2(\ar0135_i2c_config_index[3] ), .O(n14866)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he3e3 */ ; + defparam LUT__22500.LUTMASK = 16'he3e3; + EFX_LUT4 LUT__22501 (.I0(n14866), .I1(\ar0135_i2c_config_index[0] ), + .I2(n14785), .O(n14867)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5c5c */ ; + defparam LUT__22501.LUTMASK = 16'h5c5c; + EFX_LUT4 LUT__22502 (.I0(\ar0135_i2c_config_index[1] ), .I1(n14866), + .O(n14868)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22502.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22503 (.I0(n14867), .I1(n14837), .I2(n14868), .I3(n14734), + .O(n14869)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0e00 */ ; + defparam LUT__22503.LUTMASK = 16'h0e00; + EFX_LUT4 LUT__22504 (.I0(n14869), .I1(n14865), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .O(n14870)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22504.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22505 (.I0(\ar0135_i2c_config_index[2] ), .I1(\ar0135_i2c_config_index[4] ), + .I2(\ar0135_i2c_config_index[1] ), .I3(n14842), .O(n14871)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9000 */ ; + defparam LUT__22505.LUTMASK = 16'h9000; + EFX_LUT4 LUT__22506 (.I0(n14860), .I1(n14871), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .I3(n14864), .O(n14872)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcfa0 */ ; + defparam LUT__22506.LUTMASK = 16'hcfa0; + EFX_LUT4 LUT__22507 (.I0(n14872), .I1(n14870), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .O(n14873)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22507.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22508 (.I0(n14873), .I1(n14861), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .O(\u_i2c_timing_ctrl_16reg_16bit/n505 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3a3a */ ; + defparam LUT__22508.LUTMASK = 16'h3a3a; + EFX_LUT4 LUT__22509 (.I0(\ar0135_i2c_config_index[3] ), .I1(\ar0135_i2c_config_index[4] ), + .O(n14874)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22509.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22510 (.I0(\ar0135_i2c_config_index[0] ), .I1(\ar0135_i2c_config_index[1] ), + .I2(\ar0135_i2c_config_index[4] ), .I3(\ar0135_i2c_config_index[3] ), + .O(n14875)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfe4f */ ; + defparam LUT__22510.LUTMASK = 16'hfe4f; + EFX_LUT4 LUT__22511 (.I0(n14875), .I1(n14874), .I2(\ar0135_i2c_config_index[2] ), + .I3(n14734), .O(n14876)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc500 */ ; + defparam LUT__22511.LUTMASK = 16'hc500; + EFX_LUT4 LUT__22512 (.I0(n14876), .I1(n14824), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5] ), + .I3(n14778), .O(n14877)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbb0 */ ; + defparam LUT__22512.LUTMASK = 16'hbbb0; + EFX_LUT4 LUT__22513 (.I0(n14863), .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[5] ), .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .O(n14878)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbf0 */ ; + defparam LUT__22513.LUTMASK = 16'hbbf0; + EFX_LUT4 LUT__22514 (.I0(n14852), .I1(\ar0135_i2c_config_index[4] ), + .I2(n14734), .I3(\ar0135_i2c_config_index[2] ), .O(n14879)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22514.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22515 (.I0(\ar0135_i2c_config_index[3] ), .I1(\ar0135_i2c_config_index[1] ), + .I2(\ar0135_i2c_config_index[2] ), .I3(\ar0135_i2c_config_index[0] ), + .O(n14880)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f75 */ ; + defparam LUT__22515.LUTMASK = 16'h1f75; + EFX_LUT4 LUT__22516 (.I0(n14880), .I1(n14879), .I2(\ar0135_i2c_config_index[4] ), + .I3(n14734), .O(n14881)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc500 */ ; + defparam LUT__22516.LUTMASK = 16'hc500; + EFX_LUT4 LUT__22517 (.I0(n14881), .I1(n14878), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .O(n14882)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22517.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22518 (.I0(n14863), .I1(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), .O(n14883)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5353 */ ; + defparam LUT__22518.LUTMASK = 16'h5353; + EFX_LUT4 LUT__22519 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .I1(n14876), .I2(n14883), .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[2] ), + .O(n14884)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbf0 */ ; + defparam LUT__22519.LUTMASK = 16'hbbf0; + EFX_LUT4 LUT__22520 (.I0(n14884), .I1(n14882), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[3] ), + .O(n14885)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc5c5 */ ; + defparam LUT__22520.LUTMASK = 16'hc5c5; + EFX_LUT4 LUT__22521 (.I0(n14885), .I1(n14877), .I2(\u_i2c_timing_ctrl_16reg_16bit/next_state[4] ), + .O(\u_i2c_timing_ctrl_16reg_16bit/n504 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22521.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22522 (.I0(\ar0135_i2c_config_index[4] ), .I1(\ar0135_i2c_config_index[3] ), + .I2(n14858), .I3(n14734), .O(n14886)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4300 */ ; + defparam LUT__22522.LUTMASK = 16'h4300; + EFX_LUT4 LUT__22523 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6] ), .I2(n14886), + .I3(n14822), .O(n14887)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbb0f */ ; + defparam LUT__22523.LUTMASK = 16'hbb0f; + EFX_LUT4 LUT__22524 (.I0(n14781), .I1(n14758), .I2(n14879), .I3(n14855), + .O(n14888)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf800 */ ; + defparam LUT__22524.LUTMASK = 16'hf800; + EFX_LUT4 LUT__22525 (.I0(n14778), .I1(n14822), .I2(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[6] ), + .I3(n14888), .O(n14889)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h00ef */ ; + defparam LUT__22525.LUTMASK = 16'h00ef; + EFX_LUT4 LUT__22526 (.I0(n14889), .I1(n14887), .I2(n14775), .O(\u_i2c_timing_ctrl_16reg_16bit/n503 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3535 */ ; + defparam LUT__22526.LUTMASK = 16'h3535; + EFX_LUT4 LUT__22527 (.I0(n14848), .I1(n14843), .I2(\ar0135_i2c_config_index[4] ), + .I3(n14734), .O(n14890)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc500 */ ; + defparam LUT__22527.LUTMASK = 16'hc500; + EFX_LUT4 LUT__22528 (.I0(\u_i2c_timing_ctrl_16reg_16bit/next_state[0] ), + .I1(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7] ), .I2(n14890), + .I3(n14822), .O(n14891)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbb0f */ ; + defparam LUT__22528.LUTMASK = 16'hbb0f; + EFX_LUT4 LUT__22529 (.I0(\ar0135_i2c_config_index[1] ), .I1(\ar0135_i2c_config_index[2] ), + .I2(n14866), .I3(n14734), .O(n14892)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22529.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22530 (.I0(n14781), .I1(n14758), .I2(n14892), .I3(\u_i2c_timing_ctrl_16reg_16bit/next_state[1] ), + .O(n14893)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h770f */ ; + defparam LUT__22530.LUTMASK = 16'h770f; + EFX_LUT4 LUT__22531 (.I0(n14824), .I1(n14892), .I2(n14778), .I3(\u_i2c_timing_ctrl_16reg_16bit/i2c_wdata[7] ), + .O(n14894)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7077 */ ; + defparam LUT__22531.LUTMASK = 16'h7077; + EFX_LUT4 LUT__22532 (.I0(n14822), .I1(n14894), .I2(n14893), .I3(n14764), + .O(n14895)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he0ee */ ; + defparam LUT__22532.LUTMASK = 16'he0ee; + EFX_LUT4 LUT__22533 (.I0(n14895), .I1(n14891), .I2(n14775), .O(\u_i2c_timing_ctrl_16reg_16bit/n502 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3535 */ ; + defparam LUT__22533.LUTMASK = 16'h3535; + EFX_LUT4 LUT__22534 (.I0(\r_cmos_rx_vsync0_in[1] ), .I1(\r_cmos_rx_vsync0_in[0] ), + .O(n14896)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22534.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22535 (.I0(\r_cmos_fv_o[0] ), .I1(n14896), .O(n1406_2)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22535.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22536 (.I0(\r_cmos_fv_o[0] ), .I1(n14896), .I2(\r_cmos_fv_o[1] ), + .O(n1413_2)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__22536.LUTMASK = 16'h7878; + EFX_LUT4 LUT__22537 (.I0(\r_cmos_fv_o[0] ), .I1(\r_cmos_fv_o[1] ), .I2(n14896), + .O(n14897)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22537.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22538 (.I0(\r_cmos_fv_o[2] ), .I1(n14897), .O(n1418)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22538.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22539 (.I0(\r_cmos_fv_o[2] ), .I1(n14897), .I2(led_o[5]), + .O(n1423)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__22539.LUTMASK = 16'h7878; + EFX_LUT4 LUT__22540 (.I0(\dsi_pwm/rc_pwm[0] ), .I1(\dsi_pwm/rc_pwm[1] ), + .I2(\dsi_pwm/rc_pwm[2] ), .I3(\dsi_pwm/rc_pwm[3] ), .O(n14898)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22540.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22541 (.I0(\dsi_pwm/rc_pwm[5] ), .I1(\dsi_pwm/rc_pwm[4] ), + .I2(n14898), .I3(\dsi_pwm/rc_pwm[6] ), .O(\dsi_pwm/n14 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h10ff */ ; + defparam LUT__22541.LUTMASK = 16'h10ff; + EFX_LUT4 LUT__22542 (.I0(cmos_vsync), .I1(n4883), .O(\u_Sensor_Image_XYCrop/n55 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22542.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22543 (.I0(XYCrop_frame_de), .I1(cmos_href), .I2(cmos_vsync), + .O(ceg_net2404)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd0d0 */ ; + defparam LUT__22543.LUTMASK = 16'hd0d0; + EFX_LUT4 LUT__22544 (.I0(cmos_vsync), .I1(n4884), .O(\u_Sensor_Image_XYCrop/n56 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22544.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22545 (.I0(cmos_vsync), .I1(n4886), .O(\u_Sensor_Image_XYCrop/n57 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22545.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22546 (.I0(\u_Sensor_Image_XYCrop/image_ypos[0] ), .I1(cmos_vsync), + .O(\u_Sensor_Image_XYCrop/n66 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22546.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22547 (.I0(cmos_vsync), .I1(n4888), .O(\u_Sensor_Image_XYCrop/n58 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22547.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22548 (.I0(cmos_vsync), .I1(n4890), .O(\u_Sensor_Image_XYCrop/n59 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22548.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22549 (.I0(cmos_vsync), .I1(n4892), .O(\u_Sensor_Image_XYCrop/n60 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22549.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22550 (.I0(cmos_vsync), .I1(n4894), .O(\u_Sensor_Image_XYCrop/n61 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22550.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22551 (.I0(cmos_href), .I1(n3864), .O(\u_Sensor_Image_XYCrop/n111 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22551.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22552 (.I0(cmos_vsync), .I1(n4896), .O(\u_Sensor_Image_XYCrop/n62 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22552.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22553 (.I0(cmos_vsync), .I1(n4898), .O(\u_Sensor_Image_XYCrop/n63 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22553.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22554 (.I0(cmos_vsync), .I1(n4900), .O(\u_Sensor_Image_XYCrop/n64 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22554.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22555 (.I0(\u_Sensor_Image_XYCrop/image_ypos[4] ), .I1(\u_Sensor_Image_XYCrop/image_ypos[5] ), + .I2(\u_Sensor_Image_XYCrop/image_ypos[7] ), .I3(\u_Sensor_Image_XYCrop/image_ypos[6] ), + .O(n14899)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he000 */ ; + defparam LUT__22555.LUTMASK = 16'he000; + EFX_LUT4 LUT__22556 (.I0(\u_Sensor_Image_XYCrop/image_ypos[11] ), .I1(\u_Sensor_Image_XYCrop/image_ypos[10] ), + .I2(\u_Sensor_Image_XYCrop/image_xpos[11] ), .I3(cmos_href), + .O(n14900)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22556.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22557 (.I0(\u_Sensor_Image_XYCrop/image_xpos[9] ), .I1(\u_Sensor_Image_XYCrop/image_xpos[8] ), + .I2(\u_Sensor_Image_XYCrop/image_xpos[10] ), .I3(n14900), .O(n14901)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__22557.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__22558 (.I0(\u_Sensor_Image_XYCrop/image_ypos[8] ), .I1(n14899), + .I2(\u_Sensor_Image_XYCrop/image_ypos[9] ), .I3(n14901), .O(\u_Sensor_Image_XYCrop/w_image_out_href )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__22558.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__22559 (.I0(cmos_vsync), .I1(n3844), .O(\u_Sensor_Image_XYCrop/n65 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22559.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22560 (.I0(cmos_href), .I1(n4881), .O(\u_Sensor_Image_XYCrop/n110 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22560.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22561 (.I0(cmos_href), .I1(n4879), .O(\u_Sensor_Image_XYCrop/n109 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22561.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22562 (.I0(cmos_href), .I1(n4877), .O(\u_Sensor_Image_XYCrop/n108 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22562.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22563 (.I0(cmos_href), .I1(n4875), .O(\u_Sensor_Image_XYCrop/n107 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22563.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22564 (.I0(cmos_href), .I1(n4873), .O(\u_Sensor_Image_XYCrop/n106 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22564.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22565 (.I0(cmos_href), .I1(n4871), .O(\u_Sensor_Image_XYCrop/n105 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22565.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22566 (.I0(cmos_href), .I1(n4869), .O(\u_Sensor_Image_XYCrop/n104 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22566.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22567 (.I0(cmos_href), .I1(n4867), .O(\u_Sensor_Image_XYCrop/n103 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22567.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22568 (.I0(cmos_href), .I1(n4865), .O(\u_Sensor_Image_XYCrop/n102 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22568.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22569 (.I0(cmos_href), .I1(n4863), .O(\u_Sensor_Image_XYCrop/n101 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22569.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22570 (.I0(cmos_href), .I1(n4862), .O(\u_Sensor_Image_XYCrop/n100 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22570.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22571 (.I0(\w_ddr3_awaddr[22] ), .I1(\u_axi4_ctrl/r_wframe_index_last[0] ), + .I2(\u_axi4_ctrl/r_wframe_inc ), .O(\u_axi4_ctrl/n1484 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22571.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22572 (.I0(\u_axi4_ctrl/r_rframe_inc ), .I1(\u_axi4_ctrl/r_wframe_inc ), + .O(\u_axi4_ctrl/n1518 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22572.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22573 (.I0(led_o[1]), .O(n14902)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555 */ ; + defparam LUT__22573.LUTMASK = 16'h5555; + EFX_LUT4 LUT__22575 (.I0(led_o[1]), .I1(\u_axi4_ctrl/rc_w_eof[0] ), + .I2(led_o[0]), .O(n14904)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__22575.LUTMASK = 16'h7070; + EFX_LUT4 LUT__22576 (.I0(n4753), .I1(n4754), .I2(n4756), .O(n14905)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__22576.LUTMASK = 16'h0101; + EFX_LUT4 LUT__22577 (.I0(led_o[0]), .I1(n14902), .O(\u_axi4_ctrl/equal_68/n7 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__22577.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__22578 (.I0(n14905), .I1(\u_axi4_ctrl/r_weof_pending ), + .I2(\u_axi4_ctrl/equal_68/n7 ), .O(n14906)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__22578.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__22579 (.I0(n14902), .I1(n13481), .I2(n14904), .I3(n14906), + .O(\u_axi4_ctrl/n262 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hff70 */ ; + defparam LUT__22579.LUTMASK = 16'hff70; + EFX_LUT4 LUT__22580 (.I0(\u_axi4_ctrl/rc_w_eof[0] ), .I1(led_o[0]), + .O(n14907)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__22580.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__22581 (.I0(led_o[0]), .I1(n13481), .I2(n14902), .O(n14908)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22581.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22582 (.I0(\u_axi4_ctrl/r_weof_pending ), .I1(\u_axi4_ctrl/w_wfifo_empty ), + .I2(n14905), .O(\u_axi4_ctrl/n189 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22582.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22583 (.I0(\u_axi4_ctrl/equal_68/n7 ), .I1(\u_axi4_ctrl/n189 ), + .O(\u_axi4_ctrl/n263 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22583.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22584 (.I0(n14907), .I1(led_o[1]), .I2(n14908), .I3(\u_axi4_ctrl/n263 ), + .O(\u_axi4_ctrl/n261 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfff4 */ ; + defparam LUT__22584.LUTMASK = 16'hfff4; + EFX_LUT4 LUT__22585 (.I0(led_o[0]), .I1(led_o[1]), .O(\u_axi4_ctrl/n234 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22585.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22587 (.I0(\u_axi4_ctrl/rc_w_eof[0] ), .I1(\u_axi4_ctrl/n234 ), + .O(\u_axi4_ctrl/n288 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22587.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22588 (.I0(\u_axi4_ctrl/w_wfifo_empty ), .I1(\u_axi4_ctrl/r_weof_pending ), + .I2(n14905), .I3(\u_axi4_ctrl/equal_68/n7 ), .O(\u_axi4_ctrl/n1315 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h004f */ ; + defparam LUT__22588.LUTMASK = 16'h004f; + EFX_LUT4 LUT__22589 (.I0(w_ddr3_awready), .I1(\u_axi4_ctrl/n1315 ), + .O(ceg_net2429)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22589.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22590 (.I0(\u_axi4_ctrl/n1315 ), .I1(led_o[2]), .I2(n14908), + .O(\u_axi4_ctrl/n257 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0e0e */ ; + defparam LUT__22590.LUTMASK = 16'h0e0e; + EFX_LUT4 LUT__22591 (.I0(led_o[0]), .I1(n3872), .I2(\u_axi4_ctrl/rc_burst[0] ), + .I3(n14902), .O(\u_axi4_ctrl/n251 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h88f0 */ ; + defparam LUT__22591.LUTMASK = 16'h88f0; + EFX_LUT4 LUT__22592 (.I0(\u_axi4_ctrl/r_wframe_sync[1] ), .I1(\u_axi4_ctrl/r_wframe_sync[0] ), + .I2(\u_axi4_ctrl/n234 ), .O(ceg_net2431)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0d0d */ ; + defparam LUT__22592.LUTMASK = 16'h0d0d; + EFX_LUT4 LUT__22593 (.I0(\u_axi4_ctrl/rfifo_cnt[0] ), .I1(\u_axi4_ctrl/rfifo_cnt[1] ), + .I2(\u_axi4_ctrl/rfifo_cnt[2] ), .I3(\u_axi4_ctrl/rfifo_cnt[3] ), + .O(n14909)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22593.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22594 (.I0(\u_axi4_ctrl/rfifo_cnt[4] ), .I1(n14909), .O(\u_axi4_ctrl/equal_129/n9 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__22594.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__22595 (.I0(n4123), .I1(\u_axi4_ctrl/equal_129/n9 ), .O(\u_axi4_ctrl/n664 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22595.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22596 (.I0(\u_axi4_ctrl/rframe_vsync_dly ), .I1(lcd_vs), + .I2(rstn_sys), .O(\u_axi4_ctrl/n1318 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8f8f */ ; + defparam LUT__22596.LUTMASK = 16'h8f8f; + EFX_LUT4 LUT__22597 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[6] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] ), + .I3(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[7] ), + .O(n14910)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22597.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22598 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[0] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] ), + .I3(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[1] ), + .O(n14911)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22598.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22599 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[4] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] ), + .I3(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[5] ), + .O(n14912)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22599.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22600 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[8] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13] ), + .I3(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[9] ), + .O(n14913)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22600.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22601 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[2] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] ), + .I3(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.waddr_cntr_sync_g2b_r[3] ), + .O(n14914)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22601.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22602 (.I0(n14911), .I1(n14912), .I2(n14913), .I3(n14914), + .O(n14915)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22602.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22603 (.I0(n14910), .I1(n14915), .O(n14916)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22603.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22604 (.I0(lcd_request), .I1(\u_axi4_ctrl/w_rfifo_empty ), + .I2(n14916), .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0e0e */ ; + defparam LUT__22604.LUTMASK = 16'h0e0e; + EFX_LUT4 LUT__22605 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] ), + .I3(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[10] ), + .O(n14917)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22605.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22606 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[11] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9] ), + .I3(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[13] ), + .O(n14918)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0990 */ ; + defparam LUT__22606.LUTMASK = 16'h0990; + EFX_LUT4 LUT__22607 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] ), + .I3(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[12] ), + .O(n14919)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22607.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22608 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] ), + .I3(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5] ), + .O(n14920)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22608.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22609 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] ), + .I3(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9] ), + .O(n14921)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22609.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22610 (.I0(n14918), .I1(n14919), .I2(n14920), .I3(n14921), + .O(n14922)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22610.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22611 (.I0(n14922), .I1(n14917), .I2(\u_axi4_ctrl/rfifo_wenb ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/wr_en_int )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__22611.LUTMASK = 16'h7070; + EFX_LUT4 LUT__22612 (.I0(\u_axi4_ctrl/rfifo_rst ), .I1(rstn_sys), .O(\u_axi4_ctrl/w_rfifo_rst )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__22612.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__22615 (.I0(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[1] ), .I1(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[0] ), + .O(\u_axi4_ctrl/equal_139/n3 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbbbb */ ; + defparam LUT__22615.LUTMASK = 16'hbbbb; + EFX_LUT4 LUT__22617 (.I0(\w_ddr3_araddr[13] ), .I1(\w_ddr3_araddr[14] ), + .I2(\w_ddr3_araddr[15] ), .I3(\w_ddr3_araddr[16] ), .O(n14925)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22617.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22618 (.I0(\w_ddr3_araddr[17] ), .I1(\w_ddr3_araddr[18] ), + .I2(\w_ddr3_araddr[19] ), .O(n14926)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22618.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22619 (.I0(\u_axi4_ctrl/rd_state[0] ), .I1(\w_ddr3_araddr[21] ), + .I2(n4693), .I3(n4694), .O(n14927)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22619.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22620 (.I0(\u_axi4_ctrl/rd_state[1] ), .I1(\w_ddr3_araddr[20] ), + .I2(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[15] ), .I3(n14927), .O(n14928)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ; + defparam LUT__22620.LUTMASK = 16'h1000; + EFX_LUT4 LUT__22621 (.I0(\w_ddr3_araddr[12] ), .I1(n14925), .I2(n14926), + .I3(n14928), .O(\u_axi4_ctrl/n773 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4f00 */ ; + defparam LUT__22621.LUTMASK = 16'h4f00; + EFX_LUT4 LUT__22622 (.I0(\u_axi4_ctrl/rd_state[1] ), .I1(\u_axi4_ctrl/rd_state[0] ), + .O(\u_axi4_ctrl/n1516 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22622.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22623 (.I0(w_ddr3_arready), .I1(\u_axi4_ctrl/n1516 ), + .O(ceg_net2434)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22623.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22624 (.I0(n13505), .I1(\u_axi4_ctrl/n1516 ), .O(ceg_net2437)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22624.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22625 (.I0(n4777), .I1(n4779), .O(n14929)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22625.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22626 (.I0(n4102), .I1(n4767), .I2(n4771), .I3(n4773), + .O(n14930)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22626.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22627 (.I0(n4764), .I1(n4765), .I2(n4769), .I3(n4775), + .O(n14931)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22627.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22628 (.I0(n4781), .I1(n14929), .I2(n14930), .I3(n14931), + .O(n14932)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__22628.LUTMASK = 16'h4000; + EFX_LUT4 LUT__22629 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1193 ), + .I1(\u_axi4_ctrl/w_wfifo_empty ), .I2(n14932), .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0e0e */ ; + defparam LUT__22629.LUTMASK = 16'h0e0e; + EFX_LUT4 LUT__22630 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[7] ), + .I2(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] ), + .I3(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[8] ), + .O(n14933)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22630.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22631 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[2] ), + .I2(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13] ), + .I3(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[9] ), + .O(n14934)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0990 */ ; + defparam LUT__22631.LUTMASK = 16'h0990; + EFX_LUT4 LUT__22632 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[0] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] ), + .I2(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] ), + .I3(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[1] ), + .O(n14935)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22632.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22633 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[3] ), + .I2(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] ), + .I3(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[4] ), + .O(n14936)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22633.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22634 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[5] ), + .I2(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] ), + .I3(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.genblk1.raddr_cntr_sync_g2b_r[6] ), + .O(n14937)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9009 */ ; + defparam LUT__22634.LUTMASK = 16'h9009; + EFX_LUT4 LUT__22635 (.I0(n14934), .I1(n14935), .I2(n14936), .I3(n14937), + .O(n14938)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22635.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22636 (.I0(n14938), .I1(n14933), .I2(led_o[3]), .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/wr_en_int )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__22636.LUTMASK = 16'h7070; + EFX_LUT4 LUT__22637 (.I0(\w_ddr3_awaddr[23] ), .I1(\u_axi4_ctrl/r_wframe_index_last[1] ), + .I2(\u_axi4_ctrl/r_wframe_inc ), .O(\u_axi4_ctrl/n1477 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22637.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22638 (.I0(\w_ddr3_araddr[22] ), .I1(\w_ddr3_awaddr[22] ), + .I2(\w_ddr3_araddr[23] ), .I3(\w_ddr3_awaddr[23] ), .O(\u_axi4_ctrl/w_wframe_index_next[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1771 */ ; + defparam LUT__22638.LUTMASK = 16'h1771; + EFX_LUT4 LUT__22639 (.I0(\u_axi4_ctrl/r_wframe_inc ), .I1(rstn_sys), + .O(ceg_net3678)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22639.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22643 (.I0(\u_axi4_ctrl/n234 ), .I1(\w_ddr3_awaddr[4] ), + .O(\u_axi4_ctrl/n283 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22643.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22644 (.I0(\u_axi4_ctrl/n234 ), .I1(\w_ddr3_awaddr[5] ), + .O(\u_axi4_ctrl/n282 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22644.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22645 (.I0(\u_axi4_ctrl/n234 ), .I1(\w_ddr3_awaddr[6] ), + .O(\u_axi4_ctrl/n281 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22645.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22646 (.I0(\u_axi4_ctrl/n234 ), .I1(\w_ddr3_awaddr[7] ), + .O(\u_axi4_ctrl/n280 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22646.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22647 (.I0(\u_axi4_ctrl/n234 ), .I1(\w_ddr3_awaddr[8] ), + .O(\u_axi4_ctrl/n279 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22647.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22648 (.I0(\u_axi4_ctrl/n234 ), .I1(\w_ddr3_awaddr[9] ), + .O(\u_axi4_ctrl/n278 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22648.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22649 (.I0(\u_axi4_ctrl/n234 ), .I1(\w_ddr3_awaddr[10] ), + .O(\u_axi4_ctrl/n277 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22649.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22650 (.I0(led_o[0]), .I1(\w_ddr3_awaddr[11] ), .I2(led_o[1]), + .O(\u_axi4_ctrl/n276 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1c1c */ ; + defparam LUT__22650.LUTMASK = 16'h1c1c; + EFX_LUT4 LUT__22651 (.I0(led_o[0]), .I1(led_o[1]), .I2(\w_ddr3_awaddr[11] ), + .I3(\w_ddr3_awaddr[12] ), .O(\u_axi4_ctrl/n275 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3740 */ ; + defparam LUT__22651.LUTMASK = 16'h3740; + EFX_LUT4 LUT__22652 (.I0(\w_ddr3_awaddr[11] ), .I1(\w_ddr3_awaddr[12] ), + .O(n14939)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22652.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22653 (.I0(led_o[0]), .I1(led_o[1]), .I2(n14939), .I3(\w_ddr3_awaddr[13] ), + .O(\u_axi4_ctrl/n274 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3740 */ ; + defparam LUT__22653.LUTMASK = 16'h3740; + EFX_LUT4 LUT__22654 (.I0(\w_ddr3_awaddr[13] ), .I1(n14939), .O(n14940)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22654.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22655 (.I0(led_o[0]), .I1(led_o[1]), .I2(n14940), .I3(\w_ddr3_awaddr[14] ), + .O(\u_axi4_ctrl/n273 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3740 */ ; + defparam LUT__22655.LUTMASK = 16'h3740; + EFX_LUT4 LUT__22656 (.I0(\w_ddr3_awaddr[14] ), .I1(n14940), .O(n14941)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22656.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22657 (.I0(led_o[0]), .I1(led_o[1]), .I2(n14941), .I3(\w_ddr3_awaddr[15] ), + .O(\u_axi4_ctrl/n272 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3740 */ ; + defparam LUT__22657.LUTMASK = 16'h3740; + EFX_LUT4 LUT__22658 (.I0(\w_ddr3_awaddr[15] ), .I1(n14941), .O(n14942)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22658.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22659 (.I0(led_o[0]), .I1(led_o[1]), .I2(n14942), .I3(\w_ddr3_awaddr[16] ), + .O(\u_axi4_ctrl/n271 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3740 */ ; + defparam LUT__22659.LUTMASK = 16'h3740; + EFX_LUT4 LUT__22660 (.I0(\w_ddr3_awaddr[15] ), .I1(\w_ddr3_awaddr[16] ), + .I2(n14941), .O(n14943)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22660.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22661 (.I0(led_o[0]), .I1(led_o[1]), .I2(n14943), .I3(\w_ddr3_awaddr[17] ), + .O(\u_axi4_ctrl/n270 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3740 */ ; + defparam LUT__22661.LUTMASK = 16'h3740; + EFX_LUT4 LUT__22662 (.I0(\w_ddr3_awaddr[17] ), .I1(n14943), .O(n14944)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22662.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22663 (.I0(led_o[0]), .I1(led_o[1]), .I2(n14944), .I3(\w_ddr3_awaddr[18] ), + .O(\u_axi4_ctrl/n269 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3740 */ ; + defparam LUT__22663.LUTMASK = 16'h3740; + EFX_LUT4 LUT__22664 (.I0(\w_ddr3_awaddr[18] ), .I1(n14944), .O(n14945)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22664.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22665 (.I0(led_o[0]), .I1(led_o[1]), .I2(n14945), .I3(\w_ddr3_awaddr[19] ), + .O(\u_axi4_ctrl/n268 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3740 */ ; + defparam LUT__22665.LUTMASK = 16'h3740; + EFX_LUT4 LUT__22666 (.I0(\w_ddr3_awaddr[19] ), .I1(n14945), .O(n14946)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22666.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22667 (.I0(led_o[0]), .I1(led_o[1]), .I2(n14946), .I3(\w_ddr3_awaddr[20] ), + .O(\u_axi4_ctrl/n267 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3740 */ ; + defparam LUT__22667.LUTMASK = 16'h3740; + EFX_LUT4 LUT__22668 (.I0(\w_ddr3_awaddr[20] ), .I1(n14946), .O(n14947)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22668.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22669 (.I0(led_o[0]), .I1(led_o[1]), .I2(n14947), .I3(\w_ddr3_awaddr[21] ), + .O(\u_axi4_ctrl/n266 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3740 */ ; + defparam LUT__22669.LUTMASK = 16'h3740; + EFX_LUT4 LUT__22670 (.I0(led_o[0]), .I1(n4860), .I2(\u_axi4_ctrl/rc_burst[1] ), + .I3(n14902), .O(\u_axi4_ctrl/n250 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h88f0 */ ; + defparam LUT__22670.LUTMASK = 16'h88f0; + EFX_LUT4 LUT__22671 (.I0(led_o[0]), .I1(n4858), .I2(\u_axi4_ctrl/rc_burst[2] ), + .I3(n14902), .O(\u_axi4_ctrl/n249 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h88f0 */ ; + defparam LUT__22671.LUTMASK = 16'h88f0; + EFX_LUT4 LUT__22672 (.I0(led_o[0]), .I1(n4856), .I2(\u_axi4_ctrl/rc_burst[3] ), + .I3(n14902), .O(\u_axi4_ctrl/n248 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h88f0 */ ; + defparam LUT__22672.LUTMASK = 16'h88f0; + EFX_LUT4 LUT__22673 (.I0(led_o[0]), .I1(n4854), .I2(\u_axi4_ctrl/rc_burst[4] ), + .I3(n14902), .O(\u_axi4_ctrl/n247 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h88f0 */ ; + defparam LUT__22673.LUTMASK = 16'h88f0; + EFX_LUT4 LUT__22674 (.I0(led_o[0]), .I1(n4852), .I2(\u_axi4_ctrl/rc_burst[5] ), + .I3(n14902), .O(\u_axi4_ctrl/n246 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h88f0 */ ; + defparam LUT__22674.LUTMASK = 16'h88f0; + EFX_LUT4 LUT__22675 (.I0(led_o[0]), .I1(n4850), .I2(\u_axi4_ctrl/rc_burst[6] ), + .I3(n14902), .O(\u_axi4_ctrl/n245 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h88f0 */ ; + defparam LUT__22675.LUTMASK = 16'h88f0; + EFX_LUT4 LUT__22676 (.I0(led_o[0]), .I1(n4849), .I2(\u_axi4_ctrl/rc_burst[7] ), + .I3(n14902), .O(\u_axi4_ctrl/n244 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h88f0 */ ; + defparam LUT__22676.LUTMASK = 16'h88f0; + EFX_LUT4 LUT__22677 (.I0(\ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/n1193 ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .O(ceg_net2444)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22677.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22678 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i30_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i29_pre ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22678.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22679 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i28_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[8] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22679.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22680 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i27_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[7] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22680.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22681 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i26_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[6] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22681.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22682 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i25_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[5] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22682.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22683 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i24_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[4] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22683.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22684 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i23_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[3] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22684.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22685 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i22_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[2] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22685.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22686 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i21_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[1] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22686.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22687 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[1] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[1] ), + .I2(\u_axi4_ctrl/w_wfifo_empty ), .O(n12336)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3535 */ ; + defparam LUT__22687.LUTMASK = 16'h3535; + EFX_LUT4 LUT__22688 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[0] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[0] ), + .I2(\u_axi4_ctrl/w_wfifo_empty ), .O(n11392)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3535 */ ; + defparam LUT__22688.LUTMASK = 16'h3535; + EFX_LUT4 LUT__22689 (.I0(n12336), .I1(n11392), .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22689.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22692 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i42_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i41_pre ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22692.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22693 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i40_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[12] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22693.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22694 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i39_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[11] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22694.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22695 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i38_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[10] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22695.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22696 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i37_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[9] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22696.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22697 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i36_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[8] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22697.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22698 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i35_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[7] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22698.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22699 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i34_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[6] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22699.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22700 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i33_pre ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[5] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22700.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22701 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[2] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[2] ), + .I2(\u_axi4_ctrl/w_wfifo_empty ), .O(n12333)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3535 */ ; + defparam LUT__22701.LUTMASK = 16'h3535; + EFX_LUT4 LUT__22702 (.I0(n12336), .I1(n12333), .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22702.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22703 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[3] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[3] ), + .I2(\u_axi4_ctrl/w_wfifo_empty ), .O(n12330)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3535 */ ; + defparam LUT__22703.LUTMASK = 16'h3535; + EFX_LUT4 LUT__22704 (.I0(n12333), .I1(n12330), .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22704.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22705 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[4] ), + .I2(\u_axi4_ctrl/w_wfifo_empty ), .O(n12327)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3535 */ ; + defparam LUT__22705.LUTMASK = 16'h3535; + EFX_LUT4 LUT__22706 (.I0(n12330), .I1(n12327), .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22706.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22707 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[5] ), + .I2(\u_axi4_ctrl/w_wfifo_empty ), .O(n12324)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3535 */ ; + defparam LUT__22707.LUTMASK = 16'h3535; + EFX_LUT4 LUT__22708 (.I0(n12327), .I1(n12324), .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22708.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22709 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[6] ), + .I2(\u_axi4_ctrl/w_wfifo_empty ), .O(n12321)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3535 */ ; + defparam LUT__22709.LUTMASK = 16'h3535; + EFX_LUT4 LUT__22710 (.I0(n12324), .I1(n12321), .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22710.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22711 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[7] ), + .I2(\u_axi4_ctrl/w_wfifo_empty ), .O(n12318)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3535 */ ; + defparam LUT__22711.LUTMASK = 16'h3535; + EFX_LUT4 LUT__22712 (.I0(n12321), .I1(n12318), .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22712.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22713 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/raddr[8] ), + .I2(\u_axi4_ctrl/w_wfifo_empty ), .O(n12315)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3535 */ ; + defparam LUT__22713.LUTMASK = 16'h3535; + EFX_LUT4 LUT__22714 (.I0(n12318), .I1(n12315), .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22714.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22715 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[9] ), + .I2(\u_axi4_ctrl/w_wfifo_empty ), .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_w[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22715.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22716 (.I0(n12315), .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_w[9] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22716.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22717 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[4] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22717.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22718 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[5] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22718.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22719 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[6] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22719.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22720 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[7] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22720.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22721 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[8] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22721.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22722 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[9] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22722.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22723 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[10] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22723.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22724 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[11] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22724.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22725 (.I0(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/waddr[12] ), + .I1(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[13] ), + .O(\u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22725.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22726 (.I0(n4751), .I1(\u_axi4_ctrl/equal_129/n9 ), .O(\u_axi4_ctrl/n663 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22726.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22727 (.I0(n4749), .I1(\u_axi4_ctrl/equal_129/n9 ), .O(\u_axi4_ctrl/n662 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22727.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22728 (.I0(n4747), .I1(\u_axi4_ctrl/equal_129/n9 ), .O(\u_axi4_ctrl/n661 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22728.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22729 (.I0(n4746), .I1(\u_axi4_ctrl/equal_129/n9 ), .O(\u_axi4_ctrl/n660 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22729.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22730 (.I0(lcd_request), .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/rd_en_int ), + .O(ceg_net2451)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22730.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22731 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i30_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i29_pre ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22731.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22732 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i28_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[8] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22732.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22733 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i27_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[7] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22733.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22734 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i26_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[6] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22734.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22735 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i25_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[5] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22735.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22736 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i24_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[4] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22736.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22737 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i23_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[3] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22737.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22738 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i22_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[2] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22738.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22739 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.wr2rd_addr_sync/dff_5/i21_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[1] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_sync_g2b[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22739.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22740 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[0] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22740.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22743 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i42_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i41_pre ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22743.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22744 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i40_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[12] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22744.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22745 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i39_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[11] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22745.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22746 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i38_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[10] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22746.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22747 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i37_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[9] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22747.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22748 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i36_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[8] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22748.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22749 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i35_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[7] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22749.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22750 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i34_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[6] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22750.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22751 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.xrd2wr_addr_sync/dff_5/i33_pre ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[5] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_sync_g2b[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22751.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22752 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[4] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5] ), + .O(n14948)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22752.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22753 (.I0(n14948), .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[4] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] ), + .I3(\u_axi4_ctrl/w_rfifo_empty ), .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3caa */ ; + defparam LUT__22753.LUTMASK = 16'h3caa; + EFX_LUT4 LUT__22754 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[5] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6] ), + .O(n14949)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22754.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22755 (.I0(n14949), .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[5] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] ), + .I3(\u_axi4_ctrl/w_rfifo_empty ), .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3caa */ ; + defparam LUT__22755.LUTMASK = 16'h3caa; + EFX_LUT4 LUT__22756 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[6] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7] ), + .O(n14950)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22756.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22757 (.I0(n14950), .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[6] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] ), + .I3(\u_axi4_ctrl/w_rfifo_empty ), .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3caa */ ; + defparam LUT__22757.LUTMASK = 16'h3caa; + EFX_LUT4 LUT__22758 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[7] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8] ), + .O(n14951)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22758.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22759 (.I0(n14951), .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[7] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] ), + .I3(\u_axi4_ctrl/w_rfifo_empty ), .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3caa */ ; + defparam LUT__22759.LUTMASK = 16'h3caa; + EFX_LUT4 LUT__22760 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[8] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9] ), + .O(n14952)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22760.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22761 (.I0(n14952), .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[8] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] ), + .I3(\u_axi4_ctrl/w_rfifo_empty ), .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3caa */ ; + defparam LUT__22761.LUTMASK = 16'h3caa; + EFX_LUT4 LUT__22762 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[9] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10] ), + .O(n14953)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22762.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22763 (.I0(n14953), .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[9] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] ), + .I3(\u_axi4_ctrl/w_rfifo_empty ), .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3caa */ ; + defparam LUT__22763.LUTMASK = 16'h3caa; + EFX_LUT4 LUT__22764 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[10] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11] ), + .O(n14954)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22764.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22765 (.I0(n14954), .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[10] ), + .I2(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] ), + .I3(\u_axi4_ctrl/w_rfifo_empty ), .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[10] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3caa */ ; + defparam LUT__22765.LUTMASK = 16'h3caa; + EFX_LUT4 LUT__22766 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[12] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[12] ), + .I2(\u_axi4_ctrl/w_rfifo_empty ), .O(n14955)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22766.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22767 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/raddr[11] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[11] ), + .I2(\u_axi4_ctrl/w_rfifo_empty ), .I3(n14955), .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[11] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h53ac */ ; + defparam LUT__22767.LUTMASK = 16'h53ac; + EFX_LUT4 LUT__22768 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr_r[13] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/raddr_cntr[13] ), + .I2(\u_axi4_ctrl/w_rfifo_empty ), .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[13] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22768.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22769 (.I0(n14955), .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[13] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.raddr_cntr_gry[12] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22769.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22770 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[1] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22770.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22771 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[2] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22771.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22772 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[3] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22772.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22773 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[4] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22773.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22774 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[5] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22774.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22775 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[6] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22775.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22776 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[7] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22776.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22777 (.I0(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/waddr[8] ), + .I1(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/waddr_cntr[9] ), + .O(\u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/genblk7.waddr_cntr_gry[8] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22777.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22778 (.I0(\u_axi4_ctrl/dff_138/i15_rst_4 ), .I1(\u_axi4_ctrl/dff_138/i15_pre ), + .O(\u_axi4_ctrl/rfifo_wr_rst_busy_dly[14] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22778.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22783 (.I0(\u_axi4_ctrl/r_rd_pend ), .I1(w_ddr3_arvalid), + .I2(\u_axi4_ctrl/rd_state[0] ), .I3(\u_axi4_ctrl/rd_state[1] ), + .O(\u_axi4_ctrl/n772 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0ef0 */ ; + defparam LUT__22783.LUTMASK = 16'h0ef0; + EFX_LUT4 LUT__22784 (.I0(w_ddr3_arready), .I1(w_ddr3_arvalid), .O(\u_axi4_ctrl/n785 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22784.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22786 (.I0(\w_ddr3_araddr[22] ), .I1(\w_ddr3_araddr[23] ), + .I2(\w_ddr3_awaddr[22] ), .I3(\w_ddr3_awaddr[23] ), .O(\u_axi4_ctrl/w_wframe_index_next[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h07f2 */ ; + defparam LUT__22786.LUTMASK = 16'h07f2; + EFX_LUT4 LUT__22787 (.I0(\u_lcd_driver/vcnt[1] ), .I1(\u_lcd_driver/vcnt[0] ), + .I2(\u_lcd_driver/vcnt[2] ), .I3(\u_lcd_driver/vcnt[4] ), .O(n14956)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h001f */ ; + defparam LUT__22787.LUTMASK = 16'h001f; + EFX_LUT4 LUT__22788 (.I0(\u_lcd_driver/vcnt[5] ), .I1(\u_lcd_driver/vcnt[6] ), + .I2(\u_lcd_driver/vcnt[7] ), .O(n14957)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22788.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22789 (.I0(\u_lcd_driver/vcnt[4] ), .I1(\u_lcd_driver/vcnt[3] ), + .I2(n14956), .I3(n14957), .O(n14958)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0e00 */ ; + defparam LUT__22789.LUTMASK = 16'h0e00; + EFX_LUT4 LUT__22790 (.I0(\u_lcd_driver/vcnt[10] ), .I1(\u_lcd_driver/vcnt[11] ), + .O(n14959)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22790.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22791 (.I0(\u_lcd_driver/vcnt[8] ), .I1(n14958), .I2(\u_lcd_driver/vcnt[9] ), + .I3(n14959), .O(n14960)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1f00 */ ; + defparam LUT__22791.LUTMASK = 16'h1f00; + EFX_LUT4 LUT__22792 (.I0(\u_lcd_driver/vcnt[0] ), .I1(n14960), .O(\u_lcd_driver/n89 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22792.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22793 (.I0(\u_lcd_driver/hcnt[1] ), .I1(\u_lcd_driver/hcnt[2] ), + .I2(\u_lcd_driver/hcnt[3] ), .O(n14961)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__22793.LUTMASK = 16'h0101; + EFX_LUT4 LUT__22794 (.I0(\u_lcd_driver/hcnt[4] ), .I1(\u_lcd_driver/hcnt[5] ), + .I2(\u_lcd_driver/hcnt[6] ), .O(n14962)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22794.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22795 (.I0(\u_lcd_driver/hcnt[7] ), .I1(\u_lcd_driver/hcnt[8] ), + .O(n14963)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22795.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22796 (.I0(\u_lcd_driver/hcnt[0] ), .I1(n14961), .I2(n14962), + .I3(n14963), .O(n14964)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4f00 */ ; + defparam LUT__22796.LUTMASK = 16'h4f00; + EFX_LUT4 LUT__22797 (.I0(\u_lcd_driver/hcnt[11] ), .I1(\u_lcd_driver/hcnt[12] ), + .I2(\u_lcd_driver/hcnt[13] ), .O(n14965)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__22797.LUTMASK = 16'h0101; + EFX_LUT4 LUT__22798 (.I0(n14964), .I1(\u_lcd_driver/hcnt[9] ), .I2(\u_lcd_driver/hcnt[10] ), + .I3(n14965), .O(n14966)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbf00 */ ; + defparam LUT__22798.LUTMASK = 16'hbf00; + EFX_LUT4 LUT__22799 (.I0(n14966), .I1(n14963), .I2(n14961), .I3(n14965), + .O(\u_lcd_driver/equal_17/n27 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hbfff */ ; + defparam LUT__22799.LUTMASK = 16'hbfff; + EFX_LUT4 LUT__22800 (.I0(\u_lcd_driver/hcnt[9] ), .I1(\u_lcd_driver/hcnt[10] ), + .I2(n14965), .O(n14967)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22800.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22801 (.I0(\u_lcd_driver/hcnt[3] ), .I1(\u_lcd_driver/hcnt[4] ), + .O(n14968)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22801.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22802 (.I0(n14968), .I1(\u_lcd_driver/hcnt[5] ), .I2(\u_lcd_driver/hcnt[6] ), + .O(n14969)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b0b */ ; + defparam LUT__22802.LUTMASK = 16'h0b0b; + EFX_LUT4 LUT__22803 (.I0(n14963), .I1(n14967), .I2(n14969), .O(\u_lcd_driver/n39 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ; + defparam LUT__22803.LUTMASK = 16'h8080; + EFX_LUT4 LUT__22804 (.I0(\u_lcd_driver/vcnt[5] ), .I1(\u_lcd_driver/vcnt[6] ), + .I2(\u_lcd_driver/vcnt[7] ), .I3(\u_lcd_driver/vcnt[8] ), .O(n14970)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22804.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22805 (.I0(\u_lcd_driver/vcnt[9] ), .I1(n14970), .O(n14971)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22805.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22806 (.I0(\u_lcd_driver/vcnt[3] ), .I1(n14956), .I2(n14959), + .I3(n14971), .O(\u_lcd_driver/n90 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ; + defparam LUT__22806.LUTMASK = 16'h4000; + EFX_LUT4 LUT__22807 (.I0(\u_lcd_driver/equal_17/n27 ), .I1(rstn_pixel), + .O(\u_lcd_driver/n434 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22807.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22808 (.I0(\u_lcd_driver/hcnt[2] ), .I1(\u_lcd_driver/hcnt[5] ), + .I2(\u_lcd_driver/hcnt[6] ), .I3(n14968), .O(n14972)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0100 */ ; + defparam LUT__22808.LUTMASK = 16'h0100; + EFX_LUT4 LUT__22809 (.I0(\u_lcd_driver/hcnt[7] ), .I1(n14972), .I2(\u_lcd_driver/hcnt[8] ), + .I3(n14967), .O(n14973)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4f00 */ ; + defparam LUT__22809.LUTMASK = 16'h4f00; + EFX_LUT4 LUT__22810 (.I0(\u_lcd_driver/vcnt[0] ), .I1(\u_lcd_driver/vcnt[1] ), + .I2(\u_lcd_driver/vcnt[2] ), .I3(\u_lcd_driver/vcnt[3] ), .O(n14974)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfe00 */ ; + defparam LUT__22810.LUTMASK = 16'hfe00; + EFX_LUT4 LUT__22811 (.I0(\u_lcd_driver/vcnt[4] ), .I1(n14974), .I2(n14957), + .I3(\u_lcd_driver/vcnt[8] ), .O(n14975)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h001f */ ; + defparam LUT__22811.LUTMASK = 16'h001f; + EFX_LUT4 LUT__22812 (.I0(n14974), .I1(\u_lcd_driver/vcnt[4] ), .I2(n14971), + .O(n14976)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__22812.LUTMASK = 16'h7070; + EFX_LUT4 LUT__22813 (.I0(n14972), .I1(n14963), .I2(\u_lcd_driver/hcnt[9] ), + .I3(\u_lcd_driver/hcnt[10] ), .O(n14977)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7000 */ ; + defparam LUT__22813.LUTMASK = 16'h7000; + EFX_LUT4 LUT__22814 (.I0(n14977), .I1(n14965), .I2(n14959), .O(n14978)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4040 */ ; + defparam LUT__22814.LUTMASK = 16'h4040; + EFX_LUT4 LUT__22815 (.I0(n14975), .I1(\u_lcd_driver/vcnt[9] ), .I2(n14976), + .I3(n14978), .O(n14979)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0b00 */ ; + defparam LUT__22815.LUTMASK = 16'h0b00; + EFX_LUT4 LUT__22816 (.I0(n14973), .I1(n14979), .O(\u_lcd_driver/n132 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22816.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22817 (.I0(\u_lcd_driver/hcnt[0] ), .I1(\u_lcd_driver/hcnt[1] ), + .I2(\u_lcd_driver/hcnt[8] ), .I3(n14973), .O(n14980)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f00 */ ; + defparam LUT__22817.LUTMASK = 16'h7f00; + EFX_LUT4 LUT__22818 (.I0(\u_lcd_driver/hcnt[0] ), .I1(\u_lcd_driver/hcnt[1] ), + .I2(\u_lcd_driver/hcnt[9] ), .I3(\u_lcd_driver/hcnt[10] ), .O(n14981)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22818.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22819 (.I0(n14980), .I1(n14981), .I2(n14979), .O(\u_lcd_driver/n240 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22819.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22820 (.I0(\u_lcd_driver/hcnt[0] ), .I1(n14966), .O(\u_lcd_driver/n38 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22820.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22821 (.I0(n4503), .I1(n14960), .O(\u_lcd_driver/n88 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22821.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22822 (.I0(n4661), .I1(n14960), .O(\u_lcd_driver/n87 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22822.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22823 (.I0(n4659), .I1(n14960), .O(\u_lcd_driver/n86 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22823.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22824 (.I0(n4657), .I1(n14960), .O(\u_lcd_driver/n85 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22824.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22825 (.I0(n4655), .I1(n14960), .O(\u_lcd_driver/n84 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22825.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22826 (.I0(n4653), .I1(n14960), .O(\u_lcd_driver/n83 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22826.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22827 (.I0(n4651), .I1(n14960), .O(\u_lcd_driver/n82 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22827.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22828 (.I0(n4649), .I1(n14960), .O(\u_lcd_driver/n81 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22828.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22829 (.I0(n4647), .I1(n14960), .O(\u_lcd_driver/n80 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22829.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22830 (.I0(n4645), .I1(n14960), .O(\u_lcd_driver/n79 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22830.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22831 (.I0(n4644), .I1(n14960), .O(\u_lcd_driver/n78 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22831.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22832 (.I0(n4351), .I1(n14966), .O(\u_lcd_driver/n37 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22832.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22833 (.I0(n4684), .I1(n14966), .O(\u_lcd_driver/n36 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22833.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22834 (.I0(n4682), .I1(n14966), .O(\u_lcd_driver/n35 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22834.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22835 (.I0(n4680), .I1(n14966), .O(\u_lcd_driver/n34 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22835.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22836 (.I0(n4678), .I1(n14966), .O(\u_lcd_driver/n33 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22836.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22837 (.I0(n4676), .I1(n14966), .O(\u_lcd_driver/n32 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22837.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22838 (.I0(n4674), .I1(n14966), .O(\u_lcd_driver/n31 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22838.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22839 (.I0(n4672), .I1(n14966), .O(\u_lcd_driver/n30 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22839.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22840 (.I0(n4670), .I1(n14966), .O(\u_lcd_driver/n29 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22840.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22841 (.I0(n4668), .I1(n14966), .O(\u_lcd_driver/n28 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22841.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22842 (.I0(n4666), .I1(n14966), .O(\u_lcd_driver/n27 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22842.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22843 (.I0(n4664), .I1(n14966), .O(\u_lcd_driver/n26 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22843.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22844 (.I0(n4663), .I1(n14966), .O(\u_lcd_driver/n25 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22844.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22845 (.I0(\u_rgb2dvi/enc_0/acc[0] ), .I1(\u_rgb2dvi/enc_0/acc[1] ), + .I2(\u_rgb2dvi/enc_0/acc[2] ), .I3(\u_rgb2dvi/enc_0/acc[3] ), + .O(n14982)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22845.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22846 (.I0(\u_rgb2dvi/enc_0/acc[4] ), .I1(n14982), .O(n14983)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22846.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22847 (.I0(\u_lcd_driver/r_lcd_rgb[1] ), .I1(\u_lcd_driver/r_lcd_rgb[3] ), + .I2(\u_lcd_driver/r_lcd_rgb[5] ), .I3(\u_lcd_driver/r_lcd_rgb[7] ), + .O(n14984)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6996 */ ; + defparam LUT__22847.LUTMASK = 16'h6996; + EFX_LUT4 LUT__22848 (.I0(\u_lcd_driver/r_lcd_rgb[0] ), .I1(\u_lcd_driver/r_lcd_rgb[2] ), + .I2(\u_lcd_driver/r_lcd_rgb[4] ), .I3(\u_lcd_driver/r_lcd_rgb[6] ), + .O(n14985)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6996 */ ; + defparam LUT__22848.LUTMASK = 16'h6996; + EFX_LUT4 LUT__22849 (.I0(n14984), .I1(n14985), .I2(\u_lcd_driver/r_lcd_rgb[0] ), + .O(n14986)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9090 */ ; + defparam LUT__22849.LUTMASK = 16'h9090; + EFX_LUT4 LUT__22850 (.I0(\u_lcd_driver/r_lcd_rgb[0] ), .I1(\u_lcd_driver/r_lcd_rgb[1] ), + .I2(\u_lcd_driver/r_lcd_rgb[2] ), .O(n14987)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9696 */ ; + defparam LUT__22850.LUTMASK = 16'h9696; + EFX_LUT4 LUT__22851 (.I0(\u_lcd_driver/r_lcd_rgb[3] ), .I1(\u_lcd_driver/r_lcd_rgb[4] ), + .I2(\u_lcd_driver/r_lcd_rgb[5] ), .I3(\u_lcd_driver/r_lcd_rgb[6] ), + .O(n14988)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6996 */ ; + defparam LUT__22851.LUTMASK = 16'h6996; + EFX_LUT4 LUT__22852 (.I0(n14987), .I1(n14988), .I2(lcd_de), .I3(\u_lcd_driver/r_lcd_rgb[7] ), + .O(n14989)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6000 */ ; + defparam LUT__22852.LUTMASK = 16'h6000; + EFX_LUT4 LUT__22853 (.I0(\u_lcd_driver/r_lcd_rgb[0] ), .I1(\u_lcd_driver/r_lcd_rgb[1] ), + .I2(\u_lcd_driver/r_lcd_rgb[2] ), .I3(lcd_de), .O(n14990)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he800 */ ; + defparam LUT__22853.LUTMASK = 16'he800; + EFX_LUT4 LUT__22854 (.I0(\u_lcd_driver/r_lcd_rgb[3] ), .I1(\u_lcd_driver/r_lcd_rgb[4] ), + .I2(n14987), .O(n14991)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he8e8 */ ; + defparam LUT__22854.LUTMASK = 16'he8e8; + EFX_LUT4 LUT__22855 (.I0(n14986), .I1(n14989), .I2(n14990), .I3(n14991), + .O(n14992)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfdd4 */ ; + defparam LUT__22855.LUTMASK = 16'hfdd4; + EFX_LUT4 LUT__22856 (.I0(\u_lcd_driver/r_lcd_rgb[3] ), .I1(\u_lcd_driver/r_lcd_rgb[4] ), + .I2(n14987), .O(n14993)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9696 */ ; + defparam LUT__22856.LUTMASK = 16'h9696; + EFX_LUT4 LUT__22857 (.I0(\u_lcd_driver/r_lcd_rgb[5] ), .I1(n14993), + .I2(\u_lcd_driver/r_lcd_rgb[6] ), .I3(lcd_de), .O(n14994)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he800 */ ; + defparam LUT__22857.LUTMASK = 16'he800; + EFX_LUT4 LUT__22858 (.I0(n14986), .I1(n14991), .I2(n14989), .I3(n14990), + .O(n14995)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h2bbf */ ; + defparam LUT__22858.LUTMASK = 16'h2bbf; + EFX_LUT4 LUT__22859 (.I0(n14994), .I1(n14992), .I2(n14995), .O(n12107)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7070 */ ; + defparam LUT__22859.LUTMASK = 16'h7070; + EFX_LUT4 LUT__22860 (.I0(\u_lcd_driver/r_lcd_rgb[1] ), .I1(\u_lcd_driver/r_lcd_rgb[2] ), + .I2(\u_lcd_driver/r_lcd_rgb[0] ), .I3(n12107), .O(n14996)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd2b4 */ ; + defparam LUT__22860.LUTMASK = 16'hd2b4; + EFX_LUT4 LUT__22861 (.I0(lcd_de), .I1(n14984), .I2(n12107), .I3(n14985), + .O(n14997)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h2003 */ ; + defparam LUT__22861.LUTMASK = 16'h2003; + EFX_LUT4 LUT__22862 (.I0(lcd_de), .I1(n14997), .I2(n14996), .O(n14998)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd3d3 */ ; + defparam LUT__22862.LUTMASK = 16'hd3d3; + EFX_LUT4 LUT__22863 (.I0(n14987), .I1(n14988), .I2(lcd_de), .O(n14999)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__22863.LUTMASK = 16'h6060; + EFX_LUT4 LUT__22864 (.I0(\u_lcd_driver/r_lcd_rgb[5] ), .I1(n14993), + .I2(lcd_de), .O(n15000)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6060 */ ; + defparam LUT__22864.LUTMASK = 16'h6060; + EFX_LUT4 LUT__22865 (.I0(n14999), .I1(n12107), .I2(n15000), .I3(n14985), + .O(n15001)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha3ca */ ; + defparam LUT__22865.LUTMASK = 16'ha3ca; + EFX_LUT4 LUT__22866 (.I0(\u_lcd_driver/r_lcd_rgb[1] ), .I1(\u_lcd_driver/r_lcd_rgb[3] ), + .O(n15002)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22866.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22867 (.I0(n14994), .I1(n14992), .I2(n15002), .I3(n14995), + .O(n15003)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0700 */ ; + defparam LUT__22867.LUTMASK = 16'h0700; + EFX_LUT4 LUT__22868 (.I0(n15002), .I1(\u_lcd_driver/r_lcd_rgb[4] ), + .O(n15004)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22868.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22869 (.I0(\u_lcd_driver/r_lcd_rgb[0] ), .I1(\u_lcd_driver/r_lcd_rgb[2] ), + .O(n15005)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22869.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22870 (.I0(n15003), .I1(n15004), .I2(n15005), .I3(lcd_de), + .O(n15006)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'he100 */ ; + defparam LUT__22870.LUTMASK = 16'he100; + EFX_LUT4 LUT__22871 (.I0(n15001), .I1(n15006), .O(n15007)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22871.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22872 (.I0(n14996), .I1(n14997), .I2(n15001), .I3(n15006), + .O(n15008)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'heff7 */ ; + defparam LUT__22872.LUTMASK = 16'heff7; + EFX_LUT4 LUT__22873 (.I0(n15007), .I1(n14998), .I2(n15008), .I3(n14984), + .O(n15009)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h001f */ ; + defparam LUT__22873.LUTMASK = 16'h001f; + EFX_LUT4 LUT__22874 (.I0(n14984), .I1(n14985), .I2(n12107), .O(n15010)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ; + defparam LUT__22874.LUTMASK = 16'h1010; + EFX_LUT4 LUT__22875 (.I0(n14996), .I1(n15010), .I2(n15001), .I3(n15006), + .O(n15011)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4ddf */ ; + defparam LUT__22875.LUTMASK = 16'h4ddf; + EFX_LUT4 LUT__22876 (.I0(n14996), .I1(n15006), .I2(n14997), .I3(n15001), + .O(n15012)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hfee8 */ ; + defparam LUT__22876.LUTMASK = 16'hfee8; + EFX_LUT4 LUT__22877 (.I0(n14982), .I1(n15011), .I2(n15012), .I3(\u_rgb2dvi/enc_0/acc[4] ), + .O(n15013)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf0ee */ ; + defparam LUT__22877.LUTMASK = 16'hf0ee; + EFX_LUT4 LUT__22878 (.I0(n15009), .I1(n14983), .I2(n12107), .I3(n15013), + .O(n15014)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf100 */ ; + defparam LUT__22878.LUTMASK = 16'hf100; + EFX_LUT4 LUT__22879 (.I0(lcd_hs), .I1(\u_lcd_driver/r_lcd_rgb[0] ), + .I2(n15014), .I3(lcd_de), .O(\u_rgb2dvi/enc_0/n886 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc3aa */ ; + defparam LUT__22879.LUTMASK = 16'hc3aa; + EFX_LUT4 LUT__22880 (.I0(lcd_de), .I1(\u_lcd_driver/r_lcd_rgb[0] ), + .I2(\u_lcd_driver/r_lcd_rgb[1] ), .I3(n12107), .O(n15015)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd728 */ ; + defparam LUT__22880.LUTMASK = 16'hd728; + EFX_LUT4 LUT__22881 (.I0(lcd_hs), .I1(n15014), .I2(lcd_de), .I3(n15015), + .O(\u_rgb2dvi/enc_0/n765 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3ace */ ; + defparam LUT__22881.LUTMASK = 16'h3ace; + EFX_LUT4 LUT__22882 (.I0(lcd_hs), .I1(n14987), .I2(n15014), .I3(lcd_de), + .O(\u_rgb2dvi/enc_0/n771 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc355 */ ; + defparam LUT__22882.LUTMASK = 16'hc355; + EFX_LUT4 LUT__22883 (.I0(lcd_de), .I1(\u_lcd_driver/r_lcd_rgb[3] ), + .I2(n14987), .I3(n12107), .O(n15016)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd728 */ ; + defparam LUT__22883.LUTMASK = 16'hd728; + EFX_LUT4 LUT__22884 (.I0(lcd_hs), .I1(lcd_de), .I2(n15016), .I3(n15014), + .O(\u_rgb2dvi/enc_0/n777 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h2ee0 */ ; + defparam LUT__22884.LUTMASK = 16'h2ee0; + EFX_LUT4 LUT__22885 (.I0(lcd_hs), .I1(n14993), .I2(n15014), .I3(lcd_de), + .O(\u_rgb2dvi/enc_0/n783 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc355 */ ; + defparam LUT__22885.LUTMASK = 16'hc355; + EFX_LUT4 LUT__22886 (.I0(n12107), .I1(n15000), .O(n15017)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22886.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22887 (.I0(lcd_hs), .I1(lcd_de), .I2(n15017), .I3(n15014), + .O(\u_rgb2dvi/enc_0/n789 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h2ee0 */ ; + defparam LUT__22887.LUTMASK = 16'h2ee0; + EFX_LUT4 LUT__22888 (.I0(lcd_hs), .I1(n14999), .I2(lcd_de), .I3(n15014), + .O(\u_rgb2dvi/enc_0/n795 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hc531 */ ; + defparam LUT__22888.LUTMASK = 16'hc531; + EFX_LUT4 LUT__22889 (.I0(lcd_de), .I1(n14984), .I2(n14985), .I3(n12107), + .O(n15018)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hd728 */ ; + defparam LUT__22889.LUTMASK = 16'hd728; + EFX_LUT4 LUT__22890 (.I0(lcd_hs), .I1(n15014), .I2(lcd_de), .I3(n15018), + .O(\u_rgb2dvi/enc_0/n801 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h3ace */ ; + defparam LUT__22890.LUTMASK = 16'h3ace; + EFX_LUT4 LUT__22891 (.I0(n12107), .I1(lcd_hs), .I2(lcd_de), .O(\u_rgb2dvi/enc_0/n807 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'ha3a3 */ ; + defparam LUT__22891.LUTMASK = 16'ha3a3; + EFX_LUT4 LUT__22892 (.I0(n15014), .I1(lcd_vs), .I2(lcd_hs), .I3(lcd_de), + .O(\u_rgb2dvi/enc_0/n813 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h55c3 */ ; + defparam LUT__22892.LUTMASK = 16'h55c3; + EFX_LUT4 LUT__22893 (.I0(\u_rgb2dvi/enc_1/acc[0] ), .I1(\u_rgb2dvi/enc_1/acc[1] ), + .I2(\u_rgb2dvi/enc_1/acc[2] ), .I3(\u_rgb2dvi/enc_1/acc[3] ), + .O(n15019)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22893.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22894 (.I0(\u_rgb2dvi/enc_1/acc[4] ), .I1(n15019), .O(n15020)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22894.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22895 (.I0(n15011), .I1(n15019), .I2(n15012), .I3(\u_rgb2dvi/enc_1/acc[4] ), + .O(n15021)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf0ee */ ; + defparam LUT__22895.LUTMASK = 16'hf0ee; + EFX_LUT4 LUT__22896 (.I0(n15009), .I1(n15020), .I2(n12107), .I3(n15021), + .O(\u_rgb2dvi/enc_1/q_out[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0eff */ ; + defparam LUT__22896.LUTMASK = 16'h0eff; + EFX_LUT4 LUT__22897 (.I0(lcd_de), .I1(\u_lcd_driver/r_lcd_rgb[0] ), + .I2(\u_rgb2dvi/enc_1/q_out[9] ), .O(\u_rgb2dvi/enc_1/q_out[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__22897.LUTMASK = 16'h7878; + EFX_LUT4 LUT__22898 (.I0(n15015), .I1(\u_rgb2dvi/enc_1/q_out[9] ), .O(\u_rgb2dvi/enc_1/q_out[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22898.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22899 (.I0(n14987), .I1(lcd_de), .I2(\u_rgb2dvi/enc_1/q_out[9] ), + .O(\u_rgb2dvi/enc_1/q_out[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__22899.LUTMASK = 16'h7878; + EFX_LUT4 LUT__22900 (.I0(n15016), .I1(\u_rgb2dvi/enc_1/q_out[9] ), .O(\u_rgb2dvi/enc_1/q_out[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22900.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22901 (.I0(n14993), .I1(lcd_de), .I2(\u_rgb2dvi/enc_1/q_out[9] ), + .O(\u_rgb2dvi/enc_1/q_out[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__22901.LUTMASK = 16'h7878; + EFX_LUT4 LUT__22902 (.I0(n15017), .I1(\u_rgb2dvi/enc_1/q_out[9] ), .O(\u_rgb2dvi/enc_1/q_out[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22902.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22903 (.I0(n14999), .I1(\u_rgb2dvi/enc_1/q_out[9] ), .O(\u_rgb2dvi/enc_1/q_out[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22903.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22904 (.I0(n15018), .I1(\u_rgb2dvi/enc_1/q_out[9] ), .O(\u_rgb2dvi/enc_1/q_out[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22904.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22905 (.I0(\u_rgb2dvi/enc_2/acc[0] ), .I1(\u_rgb2dvi/enc_2/acc[1] ), + .I2(\u_rgb2dvi/enc_2/acc[2] ), .I3(\u_rgb2dvi/enc_2/acc[3] ), + .O(n15022)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0001 */ ; + defparam LUT__22905.LUTMASK = 16'h0001; + EFX_LUT4 LUT__22906 (.I0(\u_rgb2dvi/enc_2/acc[4] ), .I1(n15022), .O(n15023)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22906.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22907 (.I0(n15011), .I1(n15022), .I2(n15012), .I3(\u_rgb2dvi/enc_2/acc[4] ), + .O(n15024)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hf0ee */ ; + defparam LUT__22907.LUTMASK = 16'hf0ee; + EFX_LUT4 LUT__22908 (.I0(n15009), .I1(n15023), .I2(n12107), .I3(n15024), + .O(\u_rgb2dvi/enc_2/q_out[9] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0eff */ ; + defparam LUT__22908.LUTMASK = 16'h0eff; + EFX_LUT4 LUT__22909 (.I0(lcd_de), .I1(\u_lcd_driver/r_lcd_rgb[0] ), + .I2(\u_rgb2dvi/enc_2/q_out[9] ), .O(\u_rgb2dvi/enc_2/q_out[0] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__22909.LUTMASK = 16'h7878; + EFX_LUT4 LUT__22910 (.I0(n14984), .I1(lcd_de), .O(n12124)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8888 */ ; + defparam LUT__22910.LUTMASK = 16'h8888; + EFX_LUT4 LUT__22911 (.I0(n15015), .I1(\u_rgb2dvi/enc_2/q_out[9] ), .O(\u_rgb2dvi/enc_2/q_out[1] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22911.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22912 (.I0(n14987), .I1(lcd_de), .I2(\u_rgb2dvi/enc_2/q_out[9] ), + .O(\u_rgb2dvi/enc_2/q_out[2] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__22912.LUTMASK = 16'h7878; + EFX_LUT4 LUT__22913 (.I0(n15016), .I1(\u_rgb2dvi/enc_2/q_out[9] ), .O(\u_rgb2dvi/enc_2/q_out[3] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22913.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22914 (.I0(n14993), .I1(lcd_de), .I2(\u_rgb2dvi/enc_2/q_out[9] ), + .O(\u_rgb2dvi/enc_2/q_out[4] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7878 */ ; + defparam LUT__22914.LUTMASK = 16'h7878; + EFX_LUT4 LUT__22915 (.I0(n15017), .I1(\u_rgb2dvi/enc_2/q_out[9] ), .O(\u_rgb2dvi/enc_2/q_out[5] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22915.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22916 (.I0(n14999), .I1(\u_rgb2dvi/enc_2/q_out[9] ), .O(\u_rgb2dvi/enc_2/q_out[6] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22916.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22917 (.I0(n15018), .I1(\u_rgb2dvi/enc_2/q_out[9] ), .O(\u_rgb2dvi/enc_2/q_out[7] )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h9999 */ ; + defparam LUT__22917.LUTMASK = 16'h9999; + EFX_LUT4 LUT__22918 (.I0(n15007), .I1(n14998), .O(n12146)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22918.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22919 (.I0(n12124), .I1(n12146), .O(n12140)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h6666 */ ; + defparam LUT__22919.LUTMASK = 16'h6666; + EFX_LUT4 LUT__22920 (.I0(n14996), .I1(n15001), .I2(n15006), .I3(n14997), + .O(n12187)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8000 */ ; + defparam LUT__22920.LUTMASK = 16'h8000; + EFX_LUT4 LUT__22921 (.I0(n12187), .I1(n15012), .O(n12143)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ; + defparam LUT__22921.LUTMASK = 16'h4444; + EFX_LUT4 LUT__22922 (.I0(n12124), .I1(n12146), .I2(n12143), .O(n12183)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1e1e */ ; + defparam LUT__22922.LUTMASK = 16'h1e1e; + EFX_LUT4 LUT__22923 (.I0(n4641), .I1(n4622), .I2(n15024), .O(n15025)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22923.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22924 (.I0(n4631), .I1(n4599), .I2(n12107), .O(n15026)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22924.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22925 (.I0(n15009), .I1(n15023), .O(n15027)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22925.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22926 (.I0(n15026), .I1(n15025), .I2(n15027), .O(n12149)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22926.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22927 (.I0(n4642), .I1(n4623), .I2(n15024), .O(n15028)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22927.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22928 (.I0(n4632), .I1(n4627), .I2(n12107), .O(n15029)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22928.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22929 (.I0(n15029), .I1(n15028), .I2(n15027), .O(n12152)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22929.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22930 (.I0(n4625), .I1(n4613), .I2(n15024), .O(n15030)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22930.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22931 (.I0(n4629), .I1(n4602), .I2(n12107), .O(n15031)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22931.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22932 (.I0(n15031), .I1(n15030), .I2(n15027), .O(n12155)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22932.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22933 (.I0(n4585), .I1(n4564), .I2(n15024), .O(n15032)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22933.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22934 (.I0(n4604), .I1(n4600), .I2(n12107), .O(n15033)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22934.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22935 (.I0(n15033), .I1(n15032), .I2(n15027), .O(n12158)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22935.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22936 (.I0(n4641), .I1(n4622), .I2(n15021), .O(n15034)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22936.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22937 (.I0(n15009), .I1(n15020), .O(n15035)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22937.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22938 (.I0(n15026), .I1(n15034), .I2(n15035), .O(n12163)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22938.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22939 (.I0(n4642), .I1(n4623), .I2(n15021), .O(n15036)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22939.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22940 (.I0(n15029), .I1(n15036), .I2(n15035), .O(n12166)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22940.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22941 (.I0(n4625), .I1(n4613), .I2(n15021), .O(n15037)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22941.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22942 (.I0(n15031), .I1(n15037), .I2(n15035), .O(n12169)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22942.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22943 (.I0(n4585), .I1(n4564), .I2(n15021), .O(n15038)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22943.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22944 (.I0(n15033), .I1(n15038), .I2(n15035), .O(n12172)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22944.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22945 (.I0(n12124), .I1(n15012), .I2(n12146), .O(n12180)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0101 */ ; + defparam LUT__22945.LUTMASK = 16'h0101; + EFX_LUT4 LUT__22946 (.I0(n4641), .I1(n4622), .I2(n15013), .O(n15039)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22946.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22947 (.I0(n15009), .I1(n14983), .O(n15040)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ; + defparam LUT__22947.LUTMASK = 16'h1111; + EFX_LUT4 LUT__22948 (.I0(n15039), .I1(n15026), .I2(n15040), .O(n12191)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22948.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22949 (.I0(n4642), .I1(n4623), .I2(n15013), .O(n15041)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hcaca */ ; + defparam LUT__22949.LUTMASK = 16'hcaca; + EFX_LUT4 LUT__22950 (.I0(n15041), .I1(n15029), .I2(n15040), .O(n12194)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22950.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22951 (.I0(n4625), .I1(n4613), .I2(n15013), .O(n15042)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22951.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22952 (.I0(n15042), .I1(n15031), .I2(n15040), .O(n12197)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22952.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22953 (.I0(n4585), .I1(n4564), .I2(n15013), .O(n15043)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22953.LUTMASK = 16'hacac; + EFX_LUT4 LUT__22954 (.I0(n15043), .I1(n15033), .I2(n15040), .O(n12200)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'hacac */ ; + defparam LUT__22954.LUTMASK = 16'hacac; + EFX_LUT4 LUT__23195 (.I0(rstn_pixel), .O(hdmi_txc_rst_o)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23195.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23196 (.I0(\hdmi_txd0_o[9]_2 ), .O(hdmi_txd0_o[9])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23196.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23197 (.I0(\hdmi_txd0_o[8]_2 ), .O(hdmi_txd0_o[8])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23197.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23198 (.I0(\hdmi_txd0_o[6]_2 ), .O(hdmi_txd0_o[6])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23198.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23199 (.I0(\hdmi_txd0_o[4]_2 ), .O(hdmi_txd0_o[4])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23199.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23200 (.I0(\hdmi_txd0_o[2]_2 ), .O(hdmi_txd0_o[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23200.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23201 (.I0(\hdmi_txd1_o[9]_2 ), .O(hdmi_txd1_o[9])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23201.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23202 (.I0(\hdmi_txd1_o[8]_2 ), .O(hdmi_txd1_o[8])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23202.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23203 (.I0(\hdmi_txd1_o[6]_2 ), .O(hdmi_txd1_o[6])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23203.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23204 (.I0(\hdmi_txd1_o[4]_2 ), .O(hdmi_txd1_o[4])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23204.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23205 (.I0(\hdmi_txd1_o[2]_2 ), .O(hdmi_txd1_o[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23205.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23206 (.I0(\hdmi_txd2_o[9]_2 ), .O(hdmi_txd2_o[9])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23206.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23207 (.I0(\hdmi_txd2_o[6]_2 ), .O(hdmi_txd2_o[6])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23207.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23208 (.I0(\hdmi_txd2_o[4]_2 ), .O(hdmi_txd2_o[4])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23208.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23209 (.I0(\hdmi_txd2_o[2]_2 ), .O(hdmi_txd2_o[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23209.LUTMASK = 16'h5555; + EFX_LUT4 LUT__23211 (.I0(w_ddr3_atype), .O(\axi4_awar_mux/n14 )) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ; + defparam LUT__23211.LUTMASK = 16'h5555; + EFX_ADD \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_79/add_2/i2 (.I0(1'b1), .I1(1'b1), + .CO(n15071)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(93) + defparam \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_79/add_2/i2 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_79/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_52/add_2/i2 (.I0(n4584), .I1(1'b1), + .CO(n15070)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(79) + defparam \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_52/add_2/i2 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_52/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_50/add_2/i2 (.I0(n4584), .I1(1'b1), + .CO(n15069)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(74) + defparam \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_50/add_2/i2 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_50/add_2/i2 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CO__u_rgb2dvi/enc_2/sub_52/add_2/i1 (.I0(1'b0), .I1(1'b0), + .CI(n15068), .O(n4584)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(79) + defparam \AUX_ADD_CO__u_rgb2dvi/enc_2/sub_52/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CO__u_rgb2dvi/enc_2/sub_52/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_52/add_2/i1 (.I0(1'b1), .I1(1'b1), + .CO(n15067)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\hdmi_ip\tmds_channel.v(79) + defparam \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_52/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__u_rgb2dvi/enc_2/sub_52/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15065)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/R0_FIFO_8\R0_FIFO_8.v(1184) + defparam \AUX_ADD_CI__u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__u_axi4_ctrl/Gen_RFIFO_8.u_R0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_55/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__u_axi4_ctrl/sub_122/add_2/i1 (.I0(1'b1), .I1(1'b1), + .CO(n15064)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\src\axi\axi4_ctrl.v(367) + defparam \AUX_ADD_CI__u_axi4_ctrl/sub_122/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__u_axi4_ctrl/sub_122/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15063)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1191) + defparam \AUX_ADD_CI__u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_54/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i5 (.I0(1'b1), + .I1(1'b1), .CO(n15062)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/W0_FIFO_8\W0_FIFO_8.v(1189) + defparam \AUX_ADD_CI__u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i5 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__u_axi4_ctrl/Gen_FIFO_W8.u_W0_FIFO_8/u_efx_fifo_top/xefx_fifo_ctl/sub_51/add_2/i5 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15061)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/controller_main/sub_1669/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15060)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_46/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15059)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rd/sub_31/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15058)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_rdpush/sub_46/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15057)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_wr/sub_31/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15056)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_aw/sub_31/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15055)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_efx_ddr3/top_mc/fifo_ar/sub_31/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15054)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_len_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15053)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_last_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15052)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_rd_brust_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15051)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_respon_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15050)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arid_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15049)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_awid_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15048)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_wr_addr_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15047)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/u_rd_addr_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15046)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/inst_arburst_fifo/sub_13/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15045)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_83/add_2/i1 .I1_POLARITY = 1'b1; + EFX_ADD \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i1 (.I0(1'b1), + .I1(1'b1), .CO(n15044)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_ADD, I0_POLARITY=1'b1, I1_POLARITY=1'b1 */ ; // ( protected RTL ) // G:\Ti60_Release_Compile\04_Ti60_AR0135_HDMI\ip/DdrCtrl\DdrCtrl.v(0) + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i1 .I0_POLARITY = 1'b1; + defparam \AUX_ADD_CI__ddr3_ctl_axi/u_efx_ddr3_soft_controller/genblk1.inst_ddr3_axi/sub_65/add_2/i1 .I1_POLARITY = 1'b1; + +endmodule + +// +// Verific Verilog Description of module EFX_LUT40 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF3 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF4 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF5 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF6 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF7 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF8 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF9 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF10 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF11 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF12 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF13 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF14 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF15 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF16 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF17 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF18 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF19 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF20 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF21 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF22 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF23 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF24 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF25 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF26 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF27 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF28 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF29 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF30 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF31 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF32 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF33 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF34 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF35 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF36 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF37 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF38 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF39 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF40 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF41 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF42 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF43 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF44 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF45 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF46 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF47 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF48 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF49 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF50 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF51 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF52 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF53 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF54 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF55 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF56 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF57 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF58 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF59 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF60 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF61 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF62 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF63 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF64 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF65 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF66 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF67 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF68 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF69 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF70 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF71 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF72 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF73 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF74 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF75 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF76 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF77 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF78 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF79 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF80 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF81 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF82 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF83 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF84 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF85 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF86 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF87 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF88 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF89 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF90 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF91 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF92 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF93 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF94 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF95 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF96 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF97 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF98 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF99 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF100 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF101 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF102 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF103 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF104 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF105 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF106 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF107 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF108 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF109 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF110 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF111 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF112 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF113 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF114 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF115 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF116 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF117 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF118 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF119 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF120 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF121 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF122 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF123 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF124 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF125 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF126 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF127 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF128 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF129 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF130 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF131 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF132 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF133 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF134 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF135 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF136 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF137 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF138 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF139 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF140 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF141 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF142 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF143 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF144 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF145 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF146 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF147 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF148 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF149 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF150 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF151 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF152 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF153 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF154 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF155 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF156 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF157 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF158 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF159 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF160 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF161 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF162 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF163 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF164 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF165 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF166 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF167 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF168 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF169 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF170 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF171 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF172 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF173 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF174 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF175 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF176 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF177 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF178 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF179 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF180 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF181 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF182 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF183 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF184 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF185 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF186 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF187 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF188 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF189 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF190 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF191 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF192 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF193 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF194 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF195 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF196 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF197 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF198 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF199 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF200 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF201 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF202 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF203 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF204 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF205 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF206 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF207 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF208 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF209 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF210 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF211 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF212 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF213 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF214 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF215 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF216 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF217 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF218 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF219 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF220 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF221 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF222 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF223 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF224 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF225 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF226 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF227 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF228 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF229 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF230 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF231 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF232 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF233 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF234 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF235 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF236 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF237 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF238 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF239 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF240 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF241 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF242 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF243 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF244 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF245 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF246 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF247 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF248 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF249 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF250 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF251 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF252 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF253 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF254 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF255 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF256 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF257 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF258 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF259 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF260 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF261 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF262 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF263 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF264 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF265 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF266 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF267 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF268 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF269 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF270 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF271 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF272 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF273 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF274 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF275 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF276 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF277 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF278 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF279 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF280 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF281 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF282 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF283 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF284 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF285 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF286 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF287 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF288 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF289 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF290 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF291 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF292 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF293 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF294 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF295 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF296 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF297 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF298 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF299 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF300 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF301 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF302 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF303 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF304 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF305 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF306 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF307 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF308 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF309 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF310 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF311 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF312 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF313 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF314 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF315 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF316 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF317 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF318 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF319 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF320 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF321 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF322 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF323 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF324 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF325 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF326 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF327 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF328 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF329 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF330 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF331 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF332 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF333 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF334 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF335 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF336 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF337 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF338 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF339 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF340 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF341 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF342 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF343 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF344 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF345 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF346 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF347 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF348 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF349 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF350 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF351 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF352 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF353 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF354 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF355 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF356 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF357 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF358 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF359 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF360 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF361 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF362 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF363 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF364 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF365 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF366 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF367 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF368 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF369 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF370 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF371 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF372 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF373 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF374 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF375 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF376 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF377 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF378 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF379 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF380 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF381 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF382 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF383 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF384 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF385 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF386 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF387 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF388 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF389 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF390 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF391 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF392 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF393 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF394 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF395 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF396 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF397 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF398 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF399 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF400 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF401 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF402 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF403 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF404 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF405 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF406 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF407 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF408 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF409 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF410 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF411 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF412 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF413 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF414 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF415 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF416 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF417 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF418 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF419 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF420 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF421 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF422 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF423 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF424 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF425 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF426 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF427 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF428 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF429 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF430 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF431 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF432 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF433 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF434 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF435 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF436 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF437 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF438 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF439 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF440 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF441 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF442 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF443 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF444 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF445 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF446 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF447 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF448 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF449 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF450 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF451 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF452 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF453 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF454 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF455 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF456 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF457 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF458 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF459 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF460 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF461 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF462 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF463 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF464 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF465 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF466 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF467 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF468 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF469 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF470 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF471 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF472 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF473 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF474 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF475 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF476 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF477 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF478 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF479 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF480 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF481 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF482 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF483 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF484 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF485 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF486 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF487 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF488 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF489 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF490 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF491 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF492 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF493 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF494 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF495 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF496 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF497 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF498 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF499 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF500 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF501 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF502 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF503 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF504 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF505 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF506 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF507 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF508 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF509 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF510 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF511 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF512 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF513 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF514 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF515 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF516 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF517 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF518 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF519 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF520 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF521 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF522 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF523 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF524 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF525 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF526 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF527 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF528 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF529 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF530 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF531 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF532 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF533 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF534 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF535 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF536 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF537 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF538 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF539 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF540 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF541 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF542 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF543 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF544 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF545 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF546 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF547 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF548 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF549 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF550 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF551 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF552 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF553 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF554 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF555 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF556 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF557 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF558 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF559 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF560 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF561 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF562 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF563 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF564 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF565 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF566 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF567 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF568 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF569 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF570 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF571 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF572 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF573 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF574 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF575 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF576 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF577 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF578 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF579 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF580 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF581 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF582 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF583 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF584 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF585 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF586 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF587 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF588 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF589 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF590 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF591 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF592 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF593 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF594 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF595 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF596 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF597 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF598 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF599 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF600 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF601 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF602 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF603 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF604 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF605 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF606 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF607 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF608 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF609 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF610 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF611 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF612 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF613 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF614 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF615 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF616 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF617 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF618 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF619 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF620 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF621 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF622 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF623 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF624 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF625 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF626 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF627 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF628 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF629 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF630 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF631 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF632 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF633 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF634 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF635 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF636 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF637 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF638 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF639 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF640 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF641 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF642 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF643 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF644 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF645 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF646 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF647 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF648 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF649 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF650 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF651 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF652 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF653 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF654 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF655 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF656 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF657 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF658 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF659 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF660 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF661 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF662 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF663 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF664 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF665 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF666 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF667 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF668 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF669 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF670 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF671 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF672 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF673 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF674 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF675 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF676 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF677 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF678 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF679 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF680 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF681 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF682 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF683 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF684 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF685 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF686 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF687 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF688 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF689 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF690 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF691 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF692 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF693 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF694 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF695 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF696 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF697 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF698 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF699 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF700 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF701 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF702 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF703 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF704 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF705 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF706 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF707 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF708 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF709 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF710 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF711 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF712 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF713 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF714 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF715 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF716 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF717 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF718 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF719 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF720 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF721 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF722 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF723 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF724 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF725 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF726 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF727 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF728 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF729 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF730 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF731 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF732 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF733 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF734 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF735 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF736 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF737 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF738 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF739 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF740 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF741 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF742 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF743 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF744 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF745 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF746 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF747 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF748 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF749 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF750 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF751 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF752 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF753 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF754 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF755 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF756 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF757 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF758 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF759 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF760 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF761 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF762 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF763 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF764 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF765 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF766 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF767 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF768 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF769 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF770 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF771 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF772 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF773 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF774 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF775 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF776 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF777 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF778 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF779 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF780 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF781 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF782 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF783 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF784 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF785 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF786 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF787 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF788 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF789 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF790 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF791 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF792 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF793 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF794 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF795 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF796 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF797 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF798 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF799 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF800 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF801 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF802 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF803 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF804 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF805 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF806 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF807 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF808 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF809 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF810 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF811 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF812 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF813 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF814 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF815 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF816 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF817 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF818 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF819 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF820 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF821 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF822 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF823 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF824 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF825 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF826 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF827 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF828 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF829 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF830 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF831 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF832 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF833 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF834 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF835 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF836 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF837 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF838 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF839 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF840 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF841 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF842 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF843 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF844 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF845 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF846 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF847 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF848 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF849 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF850 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF851 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF852 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF853 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF854 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF855 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF856 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF857 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF858 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF859 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF860 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF861 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF862 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF863 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF864 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF865 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF866 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF867 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF868 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF869 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF870 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF871 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF872 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF873 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF874 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF875 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF876 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF877 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF878 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF879 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF880 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF881 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF882 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF883 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF884 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF885 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF886 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF887 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF888 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF889 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF890 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF891 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF892 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF893 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF894 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF895 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF896 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF897 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF898 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF899 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF900 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF901 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF902 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF903 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF904 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF905 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF906 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF907 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF908 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF909 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF910 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF911 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF912 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF913 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF914 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF915 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF916 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF917 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF918 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF919 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF920 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF921 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF922 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF923 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF924 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF925 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF926 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF927 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF928 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF929 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF930 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF931 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF932 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF933 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF934 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF935 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF936 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF937 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF938 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF939 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF940 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF941 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF942 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF943 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF944 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF945 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF946 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF947 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF948 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF949 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF950 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF951 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF952 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF953 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF954 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF955 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF956 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF957 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF958 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF959 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF960 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF961 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF962 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF963 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF964 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF965 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF966 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF967 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF968 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF969 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF970 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF971 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF972 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF973 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF974 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF975 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF976 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF977 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF978 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF979 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF980 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF981 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF982 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF983 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF984 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF985 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF986 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF987 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF988 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF989 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF990 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF991 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF992 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF993 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF994 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF995 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF996 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF997 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF998 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF999 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1000 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1001 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1002 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1003 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1004 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1005 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1006 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1007 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1008 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1009 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1010 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1011 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1012 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1013 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1014 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1015 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1016 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1017 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1018 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1019 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1020 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1021 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1022 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1023 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1024 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1025 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1026 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1027 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1028 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1029 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1030 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1031 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1032 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1033 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1034 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1035 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1036 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1037 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1038 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1039 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1040 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1041 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1042 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1043 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1044 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1045 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1046 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1047 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1048 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1049 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1050 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1051 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1052 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1053 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1054 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1055 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1056 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1057 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1058 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1059 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1060 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1061 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1062 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1063 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1064 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1065 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1066 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1067 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1068 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1069 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1070 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1071 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1072 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1073 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1074 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1075 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1076 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1077 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1078 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1079 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1080 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1081 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1082 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1083 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1084 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1085 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1086 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1087 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1088 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1089 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1090 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1091 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1092 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1093 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1094 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1095 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1096 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1097 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1098 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1099 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1100 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1101 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1102 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1103 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1104 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1105 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1106 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1107 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1108 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1109 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1110 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1111 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1112 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1113 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1114 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1115 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1116 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1117 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1118 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1119 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1120 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1121 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1122 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1123 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1124 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1125 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1126 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1127 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1128 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1129 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1130 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1131 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1132 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1133 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1134 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1135 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1136 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1137 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1138 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1139 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1140 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1141 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1142 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1143 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1144 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1145 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1146 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1147 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1148 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1149 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1150 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1151 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1152 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1153 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1154 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1155 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1156 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1157 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1158 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1159 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1160 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1161 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1162 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1163 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1164 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1165 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1166 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1167 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1168 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1169 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1170 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1171 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1172 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1173 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1174 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1175 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1176 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1177 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1178 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1179 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1180 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1181 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1182 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1183 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1184 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1185 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1186 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1187 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1188 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1189 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1190 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1191 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1192 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1193 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1194 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1195 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1196 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1197 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1198 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1199 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1200 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1201 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1202 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1203 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1204 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1205 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1206 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1207 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1208 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1209 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1210 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1211 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1212 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1213 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1214 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1215 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1216 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1217 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1218 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1219 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1220 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1221 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1222 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1223 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1224 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1225 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1226 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1227 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1228 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1229 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1230 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1231 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1232 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1233 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1234 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1235 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1236 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1237 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1238 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1239 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1240 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1241 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1242 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1243 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1244 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1245 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1246 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1247 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1248 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1249 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1250 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1251 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1252 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1253 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1254 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1255 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1256 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1257 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1258 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1259 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1260 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1261 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1262 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1263 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1264 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1265 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1266 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1267 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1268 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1269 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1270 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1271 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1272 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1273 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1274 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1275 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1276 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1277 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1278 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1279 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1280 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1281 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1282 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1283 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1284 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1285 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1286 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1287 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1288 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1289 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1290 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1291 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1292 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1293 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1294 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1295 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1296 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1297 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1298 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1299 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1300 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1301 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1302 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1303 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1304 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1305 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1306 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1307 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1308 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1309 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1310 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1311 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1312 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1313 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1314 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1315 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1316 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1317 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1318 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1319 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1320 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1321 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1322 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1323 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1324 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1325 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1326 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1327 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1328 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1329 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1330 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1331 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1332 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1333 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1334 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1335 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1336 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1337 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1338 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1339 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1340 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1341 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1342 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1343 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1344 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1345 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1346 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1347 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1348 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1349 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1350 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1351 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1352 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1353 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1354 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1355 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1356 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1357 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1358 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1359 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1360 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1361 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1362 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1363 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1364 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1365 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1366 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1367 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1368 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1369 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1370 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1371 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1372 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1373 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1374 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1375 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1376 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1377 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1378 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1379 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1380 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1381 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1382 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1383 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1384 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1385 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1386 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1387 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1388 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1389 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1390 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1391 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1392 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1393 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1394 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1395 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1396 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1397 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1398 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1399 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1400 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1401 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1402 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1403 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1404 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1405 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1406 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1407 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1408 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1409 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1410 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1411 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1412 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1413 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1414 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1415 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1416 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1417 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1418 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1419 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1420 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1421 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1422 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1423 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1424 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1425 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1426 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1427 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1428 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1429 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1430 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1431 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1432 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1433 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1434 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1435 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1436 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1437 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1438 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1439 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1440 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1441 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1442 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1443 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1444 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1445 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1446 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1447 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1448 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1449 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1450 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1451 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1452 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1453 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1454 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1455 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1456 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1457 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1458 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1459 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1460 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1461 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1462 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1463 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1464 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1465 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1466 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1467 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1468 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1469 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1470 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1471 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1472 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1473 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1474 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1475 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1476 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1477 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1478 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1479 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1480 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1481 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1482 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1483 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1484 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1485 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1486 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1487 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1488 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1489 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1490 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1491 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1492 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1493 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1494 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1495 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1496 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1497 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1498 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1499 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1500 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1501 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1502 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1503 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1504 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1505 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1506 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1507 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1508 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1509 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1510 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1511 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1512 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1513 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1514 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1515 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1516 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1517 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1518 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1519 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1520 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1521 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1522 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1523 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1524 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1525 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1526 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1527 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1528 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1529 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1530 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1531 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1532 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1533 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1534 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1535 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1536 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1537 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1538 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1539 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1540 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1541 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1542 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1543 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1544 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1545 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1546 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1547 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1548 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1549 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1550 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1551 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1552 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1553 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1554 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1555 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1556 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1557 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1558 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1559 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1560 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1561 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1562 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1563 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1564 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1565 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1566 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1567 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1568 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1569 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1570 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1571 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1572 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1573 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1574 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1575 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1576 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1577 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1578 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1579 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1580 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1581 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1582 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1583 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1584 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1585 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1586 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1587 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1588 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1589 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1590 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1591 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1592 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1593 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1594 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1595 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1596 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1597 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1598 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1599 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1600 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1601 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1602 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1603 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1604 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1605 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1606 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1607 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1608 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1609 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1610 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1611 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1612 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1613 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1614 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1615 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1616 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1617 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1618 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1619 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1620 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1621 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1622 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1623 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1624 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1625 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1626 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1627 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1628 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1629 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1630 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1631 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1632 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1633 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1634 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1635 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1636 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1637 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1638 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1639 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1640 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1641 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1642 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1643 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1644 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1645 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1646 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1647 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1648 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1649 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1650 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1651 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1652 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1653 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1654 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1655 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1656 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1657 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1658 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1659 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1660 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1661 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1662 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1663 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1664 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1665 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1666 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1667 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1668 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1669 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1670 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1671 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1672 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1673 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1674 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1675 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1676 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1677 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1678 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1679 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1680 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1681 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1682 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1683 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1684 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1685 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1686 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1687 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1688 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1689 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1690 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1691 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1692 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1693 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1694 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1695 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1696 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1697 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1698 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1699 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1700 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1701 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1702 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1703 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1704 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1705 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1706 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1707 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1708 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1709 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1710 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1711 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1712 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1713 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1714 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1715 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1716 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1717 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1718 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1719 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1720 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1721 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1722 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1723 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1724 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1725 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1726 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1727 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1728 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1729 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1730 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1731 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1732 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1733 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1734 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1735 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1736 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1737 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1738 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1739 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1740 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1741 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1742 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1743 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1744 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1745 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1746 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1747 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1748 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1749 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1750 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1751 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1752 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1753 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1754 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1755 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1756 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1757 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1758 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1759 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1760 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1761 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1762 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1763 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1764 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1765 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1766 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1767 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1768 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1769 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1770 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1771 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1772 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1773 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1774 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1775 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1776 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1777 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1778 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1779 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1780 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1781 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1782 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1783 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1784 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1785 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1786 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1787 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1788 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1789 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1790 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1791 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1792 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1793 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1794 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1795 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1796 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1797 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1798 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1799 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1800 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1801 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1802 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1803 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1804 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1805 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1806 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1807 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1808 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1809 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1810 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1811 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1812 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1813 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1814 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1815 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1816 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1817 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1818 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1819 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1820 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1821 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1822 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1823 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1824 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1825 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1826 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1827 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1828 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1829 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1830 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1831 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1832 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1833 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1834 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1835 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1836 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1837 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1838 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1839 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1840 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1841 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1842 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1843 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1844 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1845 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1846 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1847 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1848 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1849 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1850 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1851 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1852 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1853 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1854 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1855 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1856 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1857 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1858 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1859 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1860 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1861 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1862 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1863 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1864 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1865 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1866 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1867 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1868 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1869 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1870 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1871 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1872 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1873 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1874 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1875 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1876 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1877 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1878 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1879 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1880 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1881 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1882 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1883 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1884 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1885 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1886 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1887 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1888 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1889 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1890 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1891 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1892 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1893 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1894 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1895 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1896 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1897 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1898 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1899 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1900 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1901 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1902 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1903 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1904 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1905 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1906 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1907 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1908 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1909 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1910 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1911 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1912 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1913 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1914 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1915 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1916 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1917 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1918 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1919 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1920 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1921 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1922 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1923 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1924 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1925 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1926 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1927 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1928 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1929 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1930 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1931 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1932 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1933 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1934 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1935 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1936 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1937 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1938 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1939 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1940 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1941 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1942 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1943 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1944 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1945 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1946 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1947 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1948 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1949 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1950 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1951 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1952 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1953 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1954 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1955 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1956 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1957 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1958 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1959 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1960 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1961 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1962 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1963 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1964 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1965 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1966 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1967 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1968 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1969 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1970 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1971 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1972 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1973 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1974 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1975 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1976 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1977 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1978 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1979 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1980 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1981 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1982 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1983 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1984 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1985 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1986 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1987 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1988 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1989 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1990 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1991 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1992 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1993 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1994 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1995 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1996 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1997 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1998 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF1999 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2000 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2001 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2002 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2003 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2004 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2005 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2006 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2007 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2008 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2009 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2010 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2011 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2012 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2013 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2014 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2015 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2016 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2017 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2018 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2019 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2020 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2021 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2022 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2023 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2024 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2025 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2026 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2027 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2028 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2029 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2030 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2031 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2032 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2033 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2034 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2035 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2036 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2037 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2038 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2039 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2040 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2041 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2042 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2043 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2044 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2045 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2046 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2047 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2048 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2049 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2050 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2051 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2052 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2053 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2054 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2055 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2056 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2057 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2058 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2059 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2060 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2061 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2062 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2063 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2064 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2065 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2066 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2067 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2068 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2069 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2070 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2071 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2072 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2073 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2074 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2075 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2076 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2077 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2078 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2079 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2080 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2081 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2082 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2083 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2084 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2085 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2086 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2087 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2088 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2089 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2090 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2091 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2092 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2093 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2094 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2095 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2096 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2097 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2098 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2099 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2100 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2101 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2102 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2103 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2104 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2105 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2106 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2107 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2108 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2109 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2110 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2111 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2112 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2113 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2114 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2115 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2116 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2117 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2118 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2119 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2120 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2121 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2122 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2123 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2124 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2125 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2126 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2127 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2128 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2129 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2130 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2131 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2132 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2133 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2134 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2135 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2136 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2137 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2138 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2139 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2140 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2141 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2142 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2143 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2144 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2145 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2146 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2147 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2148 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2149 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2150 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2151 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2152 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2153 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2154 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2155 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2156 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2157 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2158 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2159 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2160 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2161 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2162 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2163 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2164 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2165 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2166 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2167 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2168 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2169 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2170 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2171 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2172 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2173 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2174 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2175 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2176 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2177 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2178 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2179 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2180 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2181 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2182 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2183 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2184 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2185 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2186 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2187 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2188 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2189 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2190 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2191 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2192 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2193 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2194 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2195 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2196 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2197 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2198 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2199 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2200 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2201 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2202 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2203 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2204 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2205 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2206 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2207 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2208 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2209 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2210 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2211 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2212 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2213 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2214 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2215 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2216 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2217 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2218 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2219 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2220 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2221 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2222 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2223 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2224 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2225 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2226 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2227 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2228 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2229 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2230 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2231 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2232 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2233 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2234 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2235 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2236 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2237 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2238 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2239 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2240 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2241 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2242 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2243 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2244 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2245 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2246 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2247 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2248 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2249 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2250 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2251 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2252 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2253 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2254 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2255 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2256 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2257 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2258 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2259 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2260 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2261 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2262 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2263 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2264 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2265 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2266 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2267 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2268 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2269 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2270 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2271 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2272 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2273 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2274 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2275 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2276 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2277 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2278 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2279 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2280 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2281 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2282 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2283 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2284 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2285 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2286 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2287 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2288 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2289 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2290 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2291 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2292 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2293 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2294 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2295 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2296 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2297 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2298 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2299 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2300 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2301 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2302 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2303 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2304 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2305 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2306 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2307 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2308 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2309 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2310 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2311 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2312 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2313 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2314 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2315 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2316 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2317 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2318 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2319 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2320 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2321 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2322 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2323 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2324 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2325 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2326 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2327 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2328 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2329 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2330 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2331 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2332 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2333 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2334 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2335 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2336 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2337 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2338 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2339 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2340 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2341 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2342 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2343 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2344 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2345 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2346 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2347 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2348 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2349 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2350 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2351 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2352 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2353 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2354 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2355 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2356 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2357 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2358 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2359 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2360 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2361 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2362 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2363 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2364 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2365 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT42366 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2367 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2368 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2369 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2370 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2371 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2372 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2373 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2374 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2375 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2376 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2377 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2378 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2379 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2380 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2381 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2382 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2383 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2384 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2385 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2386 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2387 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2388 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2389 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2390 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2391 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2392 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2393 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2394 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2395 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2396 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2397 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2398 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2399 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2400 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2401 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2402 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2403 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2404 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2405 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2406 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2407 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2408 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2409 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2410 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2411 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2412 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2413 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2414 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2415 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2416 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2417 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2418 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2419 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2420 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2421 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2422 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2423 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2424 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2425 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2426 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2427 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2428 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2429 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2430 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2431 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2432 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2433 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2434 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2435 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2436 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2437 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2438 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2439 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2440 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2441 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2442 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2443 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2444 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2445 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2446 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2447 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2448 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2449 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2450 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2451 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2452 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2453 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2454 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2455 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2456 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2457 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2458 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2459 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2460 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2461 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2462 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2463 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2464 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2465 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2466 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2467 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2468 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2469 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2470 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2471 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2472 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2473 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2474 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2475 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2476 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2477 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2478 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2479 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2480 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2481 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2482 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2483 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2484 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2485 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2486 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2487 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2488 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2489 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2490 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2491 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2492 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2493 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2494 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2495 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2496 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2497 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2498 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2499 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2500 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2501 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2502 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2503 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2504 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2505 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2506 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2507 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2508 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2509 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2510 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2511 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2512 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2513 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2514 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2515 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2516 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2517 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2518 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2519 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2520 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2521 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2522 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2523 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2524 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2525 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2526 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2527 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2528 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2529 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2530 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2531 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2532 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2533 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2534 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2535 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2536 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2537 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2538 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2539 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2540 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2541 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2542 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2543 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2544 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2545 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2546 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2547 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2548 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2549 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2550 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2551 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2552 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2553 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2554 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2555 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2556 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2557 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2558 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2559 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2560 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2561 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2562 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2563 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2564 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2565 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2566 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2567 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2568 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2569 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2570 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2571 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2572 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2573 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2574 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2575 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2576 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2577 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2578 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2579 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2580 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2581 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2582 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2583 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2584 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2585 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2586 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2587 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2588 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2589 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2590 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2591 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2592 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2593 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2594 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2595 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2596 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2597 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2598 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2599 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2600 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2601 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2602 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2603 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2604 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2605 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2606 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2607 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2608 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2609 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2610 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2611 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2612 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2613 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2614 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2615 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2616 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2617 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2618 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2619 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2620 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2621 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2622 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2623 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2624 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2625 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2626 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2627 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2628 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2629 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2630 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2631 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2632 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2633 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2634 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2635 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2636 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2637 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2638 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2639 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2640 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2641 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2642 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2643 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2644 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2645 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2646 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2647 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2648 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2649 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2650 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2651 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2652 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2653 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2654 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2655 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2656 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2657 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2658 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2659 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2660 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2661 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2662 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2663 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2664 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2665 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2666 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2667 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2668 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2669 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2670 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2671 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2672 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2673 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2674 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2675 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2676 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2677 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2678 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2679 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2680 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2681 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2682 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2683 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2684 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2685 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2686 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2687 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2688 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2689 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2690 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2691 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2692 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2693 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2694 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2695 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2696 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2697 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2698 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2699 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2700 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2701 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2702 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2703 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2704 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2705 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2706 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2707 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2708 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2709 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2710 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2711 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2712 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2713 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2714 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2715 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2716 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2717 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2718 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2719 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2720 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2721 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2722 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2723 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2724 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2725 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2726 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2727 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2728 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2729 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2730 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2731 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2732 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2733 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2734 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2735 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2736 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2737 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2738 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2739 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2740 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2741 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2742 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2743 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2744 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2745 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2746 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2747 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2748 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2749 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2750 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2751 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2752 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2753 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2754 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2755 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2756 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2757 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2758 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2759 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2760 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2761 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2762 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2763 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2764 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2765 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2766 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2767 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2768 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2769 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2770 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2771 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2772 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2773 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2774 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2775 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2776 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2777 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2778 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2779 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2780 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2781 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2782 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2783 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2784 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2785 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2786 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2787 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2788 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2789 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2790 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2791 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2792 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2793 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2794 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2795 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2796 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2797 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2798 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2799 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2800 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2801 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2802 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2803 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2804 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2805 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2806 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2807 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2808 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2809 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2810 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2811 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2812 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2813 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2814 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2815 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2816 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2817 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2818 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2819 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2820 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2821 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_FF2822 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2823 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2824 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2825 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2826 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2827 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2828 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2829 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2830 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2831 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2832 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2833 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2834 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2835 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2836 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2837 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2838 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2839 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2840 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2841 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2842 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2843 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2844 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2845 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2846 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2847 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2848 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2849 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2850 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2851 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2852 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2853 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2854 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2855 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2856 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2857 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2858 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2859 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2860 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2861 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2862 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2863 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2864 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2865 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2866 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2867 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2868 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2869 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2870 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2871 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2872 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2873 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2874 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2875 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2876 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2877 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2878 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2879 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2880 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2881 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2882 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2883 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2884 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2885 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2886 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2887 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2888 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2889 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2890 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2891 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2892 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2893 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2894 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2895 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2896 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2897 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2898 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2899 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2900 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2901 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2902 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2903 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2904 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2905 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2906 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2907 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2908 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2909 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2910 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2911 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2912 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2913 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2914 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2915 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2916 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2917 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2918 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2919 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2920 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2921 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2922 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2923 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2924 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2925 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2926 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2927 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2928 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2929 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2930 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2931 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2932 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2933 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2934 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2935 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2936 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2937 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2938 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2939 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2940 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2941 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2942 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2943 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2944 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2945 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2946 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2947 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2948 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2949 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2950 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2951 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2952 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2953 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2954 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2955 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2956 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2957 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2958 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2959 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2960 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2961 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2962 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2963 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2964 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2965 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2966 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2967 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2968 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2969 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2970 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2971 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2972 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2973 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2974 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2975 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2976 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2977 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2978 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2979 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2980 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2981 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2982 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2983 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2984 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2985 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2986 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2987 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2988 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2989 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2990 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2991 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2992 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2993 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2994 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2995 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2996 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2997 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2998 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD2999 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3000 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3001 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3002 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3003 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3004 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3005 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3006 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3007 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3008 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3009 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3010 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3011 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3012 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3013 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3014 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3015 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3016 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3017 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3018 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3019 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3020 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3021 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3022 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3023 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3024 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3025 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3026 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3027 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3028 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3029 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3030 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3031 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3032 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3033 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3034 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3035 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3036 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3037 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3038 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3039 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3040 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3041 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3042 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3043 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3044 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3045 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3046 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3047 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3048 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3049 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3050 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3051 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3052 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3053 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3054 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3055 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3056 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3057 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3058 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3059 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3060 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3061 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3062 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3063 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3064 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3065 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3066 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3067 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3068 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3069 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3070 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3071 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3072 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3073 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3074 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3075 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3076 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3077 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3078 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3079 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3080 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3081 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3082 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3083 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3084 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3085 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3086 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3087 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3088 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3089 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3090 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3091 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3092 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3093 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3094 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3095 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3096 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3097 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3098 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3099 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3100 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3101 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3102 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3103 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3104 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3105 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3106 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3107 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3108 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3109 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3110 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3111 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3112 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3113 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3114 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3115 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3116 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3117 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3118 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3119 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3120 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3121 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3122 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3123 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3124 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3125 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3126 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3127 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3128 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3129 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3130 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3131 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3132 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3133 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3134 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3135 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3136 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3137 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3138 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3139 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3140 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3141 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3142 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3143 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3144 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3145 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3146 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3147 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3148 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3149 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3150 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3151 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3152 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3153 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3154 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3155 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3156 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3157 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3158 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3159 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3160 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3161 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3162 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3163 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3164 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3165 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3166 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3167 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3168 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3169 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3170 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3171 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3172 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3173 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3174 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3175 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3176 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3177 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3178 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3179 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3180 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3181 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3182 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3183 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3184 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3185 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3186 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3187 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3188 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3189 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3190 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3191 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3192 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3193 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3194 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3195 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3196 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3197 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3198 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3199 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3200 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3201 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3202 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3203 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3204 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3205 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3206 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3207 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3208 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3209 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3210 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3211 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3212 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3213 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3214 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3215 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3216 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3217 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3218 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3219 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3220 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3221 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3222 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3223 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3224 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3225 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3226 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3227 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3228 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3229 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3230 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3231 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3232 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3233 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3234 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3235 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3236 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3237 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3238 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3239 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3240 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3241 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3242 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3243 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3244 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3245 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3246 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3247 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3248 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3249 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3250 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3251 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3252 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3253 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3254 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3255 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3256 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3257 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3258 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3259 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3260 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3261 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3262 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3263 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3264 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3265 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3266 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3267 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3268 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3269 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3270 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3271 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3272 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3273 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3274 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3275 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3276 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3277 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3278 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3279 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3280 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3281 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3282 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3283 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3284 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3285 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3286 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3287 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3288 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3289 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3290 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3291 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3292 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3293 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3294 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3295 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3296 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3297 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3298 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3299 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3300 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3301 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3302 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3303 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3304 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3305 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3306 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3307 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3308 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3309 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3310 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3311 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3312 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3313 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3314 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3315 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3316 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3317 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3318 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3319 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3320 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3321 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3322 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3323 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3324 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3325 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3326 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3327 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3328 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3329 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3330 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3331 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3332 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3333 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3334 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3335 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3336 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3337 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3338 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3339 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3340 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3341 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3342 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3343 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3344 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3345 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3346 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3347 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3348 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3349 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3350 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3351 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3352 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3353 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3354 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3355 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3356 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3357 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3358 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3359 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3360 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3361 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3362 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3363 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3364 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3365 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3366 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3367 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3368 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3369 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3370 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3371 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3372 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3373 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3374 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3375 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3376 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3377 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3378 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3379 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3380 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3381 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3382 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3383 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3384 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3385 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3386 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3387 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3388 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3389 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3390 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3391 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3392 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3393 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3394 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3395 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3396 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3397 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3398 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3399 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3400 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3401 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3402 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3403 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3404 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3405 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3406 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3407 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3408 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3409 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3410 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3411 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3412 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3413 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3414 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3415 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3416 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3417 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3418 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3419 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3420 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3421 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3422 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3423 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3424 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3425 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3426 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3427 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3428 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3429 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3430 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3431 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3432 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3433 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3434 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3435 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3436 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3437 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3438 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3439 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3440 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3441 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3442 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3443 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3444 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3445 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3446 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3447 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3448 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3449 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3450 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3451 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3452 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3453 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3454 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3455 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3456 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3457 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3458 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3459 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3460 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3461 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3462 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3463 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3464 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3465 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3466 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3467 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3468 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3469 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3470 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3471 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3472 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3473 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3474 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3475 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3476 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3477 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3478 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3479 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3480 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3481 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3482 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3483 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3484 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3485 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3486 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3487 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3488 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3489 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3490 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3491 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3492 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3493 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3494 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3495 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3496 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3497 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3498 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3499 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3500 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3501 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3502 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3503 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3504 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3505 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3506 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3507 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3508 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3509 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3510 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3511 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3512 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3513 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3514 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3515 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3516 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3517 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3518 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3519 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD3520 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83521 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83522 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83523 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83524 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83525 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83526 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83527 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83528 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83529 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83530 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83531 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83532 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83533 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83534 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83535 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83536 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83537 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83538 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83539 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83540 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83541 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83542 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83543 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83544 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83545 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83546 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83547 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83548 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83549 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83550 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83551 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83552 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83553 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83554 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83555 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83556 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83557 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83558 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83559 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83560 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83561 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83562 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83563 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83564 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83565 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83566 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83567 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83568 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83569 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83570 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83571 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83572 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83573 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83574 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83575 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83576 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83577 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83578 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83579 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83580 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83581 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83582 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83583 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83584 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83585 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83586 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83587 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83588 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83589 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83590 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83591 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83592 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83593 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83594 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83595 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83596 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83597 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83598 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83599 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83600 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83601 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83602 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83603 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83604 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83605 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83606 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83607 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83608 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83609 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83610 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83611 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83612 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83613 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83614 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83615 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83616 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83617 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83618 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83619 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83620 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83621 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83622 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83623 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83624 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83625 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83626 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83627 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83628 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83629 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83630 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83631 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83632 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83633 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83634 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83635 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83636 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83637 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83638 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83639 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83640 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83641 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83642 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83643 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83644 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83645 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83646 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83647 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83648 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83649 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83650 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83651 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83652 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83653 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83654 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83655 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83656 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83657 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83658 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83659 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83660 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83661 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83662 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83663 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83664 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83665 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83666 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83667 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83668 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83669 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83670 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83671 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83672 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83673 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83674 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83675 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83676 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83677 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83678 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83679 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83680 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83681 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83682 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83683 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83684 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83685 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83686 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83687 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83688 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83689 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83690 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83691 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83692 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83693 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83694 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83695 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83696 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83697 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83698 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83699 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83700 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83701 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83702 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83703 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83704 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83705 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83706 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83707 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83708 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83709 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83710 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83711 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83712 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83713 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83714 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83715 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83716 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83717 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83718 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83719 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83720 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83721 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83722 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83723 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83724 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83725 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83726 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83727 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83728 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83729 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83730 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83731 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83732 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83733 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83734 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83735 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83736 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83737 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83738 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83739 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83740 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83741 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83742 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83743 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83744 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83745 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83746 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83747 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83748 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83749 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83750 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83751 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83752 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83753 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83754 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83755 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83756 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83757 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83758 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83759 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83760 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83761 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83762 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83763 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83764 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83765 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83766 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83767 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83768 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83769 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83770 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83771 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83772 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83773 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83774 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83775 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83776 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83777 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83778 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83779 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83780 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83781 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83782 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83783 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83784 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83785 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83786 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83787 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83788 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83789 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83790 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83791 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83792 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83793 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83794 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83795 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83796 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83797 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83798 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83799 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83800 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83801 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83802 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83803 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83804 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83805 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83806 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83807 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83808 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83809 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83810 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83811 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83812 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83813 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83814 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83815 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83816 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83817 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83818 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83819 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83820 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83821 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83822 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83823 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83824 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83825 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83826 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83827 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83828 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83829 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83830 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83831 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83832 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83833 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83834 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83835 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83836 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83837 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83838 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83839 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83840 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83841 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83842 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83843 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83844 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83845 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83846 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83847 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83848 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83849 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83850 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83851 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83852 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83853 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83854 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83855 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83856 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83857 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83858 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83859 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83860 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83861 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83862 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83863 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83864 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103865 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103866 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103867 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103868 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103869 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103870 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103871 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103872 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103873 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103874 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103875 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103876 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103877 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103878 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103879 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103880 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103881 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103882 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103883 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103884 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103885 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103886 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM103887 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83888 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83889 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83890 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83891 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83892 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83893 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83894 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83895 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83896 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83897 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83898 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83899 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83900 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83901 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83902 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83903 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83904 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83905 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83906 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83907 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83908 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83909 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83910 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83911 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83912 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83913 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83914 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83915 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83916 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83917 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83918 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83919 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83920 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83921 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83922 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83923 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83924 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83925 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83926 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83927 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83928 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83929 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83930 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83931 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83932 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83933 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83934 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83935 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83936 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83937 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83938 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83939 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83940 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83941 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83942 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83943 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83944 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83945 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83946 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83947 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83948 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83949 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83950 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83951 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83952 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83953 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83954 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83955 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83956 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83957 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83958 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83959 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83960 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83961 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83962 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83963 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83964 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83965 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83966 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83967 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83968 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83969 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83970 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83971 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83972 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83973 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83974 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83975 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83976 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83977 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83978 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83979 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83980 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83981 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83982 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83983 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83984 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83985 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83986 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83987 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83988 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83989 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83990 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83991 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83992 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83993 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83994 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83995 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83996 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83997 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83998 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL83999 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84000 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84001 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84002 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84003 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84004 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84005 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84006 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84007 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84008 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84009 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84010 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84011 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84012 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84013 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84014 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84015 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84016 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84017 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84018 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84019 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84020 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84021 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84022 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84023 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84024 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84025 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84026 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84027 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84028 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84029 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84030 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84031 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84032 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84033 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104034 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104035 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104036 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104037 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84038 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84039 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84040 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104041 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104042 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104043 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104044 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104045 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104046 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104047 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104048 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104049 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84050 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84051 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84052 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84053 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84054 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84055 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84056 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84057 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84058 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84059 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84060 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84061 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84062 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84063 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84064 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84065 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84066 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84067 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84068 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84069 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104070 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104071 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104072 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104073 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104074 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104075 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_RAM104076 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84077 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84078 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84079 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84080 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84081 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84082 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84083 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84084 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84085 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84086 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84087 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84088 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84089 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84090 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84091 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84092 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84093 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84094 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84095 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84096 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_SRL84097 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44098 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44099 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44100 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44101 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44102 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44103 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44104 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44105 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44106 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44107 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44108 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44109 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44110 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44111 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44112 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44113 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44114 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44115 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44116 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44117 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44118 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44119 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44120 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44121 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44122 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44123 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44124 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44125 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44126 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44127 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44128 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44129 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44130 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44131 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44132 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44133 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44134 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44135 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44136 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44137 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44138 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44139 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44140 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44141 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44142 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44143 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44144 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44145 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44146 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44147 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44148 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44149 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44150 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44151 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44152 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44153 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44154 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44155 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44156 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44157 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44158 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44159 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44160 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44161 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44162 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44163 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44164 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44165 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44166 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44167 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44168 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44169 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44170 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44171 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44172 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44173 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44174 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44175 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44176 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44177 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44178 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44179 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44180 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44181 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44182 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44183 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44184 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44185 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44186 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44187 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44188 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44189 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44190 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44191 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44192 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44193 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44194 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44195 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44196 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44197 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44198 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44199 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44200 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44201 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44202 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44203 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44204 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44205 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44206 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44207 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44208 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44209 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44210 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44211 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44212 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44213 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44214 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44215 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44216 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44217 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44218 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44219 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44220 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44221 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44222 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44223 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44224 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44225 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44226 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44227 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44228 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44229 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44230 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44231 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44232 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44233 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44234 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44235 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44236 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44237 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44238 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44239 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44240 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44241 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44242 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44243 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44244 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44245 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44246 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44247 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44248 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44249 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44250 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44251 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44252 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44253 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44254 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44255 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44256 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44257 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44258 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44259 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44260 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44261 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44262 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44263 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44264 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44265 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44266 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44267 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44268 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44269 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44270 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44271 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44272 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44273 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44274 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44275 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44276 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44277 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44278 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44279 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44280 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44281 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44282 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44283 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44284 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44285 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44286 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44287 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44288 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44289 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44290 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44291 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44292 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44293 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44294 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44295 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44296 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44297 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44298 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44299 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44300 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44301 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44302 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44303 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44304 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44305 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44306 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44307 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44308 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44309 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44310 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44311 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44312 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44313 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44314 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44315 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44316 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44317 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44318 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44319 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44320 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44321 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44322 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44323 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44324 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44325 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44326 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44327 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44328 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44329 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44330 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44331 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44332 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44333 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44334 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44335 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44336 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44337 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44338 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44339 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44340 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44341 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44342 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44343 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44344 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44345 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44346 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44347 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44348 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44349 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44350 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44351 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44352 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44353 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44354 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44355 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44356 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44357 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44358 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44359 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44360 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44361 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44362 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44363 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44364 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44365 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44366 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44367 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44368 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44369 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44370 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44371 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44372 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44373 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44374 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44375 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44376 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44377 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44378 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44379 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44380 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44381 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44382 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44383 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44384 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44385 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44386 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44387 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44388 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44389 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44390 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44391 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44392 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44393 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44394 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44395 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44396 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44397 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44398 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44399 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44400 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44401 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44402 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44403 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44404 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44405 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44406 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44407 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44408 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44409 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44410 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44411 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44412 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44413 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44414 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44415 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44416 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44417 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44418 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44419 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44420 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44421 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44422 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44423 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44424 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44425 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44426 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44427 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44428 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44429 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44430 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44431 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44432 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44433 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44434 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44435 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44436 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44437 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44438 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44439 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44440 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44441 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44442 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44443 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44444 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44445 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44446 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44447 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44448 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44449 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44450 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44451 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44452 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44453 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44454 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44455 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44456 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44457 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44458 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44459 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44460 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44461 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44462 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44463 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44464 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44465 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44466 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44467 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44468 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44469 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44470 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44471 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44472 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44473 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44474 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44475 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44476 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44477 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44478 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44479 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44480 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44481 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44482 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44483 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44484 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44485 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44486 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44487 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44488 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44489 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44490 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44491 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44492 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44493 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44494 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44495 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44496 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44497 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44498 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44499 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44500 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44501 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44502 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44503 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44504 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44505 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44506 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44507 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44508 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44509 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44510 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44511 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44512 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44513 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44514 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44515 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44516 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44517 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44518 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44519 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44520 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44521 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44522 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44523 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44524 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44525 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44526 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44527 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44528 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44529 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44530 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44531 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44532 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44533 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44534 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44535 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44536 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44537 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44538 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44539 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44540 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44541 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44542 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44543 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44544 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44545 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44546 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44547 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44548 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44549 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44550 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44551 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44552 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44553 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44554 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44555 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44556 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44557 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44558 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44559 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44560 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44561 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44562 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44563 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44564 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44565 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44566 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44567 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44568 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44569 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44570 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44571 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44572 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44573 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44574 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44575 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44576 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44577 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44578 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44579 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44580 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44581 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44582 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44583 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44584 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44585 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44586 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44587 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44588 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44589 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44590 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44591 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44592 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44593 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44594 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44595 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44596 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44597 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44598 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44599 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44600 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44601 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44602 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44603 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44604 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44605 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44606 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44607 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44608 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44609 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44610 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44611 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44612 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44613 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44614 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44615 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44616 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44617 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44618 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44619 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44620 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44621 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44622 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44623 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44624 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44625 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44626 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44627 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44628 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44629 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44630 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44631 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44632 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44633 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44634 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44635 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44636 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44637 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44638 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44639 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44640 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44641 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44642 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44643 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44644 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44645 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44646 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44647 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44648 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44649 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44650 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44651 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44652 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44653 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44654 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44655 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44656 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44657 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44658 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44659 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44660 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44661 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44662 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44663 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44664 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44665 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44666 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44667 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44668 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44669 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44670 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44671 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44672 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44673 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44674 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44675 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44676 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44677 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44678 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44679 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44680 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44681 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44682 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44683 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44684 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44685 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44686 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44687 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44688 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44689 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44690 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44691 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44692 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44693 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44694 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44695 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44696 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44697 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44698 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44699 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44700 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44701 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44702 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44703 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44704 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44705 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44706 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44707 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44708 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44709 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44710 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44711 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44712 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44713 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44714 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44715 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44716 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44717 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44718 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44719 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44720 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44721 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44722 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44723 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44724 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44725 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44726 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44727 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44728 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44729 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44730 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44731 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44732 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44733 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44734 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44735 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44736 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44737 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44738 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44739 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44740 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44741 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44742 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44743 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44744 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44745 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44746 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44747 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44748 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44749 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44750 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44751 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44752 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44753 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44754 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44755 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44756 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44757 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44758 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44759 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44760 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44761 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44762 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44763 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44764 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44765 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44766 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44767 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44768 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44769 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44770 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44771 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44772 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44773 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44774 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44775 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44776 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44777 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44778 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44779 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44780 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44781 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44782 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44783 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44784 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44785 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44786 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44787 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44788 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44789 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44790 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44791 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44792 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44793 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44794 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44795 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44796 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44797 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44798 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44799 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44800 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44801 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44802 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44803 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44804 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44805 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44806 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44807 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44808 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44809 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44810 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44811 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44812 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44813 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44814 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44815 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44816 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44817 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44818 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44819 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44820 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44821 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44822 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44823 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44824 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44825 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44826 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44827 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44828 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44829 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44830 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44831 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44832 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44833 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44834 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44835 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44836 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44837 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44838 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44839 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44840 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44841 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44842 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44843 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44844 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44845 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44846 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44847 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44848 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44849 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44850 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44851 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44852 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44853 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44854 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44855 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44856 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44857 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44858 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44859 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44860 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44861 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44862 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44863 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44864 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44865 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44866 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44867 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44868 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44869 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44870 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44871 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44872 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44873 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44874 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44875 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44876 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44877 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44878 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44879 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44880 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44881 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44882 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44883 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44884 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44885 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44886 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44887 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44888 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44889 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44890 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44891 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44892 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44893 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44894 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44895 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44896 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44897 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44898 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44899 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44900 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44901 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44902 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44903 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44904 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44905 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44906 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44907 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44908 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44909 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44910 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44911 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44912 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44913 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44914 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44915 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44916 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44917 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44918 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44919 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44920 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44921 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44922 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44923 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44924 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44925 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44926 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44927 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44928 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44929 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44930 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44931 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44932 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44933 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44934 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44935 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44936 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44937 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44938 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44939 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44940 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44941 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44942 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44943 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44944 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44945 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44946 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44947 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44948 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44949 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44950 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44951 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44952 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44953 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44954 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44955 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44956 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44957 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44958 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44959 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44960 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44961 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44962 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44963 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44964 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44965 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44966 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44967 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44968 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44969 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44970 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44971 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44972 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44973 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44974 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44975 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44976 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44977 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44978 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44979 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44980 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44981 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44982 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44983 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44984 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44985 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44986 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44987 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44988 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44989 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44990 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44991 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44992 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44993 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44994 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44995 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44996 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44997 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44998 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT44999 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45000 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45001 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45002 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45003 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45004 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45005 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45006 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45007 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45008 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45009 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45010 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45011 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45012 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45013 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45014 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45015 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45016 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45017 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45018 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45019 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45020 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45021 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45022 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45023 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45024 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45025 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45026 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45027 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45028 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45029 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45030 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45031 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45032 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45033 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45034 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45035 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45036 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45037 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45038 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45039 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45040 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45041 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45042 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45043 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45044 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45045 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45046 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45047 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45048 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45049 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45050 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45051 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45052 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45053 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45054 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45055 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45056 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45057 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45058 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45059 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45060 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45061 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45062 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45063 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45064 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45065 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45066 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45067 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45068 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45069 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45070 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45071 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45072 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45073 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45074 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45075 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45076 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45077 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45078 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45079 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45080 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45081 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45082 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45083 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45084 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45085 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45086 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45087 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45088 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45089 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45090 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45091 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45092 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45093 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45094 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45095 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45096 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45097 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45098 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45099 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45100 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45101 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45102 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45103 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45104 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45105 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45106 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45107 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45108 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45109 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45110 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45111 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45112 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45113 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45114 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45115 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45116 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45117 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45118 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45119 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45120 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45121 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45122 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45123 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45124 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45125 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45126 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45127 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45128 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45129 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45130 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45131 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45132 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45133 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45134 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45135 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45136 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45137 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45138 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45139 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45140 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45141 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45142 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45143 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45144 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45145 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45146 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45147 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45148 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45149 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45150 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45151 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45152 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45153 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45154 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45155 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45156 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45157 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45158 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45159 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45160 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45161 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45162 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45163 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45164 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45165 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45166 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45167 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45168 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45169 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45170 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45171 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45172 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45173 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45174 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45175 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45176 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45177 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45178 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45179 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45180 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45181 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45182 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45183 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45184 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45185 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45186 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45187 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45188 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45189 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45190 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45191 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45192 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45193 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45194 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45195 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45196 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45197 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45198 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45199 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45200 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45201 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45202 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45203 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45204 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45205 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45206 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45207 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45208 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45209 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45210 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45211 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45212 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45213 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45214 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45215 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45216 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45217 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45218 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45219 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45220 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45221 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45222 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45223 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45224 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45225 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45226 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45227 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45228 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45229 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45230 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45231 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45232 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45233 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45234 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45235 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45236 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45237 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45238 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45239 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45240 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45241 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45242 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45243 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45244 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45245 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45246 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45247 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45248 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45249 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45250 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45251 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45252 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45253 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45254 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45255 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45256 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45257 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45258 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45259 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45260 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45261 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45262 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45263 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45264 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45265 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45266 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45267 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45268 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45269 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45270 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45271 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45272 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45273 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45274 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45275 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45276 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45277 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45278 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45279 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45280 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45281 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45282 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45283 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45284 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45285 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45286 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45287 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45288 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45289 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45290 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45291 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45292 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45293 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45294 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45295 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45296 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45297 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45298 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45299 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45300 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45301 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45302 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45303 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45304 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45305 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45306 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45307 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45308 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45309 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45310 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45311 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45312 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45313 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45314 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45315 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45316 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45317 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45318 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45319 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45320 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45321 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45322 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45323 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45324 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45325 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45326 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45327 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45328 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45329 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45330 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45331 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45332 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45333 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45334 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45335 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45336 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45337 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45338 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45339 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45340 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45341 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45342 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45343 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45344 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45345 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45346 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45347 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45348 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45349 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45350 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45351 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45352 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45353 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45354 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45355 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45356 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45357 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45358 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45359 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45360 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45361 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45362 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45363 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45364 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45365 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45366 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45367 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45368 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45369 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45370 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45371 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45372 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45373 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45374 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45375 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45376 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45377 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45378 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45379 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45380 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45381 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45382 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45383 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45384 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45385 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45386 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45387 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45388 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45389 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45390 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45391 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45392 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45393 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45394 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45395 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45396 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45397 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45398 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45399 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45400 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45401 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45402 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45403 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45404 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45405 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45406 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45407 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45408 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45409 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45410 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45411 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45412 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45413 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45414 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45415 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45416 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45417 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45418 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45419 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45420 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45421 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45422 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45423 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45424 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45425 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45426 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45427 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45428 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45429 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45430 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45431 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45432 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45433 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45434 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45435 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45436 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45437 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45438 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45439 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45440 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45441 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45442 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45443 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45444 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45445 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45446 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45447 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45448 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45449 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45450 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45451 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45452 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45453 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45454 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45455 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45456 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45457 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45458 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45459 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45460 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45461 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45462 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45463 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45464 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45465 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45466 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45467 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45468 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45469 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45470 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45471 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45472 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45473 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45474 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45475 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45476 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45477 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45478 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45479 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45480 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45481 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45482 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45483 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45484 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45485 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45486 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45487 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45488 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45489 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45490 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45491 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45492 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45493 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45494 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45495 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45496 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45497 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45498 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45499 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45500 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45501 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45502 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45503 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45504 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45505 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45506 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45507 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45508 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45509 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45510 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45511 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45512 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45513 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45514 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45515 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45516 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45517 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45518 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45519 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45520 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45521 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45522 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45523 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45524 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45525 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45526 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45527 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45528 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45529 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45530 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45531 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45532 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45533 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45534 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45535 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45536 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45537 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45538 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45539 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45540 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45541 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45542 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45543 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45544 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45545 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45546 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45547 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45548 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45549 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45550 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45551 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45552 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45553 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45554 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45555 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45556 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45557 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45558 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45559 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45560 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45561 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45562 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45563 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45564 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45565 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45566 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45567 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45568 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45569 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45570 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45571 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45572 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45573 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45574 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45575 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45576 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45577 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45578 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45579 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45580 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45581 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45582 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45583 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45584 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45585 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45586 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45587 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45588 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45589 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45590 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45591 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45592 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45593 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45594 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45595 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45596 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45597 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45598 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45599 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45600 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45601 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45602 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45603 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45604 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45605 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45606 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45607 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45608 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45609 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45610 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45611 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45612 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45613 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45614 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45615 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45616 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45617 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45618 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45619 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45620 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45621 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45622 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45623 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45624 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45625 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45626 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45627 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45628 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45629 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45630 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45631 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45632 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45633 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45634 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45635 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45636 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45637 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45638 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45639 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45640 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45641 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45642 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45643 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45644 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45645 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45646 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45647 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45648 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45649 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45650 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45651 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45652 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45653 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45654 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45655 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45656 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45657 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45658 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45659 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45660 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45661 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45662 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45663 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45664 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45665 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45666 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45667 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45668 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45669 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45670 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45671 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45672 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45673 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45674 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45675 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45676 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45677 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45678 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45679 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45680 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45681 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45682 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45683 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45684 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45685 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45686 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45687 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45688 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45689 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45690 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45691 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45692 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45693 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45694 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45695 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45696 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45697 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45698 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45699 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45700 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45701 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45702 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45703 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45704 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45705 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45706 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45707 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45708 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45709 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45710 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45711 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45712 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45713 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45714 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45715 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45716 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45717 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45718 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45719 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45720 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45721 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45722 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45723 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45724 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45725 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45726 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45727 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45728 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45729 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45730 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45731 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45732 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45733 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45734 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45735 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45736 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45737 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45738 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45739 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45740 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45741 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45742 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45743 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45744 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45745 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45746 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45747 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45748 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45749 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45750 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45751 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45752 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45753 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45754 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45755 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45756 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45757 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45758 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45759 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45760 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45761 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45762 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45763 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45764 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45765 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45766 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45767 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45768 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45769 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45770 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45771 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45772 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45773 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45774 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45775 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45776 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45777 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45778 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45779 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45780 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45781 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45782 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45783 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45784 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45785 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45786 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45787 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45788 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45789 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45790 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45791 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45792 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45793 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45794 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45795 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45796 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45797 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45798 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45799 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45800 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45801 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45802 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45803 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45804 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45805 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45806 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45807 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45808 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45809 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45810 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45811 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45812 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45813 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45814 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45815 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45816 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45817 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45818 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45819 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45820 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45821 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45822 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45823 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45824 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45825 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45826 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45827 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45828 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45829 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45830 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45831 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45832 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45833 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45834 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45835 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45836 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45837 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45838 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45839 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45840 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45841 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45842 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45843 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45844 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45845 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45846 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45847 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45848 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45849 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45850 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45851 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45852 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45853 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45854 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45855 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45856 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45857 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45858 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45859 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45860 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45861 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45862 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45863 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45864 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45865 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45866 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45867 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45868 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45869 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45870 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45871 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45872 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45873 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45874 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45875 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45876 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45877 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45878 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45879 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45880 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45881 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45882 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45883 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45884 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45885 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45886 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45887 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45888 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45889 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45890 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45891 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45892 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45893 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45894 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45895 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45896 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45897 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45898 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45899 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45900 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45901 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45902 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45903 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45904 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45905 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45906 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45907 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45908 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45909 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45910 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45911 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45912 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45913 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45914 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45915 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45916 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45917 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45918 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45919 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45920 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45921 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45922 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45923 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45924 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45925 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45926 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45927 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45928 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45929 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45930 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45931 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45932 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45933 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45934 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45935 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45936 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45937 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45938 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45939 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45940 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45941 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45942 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45943 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45944 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45945 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45946 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45947 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45948 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45949 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45950 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45951 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45952 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45953 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45954 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45955 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45956 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45957 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45958 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45959 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45960 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45961 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45962 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45963 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45964 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45965 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45966 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45967 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45968 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45969 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45970 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45971 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45972 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45973 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45974 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45975 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45976 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45977 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45978 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45979 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45980 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45981 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45982 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45983 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45984 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45985 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45986 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45987 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45988 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45989 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45990 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45991 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45992 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45993 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45994 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45995 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45996 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45997 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45998 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT45999 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46000 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46001 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46002 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46003 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46004 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46005 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46006 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46007 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46008 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46009 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46010 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46011 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46012 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46013 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46014 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46015 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46016 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46017 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46018 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46019 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46020 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46021 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46022 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46023 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46024 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46025 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46026 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46027 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46028 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46029 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46030 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46031 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46032 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46033 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46034 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46035 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46036 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46037 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46038 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46039 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46040 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46041 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46042 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46043 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46044 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46045 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46046 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46047 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46048 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46049 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46050 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46051 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46052 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46053 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46054 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46055 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46056 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46057 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46058 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46059 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46060 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46061 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46062 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46063 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46064 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46065 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46066 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46067 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46068 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46069 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46070 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46071 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46072 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46073 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46074 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46075 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46076 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46077 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46078 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46079 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46080 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46081 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46082 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46083 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46084 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46085 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46086 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46087 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46088 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46089 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46090 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46091 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46092 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46093 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46094 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46095 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46096 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46097 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46098 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46099 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46100 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46101 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46102 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46103 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46104 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46105 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46106 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46107 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46108 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46109 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46110 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46111 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46112 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46113 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46114 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46115 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46116 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46117 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46118 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46119 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46120 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46121 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46122 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46123 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46124 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46125 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46126 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46127 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46128 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46129 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46130 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46131 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46132 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46133 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46134 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46135 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46136 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46137 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46138 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46139 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46140 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46141 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46142 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46143 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46144 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46145 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46146 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46147 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46148 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46149 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46150 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46151 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46152 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46153 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46154 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46155 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46156 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46157 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46158 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46159 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46160 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46161 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46162 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46163 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46164 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46165 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46166 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46167 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46168 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46169 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46170 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46171 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46172 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46173 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46174 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46175 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46176 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46177 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46178 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46179 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46180 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46181 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46182 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46183 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46184 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46185 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46186 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46187 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46188 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46189 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46190 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46191 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46192 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46193 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46194 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46195 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46196 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46197 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46198 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46199 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46200 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46201 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46202 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46203 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46204 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46205 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46206 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46207 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46208 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46209 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46210 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46211 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46212 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46213 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46214 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46215 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46216 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46217 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46218 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46219 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46220 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46221 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46222 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46223 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46224 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46225 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46226 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46227 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46228 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46229 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46230 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46231 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46232 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46233 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46234 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46235 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46236 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46237 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46238 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46239 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46240 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46241 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46242 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46243 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46244 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46245 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46246 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46247 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46248 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46249 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46250 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46251 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46252 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46253 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46254 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46255 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46256 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46257 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46258 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46259 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46260 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46261 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46262 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46263 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46264 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46265 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46266 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46267 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46268 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46269 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46270 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46271 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46272 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46273 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46274 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46275 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46276 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46277 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46278 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46279 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46280 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46281 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46282 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46283 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46284 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46285 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46286 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46287 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46288 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46289 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46290 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46291 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46292 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46293 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46294 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46295 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46296 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46297 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46298 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46299 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46300 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46301 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46302 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46303 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46304 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46305 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46306 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46307 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46308 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46309 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46310 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46311 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46312 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46313 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46314 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46315 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46316 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46317 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46318 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46319 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46320 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46321 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46322 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46323 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46324 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46325 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46326 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46327 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46328 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46329 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46330 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46331 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46332 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46333 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46334 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46335 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46336 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46337 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46338 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46339 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46340 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46341 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46342 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46343 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46344 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46345 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46346 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46347 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46348 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46349 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46350 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46351 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46352 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46353 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46354 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46355 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46356 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46357 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46358 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46359 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46360 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46361 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46362 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46363 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46364 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46365 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46366 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46367 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46368 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46369 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46370 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46371 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46372 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46373 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46374 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46375 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46376 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46377 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46378 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46379 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46380 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46381 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46382 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46383 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46384 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46385 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46386 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46387 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46388 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46389 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46390 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46391 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46392 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46393 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46394 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46395 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46396 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46397 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46398 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46399 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46400 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46401 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46402 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46403 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46404 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46405 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46406 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46407 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46408 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46409 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46410 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46411 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46412 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46413 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46414 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46415 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46416 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46417 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46418 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46419 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46420 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46421 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46422 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46423 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46424 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46425 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46426 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46427 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46428 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46429 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46430 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46431 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46432 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46433 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46434 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46435 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46436 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46437 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46438 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46439 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46440 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46441 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46442 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46443 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46444 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46445 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46446 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46447 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46448 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46449 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46450 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46451 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46452 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46453 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46454 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46455 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46456 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46457 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46458 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46459 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46460 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46461 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46462 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46463 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46464 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46465 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46466 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46467 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46468 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46469 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46470 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46471 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46472 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46473 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46474 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46475 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46476 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46477 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46478 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46479 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46480 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46481 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46482 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46483 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46484 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46485 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46486 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46487 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46488 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46489 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46490 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46491 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46492 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46493 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46494 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46495 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46496 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46497 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46498 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46499 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46500 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46501 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46502 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46503 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46504 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46505 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46506 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46507 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46508 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46509 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46510 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46511 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46512 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46513 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46514 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46515 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46516 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46517 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46518 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46519 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46520 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46521 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46522 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46523 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46524 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46525 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46526 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46527 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46528 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46529 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46530 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46531 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46532 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46533 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46534 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46535 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46536 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46537 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46538 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46539 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46540 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46541 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46542 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46543 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46544 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46545 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46546 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46547 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46548 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46549 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46550 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46551 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46552 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46553 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46554 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46555 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46556 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46557 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46558 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46559 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46560 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46561 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46562 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46563 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46564 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46565 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46566 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46567 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46568 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46569 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46570 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46571 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46572 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46573 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46574 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46575 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46576 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46577 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46578 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46579 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46580 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46581 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46582 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46583 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46584 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46585 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46586 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46587 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46588 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46589 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46590 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46591 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46592 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46593 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46594 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46595 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46596 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46597 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46598 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46599 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46600 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46601 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46602 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46603 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46604 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46605 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46606 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46607 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46608 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46609 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46610 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46611 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46612 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46613 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46614 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46615 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46616 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46617 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46618 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46619 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46620 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46621 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46622 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46623 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46624 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46625 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46626 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46627 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46628 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46629 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46630 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46631 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46632 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46633 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46634 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46635 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46636 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46637 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46638 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46639 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46640 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46641 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46642 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46643 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46644 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46645 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46646 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46647 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46648 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46649 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46650 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46651 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46652 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46653 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46654 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46655 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46656 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46657 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46658 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46659 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46660 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46661 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46662 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46663 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46664 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46665 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46666 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46667 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46668 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46669 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46670 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46671 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46672 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46673 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46674 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46675 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46676 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46677 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46678 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46679 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46680 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46681 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46682 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46683 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46684 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46685 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46686 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46687 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46688 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46689 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46690 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46691 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46692 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46693 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46694 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46695 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46696 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46697 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46698 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46699 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46700 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46701 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46702 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46703 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46704 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46705 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46706 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46707 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46708 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46709 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46710 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46711 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46712 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46713 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46714 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46715 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46716 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46717 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46718 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46719 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46720 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46721 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46722 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46723 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46724 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46725 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46726 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46727 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46728 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46729 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46730 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46731 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46732 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46733 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46734 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46735 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46736 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46737 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46738 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46739 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46740 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46741 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46742 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46743 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46744 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46745 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46746 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46747 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46748 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46749 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46750 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46751 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46752 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46753 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46754 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46755 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46756 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46757 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46758 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46759 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46760 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46761 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46762 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46763 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46764 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46765 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46766 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46767 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46768 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46769 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46770 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46771 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46772 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46773 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46774 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46775 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46776 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46777 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46778 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46779 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46780 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46781 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46782 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46783 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46784 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46785 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46786 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46787 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46788 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46789 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46790 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46791 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46792 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46793 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46794 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46795 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46796 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46797 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46798 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46799 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46800 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46801 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46802 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46803 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46804 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46805 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46806 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46807 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46808 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46809 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46810 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46811 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46812 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46813 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46814 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46815 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46816 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46817 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46818 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46819 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46820 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46821 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46822 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46823 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46824 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46825 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46826 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46827 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46828 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46829 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46830 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46831 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46832 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46833 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46834 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46835 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46836 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46837 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46838 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46839 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46840 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46841 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46842 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46843 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46844 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46845 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46846 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46847 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46848 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46849 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46850 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46851 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46852 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46853 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46854 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46855 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46856 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46857 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46858 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46859 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46860 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46861 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46862 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46863 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46864 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46865 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46866 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46867 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46868 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46869 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46870 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46871 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46872 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46873 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46874 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46875 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46876 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46877 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46878 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46879 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46880 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46881 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46882 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46883 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46884 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46885 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46886 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46887 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46888 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46889 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46890 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46891 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46892 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46893 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46894 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46895 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46896 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46897 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46898 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46899 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46900 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46901 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46902 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46903 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46904 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46905 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46906 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46907 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46908 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46909 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46910 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46911 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46912 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46913 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46914 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46915 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46916 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46917 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46918 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46919 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46920 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46921 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46922 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46923 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46924 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46925 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46926 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46927 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46928 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46929 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46930 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46931 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46932 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46933 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46934 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46935 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46936 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46937 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46938 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46939 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46940 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46941 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46942 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46943 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46944 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46945 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46946 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46947 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46948 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46949 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46950 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46951 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46952 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46953 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46954 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46955 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46956 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46957 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46958 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46959 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46960 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46961 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46962 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46963 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46964 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46965 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46966 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46967 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46968 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46969 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46970 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46971 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46972 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46973 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46974 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46975 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46976 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46977 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46978 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46979 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46980 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46981 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46982 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46983 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46984 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46985 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46986 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46987 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46988 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46989 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46990 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46991 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46992 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46993 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46994 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46995 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46996 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46997 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46998 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT46999 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47000 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47001 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47002 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47003 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47004 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47005 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47006 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47007 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47008 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47009 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47010 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47011 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47012 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47013 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47014 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47015 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47016 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47017 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47018 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47019 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47020 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47021 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47022 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47023 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47024 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47025 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47026 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47027 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47028 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47029 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47030 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47031 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47032 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47033 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47034 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47035 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47036 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47037 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47038 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47039 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47040 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47041 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47042 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47043 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47044 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47045 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47046 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47047 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47048 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47049 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47050 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47051 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47052 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47053 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47054 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47055 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47056 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47057 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47058 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47059 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47060 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47061 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47062 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47063 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47064 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47065 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47066 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47067 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47068 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47069 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47070 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47071 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47072 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47073 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47074 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47075 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47076 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47077 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47078 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47079 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47080 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47081 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47082 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47083 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47084 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47085 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47086 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47087 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47088 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47089 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47090 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47091 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47092 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47093 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47094 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47095 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47096 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47097 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47098 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47099 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47100 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47101 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47102 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47103 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47104 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47105 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47106 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47107 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47108 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47109 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47110 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47111 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47112 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47113 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47114 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47115 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47116 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47117 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47118 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47119 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47120 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47121 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47122 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47123 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47124 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47125 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47126 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47127 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47128 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47129 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47130 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47131 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47132 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47133 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47134 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47135 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47136 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47137 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47138 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47139 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47140 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47141 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47142 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47143 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47144 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47145 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47146 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47147 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47148 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47149 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47150 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47151 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47152 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47153 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47154 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47155 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47156 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47157 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47158 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47159 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47160 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47161 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47162 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47163 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47164 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47165 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47166 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47167 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47168 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47169 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47170 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47171 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47172 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47173 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47174 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47175 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47176 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47177 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47178 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47179 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47180 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47181 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47182 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47183 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47184 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47185 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47186 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47187 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47188 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47189 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47190 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47191 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47192 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47193 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47194 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47195 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47196 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47197 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47198 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47199 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47200 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47201 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47202 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47203 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47204 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47205 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47206 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47207 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47208 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47209 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47210 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47211 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47212 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47213 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47214 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47215 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47216 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47217 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47218 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47219 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47220 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47221 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47222 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47223 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47224 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47225 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47226 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47227 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47228 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47229 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47230 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47231 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47232 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47233 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47234 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47235 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47236 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47237 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47238 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47239 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47240 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47241 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47242 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47243 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47244 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47245 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47246 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47247 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47248 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47249 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47250 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47251 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47252 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47253 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47254 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47255 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47256 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47257 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47258 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47259 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47260 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47261 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47262 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47263 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47264 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47265 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47266 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47267 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47268 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47269 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47270 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47271 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47272 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47273 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47274 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47275 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47276 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47277 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47278 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47279 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47280 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47281 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47282 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47283 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47284 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47285 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47286 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47287 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47288 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47289 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47290 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47291 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47292 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47293 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47294 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47295 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47296 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47297 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47298 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47299 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47300 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47301 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47302 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47303 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47304 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47305 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47306 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47307 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47308 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47309 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47310 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47311 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47312 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47313 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47314 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47315 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47316 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47317 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47318 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47319 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47320 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47321 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47322 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47323 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47324 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47325 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47326 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47327 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47328 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47329 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47330 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47331 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47332 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47333 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47334 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47335 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47336 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47337 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47338 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47339 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47340 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47341 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47342 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47343 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47344 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47345 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47346 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47347 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47348 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47349 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47350 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47351 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47352 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47353 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47354 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47355 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47356 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47357 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47358 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47359 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47360 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47361 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47362 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47363 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47364 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47365 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47366 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47367 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47368 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47369 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47370 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47371 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47372 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47373 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47374 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47375 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47376 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47377 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47378 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47379 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47380 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47381 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47382 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47383 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47384 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47385 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47386 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47387 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47388 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47389 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47390 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47391 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47392 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47393 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47394 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47395 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47396 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47397 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47398 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47399 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47400 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47401 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47402 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47403 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47404 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47405 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47406 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47407 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47408 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47409 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47410 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47411 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47412 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47413 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47414 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47415 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47416 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47417 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47418 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47419 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47420 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47421 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47422 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47423 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47424 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47425 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47426 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47427 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47428 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47429 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47430 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47431 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47432 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47433 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47434 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47435 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47436 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47437 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47438 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47439 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47440 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47441 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47442 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47443 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47444 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47445 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47446 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47447 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47448 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47449 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47450 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47451 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47452 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47453 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47454 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47455 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47456 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47457 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47458 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47459 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47460 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47461 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47462 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47463 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47464 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47465 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47466 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47467 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47468 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47469 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47470 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47471 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47472 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47473 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47474 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47475 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47476 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47477 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47478 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47479 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47480 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47481 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47482 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47483 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47484 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47485 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47486 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47487 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47488 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47489 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47490 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47491 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47492 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47493 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47494 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47495 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47496 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47497 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47498 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47499 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47500 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47501 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47502 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47503 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47504 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47505 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47506 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47507 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47508 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47509 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47510 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47511 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47512 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47513 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47514 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47515 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47516 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47517 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47518 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47519 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47520 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47521 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47522 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47523 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47524 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47525 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47526 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47527 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47528 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47529 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47530 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47531 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47532 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47533 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47534 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_LUT47535 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7536 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7537 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7538 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7539 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7540 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7541 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7542 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7543 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7544 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7545 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7546 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7547 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7548 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7549 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7550 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7551 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7552 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7553 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7554 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7555 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7556 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7557 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7558 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7559 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7560 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7561 +// module not written out since it is a black box. +// + + +// +// Verific Verilog Description of module EFX_ADD7562 +// module not written out since it is a black box. +// + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/outflow/Ti60_Demo.pt.sdc b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/outflow/Ti60_Demo.pt.sdc new file mode 100644 index 0000000000000000000000000000000000000000..9550722215b4582ac2af70a313f10e6323c7c913 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/outflow/Ti60_Demo.pt.sdc @@ -0,0 +1,362 @@ + +# Auto-generated by Interface Designer +# +# WARNING: Any manual changes made to this file will be lost when generating constraints. + +# Efinity Interface Designer SDC +# Version: 2023.2.307.5.10 +# Date: 2024-11-28 16:28 + +# Copyright (C) 2013 - 2023 Efinix Inc. All rights reserved. + +# Device: Ti60F225 +# Project: Ti60_Demo +# Timing Model: C4 (final) + +# PLL Constraints +################# +create_clock -period 1.9685 tdqss_clk +create_clock -period 3.9370 core_clk +create_clock -period 1.9685 tac_clk +create_clock -waveform {0.4921 1.4764} -period 1.9685 twd_clk +create_clock -period 41.6667 ddr_pll_CLKOUT4 +create_clock -period 40.0000 clk_sys +create_clock -period 6.6667 clk_pixel_2x +create_clock -period 6.6667 clk_pixel +create_clock -waveform {0.3333 1.0000} -period 1.3333 clk_pixel_10x +create_clock -period 10.4167 clk_96m +create_clock -period 166.6667 clk_6m +create_clock -period 13.3929 clk_75m +create_clock -period 10.4167 clk_100m + +# GPIO Constraints +#################### +# set_input_delay -clock [-reference_pin ] -max [get_ports {fpga_rxd_1}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {fpga_rxd_1}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {fpga_txd_1}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {fpga_txd_1}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {led_o[0]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {led_o[0]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {led_o[1]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {led_o[1]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {led_o[2]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {led_o[2]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {led_o[3]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {led_o[3]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {led_o[4]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {led_o[4]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {led_o[5]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {led_o[5]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {led_o[6]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {led_o[6]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {led_o[7]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {led_o[7]}] + +# HSIO GPIO Constraints +######################### +# set_input_delay -clock [-reference_pin ] -max [get_ports {fpga_rxd_0}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {fpga_rxd_0}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[0]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[0]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[1]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[1]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[2]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[2]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[3]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[3]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[4]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[4]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[5]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[5]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[6]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[6]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[7]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[7]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[8]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[8]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[9]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[9]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[10]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[10]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[11]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[11]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[12]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[12]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[13]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[13]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[14]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[14]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[15]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[15]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[16]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[16]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[17]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[17]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[18]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[18]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[19]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[19]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[20]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[20]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[21]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[21]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[22]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[22]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_data_i[23]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_data_i[23]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_de_i}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_de_i}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_hs_i}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_hs_i}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_pclk_i}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_pclk_i}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_vs_i}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_vs_i}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~95}] -max 0.263 [get_ports {addr[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~95}] -min -0.140 [get_ports {addr[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~36}] -max 0.263 [get_ports {addr[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~36}] -min -0.140 [get_ports {addr[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~70}] -max 0.263 [get_ports {addr[2]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~70}] -min -0.140 [get_ports {addr[2]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~50~1}] -max 0.263 [get_ports {addr[3]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~50~1}] -min -0.140 [get_ports {addr[3]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~25}] -max 0.263 [get_ports {addr[4]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~25}] -min -0.140 [get_ports {addr[4]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~142~1}] -max 0.263 [get_ports {addr[5]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~142~1}] -min -0.140 [get_ports {addr[5]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~59}] -max 0.263 [get_ports {addr[6]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~59}] -min -0.140 [get_ports {addr[6]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~110}] -max 0.263 [get_ports {addr[7]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~110}] -min -0.140 [get_ports {addr[7]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~26}] -max 0.263 [get_ports {addr[8]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~26}] -min -0.140 [get_ports {addr[8]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~127}] -max 0.263 [get_ports {addr[9]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~127}] -min -0.140 [get_ports {addr[9]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~138}] -max 0.263 [get_ports {addr[10]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~138}] -min -0.140 [get_ports {addr[10]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~60}] -max 0.263 [get_ports {addr[11]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~60}] -min -0.140 [get_ports {addr[11]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~35}] -max 0.263 [get_ports {addr[12]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~35}] -min -0.140 [get_ports {addr[12]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~71}] -max 0.263 [get_ports {addr[13]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~71}] -min -0.140 [get_ports {addr[13]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~109}] -max 0.263 [get_ports {addr[14]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~109}] -min -0.140 [get_ports {addr[14]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~143~1}] -max 0.263 [get_ports {addr[15]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~143~1}] -min -0.140 [get_ports {addr[15]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {adv7611_rstn}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {adv7611_rstn}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~74~1}] -max 0.263 [get_ports {ba[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~74~1}] -min -0.140 [get_ports {ba[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~132~1}] -max 0.263 [get_ports {ba[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~132~1}] -min -0.140 [get_ports {ba[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~126}] -max 0.263 [get_ports {ba[2]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~126}] -min -0.140 [get_ports {ba[2]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~49}] -max 0.263 [get_ports {cas}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~49}] -min -0.140 [get_ports {cas}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~123~1}] -max 0.263 [get_ports {cke}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~123~1}] -min -0.140 [get_ports {cke}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~150}] -max 0.263 [get_ports {clk_n_lo clk_n_hi}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~150}] -min -0.140 [get_ports {clk_n_lo clk_n_hi}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~149}] -max 0.263 [get_ports {clk_p_lo clk_p_hi}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~149}] -min -0.140 [get_ports {clk_p_lo clk_p_hi}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~95~1}] -max 0.263 [get_ports {cs}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~95~1}] -min -0.140 [get_ports {cs}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~131~1}] -max 0.263 [get_ports {o_dm_lo[0] o_dm_hi[0]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~131~1}] -min -0.140 [get_ports {o_dm_lo[0] o_dm_hi[0]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~83~1}] -max 0.263 [get_ports {o_dm_lo[1] o_dm_hi[1]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~83~1}] -min -0.140 [get_ports {o_dm_lo[1] o_dm_hi[1]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {fpga_txd_0}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {fpga_txd_0}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {hdmi_scl_io}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {hdmi_scl_io}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~73~1}] -max 0.263 [get_ports {odt}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~73~1}] -min -0.140 [get_ports {odt}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~48}] -max 0.263 [get_ports {ras}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~48}] -min -0.140 [get_ports {ras}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~139}] -max 0.263 [get_ports {reset}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~139}] -min -0.140 [get_ports {reset}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~94}] -max 0.263 [get_ports {we}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~94}] -min -0.140 [get_ports {we}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~148~1}] -max 0.414 [get_ports {i_dq_lo[0] i_dq_hi[0]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~148~1}] -min 0.276 [get_ports {i_dq_lo[0] i_dq_hi[0]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~150~1}] -max 0.263 [get_ports {o_dq_lo[0] o_dq_hi[0]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~150~1}] -min -0.140 [get_ports {o_dq_lo[0] o_dq_hi[0]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~150~1}] -max 0.263 [get_ports {o_dq_oe[0]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~150~1}] -min -0.140 [get_ports {o_dq_oe[0]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~157~1}] -max 0.414 [get_ports {i_dq_lo[1] i_dq_hi[1]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~157~1}] -min 0.276 [get_ports {i_dq_lo[1] i_dq_hi[1]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~159~1}] -max 0.263 [get_ports {o_dq_lo[1] o_dq_hi[1]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~159~1}] -min -0.140 [get_ports {o_dq_lo[1] o_dq_hi[1]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~159~1}] -max 0.263 [get_ports {o_dq_oe[1]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~159~1}] -min -0.140 [get_ports {o_dq_oe[1]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~164~1}] -max 0.414 [get_ports {i_dq_lo[2] i_dq_hi[2]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~164~1}] -min 0.276 [get_ports {i_dq_lo[2] i_dq_hi[2]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~166~1}] -max 0.263 [get_ports {o_dq_lo[2] o_dq_hi[2]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~166~1}] -min -0.140 [get_ports {o_dq_lo[2] o_dq_hi[2]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~166~1}] -max 0.263 [get_ports {o_dq_oe[2]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~166~1}] -min -0.140 [get_ports {o_dq_oe[2]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~149~1}] -max 0.414 [get_ports {i_dq_lo[3] i_dq_hi[3]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~149~1}] -min 0.276 [get_ports {i_dq_lo[3] i_dq_hi[3]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~151~1}] -max 0.263 [get_ports {o_dq_lo[3] o_dq_hi[3]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~151~1}] -min -0.140 [get_ports {o_dq_lo[3] o_dq_hi[3]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~151~1}] -max 0.263 [get_ports {o_dq_oe[3]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~151~1}] -min -0.140 [get_ports {o_dq_oe[3]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~189~1}] -max 0.414 [get_ports {i_dq_lo[4] i_dq_hi[4]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~189~1}] -min 0.276 [get_ports {i_dq_lo[4] i_dq_hi[4]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~191~1}] -max 0.263 [get_ports {o_dq_lo[4] o_dq_hi[4]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~191~1}] -min -0.140 [get_ports {o_dq_lo[4] o_dq_hi[4]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~191~1}] -max 0.263 [get_ports {o_dq_oe[4]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~191~1}] -min -0.140 [get_ports {o_dq_oe[4]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~156~1}] -max 0.414 [get_ports {i_dq_lo[5] i_dq_hi[5]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~156~1}] -min 0.276 [get_ports {i_dq_lo[5] i_dq_hi[5]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~158~1}] -max 0.263 [get_ports {o_dq_lo[5] o_dq_hi[5]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~158~1}] -min -0.140 [get_ports {o_dq_lo[5] o_dq_hi[5]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~158~1}] -max 0.263 [get_ports {o_dq_oe[5]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~158~1}] -min -0.140 [get_ports {o_dq_oe[5]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~165~1}] -max 0.414 [get_ports {i_dq_lo[6] i_dq_hi[6]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~165~1}] -min 0.276 [get_ports {i_dq_lo[6] i_dq_hi[6]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~167~1}] -max 0.263 [get_ports {o_dq_lo[6] o_dq_hi[6]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~167~1}] -min -0.140 [get_ports {o_dq_lo[6] o_dq_hi[6]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~167~1}] -max 0.263 [get_ports {o_dq_oe[6]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~167~1}] -min -0.140 [get_ports {o_dq_oe[6]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~188~1}] -max 0.414 [get_ports {i_dq_lo[7] i_dq_hi[7]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~188~1}] -min 0.276 [get_ports {i_dq_lo[7] i_dq_hi[7]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~190~1}] -max 0.263 [get_ports {o_dq_lo[7] o_dq_hi[7]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~190~1}] -min -0.140 [get_ports {o_dq_lo[7] o_dq_hi[7]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~190~1}] -max 0.263 [get_ports {o_dq_oe[7]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~190~1}] -min -0.140 [get_ports {o_dq_oe[7]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~82~1}] -max 0.414 [get_ports {i_dq_lo[8] i_dq_hi[8]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~82~1}] -min 0.276 [get_ports {i_dq_lo[8] i_dq_hi[8]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~84~1}] -max 0.263 [get_ports {o_dq_lo[8] o_dq_hi[8]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~84~1}] -min -0.140 [get_ports {o_dq_lo[8] o_dq_hi[8]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~84~1}] -max 0.263 [get_ports {o_dq_oe[8]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~84~1}] -min -0.140 [get_ports {o_dq_oe[8]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~39~1}] -max 0.414 [get_ports {i_dq_lo[9] i_dq_hi[9]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~39~1}] -min 0.276 [get_ports {i_dq_lo[9] i_dq_hi[9]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~41~1}] -max 0.263 [get_ports {o_dq_lo[9] o_dq_hi[9]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~41~1}] -min -0.140 [get_ports {o_dq_lo[9] o_dq_hi[9]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~41~1}] -max 0.263 [get_ports {o_dq_oe[9]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~41~1}] -min -0.140 [get_ports {o_dq_oe[9]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~22~1}] -max 0.414 [get_ports {i_dq_lo[10] i_dq_hi[10]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~22~1}] -min 0.276 [get_ports {i_dq_lo[10] i_dq_hi[10]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~24~1}] -max 0.263 [get_ports {o_dq_lo[10] o_dq_hi[10]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~24~1}] -min -0.140 [get_ports {o_dq_lo[10] o_dq_hi[10]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~24~1}] -max 0.263 [get_ports {o_dq_oe[10]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~24~1}] -min -0.140 [get_ports {o_dq_oe[10]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~92~1}] -max 0.414 [get_ports {i_dq_lo[11] i_dq_hi[11]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~92~1}] -min 0.276 [get_ports {i_dq_lo[11] i_dq_hi[11]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~94~1}] -max 0.263 [get_ports {o_dq_lo[11] o_dq_hi[11]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~94~1}] -min -0.140 [get_ports {o_dq_lo[11] o_dq_hi[11]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~94~1}] -max 0.263 [get_ports {o_dq_oe[11]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~94~1}] -min -0.140 [get_ports {o_dq_oe[11]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~23~1}] -max 0.414 [get_ports {i_dq_lo[12] i_dq_hi[12]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~23~1}] -min 0.276 [get_ports {i_dq_lo[12] i_dq_hi[12]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~25~1}] -max 0.263 [get_ports {o_dq_lo[12] o_dq_hi[12]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~25~1}] -min -0.140 [get_ports {o_dq_lo[12] o_dq_hi[12]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~25~1}] -max 0.263 [get_ports {o_dq_oe[12]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~25~1}] -min -0.140 [get_ports {o_dq_oe[12]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~38~1}] -max 0.414 [get_ports {i_dq_lo[13] i_dq_hi[13]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~38~1}] -min 0.276 [get_ports {i_dq_lo[13] i_dq_hi[13]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~40~1}] -max 0.263 [get_ports {o_dq_lo[13] o_dq_hi[13]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~40~1}] -min -0.140 [get_ports {o_dq_lo[13] o_dq_hi[13]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~40~1}] -max 0.263 [get_ports {o_dq_oe[13]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~40~1}] -min -0.140 [get_ports {o_dq_oe[13]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~11~1}] -max 0.414 [get_ports {i_dq_lo[14] i_dq_hi[14]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~11~1}] -min 0.276 [get_ports {i_dq_lo[14] i_dq_hi[14]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~13~1}] -max 0.263 [get_ports {o_dq_lo[14] o_dq_hi[14]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~13~1}] -min -0.140 [get_ports {o_dq_lo[14] o_dq_hi[14]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~13~1}] -max 0.263 [get_ports {o_dq_oe[14]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~13~1}] -min -0.140 [get_ports {o_dq_oe[14]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~12~1}] -max 0.414 [get_ports {i_dq_lo[15] i_dq_hi[15]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~12~1}] -min 0.276 [get_ports {i_dq_lo[15] i_dq_hi[15]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~14~1}] -max 0.263 [get_ports {o_dq_lo[15] o_dq_hi[15]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~14~1}] -min -0.140 [get_ports {o_dq_lo[15] o_dq_hi[15]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~14~1}] -max 0.263 [get_ports {o_dq_oe[15]}] +set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~14~1}] -min -0.140 [get_ports {o_dq_oe[15]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~172~1}] -max 0.414 [get_ports {i_dqs_lo[0] i_dqs_hi[0]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~172~1}] -min 0.276 [get_ports {i_dqs_lo[0] i_dqs_hi[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~174~1}] -max 0.263 [get_ports {o_dqs_lo[0] o_dqs_hi[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~174~1}] -min -0.140 [get_ports {o_dqs_lo[0] o_dqs_hi[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~174~1}] -max 0.263 [get_ports {o_dqs_oe[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~174~1}] -min -0.140 [get_ports {o_dqs_oe[0]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~30~1}] -max 0.414 [get_ports {i_dqs_lo[1] i_dqs_hi[1]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~30~1}] -min 0.276 [get_ports {i_dqs_lo[1] i_dqs_hi[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~32~1}] -max 0.263 [get_ports {o_dqs_lo[1] o_dqs_hi[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~32~1}] -min -0.140 [get_ports {o_dqs_lo[1] o_dqs_hi[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~32~1}] -max 0.263 [get_ports {o_dqs_oe[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~32~1}] -min -0.140 [get_ports {o_dqs_oe[1]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~173~1}] -max 0.414 [get_ports {i_dqs_n_lo[0] i_dqs_n_hi[0]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~173~1}] -min 0.276 [get_ports {i_dqs_n_lo[0] i_dqs_n_hi[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~175~1}] -max 0.263 [get_ports {o_dqs_n_lo[0] o_dqs_n_hi[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~175~1}] -min -0.140 [get_ports {o_dqs_n_lo[0] o_dqs_n_hi[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~175~1}] -max 0.263 [get_ports {o_dqs_n_oe[0]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~175~1}] -min -0.140 [get_ports {o_dqs_n_oe[0]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~31~1}] -max 0.414 [get_ports {i_dqs_n_lo[1] i_dqs_n_hi[1]}] +set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~31~1}] -min 0.276 [get_ports {i_dqs_n_lo[1] i_dqs_n_hi[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~33~1}] -max 0.263 [get_ports {o_dqs_n_lo[1] o_dqs_n_hi[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~33~1}] -min -0.140 [get_ports {o_dqs_n_lo[1] o_dqs_n_hi[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~33~1}] -max 0.263 [get_ports {o_dqs_n_oe[1]}] +set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~33~1}] -min -0.140 [get_ports {o_dqs_n_oe[1]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {hdmi_sda_io_IN}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {hdmi_sda_io_IN}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {hdmi_sda_io_OUT}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {hdmi_sda_io_OUT}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {hdmi_sda_io_OE}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {hdmi_sda_io_OE}] + +# LVDS Tx Constraints +####################### +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -max 0.378 [get_ports {hdmi_txc_o[*]}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -min -0.140 [get_ports {hdmi_txc_o[*]}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -max 0.378 [get_ports {hdmi_txc_oe}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -min -0.140 [get_ports {hdmi_txc_oe}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -max 0.378 [get_ports {hdmi_txd0_o[*]}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -min -0.140 [get_ports {hdmi_txd0_o[*]}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -max 0.378 [get_ports {hdmi_txd0_oe}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -min -0.140 [get_ports {hdmi_txd0_oe}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -max 0.378 [get_ports {hdmi_txd1_o[*]}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -min -0.140 [get_ports {hdmi_txd1_o[*]}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -max 0.378 [get_ports {hdmi_txd1_oe}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -min -0.140 [get_ports {hdmi_txd1_oe}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -max 0.378 [get_ports {hdmi_txd2_o[*]}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -min -0.140 [get_ports {hdmi_txd2_o[*]}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -max 0.378 [get_ports {hdmi_txd2_oe}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -min -0.140 [get_ports {hdmi_txd2_oe}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -max 0.420 [get_ports {hdmi_txc_rst_o}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -min -0.175 [get_ports {hdmi_txc_rst_o}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -max 0.420 [get_ports {hdmi_txd0_rst_o}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -min -0.175 [get_ports {hdmi_txd0_rst_o}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -max 0.420 [get_ports {hdmi_txd1_rst_o}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -min -0.175 [get_ports {hdmi_txd1_rst_o}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -max 0.420 [get_ports {hdmi_txd2_rst_o}] +set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -min -0.175 [get_ports {hdmi_txd2_rst_o}] + +# Clock Latency Constraints +############################ +# set_clock_latency -source -setup [get_ports {tdqss_clk}] +# set_clock_latency -source -hold [get_ports {tdqss_clk}] +# set_clock_latency -source -setup [get_ports {core_clk}] +# set_clock_latency -source -hold [get_ports {core_clk}] +# set_clock_latency -source -setup [get_ports {tac_clk}] +# set_clock_latency -source -hold [get_ports {tac_clk}] +# set_clock_latency -source -setup [get_ports {twd_clk}] +# set_clock_latency -source -hold [get_ports {twd_clk}] +# set_clock_latency -source -setup [get_ports {ddr_pll_CLKOUT4}] +# set_clock_latency -source -hold [get_ports {ddr_pll_CLKOUT4}] +# set_clock_latency -source -setup [get_ports {clk_sys}] +# set_clock_latency -source -hold [get_ports {clk_sys}] +# set_clock_latency -source -setup [get_ports {clk_pixel_2x}] +# set_clock_latency -source -hold [get_ports {clk_pixel_2x}] +# set_clock_latency -source -setup [get_ports {clk_pixel}] +# set_clock_latency -source -hold [get_ports {clk_pixel}] +# set_clock_latency -source -setup [get_ports {clk_pixel_10x}] +# set_clock_latency -source -hold [get_ports {clk_pixel_10x}] +# set_clock_latency -source -setup [get_ports {clk_96m}] +# set_clock_latency -source -hold [get_ports {clk_96m}] +# set_clock_latency -source -setup [get_ports {clk_6m}] +# set_clock_latency -source -hold [get_ports {clk_6m}] +# set_clock_latency -source -setup [get_ports {clk_75m}] +# set_clock_latency -source -hold [get_ports {clk_75m}] +# set_clock_latency -source -setup [get_ports {clk_100m}] +# set_clock_latency -source -hold [get_ports {clk_100m}] diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/outflow/Ti60_Demo_template.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/outflow/Ti60_Demo_template.v new file mode 100644 index 0000000000000000000000000000000000000000..8d3dfb4a28a4439c3458a05fe42b01a74973c88f --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/outflow/Ti60_Demo_template.v @@ -0,0 +1,107 @@ + +// Efinity Top-level template +// Version: 2023.2.307.5.10 +// Date: 2024-11-28 16:28 + +// Copyright (C) 2013 - 2023 Efinix Inc. All rights reserved. + +// This file may be used as a starting point for Efinity synthesis top-level target. +// The port list here matches what is expected by Efinity constraint files generated +// by the Efinity Interface Designer. + +// To use this: +// #1) Save this file with a different name to a different directory, where source files are kept. +// Example: you may wish to save as C:\Users\32954\Desktop\fpga2\1080norst_bicubic32ok (2)\1051\Ti60_Demo.v +// #2) Add the newly saved file into Efinity project as design file +// #3) Edit the top level entity in Efinity project to: Ti60_Demo +// #4) Insert design content. + + +module Ti60_Demo +( + input clk_24m, + input clk_25m, + input fpga_rxd_1, + input sys_pll_lock, + input ddr_pll_CLKOUT4, + input ddr_pll_lock, + input input_pll_lock, + input twd_clk, + input tac_clk, + input tdqss_clk, + input clk_sys, + input clk_pixel, + input core_clk, + input clk_6m, + input clk_96m, + input clk_75m, + input clk_100m, + input clk_pixel_10x, + input clk_pixel_2x, + input [15:0] i_dq_hi, + input [15:0] i_dq_lo, + input [1:0] i_dqs_hi, + input [1:0] i_dqs_lo, + input [1:0] i_dqs_n_hi, + input [1:0] i_dqs_n_lo, + input fpga_rxd_0, + input [23:0] hdmi_data_i, + input hdmi_de_i, + input hdmi_hs_i, + input hdmi_pclk_i, + input hdmi_sda_io_IN, + input hdmi_vs_i, + output fpga_txd_1, + output [7:0] led_o, + output sys_pll_rstn_o, + output ddr_pll_rstn_o, + output [2:0] shift, + output shift_ena, + output [4:0] shift_sel, + output input_pll_rstn_o, + output hdmi_txc_oe, + output [9:0] hdmi_txc_o, + output hdmi_txc_rst_o, + output hdmi_txd0_oe, + output [9:0] hdmi_txd0_o, + output hdmi_txd0_rst_o, + output hdmi_txd1_oe, + output [9:0] hdmi_txd1_o, + output hdmi_txd1_rst_o, + output hdmi_txd2_oe, + output [9:0] hdmi_txd2_o, + output hdmi_txd2_rst_o, + output [15:0] addr, + output adv7611_rstn, + output [2:0] ba, + output cas, + output cke, + output clk_n_hi, + output clk_n_lo, + output clk_p_hi, + output clk_p_lo, + output cs, + output [1:0] o_dm_hi, + output [1:0] o_dm_lo, + output [15:0] o_dq_hi, + output [15:0] o_dq_lo, + output [15:0] o_dq_oe, + output [1:0] o_dqs_hi, + output [1:0] o_dqs_lo, + output [1:0] o_dqs_oe, + output [1:0] o_dqs_n_hi, + output [1:0] o_dqs_n_lo, + output [1:0] o_dqs_n_oe, + output fpga_txd_0, + output hdmi_scl_io, + output hdmi_sda_io_OUT, + output hdmi_sda_io_OE, + output odt, + output ras, + output reset, + output we +); + + +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/adv7611/I2C_ADV7611_Config.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/adv7611/I2C_ADV7611_Config.v new file mode 100644 index 0000000000000000000000000000000000000000..1510ff19e11fe27f51dabd780798899fbbcc3ffe --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/adv7611/I2C_ADV7611_Config.v @@ -0,0 +1,622 @@ +// /*------------------------------------------------------------------------- +// This confidential and proprietary software may be only used as authorized +// by a licensing agreement from CrazyBingo.www.cnblogs.com/crazybingo +// (C) COPYRIGHT 2012 CrazyBingo. ALL RIGHTS RESERVED +// Filename : I2C_SC130GS_12801024_Config.v +// Author : CrazyBingo +// Date : 2019-08-03 +// Version : 1.0 +// Description : I2C Configure Data of AR0135. +// Modification History : +// Date By Version Change Description +// =========================================================================== +// 19/08/03 CrazyBingo 1.0 Original +// --------------------------------------------------------------------------*/ + +// `timescale 1ns/1ns + +// module I2C_ADV7611_Config //1920*1080 +// ( +// input [8:0] LUT_INDEX, +// output reg [23:0] LUT_DATA, +// output [8:0] LUT_SIZE +// ); +// assign LUT_SIZE = 181 + 1; + +// //----------------------------------------------------------------- +// ///////////////////// Config Data LUT ////////////////////////// + +// // 1. Changed crystal to 27MHz. +// // 2. Invert HS, VS. +// // 3. Use SDR clock. + +// always@(*) +// begin +// case(LUT_INDEX) +// 0: LUT_DATA = {8'h98, 8'hF4, 8'h80}; //Manufacturer ID Byte - High (Read only) +// 1: LUT_DATA = {8'h98, 8'hF5, 8'h7c}; //Manufacturer ID Byte - Low (Read only) +// 2: LUT_DATA = {8'h98, 8'hF8, 8'h4c}; // BIT[7]-Reset all the Reg +// 3: LUT_DATA = {8'h98, 8'hF9, 8'h64}; //DC offset for analog process +// 4: LUT_DATA = {8'h98, 8'hFA, 8'h6c}; //COM10: href/vsync/pclk/data reverse(Vsync H valid) +// 5: LUT_DATA = {8'h98, 8'hFB, 8'h68}; //VGA: 8'h22; QVGA: 8'h3f; +// 6: LUT_DATA = {8'h98, 8'hFD, 8'h44}; //VGA: 8'ha4; QVGA: 8'h50; +// 7: LUT_DATA = {8'h98, 8'h01, 8'h05}; //VGA: 8'h07; QVGA: 8'h03; +// 8: LUT_DATA = {8'h98, 8'h00, 8'h13}; //VGA: 8'hf0; QVGA: 8'h78; +// 9: LUT_DATA = {8'h98, 8'h02, 8'hF7}; //HREF / 8'h80 +// 10: LUT_DATA = {8'h98, 8'h03, 8'h40}; // 0x40:SDR. 0x60:DDR. +// 11: LUT_DATA = {8'h98, 8'h04, 8'h60}; // [2:1]0:27MHz. 1:28.63MHz. 2:24.576MHz. 3:24MHz. [7:5]010:BGR, 011:RGB +// 12: LUT_DATA = {8'h98, 8'h05, 8'h28}; // +// 13: LUT_DATA = {8'h98, 8'h06, 8'ha6}; // HS / VS Inverted. CLK / DE Not Inverted. Track rising edge of CLK. +// 14: LUT_DATA = {8'h98, 8'h0b, 8'h44}; //BIT[6]: 0:VGA; 1;QVGA +// 15: LUT_DATA = {8'h98, 8'h0C, 8'h42}; // +// 16: LUT_DATA = {8'h98, 8'h15, 8'h80}; // +// 17: LUT_DATA = {8'h98, 8'h19, 8'h80}; // LLC_DLL_PHASE. [7]En, [4:0]Phase. +// 18: LUT_DATA = {8'h98, 8'h33, 8'h40}; // +// 19: LUT_DATA = {8'h98, 8'h14, 8'h3f}; // +// 20: LUT_DATA = {8'h44, 8'hba, 8'h01}; // +// 21: LUT_DATA = {8'h44, 8'h7c, 8'h01}; // +// 22: LUT_DATA = {8'h64, 8'h40, 8'h81}; //DSP_Ctrl4:00/01: YUV or RGB; 10: RAW8; 11: RAW10 +// 23: LUT_DATA = {8'h68, 8'h9b, 8'h03}; //ADI recommanded setting +// 24: LUT_DATA = {8'h68, 8'hc1, 8'h01}; //ADI recommanded setting +// 25: LUT_DATA = {8'h68, 8'hc2, 8'h01}; //ADI recommanded setting +// 26: LUT_DATA = {8'h68, 8'hc3, 8'h01}; //ADI recommanded setting +// 27: LUT_DATA = {8'h68, 8'hc4, 8'h01}; //ADI recommanded setting +// 28: LUT_DATA = {8'h68, 8'hc5, 8'h01}; //ADI recommanded setting +// 29: LUT_DATA = {8'h68, 8'hc6, 8'h01}; //ADI recommanded setting +// 30: LUT_DATA = {8'h68, 8'hc7, 8'h01}; //ADI recommanded setting +// 31: LUT_DATA = {8'h68, 8'hc8, 8'h01}; //ADI recommanded setting +// 32: LUT_DATA = {8'h68, 8'hc9, 8'h01}; //ADI recommanded settin g +// 33: LUT_DATA = {8'h68, 8'hca, 8'h01}; //ADI recommanded setting +// 34: LUT_DATA = {8'h68, 8'hcb, 8'h01}; //ADI recommanded setting +// 35: LUT_DATA = {8'h68, 8'hcc, 8'h01}; //ADI recommanded setting +// 36: LUT_DATA = {8'h68, 8'h00, 8'h00}; //Set HDMI input Port A +// 37: LUT_DATA = {8'h68, 8'h83, 8'hfe}; //terminator for Port A +// 38: LUT_DATA = {8'h68, 8'h6f, 8'h08}; //ADI recommended setting +// 39: LUT_DATA = {8'h68, 8'h85, 8'h1f}; //ADI recommended setting +// 40: LUT_DATA = {8'h68, 8'h87, 8'h70}; //ADI recommended setting +// 41: LUT_DATA = {8'h68, 8'h8d, 8'h04}; //LFG +// 42: LUT_DATA = {8'h68, 8'h8e, 8'h1e}; //HFG +// 43: LUT_DATA = {8'h68, 8'h1a, 8'h8a}; //unmute audio +// 44: LUT_DATA = {8'h68, 8'h57, 8'hda}; // ADI recommended setting +// 45: LUT_DATA = {8'h68, 8'h58, 8'h01}; +// 46: LUT_DATA = {8'h68, 8'h75, 8'h10}; +// 47: LUT_DATA = {8'h68, 8'h6c, 8'ha3};//enable manual HPA +// 48: LUT_DATA = {8'h98, 8'h20, 8'h70};//HPD low +// 49: LUT_DATA = {8'h64, 8'h74, 8'h00};//disable internal EDID +// //edid +// //0: LUT_DATA = {8'h68, 8'h6c, 8'ha3};//// enable manual HPA +// //1: LUT_DATA = {8'h98, 8'h20, 8'h70};//HPD low +// //2: LUT_DATA = {8'h64, 8'h74, 8'h00};//disable internal EDID +// //edid par +// 50: LUT_DATA = {8'h6c, 8'd0, 8'h00}; +// 51: LUT_DATA = {8'h6c, 8'd1, 8'hFF}; +// 52: LUT_DATA = {8'h6c, 8'd2, 8'hFF}; +// 53: LUT_DATA = {8'h6c, 8'd3, 8'hFF}; +// 54: LUT_DATA = {8'h6c, 8'd4, 8'hFF}; +// 55: LUT_DATA = {8'h6c, 8'd5, 8'hFF}; +// 56: LUT_DATA = {8'h6c, 8'd6, 8'hFF}; +// 57: LUT_DATA = {8'h6c, 8'd7, 8'h00}; +// 58: LUT_DATA = {8'h6c, 8'd8, 8'h20}; +// 59: LUT_DATA = {8'h6c, 8'd9, 8'hA3}; +// 60: LUT_DATA = {8'h6c, 8'd10, 8'h29}; +// 61: LUT_DATA = {8'h6c, 8'd11, 8'h00}; +// 62: LUT_DATA = {8'h6c, 8'd12, 8'h01}; +// 63: LUT_DATA = {8'h6c, 8'd13, 8'h00}; +// 64: LUT_DATA = {8'h6c, 8'd14, 8'h00}; +// 65: LUT_DATA = {8'h6c, 8'd15, 8'h00}; +// 66: LUT_DATA = {8'h6c, 8'd16, 8'h23}; +// 67: LUT_DATA = {8'h6c, 8'd17, 8'h12}; +// 68: LUT_DATA = {8'h6c, 8'd18, 8'h01}; +// 69: LUT_DATA = {8'h6c, 8'd19, 8'h03}; +// 70: LUT_DATA = {8'h6c, 8'd20, 8'h80}; +// 71: LUT_DATA = {8'h6c, 8'd21, 8'h73}; +// 72: LUT_DATA = {8'h6c, 8'd22, 8'h41}; +// 73: LUT_DATA = {8'h6c, 8'd23, 8'h78}; +// 74: LUT_DATA = {8'h6c, 8'd24, 8'h0A}; +// 75: LUT_DATA = {8'h6c, 8'd25, 8'hF3}; +// 76: LUT_DATA = {8'h6c, 8'd26, 8'h30}; +// 77: LUT_DATA = {8'h6c, 8'd27, 8'hA7}; +// 78: LUT_DATA = {8'h6c, 8'd28, 8'h54}; +// 79: LUT_DATA = {8'h6c, 8'd29, 8'h42}; +// 80: LUT_DATA = {8'h6c, 8'd30, 8'hAA}; +// 81: LUT_DATA = {8'h6c, 8'd31, 8'h26}; +// 82: LUT_DATA = {8'h6c, 8'd32, 8'h0F}; +// 83: LUT_DATA = {8'h6c, 8'd33, 8'h50}; +// 84: LUT_DATA = {8'h6c, 8'd34, 8'h54}; +// 85: LUT_DATA = {8'h6c, 8'd35, 8'h25}; +// 86: LUT_DATA = {8'h6c, 8'd36, 8'hC8}; +// 87: LUT_DATA = {8'h6c, 8'd37, 8'h00}; + +// 88: LUT_DATA = {8'h6c, 8'd38, 8'h61}; +// 89: LUT_DATA = {8'h6c, 8'd39, 8'h4F}; +// 90: LUT_DATA = {8'h6c, 8'd40, 8'h01}; +// 91: LUT_DATA = {8'h6c, 8'd41, 8'h01}; +// 92: LUT_DATA = {8'h6c, 8'd42, 8'h01}; +// 93: LUT_DATA = {8'h6c, 8'd43, 8'h01}; +// 94: LUT_DATA = {8'h6c, 8'd44, 8'h01}; +// 95: LUT_DATA = {8'h6c, 8'd45, 8'h01}; +// 96: LUT_DATA = {8'h6c, 8'd46, 8'h01}; +// 97: LUT_DATA = {8'h6c, 8'd47, 8'h01}; +// 98: LUT_DATA = {8'h6c, 8'd48, 8'h01}; +// 99: LUT_DATA = {8'h6c, 8'd49, 8'h01}; +// 100: LUT_DATA = {8'h6c, 8'd50, 8'h01}; +// 101: LUT_DATA = {8'h6c, 8'd51, 8'h01}; +// 102: LUT_DATA = {8'h6c, 8'd52, 8'h01}; +// 103: LUT_DATA = {8'h6c, 8'd53, 8'h01}; + + // 104: LUT_DATA = {8'h6c, 8'd54, 8'h02};//1080p@60 + // 105: LUT_DATA = {8'h6c, 8'd55, 8'h3A}; + // 106: LUT_DATA = {8'h6c, 8'd56, 8'h80}; + // 107: LUT_DATA = {8'h6c, 8'd57, 8'h18}; + // 108: LUT_DATA = {8'h6c, 8'd58, 8'h71}; + // 109: LUT_DATA = {8'h6c, 8'd59, 8'h38}; + // 110: LUT_DATA = {8'h6c, 8'd60, 8'h2D}; + // 111: LUT_DATA = {8'h6c, 8'd61, 8'h40}; + // 112: LUT_DATA = {8'h6c, 8'd62, 8'h58}; + // 113: LUT_DATA = {8'h6c, 8'd63, 8'h2C}; + // 114: LUT_DATA = {8'h6c, 8'd64, 8'h45}; + // 115: LUT_DATA = {8'h6c, 8'd65, 8'h00}; + // 116: LUT_DATA = {8'h6c, 8'd66, 8'h80}; + // 117: LUT_DATA = {8'h6c, 8'd67, 8'h88}; + // 118: LUT_DATA = {8'h6c, 8'd68, 8'h42}; + // 119: LUT_DATA = {8'h6c, 8'd69, 8'h00}; + // 120: LUT_DATA = {8'h6c, 8'd70, 8'h00}; + // 121: LUT_DATA = {8'h6c, 8'd71, 8'h1E}; + + // 122: LUT_DATA = {8'h6c, 8'd72, 8'h8C};//1080p@120 + // 123: LUT_DATA = {8'h6c, 8'd73, 8'h0A}; + // 124: LUT_DATA = {8'h6c, 8'd74, 8'hD0}; + // 125: LUT_DATA = {8'h6c, 8'd75, 8'h8A}; + // 126: LUT_DATA = {8'h6c, 8'd76, 8'h20}; + // 127: LUT_DATA = {8'h6c, 8'd77, 8'hE0}; + // 128: LUT_DATA = {8'h6c, 8'd78, 8'h2D}; + // 129: LUT_DATA = {8'h6c, 8'd79, 8'h10}; + // 130: LUT_DATA = {8'h6c, 8'd80, 8'h10}; + // 131: LUT_DATA = {8'h6c, 8'd81, 8'h3E}; + // 132: LUT_DATA = {8'h6c, 8'd82, 8'h96}; + // 133: LUT_DATA = {8'h6c, 8'd83, 8'h00}; + // 134: LUT_DATA = {8'h6c, 8'd84, 8'h80}; + // 135: LUT_DATA = {8'h6c, 8'd85, 8'h88}; + // 136: LUT_DATA = {8'h6c, 8'd86, 8'h42}; + // 137: LUT_DATA = {8'h6c, 8'd87, 8'h00}; + // 138: LUT_DATA = {8'h6c, 8'd88, 8'h00}; + // 139: LUT_DATA = {8'h6c, 8'd89, 8'h18}; + + // 140: LUT_DATA = {8'h6c, 8'd90, 8'h00};//HDMI + // 141: LUT_DATA = {8'h6c, 8'd91, 8'h00}; + // 142: LUT_DATA = {8'h6c, 8'd92, 8'h00}; + // 143: LUT_DATA = {8'h6c, 8'd93, 8'hFC}; + // 144: LUT_DATA = {8'h6c, 8'd94, 8'h00}; + // 145: LUT_DATA = {8'h6c, 8'd95, 8'h48}; + // 146: LUT_DATA = {8'h6c, 8'd96, 8'h44}; + // 147: LUT_DATA = {8'h6c, 8'd97, 8'h4D}; + // 148: LUT_DATA = {8'h6c, 8'd98, 8'h49}; + // 149: LUT_DATA = {8'h6c, 8'd99, 8'h20}; + // 150: LUT_DATA = {8'h6c, 8'd100, 8'h20}; + // 151: LUT_DATA = {8'h6c, 8'd101, 8'h20}; + // 152: LUT_DATA = {8'h6c, 8'd102, 8'h20}; + // 153: LUT_DATA = {8'h6c, 8'd103, 8'h0A}; + // 154: LUT_DATA = {8'h6c, 8'd104, 8'h20}; + // 155: LUT_DATA = {8'h6c, 8'd105, 8'h20}; + // 156: LUT_DATA = {8'h6c, 8'd106, 8'h20}; + // 157: LUT_DATA = {8'h6c, 8'd107, 8'h20}; + + // 158: LUT_DATA = {8'h6c, 8'd108, 8'h00}; + // 159: LUT_DATA = {8'h6c, 8'd109, 8'h00}; + // 160: LUT_DATA = {8'h6c, 8'd110, 8'h00}; + // 161: LUT_DATA = {8'h6c, 8'd111, 8'hFD}; + // 162: LUT_DATA = {8'h6c, 8'd112, 8'h00}; + // 163: LUT_DATA = {8'h6c, 8'd113, 8'h32}; + // 164: LUT_DATA = {8'h6c, 8'd114, 8'h55}; + // 165: LUT_DATA = {8'h6c, 8'd115, 8'h1F}; + // 166: LUT_DATA = {8'h6c, 8'd116, 8'h45}; + // 167: LUT_DATA = {8'h6c, 8'd117, 8'h0F}; + // 168: LUT_DATA = {8'h6c, 8'd118, 8'h00}; + // 169: LUT_DATA = {8'h6c, 8'd119, 8'h0A}; + // 170: LUT_DATA = {8'h6c, 8'd120, 8'h20}; + // 171: LUT_DATA = {8'h6c, 8'd121, 8'h20}; + // 172: LUT_DATA = {8'h6c, 8'd122, 8'h20}; + // 173: LUT_DATA = {8'h6c, 8'd123, 8'h20}; + // 174: LUT_DATA = {8'h6c, 8'd124, 8'h20}; + // 175: LUT_DATA = {8'h6c, 8'd125, 8'h20}; + +// 176: LUT_DATA = {8'h6c, 8'd126, 8'h01}; +// 177: LUT_DATA = {8'h6c, 8'd127, 8'h24}; +// 178: LUT_DATA = {8'h64, 8'h74, 8'h01};// enable internal EDID +// 179: LUT_DATA = {8'h98, 8'h20, 8'hf0};// HPD high +// 180: LUT_DATA = {8'h68, 8'h6c, 8'ha2};// disable manual HPA +// 181: LUT_DATA = {8'h98, 8'hf4, 8'h00}; +// default:LUT_DATA =0; +// endcase +// end + + + +// endmodule + + + +`timescale 1ns/1ns + +module I2C_ADV7611_Config //1920*1080 +( + input [8:0] LUT_INDEX, + output reg [23:0] LUT_DATA, + output [8:0] LUT_SIZE +); +assign LUT_SIZE = 181 + 1; + +//----------------------------------------------------------------- +///////////////////// Config Data LUT ////////////////////////// + +// 1. Changed crystal to 27MHz. +// 2. Invert HS, VS. +// 3. Use SDR clock. + +always@(*) +begin + case(LUT_INDEX) + 0: LUT_DATA = {8'h98, 8'hF4, 8'h80}; //Manufacturer ID Byte - High (Read only) + 1: LUT_DATA = {8'h98, 8'hF5, 8'h7c}; //Manufacturer ID Byte - Low (Read only) + 2: LUT_DATA = {8'h98, 8'hF8, 8'h4c}; // BIT[7]-Reset all the Reg + 3: LUT_DATA = {8'h98, 8'hF9, 8'h64}; //DC offset for analog process + 4: LUT_DATA = {8'h98, 8'hFA, 8'h6c}; //COM10: href/vsync/pclk/data reverse(Vsync H valid) + 5: LUT_DATA = {8'h98, 8'hFB, 8'h68}; //VGA: 8'h22; QVGA: 8'h3f; + 6: LUT_DATA = {8'h98, 8'hFD, 8'h44}; //VGA: 8'ha4; QVGA: 8'h50; + 7: LUT_DATA = {8'h98, 8'h01, 8'h05}; //VGA: 8'h07; QVGA: 8'h03; + 8: LUT_DATA = {8'h98, 8'h00, 8'h13}; //VGA: 8'hf0; QVGA: 8'h78; + 9: LUT_DATA = {8'h98, 8'h02, 8'hF7}; //HREF / 8'h80 + 10: LUT_DATA = {8'h98, 8'h03, 8'h40}; // 0x40:SDR. 0x60:DDR. + 11: LUT_DATA = {8'h98, 8'h04, 8'h60}; // [2:1]0:27MHz. 1:28.63MHz. 2:24.576MHz. 3:24MHz. [7:5]010:BGR, 011:RGB + 12: LUT_DATA = {8'h98, 8'h05, 8'h28}; // + 13: LUT_DATA = {8'h98, 8'h06, 8'ha6}; // HS / VS Inverted. CLK / DE Not Inverted. Track rising edge of CLK. + 14: LUT_DATA = {8'h98, 8'h0b, 8'h44}; //BIT[6]: 0:VGA; 1;QVGA + 15: LUT_DATA = {8'h98, 8'h0C, 8'h42}; // + 16: LUT_DATA = {8'h98, 8'h15, 8'h80}; // + 17: LUT_DATA = {8'h98, 8'h19, 8'h80}; // LLC_DLL_PHASE. [7]En, [4:0]Phase. + 18: LUT_DATA = {8'h98, 8'h33, 8'h40}; // + 19: LUT_DATA = {8'h98, 8'h14, 8'h3f}; // + 20: LUT_DATA = {8'h44, 8'hba, 8'h01}; // + 21: LUT_DATA = {8'h44, 8'h7c, 8'h01}; // + 22: LUT_DATA = {8'h64, 8'h40, 8'h81}; //DSP_Ctrl4:00/01: YUV or RGB; 10: RAW8; 11: RAW10 + 23: LUT_DATA = {8'h68, 8'h9b, 8'h03}; //ADI recommanded setting + 24: LUT_DATA = {8'h68, 8'hc1, 8'h01}; //ADI recommanded setting + 25: LUT_DATA = {8'h68, 8'hc2, 8'h01}; //ADI recommanded setting + 26: LUT_DATA = {8'h68, 8'hc3, 8'h01}; //ADI recommanded setting + 27: LUT_DATA = {8'h68, 8'hc4, 8'h01}; //ADI recommanded setting + 28: LUT_DATA = {8'h68, 8'hc5, 8'h01}; //ADI recommanded setting + 29: LUT_DATA = {8'h68, 8'hc6, 8'h01}; //ADI recommanded setting + 30: LUT_DATA = {8'h68, 8'hc7, 8'h01}; //ADI recommanded setting + 31: LUT_DATA = {8'h68, 8'hc8, 8'h01}; //ADI recommanded setting + 32: LUT_DATA = {8'h68, 8'hc9, 8'h01}; //ADI recommanded settin g + 33: LUT_DATA = {8'h68, 8'hca, 8'h01}; //ADI recommanded setting + 34: LUT_DATA = {8'h68, 8'hcb, 8'h01}; //ADI recommanded setting + 35: LUT_DATA = {8'h68, 8'hcc, 8'h01}; //ADI recommanded setting + 36: LUT_DATA = {8'h68, 8'h00, 8'h00}; //Set HDMI input Port A + 37: LUT_DATA = {8'h68, 8'h83, 8'hfe}; //terminator for Port A + 38: LUT_DATA = {8'h68, 8'h6f, 8'h08}; //ADI recommended setting + 39: LUT_DATA = {8'h68, 8'h85, 8'h1f}; //ADI recommended setting + 40: LUT_DATA = {8'h68, 8'h87, 8'h70}; //ADI recommended setting + 41: LUT_DATA = {8'h68, 8'h8d, 8'h04}; //LFG + 42: LUT_DATA = {8'h68, 8'h8e, 8'h1e}; //HFG + 43: LUT_DATA = {8'h68, 8'h1a, 8'h8a}; //unmute audio + 44: LUT_DATA = {8'h68, 8'h57, 8'hda}; // ADI recommended setting + 45: LUT_DATA = {8'h68, 8'h58, 8'h01}; + 46: LUT_DATA = {8'h68, 8'h75, 8'h10}; + 47: LUT_DATA = {8'h68, 8'h6c, 8'ha3};//enable manual HPA + 48: LUT_DATA = {8'h98, 8'h20, 8'h70};//HPD low + 49: LUT_DATA = {8'h64, 8'h74, 8'h00};//disable internal EDID + //edid + //0: LUT_DATA = {8'h68, 8'h6c, 8'ha3};//// enable manual HPA + //1: LUT_DATA = {8'h98, 8'h20, 8'h70};//HPD low + //2: LUT_DATA = {8'h64, 8'h74, 8'h00};//disable internal EDID + //edid par + // 50: LUT_DATA = {8'h6c, 8'd0, 8'h00}; + // 51: LUT_DATA = {8'h6c, 8'd1, 8'hFF}; + // 52: LUT_DATA = {8'h6c, 8'd2, 8'hFF}; + // 53: LUT_DATA = {8'h6c, 8'd3, 8'hFF}; + // 54: LUT_DATA = {8'h6c, 8'd4, 8'hFF}; + // 55: LUT_DATA = {8'h6c, 8'd5, 8'hFF}; + // 56: LUT_DATA = {8'h6c, 8'd6, 8'hFF}; + // 57: LUT_DATA = {8'h6c, 8'd7, 8'h00}; + // 58: LUT_DATA = {8'h6c, 8'd8, 8'h3E}; + // 59: LUT_DATA = {8'h6c, 8'd9, 8'hD3}; + // 60: LUT_DATA = {8'h6c, 8'd10, 8'h11}; + // 61: LUT_DATA = {8'h6c, 8'd11, 8'h11}; + // 62: LUT_DATA = {8'h6c, 8'd12, 8'hE0}; + // 63: LUT_DATA = {8'h6c, 8'd13, 8'hC5}; + // 64: LUT_DATA = {8'h6c, 8'd14, 8'h09}; + // 65: LUT_DATA = {8'h6c, 8'd15, 8'h00}; + // 66: LUT_DATA = {8'h6c, 8'd16, 8'h01}; + // 67: LUT_DATA = {8'h6c, 8'd17, 8'h21}; + // 68: LUT_DATA = {8'h6c, 8'd18, 8'h01}; + // 69: LUT_DATA = {8'h6c, 8'd19, 8'h03}; + // 70: LUT_DATA = {8'h6c, 8'd20, 8'h80}; + // 71: LUT_DATA = {8'h6c, 8'd21, 8'h40}; + // 72: LUT_DATA = {8'h6c, 8'd22, 8'h30}; + // 73: LUT_DATA = {8'h6c, 8'd23, 8'h78}; + // 74: LUT_DATA = {8'h6c, 8'd24, 8'h02}; + // 75: LUT_DATA = {8'h6c, 8'd25, 8'h1F}; + // 76: LUT_DATA = {8'h6c, 8'd26, 8'h65}; + // 77: LUT_DATA = {8'h6c, 8'd27, 8'hA4}; + // 78: LUT_DATA = {8'h6c, 8'd28, 8'h55}; + // 79: LUT_DATA = {8'h6c, 8'd29, 8'h50}; + // 80: LUT_DATA = {8'h6c, 8'd30, 8'h9F}; + // 81: LUT_DATA = {8'h6c, 8'd31, 8'h26}; + // 82: LUT_DATA = {8'h6c, 8'd32, 8'h0C}; + // 83: LUT_DATA = {8'h6c, 8'd33, 8'h50}; + // 84: LUT_DATA = {8'h6c, 8'd34, 8'h54}; + // 85: LUT_DATA = {8'h6c, 8'd35, 8'h20}; + // 86: LUT_DATA = {8'h6c, 8'd36, 8'h00}; + // 87: LUT_DATA = {8'h6c, 8'd37, 8'h00}; //DB5 from head to here + + // 88: LUT_DATA = {8'h6c, 8'd38, 8'h31}; + // 89: LUT_DATA = {8'h6c, 8'd39, 8'h40}; + // 90: LUT_DATA = {8'h6c, 8'd40, 8'hD1}; //1080p + // 91: LUT_DATA = {8'h6c, 8'd41, 8'hC0}; + // 92: LUT_DATA = {8'h6c, 8'd42, 8'h01}; //FB8 + // 93: LUT_DATA = {8'h6c, 8'd43, 8'h00}; + // 94: LUT_DATA = {8'h6c, 8'd44, 8'h01}; + // 95: LUT_DATA = {8'h6c, 8'd45, 8'h00}; + // 96: LUT_DATA = {8'h6c, 8'd46, 8'h01}; + // 97: LUT_DATA = {8'h6c, 8'd47, 8'h00}; + // 98: LUT_DATA = {8'h6c, 8'd48, 8'h01}; + // 99: LUT_DATA = {8'h6c, 8'd49, 8'h00}; + // 100: LUT_DATA = {8'h6c, 8'd50, 8'h01}; + // 101: LUT_DATA = {8'h6c, 8'd51, 8'h00}; + // 102: LUT_DATA = {8'h6c, 8'd52, 8'h01}; //FBD + // 103: LUT_DATA = {8'h6c, 8'd53, 8'h00}; + + // 104: LUT_DATA = {8'h6c, 8'd54, 8'h76}; //76(15hz) //D8(60hz) + // 105: LUT_DATA = {8'h6c, 8'd55, 8'h02}; //25.2Mpclk//02(15hz) //09(60hz) + // 106: LUT_DATA = {8'h6c, 8'd56, 8'h80}; + // 107: LUT_DATA = {8'h6c, 8'd57, 8'hA0}; + // 108: LUT_DATA = {8'h6c, 8'd58, 8'h20}; //640-800 + // 109: LUT_DATA = {8'h6c, 8'd59, 8'hE0}; + // 110: LUT_DATA = {8'h6c, 8'd60, 8'h2D}; + // 111: LUT_DATA = {8'h6c, 8'd61, 8'h10}; //480-525 + // 112: LUT_DATA = {8'h6c, 8'd62, 8'h10}; //16 + // 113: LUT_DATA = {8'h6c, 8'd63, 8'h20}; //32?/96in para + // 114: LUT_DATA = {8'h6c, 8'd64, 8'hA2}; //10,2 + // 115: LUT_DATA = {8'h6c, 8'd65, 8'h00}; //00 + // 116: LUT_DATA = {8'h6c, 8'd66, 8'h80}; //scale + // 117: LUT_DATA = {8'h6c, 8'd67, 8'hE0}; + // 118: LUT_DATA = {8'h6c, 8'd68, 8'h21}; + // 119: LUT_DATA = {8'h6c, 8'd69, 8'h00}; + // 120: LUT_DATA = {8'h6c, 8'd70, 8'h00}; + // 121: LUT_DATA = {8'h6c, 8'd71, 8'h1E}; //5AF block + + // 122: LUT_DATA = {8'h6c, 8'd72, 8'h02}; + // 123: LUT_DATA = {8'h6c, 8'd73, 8'h3A}; //148.5 + // 124: LUT_DATA = {8'h6c, 8'd74, 8'h80}; + // 125: LUT_DATA = {8'h6c, 8'd75, 8'h18}; + // 126: LUT_DATA = {8'h6c, 8'd76, 8'h71}; //1920-2200 + // 127: LUT_DATA = {8'h6c, 8'd77, 8'h38}; + // 128: LUT_DATA = {8'h6c, 8'd78, 8'h2D}; + // 129: LUT_DATA = {8'h6c, 8'd79, 8'h40}; //1080-1125 + // 130: LUT_DATA = {8'h6c, 8'd80, 8'h58}; //88 + // 131: LUT_DATA = {8'h6c, 8'd81, 8'h2C};//44? + // 132: LUT_DATA = {8'h6c, 8'd82, 8'hA2}; //4,5 + // 133: LUT_DATA = {8'h6c, 8'd83, 8'h00}; //00 + // 134: LUT_DATA = {8'h6c, 8'd84, 8'h80}; + // 135: LUT_DATA = {8'h6c, 8'd85, 8'h88}; + // 136: LUT_DATA = {8'h6c, 8'd86, 8'h42}; + // 137: LUT_DATA = {8'h6c, 8'd87, 8'h00}; + // 138: LUT_DATA = {8'h6c, 8'd88, 8'h00}; + // 139: LUT_DATA = {8'h6c, 8'd89, 8'h1E}; //11B block + + // // 140: LUT_DATA = {8'h6c, 8'd90, 8'h00}; + // // 141: LUT_DATA = {8'h6c, 8'd91, 8'h00}; + // // 142: LUT_DATA = {8'h6c, 8'd92, 8'h00}; + // // 143: LUT_DATA = {8'h6c, 8'd93, 8'h10}; + // // 144: LUT_DATA = {8'h6c, 8'd94, 8'h00}; + // // 145: LUT_DATA = {8'h6c, 8'd95, 8'h00}; + // // 146: LUT_DATA = {8'h6c, 8'd96, 8'h00}; + // // 147: LUT_DATA = {8'h6c, 8'd97, 8'h00}; + // // 148: LUT_DATA = {8'h6c, 8'd98, 8'h00}; + // // 149: LUT_DATA = {8'h6c, 8'd99, 8'h00}; + // // 150: LUT_DATA = {8'h6c, 8'd100, 8'h00}; + // // 151: LUT_DATA = {8'h6c, 8'd101, 8'h00}; + // // 152: LUT_DATA = {8'h6c, 8'd102, 8'h00}; + // // 153: LUT_DATA = {8'h6c, 8'd103, 8'h00}; + // // 154: LUT_DATA = {8'h6c, 8'd104, 8'h00}; + // // 155: LUT_DATA = {8'h6c, 8'd105, 8'h00}; + // // 156: LUT_DATA = {8'h6c, 8'd106, 8'h00}; + // // 157: LUT_DATA = {8'h6c, 8'd107, 8'h00}; + // 140: LUT_DATA = {8'h6c, 8'd90, 8'h00};//HDMI + // 141: LUT_DATA = {8'h6c, 8'd91, 8'h00}; + // 142: LUT_DATA = {8'h6c, 8'd92, 8'h00}; + // 143: LUT_DATA = {8'h6c, 8'd93, 8'hFC}; + // 144: LUT_DATA = {8'h6c, 8'd94, 8'h00}; + // 145: LUT_DATA = {8'h6c, 8'd95, 8'h48}; + // 146: LUT_DATA = {8'h6c, 8'd96, 8'h44}; + // 147: LUT_DATA = {8'h6c, 8'd97, 8'h4D}; + // 148: LUT_DATA = {8'h6c, 8'd98, 8'h49};//11E + // 149: LUT_DATA = {8'h6c, 8'd99, 8'h20}; + // 150: LUT_DATA = {8'h6c, 8'd100, 8'h20}; + // 151: LUT_DATA = {8'h6c, 8'd101, 8'h20}; + // 152: LUT_DATA = {8'h6c, 8'd102, 8'h20}; + // 153: LUT_DATA = {8'h6c, 8'd103, 8'h0A}; + // 154: LUT_DATA = {8'h6c, 8'd104, 8'h20}; + // 155: LUT_DATA = {8'h6c, 8'd105, 8'h20}; + // 156: LUT_DATA = {8'h6c, 8'd106, 8'h20}; + // 157: LUT_DATA = {8'h6c, 8'd107, 8'h20};//28 block + + // // 158: LUT_DATA = {8'h6c, 8'd108, 8'h00}; + // // 159: LUT_DATA = {8'h6c, 8'd109, 8'h00}; + // // 160: LUT_DATA = {8'h6c, 8'd110, 8'h00}; + // // 161: LUT_DATA = {8'h6c, 8'd111, 8'h10}; + // // 162: LUT_DATA = {8'h6c, 8'd112, 8'h00}; + // // 163: LUT_DATA = {8'h6c, 8'd113, 8'h00}; + // // 164: LUT_DATA = {8'h6c, 8'd114, 8'h00}; + // // 165: LUT_DATA = {8'h6c, 8'd115, 8'h00}; + // // 166: LUT_DATA = {8'h6c, 8'd116, 8'h00}; + // // 167: LUT_DATA = {8'h6c, 8'd117, 8'h00}; + // // 168: LUT_DATA = {8'h6c, 8'd118, 8'h00}; + // // 169: LUT_DATA = {8'h6c, 8'd119, 8'h00}; + // // 170: LUT_DATA = {8'h6c, 8'd120, 8'h00}; + // // 171: LUT_DATA = {8'h6c, 8'd121, 8'h00}; + // // 172: LUT_DATA = {8'h6c, 8'd122, 8'h00}; + // // 173: LUT_DATA = {8'h6c, 8'd123, 8'h00}; + // // 174: LUT_DATA = {8'h6c, 8'd124, 8'h00}; + // // 175: LUT_DATA = {8'h6c, 8'd125, 8'h00}; + // 158: LUT_DATA = {8'h6c, 8'd108, 8'h00}; + // 159: LUT_DATA = {8'h6c, 8'd109, 8'h00}; + // 160: LUT_DATA = {8'h6c, 8'd110, 8'h00}; + // 161: LUT_DATA = {8'h6c, 8'd111, 8'hFD}; + // 162: LUT_DATA = {8'h6c, 8'd112, 8'h00}; + // 163: LUT_DATA = {8'h6c, 8'd113, 8'h32}; + // 164: LUT_DATA = {8'h6c, 8'd114, 8'h55}; + // 165: LUT_DATA = {8'h6c, 8'd115, 8'h1F}; + // 166: LUT_DATA = {8'h6c, 8'd116, 8'h45}; + // 167: LUT_DATA = {8'h6c, 8'd117, 8'h0F}; + // 168: LUT_DATA = {8'h6c, 8'd118, 8'h00}; + // 169: LUT_DATA = {8'h6c, 8'd119, 8'h0A};//101 + // 170: LUT_DATA = {8'h6c, 8'd120, 8'h20}; + // 171: LUT_DATA = {8'h6c, 8'd121, 8'h20}; + // 172: LUT_DATA = {8'h6c, 8'd122, 8'h20}; + // 173: LUT_DATA = {8'h6c, 8'd123, 8'h20}; + // 174: LUT_DATA = {8'h6c, 8'd124, 8'h20}; + // 175: LUT_DATA = {8'h6c, 8'd125, 8'h20};//C1 block + + // 176: LUT_DATA = {8'h6c, 8'd126, 8'h01}; + // 177: LUT_DATA = {8'h6c, 8'd127, 8'h9A}; //?//8F//32(60hz)//9B(15hz) + 50: LUT_DATA = {8'h6c, 8'd0, 8'h00}; + 51: LUT_DATA = {8'h6c, 8'd1, 8'hFF}; + 52: LUT_DATA = {8'h6c, 8'd2, 8'hFF}; + 53: LUT_DATA = {8'h6c, 8'd3, 8'hFF}; + 54: LUT_DATA = {8'h6c, 8'd4, 8'hFF}; + 55: LUT_DATA = {8'h6c, 8'd5, 8'hFF}; + 56: LUT_DATA = {8'h6c, 8'd6, 8'hFF}; + 57: LUT_DATA = {8'h6c, 8'd7, 8'h00}; + 58: LUT_DATA = {8'h6c, 8'd8, 8'h3E}; + 59: LUT_DATA = {8'h6c, 8'd9, 8'hD3}; + 60: LUT_DATA = {8'h6c, 8'd10, 8'h11}; + 61: LUT_DATA = {8'h6c, 8'd11, 8'h11}; + 62: LUT_DATA = {8'h6c, 8'd12, 8'hE0}; + 63: LUT_DATA = {8'h6c, 8'd13, 8'hC5}; + 64: LUT_DATA = {8'h6c, 8'd14, 8'h09}; + 65: LUT_DATA = {8'h6c, 8'd15, 8'h00}; + 66: LUT_DATA = {8'h6c, 8'd16, 8'h01}; + 67: LUT_DATA = {8'h6c, 8'd17, 8'h21}; + 68: LUT_DATA = {8'h6c, 8'd18, 8'h01}; + 69: LUT_DATA = {8'h6c, 8'd19, 8'h03}; + 70: LUT_DATA = {8'h6c, 8'd20, 8'h80}; + 71: LUT_DATA = {8'h6c, 8'd21, 8'h40}; + 72: LUT_DATA = {8'h6c, 8'd22, 8'h30}; + 73: LUT_DATA = {8'h6c, 8'd23, 8'h78}; + 74: LUT_DATA = {8'h6c, 8'd24, 8'h02}; + 75: LUT_DATA = {8'h6c, 8'd25, 8'h1F}; + 76: LUT_DATA = {8'h6c, 8'd26, 8'h65}; + 77: LUT_DATA = {8'h6c, 8'd27, 8'hA4}; + 78: LUT_DATA = {8'h6c, 8'd28, 8'h55}; + 79: LUT_DATA = {8'h6c, 8'd29, 8'h50}; + 80: LUT_DATA = {8'h6c, 8'd30, 8'h9F}; + 81: LUT_DATA = {8'h6c, 8'd31, 8'h26}; + 82: LUT_DATA = {8'h6c, 8'd32, 8'h0C}; + 83: LUT_DATA = {8'h6c, 8'd33, 8'h50}; + 84: LUT_DATA = {8'h6c, 8'd34, 8'h54}; + 85: LUT_DATA = {8'h6c, 8'd35, 8'h20}; + 86: LUT_DATA = {8'h6c, 8'd36, 8'h00}; + 87: LUT_DATA = {8'h6c, 8'd37, 8'h00}; + 88: LUT_DATA = {8'h6c, 8'd38, 8'h31}; + 89: LUT_DATA = {8'h6c, 8'd39, 8'h40}; + 90: LUT_DATA = {8'h6c, 8'd40, 8'h01}; + 91: LUT_DATA = {8'h6c, 8'd41, 8'h00}; + 92: LUT_DATA = {8'h6c, 8'd42, 8'h01}; + 93: LUT_DATA = {8'h6c, 8'd43, 8'h00}; + 94: LUT_DATA = {8'h6c, 8'd44, 8'h01}; + 95: LUT_DATA = {8'h6c, 8'd45, 8'h00}; + 96: LUT_DATA = {8'h6c, 8'd46, 8'h01}; + 97: LUT_DATA = {8'h6c, 8'd47, 8'h00}; + 98: LUT_DATA = {8'h6c, 8'd48, 8'h01}; + 99: LUT_DATA = {8'h6c, 8'd49, 8'h00}; + 100: LUT_DATA = {8'h6c, 8'd50, 8'h01}; + 101: LUT_DATA = {8'h6c, 8'd51, 8'h00}; + 102: LUT_DATA = {8'h6c, 8'd52, 8'h01}; + 103: LUT_DATA = {8'h6c, 8'd53, 8'h00}; + + 104: LUT_DATA = {8'h6c, 8'd54, 8'hD8}; + 105: LUT_DATA = {8'h6c, 8'd55, 8'h09}; + 106: LUT_DATA = {8'h6c, 8'd56, 8'h80}; + 107: LUT_DATA = {8'h6c, 8'd57, 8'hA0}; + 108: LUT_DATA = {8'h6c, 8'd58, 8'h20}; + 109: LUT_DATA = {8'h6c, 8'd59, 8'hE0}; + 110: LUT_DATA = {8'h6c, 8'd60, 8'h2D}; + 111: LUT_DATA = {8'h6c, 8'd61, 8'h10}; + 112: LUT_DATA = {8'h6c, 8'd62, 8'h10}; + 113: LUT_DATA = {8'h6c, 8'd63, 8'h60}; + 114: LUT_DATA = {8'h6c, 8'd64, 8'hA2}; + 115: LUT_DATA = {8'h6c, 8'd65, 8'h00}; + 116: LUT_DATA = {8'h6c, 8'd66, 8'h80}; + 117: LUT_DATA = {8'h6c, 8'd67, 8'hE0}; + 118: LUT_DATA = {8'h6c, 8'd68, 8'h21}; + 119: LUT_DATA = {8'h6c, 8'd69, 8'h00}; + 120: LUT_DATA = {8'h6c, 8'd70, 8'h00}; + 121: LUT_DATA = {8'h6c, 8'd71, 8'h1E}; + 122: LUT_DATA = {8'h6c, 8'd72, 8'h00}; + 123: LUT_DATA = {8'h6c, 8'd73, 8'h00}; + 124: LUT_DATA = {8'h6c, 8'd74, 8'h00}; + 125: LUT_DATA = {8'h6c, 8'd75, 8'h10}; + 126: LUT_DATA = {8'h6c, 8'd76, 8'h00}; + 127: LUT_DATA = {8'h6c, 8'd77, 8'h00}; + 128: LUT_DATA = {8'h6c, 8'd78, 8'h00}; + 129: LUT_DATA = {8'h6c, 8'd79, 8'h00}; + 130: LUT_DATA = {8'h6c, 8'd80, 8'h00}; + 131: LUT_DATA = {8'h6c, 8'd81, 8'h00}; + 132: LUT_DATA = {8'h6c, 8'd82, 8'h00}; + 133: LUT_DATA = {8'h6c, 8'd83, 8'h00}; + 134: LUT_DATA = {8'h6c, 8'd84, 8'h00}; + 135: LUT_DATA = {8'h6c, 8'd85, 8'h00}; + 136: LUT_DATA = {8'h6c, 8'd86, 8'h00}; + 137: LUT_DATA = {8'h6c, 8'd87, 8'h00}; + 138: LUT_DATA = {8'h6c, 8'd88, 8'h00}; + 139: LUT_DATA = {8'h6c, 8'd89, 8'h00}; + 140: LUT_DATA = {8'h6c, 8'd90, 8'h00}; + 141: LUT_DATA = {8'h6c, 8'd91, 8'h00}; + 142: LUT_DATA = {8'h6c, 8'd92, 8'h00}; + 143: LUT_DATA = {8'h6c, 8'd93, 8'h10}; + 144: LUT_DATA = {8'h6c, 8'd94, 8'h00}; + 145: LUT_DATA = {8'h6c, 8'd95, 8'h00}; + 146: LUT_DATA = {8'h6c, 8'd96, 8'h00}; + 147: LUT_DATA = {8'h6c, 8'd97, 8'h00}; + 148: LUT_DATA = {8'h6c, 8'd98, 8'h00}; + 149: LUT_DATA = {8'h6c, 8'd99, 8'h00}; + 150: LUT_DATA = {8'h6c, 8'd100, 8'h00}; + 151: LUT_DATA = {8'h6c, 8'd101, 8'h00}; + 152: LUT_DATA = {8'h6c, 8'd102, 8'h00}; + 153: LUT_DATA = {8'h6c, 8'd103, 8'h00}; + 154: LUT_DATA = {8'h6c, 8'd104, 8'h00}; + 155: LUT_DATA = {8'h6c, 8'd105, 8'h00}; + 156: LUT_DATA = {8'h6c, 8'd106, 8'h00}; + 157: LUT_DATA = {8'h6c, 8'd107, 8'h00}; + 158: LUT_DATA = {8'h6c, 8'd108, 8'h00}; + 159: LUT_DATA = {8'h6c, 8'd109, 8'h00}; + 160: LUT_DATA = {8'h6c, 8'd110, 8'h00}; + 161: LUT_DATA = {8'h6c, 8'd111, 8'h10}; + 162: LUT_DATA = {8'h6c, 8'd112, 8'h00}; + 163: LUT_DATA = {8'h6c, 8'd113, 8'h00}; + 164: LUT_DATA = {8'h6c, 8'd114, 8'h00}; + 165: LUT_DATA = {8'h6c, 8'd115, 8'h00}; + 166: LUT_DATA = {8'h6c, 8'd116, 8'h00}; + 167: LUT_DATA = {8'h6c, 8'd117, 8'h00}; + 168: LUT_DATA = {8'h6c, 8'd118, 8'h00}; + 169: LUT_DATA = {8'h6c, 8'd119, 8'h00}; + 170: LUT_DATA = {8'h6c, 8'd120, 8'h00}; + 171: LUT_DATA = {8'h6c, 8'd121, 8'h00}; + 172: LUT_DATA = {8'h6c, 8'd122, 8'h00}; + 173: LUT_DATA = {8'h6c, 8'd123, 8'h00}; + 174: LUT_DATA = {8'h6c, 8'd124, 8'h00}; + 175: LUT_DATA = {8'h6c, 8'd125, 8'h00}; + 176: LUT_DATA = {8'h6c, 8'd126, 8'h01}; + 177: LUT_DATA = {8'h6c, 8'd127, 8'h9B}; + + 178: LUT_DATA = {8'h64, 8'h74, 8'h01};// enable internal EDID + 179: LUT_DATA = {8'h98, 8'h20, 8'hf0};// HPD high + 180: LUT_DATA = {8'h68, 8'h6c, 8'ha2};// disable manual HPA + 181: LUT_DATA = {8'h98, 8'hf4, 8'h00}; + default:LUT_DATA =0; + endcase +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/adv7611/i2c_timing_ctrl_reg8_dat8_wronly.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/adv7611/i2c_timing_ctrl_reg8_dat8_wronly.v new file mode 100644 index 0000000000000000000000000000000000000000..8ffac1e49bdb7634e7827b36725b7d57872bf731 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/adv7611/i2c_timing_ctrl_reg8_dat8_wronly.v @@ -0,0 +1,468 @@ +/*----------------------------------------------------------------------- + \\\|/// + \\ - - // + ( @ @ ) ++-----------------------------oOOo-(_)-oOOo-----------------------------+ +CONFIDENTIAL IN CONFIDENCE +This confidential and proprietary software may be only used as authorized +by a licensing agreement from CrazyBingo (Thereturnofbingo). +In the event of publication, the following notice is applicable: +Copyright (C) 2013-20xx CrazyBingo Corporation +The entire notice above must be reproduced on all authorized copies. +Author : CrazyBingo +Technology blogs : www.crazyfpga.com +Email Address : crazyfpga@vip.qq.com +Filename : i2c_timing_ctrl.v +Date : 2013-04-13 +Description : The testbench of I2C Ctrl timing. +Modification History : +Date By Version Change Description +========================================================================= +13/04/13 CrazyBingo 1.0 Original +13/04/14 CrazyBingo 1.1 add i2c_wdata for avoid bit width warming +------------------------------------------------------------------------- +| Oooo | ++-------------------------------oooO--( )-----------------------------+ + ( ) ) / + \ ( (_/ + \_) +-----------------------------------------------------------------------*/ +`timescale 1ns/1ns +module i2c_timing_ctrl +#( + parameter CLK_FREQ = 100_000000, //100 MHz + parameter I2C_FREQ = 10_000 //10 KHz(< 400KHz) +) +( + //global clock + input clk, //100MHz + input rst_n, //system reset + + //i2c interface + output i2c_sclk, //i2c clock + + + // inout i2c_sdat, //i2c data for bidirection + input i2c_sdat_IN, + output i2c_sdat_OUT, + output i2c_sdat_OE, + + //user interface + input [7:0] i2c_config_size, //i2c config data counte + output reg [7:0] i2c_config_index, //i2c config reg index, read 2 reg and write xx reg + input [23:0] i2c_config_data, //i2c config data + output i2c_config_done, //i2c config timing complete + output reg [7:0] i2c_rdata //i2c register data while read i2c slave +); + +//---------------------------------------- +//Delay xxus until i2c slave is steady +reg [19:0] delay_cnt; +localparam DELAY_TOP = CLK_FREQ/1000; //1ms Setting time after software/hardware reset +// localparam DELAY_TOP = 17'hff; //Just for test +always@(posedge clk or negedge rst_n) +begin + if(!rst_n) + delay_cnt <= 0; + else if(delay_cnt < DELAY_TOP - 1'b1) + delay_cnt <= delay_cnt + 1'b1; + else + delay_cnt <= delay_cnt; +end +wire delay_done = (delay_cnt == DELAY_TOP - 1'b1) ? 1'b1 : 1'b0; //1ms delay + + +//---------------------------------------- +//I2C Control Clock generate +/****************************************** + _______ _______ +SCLK ____| |________| | + ________________ ______________ +SDAT |________________|______________ + _ _ +CLK_EN | |______________| |____________ + _ _ +CAP_EN _______| |______________| |_____ +*******************************************/ +reg [15:0] clk_cnt; //divide for i2c clock +reg i2c_ctrl_clk; //i2c control clock, H: valid; L: valid +reg i2c_transfer_en; //send i2c data before, make sure that sdat is steady when i2c_sclk is valid +reg i2c_capture_en; //capture i2c data while sdat is steady from cmos +always@(posedge clk or negedge rst_n) +begin + if(!rst_n) + begin + clk_cnt <= 0; + i2c_ctrl_clk <= 0; + i2c_transfer_en <= 0; + i2c_capture_en <= 0; + end + else if(delay_done) + begin + if(clk_cnt < (CLK_FREQ/I2C_FREQ) - 1'b1) + clk_cnt <= clk_cnt + 1'd1; + else + clk_cnt <= 0; + //i2c control clock, H: valid; L: valid + i2c_ctrl_clk <= ((clk_cnt >= (CLK_FREQ/I2C_FREQ)/4 + 1'b1) && + (clk_cnt < (3*CLK_FREQ/I2C_FREQ)/4 + 1'b1)) ? 1'b1 : 1'b0; + //send i2c data before, make sure that sdat is steady when i2c_sclk is valid + i2c_transfer_en <= (clk_cnt == 16'd0) ? 1'b1 : 1'b0; + i2c_capture_en <= (clk_cnt == (2*CLK_FREQ/I2C_FREQ)/4 - 1'b1) ? 1'b1 : 1'b0; + end + else + begin + clk_cnt <= 0; + i2c_ctrl_clk <= 0; + i2c_transfer_en <= 0; + i2c_capture_en <= 0; + end +end + +//----------------------------------------- +//I2C Timing state Parameter +localparam I2C_IDLE = 5'd0; +//Write I2C: {ID_Address, REG_Address, W_REG_Data} +localparam I2C_WR_START = 5'd1; +localparam I2C_WR_IDADDR = 5'd2; +localparam I2C_WR_ACK1 = 5'd3; +localparam I2C_WR_REGADDR = 5'd4; +localparam I2C_WR_ACK2 = 5'd5; +localparam I2C_WR_REGDATA = 5'd6; +localparam I2C_WR_ACK3 = 5'd7; +localparam I2C_WR_STOP = 5'd8; +//I2C Read: {ID_Address + REG_Address} + {ID_Address + R_REG_Data} +localparam I2C_RD_START1 = 5'd9; +localparam I2C_RD_IDADDR1 = 5'd10; +localparam I2C_RD_ACK1 = 5'd11; +localparam I2C_RD_REGADDR = 5'd12; +localparam I2C_RD_ACK2 = 5'd13; +localparam I2C_RD_STOP1 = 5'd14; +localparam I2C_RD_IDLE = 5'd15; +localparam I2C_RD_START2 = 5'd16; +localparam I2C_RD_IDADDR2 = 5'd17; +localparam I2C_RD_ACK3 = 5'd18; +localparam I2C_RD_REGDATA = 5'd19; +localparam I2C_RD_NACK = 5'd20; +localparam I2C_RD_STOP2 = 5'd21; + + +//----------------------------------------- +// FSM: always1 next_state for current_state +reg [4:0] current_state, next_state; //i2c write and read state +always@(posedge clk or negedge rst_n) +begin + if(!rst_n) + current_state <= I2C_IDLE; + else if(i2c_transfer_en) + current_state <= next_state; +end + +//----------------------------------------- +wire i2c_transfer_end = (current_state == I2C_WR_STOP || current_state == I2C_RD_STOP2) ? 1'b1 : 1'b0; +reg i2c_ack; //i2c slave renpose successed +always@(posedge clk or negedge rst_n) +begin + if(!rst_n) + i2c_config_index <= 0; + else if(i2c_transfer_en) + begin + if(i2c_transfer_end /*& ~i2c_ack*/) +// if(i2c_transfer_end /*& ~i2c_ack*/) //Just for test + begin + if(i2c_config_index < i2c_config_size) + i2c_config_index <= i2c_config_index + 1'b1; + // i2c_config_index <= 10; +// i2c_config_index <= {i2c_config_index[7:1], ~i2c_config_index[0]}; //Just for test + else + i2c_config_index <= i2c_config_size; + end + else + i2c_config_index <= i2c_config_index; + end + else + i2c_config_index <= i2c_config_index; +end +assign i2c_config_done = (i2c_config_index == i2c_config_size) ? 1'b1 : 1'b0; + + +//----------------------------------------- +// FSM: always2 for the skip function +reg [3:0] i2c_stream_cnt; //i2c data bit stream count +always@(*) +begin + next_state = I2C_IDLE; //state initialization + case(current_state) + I2C_IDLE: //5'd0 + begin + if(delay_done) //1ms Setting time after software/hardware reset + begin + if(i2c_transfer_en) + begin + /*if(i2c_config_index < 8'd2) + next_state = I2C_RD_START1; //Read I2C Slave ID + else */if(i2c_config_index < i2c_config_size) + next_state = I2C_WR_START; //Write Data to I2C + else// if(i2c_config_index >= i2c_config_size) + next_state = I2C_IDLE; //Config I2C Complete + end + else + next_state = next_state; + end + else + next_state = I2C_IDLE; //Wait I2C Bus is steady + end + //Write I2C: {ID_Address, REG_Address, W_REG_Data} + I2C_WR_START: //5'd1 + begin + if(i2c_transfer_en) next_state = I2C_WR_IDADDR; + else next_state = I2C_WR_START; + end + I2C_WR_IDADDR: //5'd2 + if(i2c_transfer_en == 1'b1 && i2c_stream_cnt == 4'd8) + next_state = I2C_WR_ACK1; + else next_state = I2C_WR_IDADDR; + I2C_WR_ACK1: //5'd3 + if(i2c_transfer_en) next_state = I2C_WR_REGADDR; + else next_state = I2C_WR_ACK1; + I2C_WR_REGADDR: //5'd4 + if(i2c_transfer_en == 1'b1 && i2c_stream_cnt == 4'd8) + next_state = I2C_WR_ACK2; + else next_state = I2C_WR_REGADDR; + I2C_WR_ACK2: //5'd5 + if(i2c_transfer_en) next_state = I2C_WR_REGDATA; + else next_state = I2C_WR_ACK2; + I2C_WR_REGDATA: //5'd6 + if(i2c_transfer_en == 1'b1 && i2c_stream_cnt == 4'd8) + next_state = I2C_WR_ACK3; + else next_state = I2C_WR_REGDATA; + I2C_WR_ACK3: //5'd7 + if(i2c_transfer_en) next_state = I2C_WR_STOP; + else next_state = I2C_WR_ACK3; + I2C_WR_STOP: //5'd8 + if(i2c_transfer_en) next_state = I2C_IDLE; + else next_state = I2C_WR_STOP; +//------------------------I2C Read: {ID_Address + REG_Address} + {ID_Address + R_REG_Data} + I2C_RD_START1: //5'd9 + if(i2c_transfer_en) next_state = I2C_RD_IDADDR1; + else next_state = I2C_RD_START1; + I2C_RD_IDADDR1: //5'd10 + if(i2c_transfer_en == 1'b1 && i2c_stream_cnt == 4'd8) + next_state = I2C_RD_ACK1; + else next_state = I2C_RD_IDADDR1; + I2C_RD_ACK1: //5'd11 + if(i2c_transfer_en) next_state = I2C_RD_REGADDR; + else next_state = I2C_RD_ACK1; + I2C_RD_REGADDR: //5'd12 + if(i2c_transfer_en == 1'b1 && i2c_stream_cnt == 4'd8) + next_state = I2C_RD_ACK2; + else next_state = I2C_RD_REGADDR; + I2C_RD_ACK2: //5'd13 + if(i2c_transfer_en) next_state = I2C_RD_STOP1; + else next_state = I2C_RD_ACK2; + I2C_RD_STOP1: //5'd14 + if(i2c_transfer_en) next_state = I2C_RD_IDLE; + else next_state = I2C_RD_STOP1; + I2C_RD_IDLE: //5'd15 + if(i2c_transfer_en) next_state = I2C_RD_START2; + else next_state = I2C_RD_IDLE; + I2C_RD_START2: //5'd16 + if(i2c_transfer_en) next_state = I2C_RD_IDADDR2; + else next_state = I2C_RD_START2; + I2C_RD_IDADDR2: //5'd17 + if(i2c_transfer_en == 1'b1 && i2c_stream_cnt == 4'd8) + next_state = I2C_RD_ACK3; + else next_state = I2C_RD_IDADDR2; + I2C_RD_ACK3: //5'd18 + if(i2c_transfer_en) next_state = I2C_RD_REGDATA; + else next_state = I2C_RD_ACK3; + I2C_RD_REGDATA: //5'd19 + if(i2c_transfer_en == 1'b1 && i2c_stream_cnt == 4'd8) + next_state = I2C_RD_NACK; + else next_state = I2C_RD_REGDATA; + I2C_RD_NACK: //5'd20 + if(i2c_transfer_en) next_state = I2C_RD_STOP2; + else next_state = I2C_RD_NACK; + I2C_RD_STOP2: //5'd21 + if(i2c_transfer_en) next_state = I2C_IDLE; + else next_state = I2C_RD_STOP2; + default:; //default vaule + endcase +end + +//----------------------------------------- +// FSM: always3 for data value +//reg i2c_write_flag, i2c_read_flag; +reg i2c_sdat_out; //i2c data output +//reg [3:0] i2c_stream_cnt; //i2c data bit stream count +reg [7:0] i2c_wdata; //i2c data prepared to transfer +always@(posedge clk or negedge rst_n) +begin + if(!rst_n) + begin + i2c_sdat_out <= 1'b1; + i2c_stream_cnt <= 0; + i2c_wdata <= 0; + end + else if(i2c_transfer_en) + begin + case(next_state) + I2C_IDLE: //5'd0 + begin + i2c_sdat_out <= 1'b1; //idle state + i2c_stream_cnt <= 0; + i2c_wdata <= 0; + end + //Write I2C: {ID_Address, REG_Address, W_REG_Data} + I2C_WR_START: //5'd1 + begin + i2c_sdat_out <= 1'b0; + i2c_stream_cnt <= 0; + i2c_wdata <= i2c_config_data[23:16]; //ID_Address + end + I2C_WR_IDADDR: //5'd2 + begin + i2c_stream_cnt <= i2c_stream_cnt + 1'b1; + i2c_sdat_out <= i2c_wdata[3'd7 - i2c_stream_cnt];//MSB + end + I2C_WR_ACK1: //5'd3 + begin + i2c_stream_cnt <= 0; + i2c_wdata <= i2c_config_data[15:8]; //REG_Address + end + I2C_WR_REGADDR: //5'd4 + begin + i2c_stream_cnt <= i2c_stream_cnt + 1'b1; + i2c_sdat_out <= i2c_wdata[3'd7 - i2c_stream_cnt]; + end + I2C_WR_ACK2: //5'd5 + begin + i2c_stream_cnt <= 0; + i2c_wdata <= i2c_config_data[7:0]; //W_REG_Data + end + I2C_WR_REGDATA: //5'd6 + begin + i2c_stream_cnt <= i2c_stream_cnt + 1'b1; + i2c_sdat_out <= i2c_wdata[3'd7 - i2c_stream_cnt]; + end + I2C_WR_ACK3: //5'd7 + i2c_stream_cnt <= 0; + I2C_WR_STOP: //5'd8 + i2c_sdat_out <= 1'b0; +//---------------------------------------------------I2C Read: {ID_Address + REG_Address} + {ID_Address + R_REG_Data} + I2C_RD_START1: //5'd10 + begin + i2c_sdat_out <= 1'b0; + i2c_stream_cnt <= 0; + i2c_wdata <= i2c_config_data[23:16]; + end + I2C_RD_IDADDR1: //5'd11 + begin + i2c_stream_cnt <= i2c_stream_cnt + 1'b1; + i2c_sdat_out <= i2c_wdata[3'd7 - i2c_stream_cnt]; + end + I2C_RD_ACK1: //5'd11 + begin + i2c_stream_cnt <= 0; + i2c_wdata <= i2c_config_data[15:8]; + end + I2C_RD_REGADDR: //5'd12 + begin + i2c_stream_cnt <= i2c_stream_cnt + 1'b1; + i2c_sdat_out <= i2c_wdata[3'd7 - i2c_stream_cnt]; + end + I2C_RD_ACK2: //5'd13 + i2c_stream_cnt <= 0; + I2C_RD_STOP1: //5'd14 + i2c_sdat_out <= 1'b0; + I2C_RD_IDLE: //5'd15 + i2c_sdat_out <= 1'b1; //idle state +//-------------------------stage2------------------------------------------- + I2C_RD_START2: //5'd16 + begin + i2c_sdat_out <= 1'b0; + i2c_stream_cnt <= 0; + i2c_wdata <= i2c_config_data[23:16]; + end + I2C_RD_IDADDR2: //5'd17 + begin + i2c_stream_cnt <= i2c_stream_cnt + 1'b1; + if(i2c_stream_cnt < 5'd7) + i2c_sdat_out <= i2c_wdata[3'd7 - i2c_stream_cnt]; + else + i2c_sdat_out <= 1'b1; //Read flag for I2C Timing + end + I2C_RD_ACK3: //5'd18 + i2c_stream_cnt <= 0; + I2C_RD_REGDATA: //5'd19 + i2c_stream_cnt <= i2c_stream_cnt + 1'b1; + I2C_RD_NACK: //5'd20 + i2c_sdat_out <= 1'b1; //NACK + I2C_RD_STOP2: //5'd21 + i2c_sdat_out <= 1'b0; + endcase + end + else + begin + i2c_stream_cnt <= i2c_stream_cnt; + i2c_sdat_out <= i2c_sdat_out; + end +end + +//--------------------------------------------- +//respone from slave for i2c data transfer +reg i2c_ack1, i2c_ack2, i2c_ack3; +//reg i2c_ack; +//reg [7:0] i2c_rdata; +always@(posedge clk or negedge rst_n) +begin + if(!rst_n) + begin + {i2c_ack1, i2c_ack2, i2c_ack3} <= 3'b111; + i2c_ack <= 1'b1; + i2c_rdata <= 0; + end + else if(i2c_capture_en) + begin + case(next_state) + I2C_IDLE: + begin + {i2c_ack1, i2c_ack2, i2c_ack3} <= 3'b111; + i2c_ack <= 1'b1; + end + //Write I2C: {ID_Address, REG_Address, W_REG_Data} + I2C_WR_ACK1: i2c_ack1 <= i2c_sdat_IN; + I2C_WR_ACK2: i2c_ack2 <= i2c_sdat_IN; + I2C_WR_ACK3: i2c_ack3 <= i2c_sdat_IN; + I2C_WR_STOP: i2c_ack <= (i2c_ack1 | i2c_ack2 | i2c_ack3); + //I2C Read: {ID_Address + REG_Address} + {ID_Address + R_REG_Data} + I2C_RD_ACK1: i2c_ack1 <= i2c_sdat_IN; + I2C_RD_ACK2: i2c_ack2 <= i2c_sdat_IN; + I2C_RD_ACK3: i2c_ack3 <= i2c_sdat_IN; + I2C_RD_STOP2: i2c_ack <= (i2c_ack1 | i2c_ack2 | i2c_ack3); + I2C_RD_REGDATA: i2c_rdata <= {i2c_rdata[6:0], i2c_sdat_IN}; + endcase + end + else + begin + {i2c_ack1, i2c_ack2, i2c_ack3} <= {i2c_ack1, i2c_ack2, i2c_ack3}; + i2c_ack <= i2c_ack; + end +end + +//--------------------------------------------------- +wire bir_en =( current_state == I2C_WR_ACK1 || current_state == I2C_WR_ACK2 || current_state == I2C_WR_ACK3 || + current_state == I2C_RD_ACK1 || current_state == I2C_RD_ACK2 || current_state == I2C_RD_ACK3 || + current_state == I2C_RD_REGDATA) ? 1'b1 : 1'b0; +// wire bir_en =( current_state == I2C_WR_ACK1 || current_state == I2C_WR_ACK2 || current_state == I2C_WR_ACK3 ) ? 1'b1 : 1'b0; +assign i2c_sclk = (current_state >= I2C_WR_IDADDR && current_state <= I2C_WR_ACK3 || + current_state >= I2C_RD_IDADDR1 && current_state <= I2C_RD_ACK2 || + current_state >= I2C_RD_IDADDR2 && current_state <= I2C_RD_NACK) ? + i2c_ctrl_clk : 1'b1; +// assign i2c_sclk = (current_state >= I2C_WR_IDADDR && current_state <= I2C_WR_ACK3 ) ? i2c_ctrl_clk : 1'b1; +//assign i2c_sdat = (~bir_en) ? i2c_sdat_out : 1'bz; +assign i2c_sdat_OUT = i2c_sdat_out; +assign i2c_sdat_OE = ~bir_en; + + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/axi/AXI4_AWARMux.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/axi/AXI4_AWARMux.v new file mode 100644 index 0000000000000000000000000000000000000000..cadbff616517f9059e03c09637588e020cdc2220 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/axi/AXI4_AWARMux.v @@ -0,0 +1,113 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Create Date: 15:58:46 04/08/2023 +// Module Name: AXI4_AWARMux +////////////////////////////////////////////////////////////////////////////////// + +// AXI4 AW / AR Path Mux. +// This module works with Efinix AXI4-Modified Interface. +// atype_o = 1 for DDR Write, and atype_o = 0 for DDR Read. + +module AXI4_AWARMux #( + parameter AID_LEN = 8, + AADDR_LEN = 32 +)( + input aclk_i, + input arst_i, + + // AW + input [AID_LEN-1:0] awid_i, + input [AADDR_LEN-1:0] awaddr_i, + input [7:0] awlen_i, + input awvalid_i, + output reg awready_o, + + // AR + input [AID_LEN-1:0] arid_i, + input [AADDR_LEN-1:0] araddr_i, + input [7:0] arlen_i, + input arvalid_i, + output reg arready_o, + + // A + output [AID_LEN-1:0] aid_o, + output [AADDR_LEN-1:0] aaddr_o, + output [7:0] alen_o, + output atype_o, + output reg avalid_o, + input aready_i +); + + // R/W Wrapper. atype_o = 1 for DDR Write, and atype_o = 0 for DDR Read. + // Assert R/W in round robin mode. + reg [1:0] rs_req = 0; // DDR3 Request State Machine + wire [1:0] ws_req_idle = 0; + wire [1:0] ws_req_bridge = 1; + wire [1:0] ws_req_inc = 2; + + reg r_reqtype = 0; // Type = 0 for read, and type = 1 for write. Toggle when aready. + reg r_reqen = 0; // Request En + + always @(posedge aclk_i) begin + // Clear AREADY by default. + arready_o <= 0; + awready_o <= 0; + + case (rs_req) + ws_req_idle: begin + // By default toggle reqtype when no commands. + rs_req <= ws_req_inc; + + // Type = 0 for read. + if(r_reqtype == 0) begin + // When read request, bridge to AR path. + if(arvalid_i) begin + avalid_o <= 1; + rs_req <= ws_req_bridge; + end else begin + end + end else begin + // When write request, bridge to AR path. + if(awvalid_i) begin + avalid_o <= 1; + rs_req <= ws_req_bridge; + end else begin + end + end + end + ws_req_bridge: begin + if(aready_i) begin + avalid_o <= 0; + + // Respond to AR / AW. + arready_o <= (r_reqtype == 0); + awready_o <= (r_reqtype == 1); + rs_req <= ws_req_inc; + end else begin + end + end + ws_req_inc: begin + r_reqtype <= r_reqtype + 1; + rs_req <= ws_req_idle; + end + endcase + + if(arst_i) begin + rs_req <= 0; + r_reqtype <= 0; + r_reqen <= 0; + + //awready_o <= 0; + //arready_o <= 0; + avalid_o <= 0; + end else begin + end + end + + // Type = 0 for read. Bridge to AR path. + assign aid_o = (r_reqtype == 0) ? arid_i : awid_i; + assign aaddr_o = (r_reqtype == 0) ? araddr_i : awaddr_i; + assign alen_o = (r_reqtype == 0) ? arlen_i : awlen_i; + assign atype_o = r_reqtype; + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/axi/axi4_ctrl.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/axi/axi4_ctrl.v new file mode 100644 index 0000000000000000000000000000000000000000..fe082a2e67f9f4fae2ff3ac3ed5aa0d3e42f5feb --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/axi/axi4_ctrl.v @@ -0,0 +1,667 @@ +// by CrazyBird +module axi4_ctrl #( + parameter C_ID_LEN = 4, + C_DATA_LEN = 128, + C_DATA_SIZE = 4, // C_DATA_LEN=8:0, 16:1, 32:2, 64:3, 128:4, 256:5, 512:6, 1024:7 + + C_BURST_LEN = 128, + + C_STRB_LEN = C_DATA_LEN / 8, + C_ADDR_INC = C_BURST_LEN * C_STRB_LEN, + +// C_BASE_ADDR = 32'h00000000, // Start at 0x00000000 by default + C_BUF_SIZE = 24, // Allocate 2^22 bytes (4MB) by default. The module takes 4*4MB by default. +// C_RD_END_ADDR = 1280 * 720, + + C_W_WIDTH = 32, + C_R_WIDTH = 32 +)( + input wire axi_clk , + input wire axi_reset , + + output [C_ID_LEN-1:0] axi_awid , + output [31:0] axi_awaddr , + output [ 7:0] axi_awlen , + output [ 2:0] axi_awsize , + output [ 1:0] axi_awburst , + output axi_awlock , + output [ 3:0] axi_awcache , + output [ 2:0] axi_awprot , + output [ 3:0] axi_awqos , + output reg axi_awvalid , + input wire axi_awready , + + output [C_DATA_LEN-1:0] axi_wdata , + output [C_STRB_LEN-1:0] axi_wstrb , + output axi_wlast , + output reg axi_wvalid , + input wire axi_wready , + + input wire [C_ID_LEN-1:0] axi_bid , + input wire [ 1:0] axi_bresp , + input wire axi_bvalid , + output axi_bready , + + output [C_ID_LEN-1:0] axi_arid , + output [31:0] axi_araddr , + output [ 7:0] axi_arlen , + output [ 2:0] axi_arsize , + output [ 1:0] axi_arburst , + output axi_arlock , + output [ 3:0] axi_arcache , + output [ 2:0] axi_arprot , + output [ 3:0] axi_arqos , + output reg axi_arvalid , + input wire axi_arready , + + input wire [C_ID_LEN-1:0] axi_rid , + input wire [C_DATA_LEN-1:0] axi_rdata , + input wire [ 1:0] axi_rresp , + input wire axi_rlast , + input wire axi_rvalid , + output axi_rready , + + input wire wframe_pclk , + input wire wframe_vsync , // Writter VSync. Flush on falling edge. Connect to EOF. + input wire wframe_data_en , + input wire [C_W_WIDTH-1:0] wframe_data , + + input wire rframe_pclk , + input wire rframe_vsync , // Reader VSync. Flush on falling edge. Connect to ~EOF. + input wire rframe_data_en , + output wire [C_R_WIDTH-1:0] rframe_data , + + output [31:0] tp_o, + + input wire [31:0] W_C_BASE_ADDR, + input wire [31:0] R_C_BASE_ADDR, + //input wire [31:0] w_C_RD_END_ADDR, + input wire [31:0] R_C_RD_END_ADDR, + + output wire w_full_o, + output wire r_full_o +); + + initial begin + axi_awvalid <= 0; + axi_wvalid <= 0; + axi_arvalid <= 0; + end + + assign axi_awid = {C_ID_LEN{1'b0}}; + assign axi_awlen = C_BURST_LEN - 1'b1; + assign axi_awsize = C_DATA_SIZE; + assign axi_awburst = 2'b01; // INCR + assign axi_awlock = 1'b0; + assign axi_awcache = 0; + assign axi_awprot = 3'b0; + assign axi_awqos = 4'b0; + assign axi_wstrb = 32'hFFFFFFFF; + assign axi_bready = 1; + + assign axi_arid = {C_ID_LEN{1'b0}}; + assign axi_arlen = C_BURST_LEN - 1'b1; + assign axi_arsize = C_DATA_SIZE; + assign axi_arburst = 2'b01; // INCR + assign axi_arlock = 1'b0; + assign axi_arcache = 0; + assign axi_arprot = 3'b0; + assign axi_arqos = 4'b0; + assign axi_rready = 1; + + + + + //////////////////////////////////////////////////////////////// + // R/W Schedule + reg [1:0] rc_wframe_index; + reg [1:0] rc_rframe_index; + + // Use 4 data buffers to simplify control. + wire [1:0] w_wframe_index_p1 = rc_wframe_index + 1; + wire [1:0] w_wframe_index_next = (w_wframe_index_p1 == rc_rframe_index) ? rc_wframe_index + 2 : rc_wframe_index + 1; + + reg [1:0] r_wframe_index_last = 0; + + reg r_wframe_inc = 0, r_rframe_inc = 0; + + always @(posedge axi_clk) begin + if(axi_reset) begin + rc_wframe_index <= 2'b0; + rc_rframe_index <= 2'd2; + r_wframe_index_last <= 0; + + end else begin + rc_wframe_index <= rc_wframe_index; + rc_rframe_index <= rc_rframe_index; + + // When wfifo_rd_rst_busy_neg, write pointer increments. When rfifo_wr_rst_busy_neg, read pointer increments. + case ({r_rframe_inc, r_wframe_inc}) + 2'b01: begin + // Write increment only. + rc_wframe_index <= w_wframe_index_next; // Use 4 buffers. + r_wframe_index_last <= rc_wframe_index; + end + 2'b10: begin + // Use r_wframe_index_last. + rc_rframe_index <= r_wframe_index_last; + end + 2'b11: begin + // Update write & read pointer simutaneously. + rc_wframe_index <= w_wframe_index_next; // Use 4 buffers. + rc_rframe_index <= rc_wframe_index; + end + endcase + + end + end + + + + //////////////////////////////////////////////////////////////// + // AXI Writter + + wire w_wfifo_pempty, w_wfifo_empty; + wire w_wfifo_ren; + wire [C_DATA_LEN-1:0] w_wfifo_rdata; + + // On EOF when ~empty, flush the last data then reset FIFO. + reg [3:0] rs_w = 0; + wire [3:0] ws_w_idle = 0; + wire [3:0] ws_w_wdata = 1; + wire [3:0] ws_w_winc = 2; + wire [3:0] ws_w_eof = 3; + + // Write Pointer. Burst bytes is always C_ADDR_INC. + reg [C_BUF_SIZE-1:0] rc_w_ptr = 0; + reg [0:0] rc_w_eof = 0; + reg r_w_rst = 1; + + // Burst Control + reg [7:0] rc_burst = 0; // Compare to C_BURST_LEN - 1. + + // EOF Monitor. + reg [1:0] r_wframe_sync = 0; + reg r_weof_pending = 0; + + always @(posedge axi_clk or posedge axi_reset) begin + if(axi_reset) begin + rs_w <= 0; + rc_w_ptr <= 0; + rc_w_eof <= 0; + r_w_rst <= 1; + axi_awvalid <= 0; + axi_wvalid <= 0; + r_wframe_sync <= 0; + r_weof_pending <= 0; + r_wframe_inc <= 0; + + end else begin + rc_w_eof <= 0; + r_wframe_inc <= 0; + + // Raise EOF on falling edge of VSYNC. + r_wframe_sync <= {r_wframe_sync, wframe_vsync}; + if(r_wframe_sync == 2'b10) begin + r_weof_pending <= 1; + end else begin + end + + if(axi_awready) begin + axi_awvalid <= 0; + end else begin + end + + case (rs_w) + ws_w_idle: begin + rc_burst <= 0; + r_w_rst <= 0; + + if(~w_wfifo_pempty) begin + axi_awvalid <= 1; + axi_wvalid <= 1; + rs_w <= ws_w_wdata; + + end else if(r_weof_pending && (~w_wfifo_empty)) begin + // There's some data in the FIFO. write last. + axi_awvalid <= 1; + axi_wvalid <= 1; + rs_w <= ws_w_wdata; + + end else if(r_weof_pending) begin + // EOF. Reset FIFO. Increment write pointer. + r_w_rst <= 1; + r_wframe_inc <= 1; + rs_w <= ws_w_eof; + + end else begin + end + end + + ws_w_eof: begin + // Wait for some cycles to release reset. + r_weof_pending <= 0; + rc_w_ptr <= 0; + + rc_w_eof <= rc_w_eof + 1; + if(&rc_w_eof) + rs_w <= ws_w_idle; + else begin + end + end + + ws_w_wdata: begin + rc_burst <= rc_burst + axi_wready; + + // On last transaction terminate write. + if(axi_wlast && axi_wready) begin + axi_wvalid <= 0; + rs_w <= ws_w_winc; + end else begin + end + end + + ws_w_winc: begin + rc_w_ptr <= rc_w_ptr + C_ADDR_INC; + rs_w <= ws_w_idle; + end + endcase + end + end + assign axi_awaddr = W_C_BASE_ADDR + {rc_wframe_index, rc_w_ptr}; + assign axi_wdata = w_wfifo_rdata; + assign axi_wlast = (rc_burst >= C_BURST_LEN - 1); + + assign w_wfifo_ren = axi_wvalid && axi_wready; + + + assign tp_o[1:0] = {rs_w[1:0]}; + assign tp_o[2] = axi_wvalid; + assign tp_o[3] = wframe_data_en; + + + // generate + // if(C_W_WIDTH == 64) begin: Gen_FIFO_W64 + // W0_FIFO_64 u_W0_FIFO_64 + // ( + // .wr_clk_i (wframe_pclk ), + // .wr_en_i (wframe_data_en), + // .wdata (wframe_data ), + + // .a_rst_i (r_w_rst), + + // .rd_clk_i (axi_clk ), + // .rd_en_i (w_wfifo_ren ), + // .rdata (w_wfifo_rdata ), + // .prog_empty_o (w_wfifo_pempty), + // .empty_o (w_wfifo_empty) + // ); + // end else if(C_W_WIDTH == 32) begin: Gen_FIFO_W32 + // W0_FIFO_32 u_W0_FIFO_32 + // ( + // .wr_clk_i (wframe_pclk ), + // .wr_en_i (wframe_data_en), + // .wdata (wframe_data ), + + // .a_rst_i (r_w_rst), + + // .rd_clk_i (axi_clk ), + // .rd_en_i (w_wfifo_ren ), + // .rdata (w_wfifo_rdata ), + // .prog_empty_o (w_wfifo_pempty), + // .empty_o (w_wfifo_empty) + // ); + // end else if(C_W_WIDTH == 8) begin: Gen_FIFO_W8 + // W0_FIFO_8 u_W0_FIFO_8 + // ( + // .wr_clk_i (wframe_pclk ), + // .wr_en_i (wframe_data_en), + // .wdata (wframe_data ), + + // .a_rst_i (r_w_rst), + + // .rd_clk_i (axi_clk ), + // .rd_en_i (w_wfifo_ren ), + // .rdata (w_wfifo_rdata ), + // .prog_empty_o (w_wfifo_pempty), + // .empty_o (w_wfifo_empty) + // ); + // end + // endgenerate + + W0_FIFO_32 u_W0_FIFO_32 + ( + .wr_clk_i (wframe_pclk ), + .wr_en_i (wframe_data_en), + .wdata (wframe_data ), + + .a_rst_i (r_w_rst), + + .rd_clk_i (axi_clk ), + .rd_en_i (w_wfifo_ren ), + .rdata (w_wfifo_rdata ), + .prog_empty_o (w_wfifo_pempty), + .empty_o (w_wfifo_empty), + + .full_o(w_full_o) + ); + + + + + + + + + + + + + + + + + + + +reg rframe_vsync_dly; + +always @(posedge rframe_pclk) +begin + if(axi_reset == 1'b1) + rframe_vsync_dly <= 1'b0; + else + rframe_vsync_dly <= rframe_vsync; +end + +wire rframe_vsync_neg; +assign rframe_vsync_neg = rframe_vsync_dly & ~rframe_vsync; + +reg [4:0] rfifo_cnt; + +always @(posedge rframe_pclk) +begin + if(axi_reset == 1'b1) + rfifo_cnt <= 5'h1f; + else + begin + if(rframe_vsync_neg == 1'b1) + rfifo_cnt <= 5'h1f; + else if(rfifo_cnt > 5'd0) + rfifo_cnt <= rfifo_cnt - 1'b1; + else + rfifo_cnt <= 5'b0; + end +end + +reg rfifo_rst; + +always @(posedge rframe_pclk) +begin + if(axi_reset == 1'b1) + rfifo_rst <= 1'b1; + else + begin + if(rfifo_cnt == 5'b0) + rfifo_rst <= 1'b0; + else + rfifo_rst <= 1'b1; + end +end + + +wire w_rfifo_rst = axi_reset || rfifo_rst; + +reg rfifo_wenb; +reg [C_DATA_LEN-1:0] rfifo_wdata; +wire [ 9:0] rfifo_wcnt; +wire rfifo_wfull; +wire rfifo_wr_rst_busy; +wire w_rfifo_aempty; +wire w_rfifo_empty; + + +// generate +// if(C_R_WIDTH == 8) begin: Gen_RFIFO_8 +// R0_FIFO_8 u_R0_FIFO_8 +// ( +// .wr_clk_i (axi_clk), +// .wr_en_i (rfifo_wenb), +// .wdata (rfifo_wdata), +// .a_rst_i (w_rfifo_rst), +// .prog_full_o (rfifo_wfull), + +// .rd_clk_i (rframe_pclk), +// .rd_en_i (rframe_data_en), +// .rdata (rframe_data), +// .empty_o (w_rfifo_empty), +// .almost_empty_o (w_rfifo_aempty) +// ); +// end else if(C_R_WIDTH == 16) begin: Gen_RFIFO_16 +// R0_FIFO_16 u_R0_FIFO_16 +// ( +// .wr_clk_i (axi_clk), +// .wr_en_i (rfifo_wenb), +// .wdata (rfifo_wdata), +// .a_rst_i (w_rfifo_rst), +// .prog_full_o (rfifo_wfull), + +// .rd_clk_i (rframe_pclk), +// .rd_en_i (rframe_data_en), +// .rdata (rframe_data), +// .empty_o (w_rfifo_empty), +// .almost_empty_o (w_rfifo_aempty) +// ); +// end else if(C_R_WIDTH == 32) begin: Gen_RFIFO_32 +// R0_FIFO_32 u_R0_FIFO_32 +// ( +// .wr_clk_i (axi_clk), +// .wr_en_i (rfifo_wenb), +// .wdata (rfifo_wdata), +// .a_rst_i (w_rfifo_rst), +// .prog_full_o (rfifo_wfull), + +// .rd_clk_i (rframe_pclk), +// .rd_en_i (rframe_data_en), +// .rdata (rframe_data), +// .empty_o (w_rfifo_empty), +// .almost_empty_o (w_rfifo_aempty) +// ); +// end +// endgenerate + + R0_FIFO_32 u_R0_FIFO_32 + ( + .wr_clk_i (axi_clk), + .wr_en_i (rfifo_wenb), + .wdata (rfifo_wdata), + .a_rst_i (w_rfifo_rst), + .prog_full_o (rfifo_wfull), + + .rd_clk_i (rframe_pclk), + .rd_en_i (rframe_data_en), + .rdata (rframe_data), + .empty_o (w_rfifo_empty), + .almost_empty_o (w_rfifo_aempty), + + .full_o(r_full_o) + ); + + + + +reg r_rfifo_rst = 0; +always @(posedge axi_clk) +begin + r_rfifo_rst <= w_rfifo_rst; +end + +//assign tp_o[7:0] = {w_rfifo_empty, rfifo_wfull, rframe_data_en, rfifo_wenb, rfifo_rst, axi_reset, rframe_pclk, axi_clk}; + +reg [15:0] rfifo_wr_rst_busy_dly = 2'b0; + +always @(posedge axi_clk or posedge r_rfifo_rst) +begin + if(r_rfifo_rst == 1'b1) + rfifo_wr_rst_busy_dly <= 0; + else + rfifo_wr_rst_busy_dly <= {rfifo_wr_rst_busy_dly,1'b1}; +end + +wire rfifo_wr_rst_busy_neg; +assign rfifo_wr_rst_busy_neg = (rfifo_wr_rst_busy_dly[1:0] == 2'b01) ? 1'b1 : 1'b0; + +reg [4:0] read_ddr_delay_cnt; + +always @(posedge axi_clk or posedge r_rfifo_rst) +begin + if(r_rfifo_rst == 1'b1) + read_ddr_delay_cnt <= 5'b0; + else + begin + if(rfifo_wr_rst_busy_neg == 1'b1) + read_ddr_delay_cnt <= 5'd31; + else if(read_ddr_delay_cnt > 5'b0) + read_ddr_delay_cnt <= read_ddr_delay_cnt - 1'b1; + else + read_ddr_delay_cnt <= 5'b0; + end +end + +always @(posedge axi_clk or posedge axi_reset) begin + if(axi_reset) + r_rframe_inc <= 0; + else + r_rframe_inc <= rfifo_wr_rst_busy_neg; +end + + +wire read_ddr_init_flag; +assign read_ddr_init_flag = (read_ddr_delay_cnt == 5'd1) ? 1'b1 : 1'b0; + +//---------------------------------------------------------------------- + + + + +//---------------------------------------------------------------------- +localparam S_READ_IDLE = 2'd0; +localparam S_READ_ADDR = 2'd1; +localparam S_READ_DATA = 2'd2; + +reg [ 1:0] rd_state; +reg [ 8:0] rdata_cnt; +reg [C_BUF_SIZE-1:0] araddr; +reg r_rd_pend = 0; + + +always @(posedge axi_clk or posedge r_rfifo_rst) +begin + if(r_rfifo_rst) begin + rd_state <= S_READ_IDLE; + axi_arvalid <= 0; + r_rd_pend <= 0; + end else + begin + + + + if(axi_arready) begin + axi_arvalid <= 0; + end else begin + end + if(axi_rvalid && axi_rlast) begin + r_rd_pend <= 0; + end else begin + end + + case(rd_state) + S_READ_IDLE : + begin + // Continue if RFIFO ~Full. + if(rfifo_wr_rst_busy_dly[15] && (araddr < R_C_RD_END_ADDR)&&(~rfifo_wfull)) begin // rfifo_wcnt < 10'd256)) + rd_state <= S_READ_ADDR; + end else + rd_state <= S_READ_IDLE; + end + + S_READ_ADDR : + begin + axi_arvalid <= 1; + r_rd_pend <= 1; + rd_state <= S_READ_DATA; + end + S_READ_DATA : + begin + // Return when ~arvalid && ~rd_pend. + if((~axi_arvalid) && (~r_rd_pend)) + //if((axi_rvalid == 1'b1)&&(axi_rready == 1'b1)&&(rdata_cnt == C_BURST_LEN)) + rd_state <= S_READ_IDLE; + else + rd_state <= S_READ_DATA; + end + default : + begin + rd_state <= S_READ_IDLE; + end + endcase + end +end + +always @(posedge axi_clk or posedge r_rfifo_rst) +begin + if(r_rfifo_rst == 1'b1) + araddr <= 0; + else + begin + if((axi_arvalid == 1'b1)&&(axi_arready == 1'b1)) + araddr <= araddr + C_ADDR_INC; + else + araddr <= araddr; + end +end + +assign axi_araddr = R_C_BASE_ADDR + {rc_rframe_index, araddr}; + + +reg [8:0] rdata_cnt_dly; + +always @(posedge axi_clk) +begin + rdata_cnt_dly <= rdata_cnt; +end + +always @(*) +begin + if(rd_state == S_READ_DATA) + begin + if((axi_rvalid == 1'b1)&&(axi_rready == 1'b1)) + rdata_cnt = rdata_cnt_dly + 1'b1; + else + rdata_cnt = rdata_cnt_dly; + end + else + rdata_cnt = 9'b0; +end + +assign axi_rready = 1; + +always @(posedge axi_clk) +begin + if(axi_reset == 1'b1) + rfifo_wenb <= 1'b0; + else + begin + if((axi_rvalid == 1'b1)&&(axi_rready == 1'b1)) + rfifo_wenb <= 1'b1; + else + rfifo_wenb <= 1'b0; + end +end + +always @(posedge axi_clk) +begin + rfifo_wdata <= axi_rdata; +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/axi/axi4_ctrl_tb.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/axi/axi4_ctrl_tb.v new file mode 100644 index 0000000000000000000000000000000000000000..0acf8bb8e8706ad97d82fa489ada5bd8e9823a3d --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/axi/axi4_ctrl_tb.v @@ -0,0 +1,185 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:42:17 05/27/2023 +// Design Name: axi4_ctrl +// Module Name: D:/SVN_Path/DevKitProjects/PH100/Dev/08_CMOS_AR0135_HDMI_720P/src/axi4_ctrl_tb.v +// Project Name: CMOS_AR0135_HDMI_720P +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: axi4_ctrl +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module axi4_ctrl_tb; + + // Inputs + reg axi_clk; + reg axi_reset; + reg axi_awready; + reg axi_wready; + reg [3:0] axi_bid; + reg [1:0] axi_bresp; + reg axi_bvalid; + reg axi_arready; + reg [3:0] axi_rid; + reg [127:0] axi_rdata; + reg [1:0] axi_rresp; + reg axi_rlast; + reg axi_rvalid; + reg wframe_pclk; + reg wframe_vsync; + reg wframe_data_en; + reg [63:0] wframe_data; + reg rframe_pclk; + reg rframe_vsync; + reg rframe_data_en; + + // Outputs + wire [3:0] axi_awid; + wire [29:0] axi_awaddr; + wire [3:0] axi_awlen; + wire [2:0] axi_awsize; + wire [1:0] axi_awburst; + wire axi_awlock; + wire [3:0] axi_awcache; + wire [2:0] axi_awprot; + wire [3:0] axi_awqos; + wire axi_awvalid; + wire [127:0] axi_wdata; + wire [15:0] axi_wstrb; + wire axi_wlast; + wire axi_wvalid; + wire axi_bready; + wire [3:0] axi_arid; + wire [29:0] axi_araddr; + wire [3:0] axi_arlen; + wire [2:0] axi_arsize; + wire [1:0] axi_arburst; + wire axi_arlock; + wire [3:0] axi_arcache; + wire [2:0] axi_arprot; + wire [3:0] axi_arqos; + wire axi_arvalid; + wire axi_rready; + wire [15:0] rframe_data; + + // Instantiate the Unit Under Test (UUT) + axi4_ctrl #(.C_W_WIDTH(32), .C_R_WIDTH(16)) uut ( + .axi_clk(axi_clk), + .axi_reset(axi_reset), + .axi_awid(axi_awid), + .axi_awaddr(axi_awaddr), + .axi_awlen(axi_awlen), + .axi_awsize(axi_awsize), + .axi_awburst(axi_awburst), + .axi_awlock(axi_awlock), + .axi_awcache(axi_awcache), + .axi_awprot(axi_awprot), + .axi_awqos(axi_awqos), + .axi_awvalid(axi_awvalid), + .axi_awready(axi_awready), + .axi_wdata(axi_wdata), + .axi_wstrb(axi_wstrb), + .axi_wlast(axi_wlast), + .axi_wvalid(axi_wvalid), + .axi_wready(axi_wready), + .axi_bid(axi_bid), + .axi_bresp(axi_bresp), + .axi_bvalid(axi_bvalid), + .axi_bready(axi_bready), + .axi_arid(axi_arid), + .axi_araddr(axi_araddr), + .axi_arlen(axi_arlen), + .axi_arsize(axi_arsize), + .axi_arburst(axi_arburst), + .axi_arlock(axi_arlock), + .axi_arcache(axi_arcache), + .axi_arprot(axi_arprot), + .axi_arqos(axi_arqos), + .axi_arvalid(axi_arvalid), + .axi_arready(axi_arready), + .axi_rid(axi_rid), + .axi_rdata(axi_rdata), + .axi_rresp(axi_rresp), + .axi_rlast(axi_rlast), + .axi_rvalid(axi_rvalid), + .axi_rready(axi_rready), + .wframe_pclk(wframe_pclk), + .wframe_vsync(wframe_vsync), + .wframe_data_en(wframe_data_en), + .wframe_data(wframe_data), + .rframe_pclk(rframe_pclk), + .rframe_vsync(rframe_vsync), + .rframe_data_en(rframe_data_en), + .rframe_data(rframe_data) + ); + + initial begin + // Initialize Inputs + axi_clk = 0; + axi_reset = 1; + axi_awready = 1; + axi_wready = 1; + axi_bid = 0; + axi_bresp = 0; + axi_bvalid = 1; + axi_arready = 0; + axi_rid = 0; + axi_rdata = 0; + axi_rresp = 0; + axi_rlast = 0; + axi_rvalid = 0; + wframe_pclk = 0; + wframe_vsync = 0; + wframe_data_en = 0; + wframe_data = 0; + rframe_pclk = 0; + rframe_vsync = 0; + rframe_data_en = 0; + + // Wait 100 ns for global reset to finish + #100; axi_reset = 0; #96; + + // Add stimulus here + + end + + always #5 axi_clk = ~axi_clk; + always #5 wframe_pclk = ~wframe_pclk; + always #5 rframe_pclk = ~rframe_pclk; + + always @(posedge axi_clk) begin + if(axi_arvalid) begin + #41; axi_arready = 1; #10; axi_arready = 0; #80; axi_rvalid = 1; #1270; axi_rlast = 1; #10; axi_rlast = 0; axi_rvalid = 0; #60; + end else begin + end + end + + always begin + #6400; + wframe_vsync = 1; #50; wframe_data_en = 1; #25620; wframe_data_en = 0; #640; wframe_vsync = 0; + end + always begin + #6400; + rframe_vsync = 1; #12800; rframe_data_en = 1; #128000; rframe_vsync = 0; rframe_data_en = 0; + end + always @(posedge wframe_pclk) begin + if(wframe_data_en) #1 wframe_data <= wframe_data + 1; + end + + //GTP_GRS GRS_INST (.GRS_N(~axi_reset)); + +endmodule + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/encode.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/encode.v new file mode 100644 index 0000000000000000000000000000000000000000..0aa0c838bda063e4e2151c6ba1866a41eced15c9 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/encode.v @@ -0,0 +1,191 @@ +////////////////////////////////////////////////////////////////////////////// +// +// Xilinx, Inc. 2008 www.xilinx.com +// +////////////////////////////////////////////////////////////////////////////// +// +// File name : encode.v +// +// Description : TMDS encoder +// +// Date - revision : Jan. 2008 - v 1.0 +// +// Author : Bob Feng +// +// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are +// provided to you "as is". Xilinx and its licensors make and you +// receive no warranties or conditions, express, implied, +// statutory or otherwise, and Xilinx specifically disclaims any +// implied warranties of merchantability, non-infringement,or +// fitness for a particular purpose. Xilinx does not warrant that +// the functions contained in these designs will meet your +// requirements, or that the operation of these designs will be +// uninterrupted or error free, or that defects in the Designs +// will be corrected. Furthermore, Xilinx does not warrantor +// make any representations regarding use or the results of the +// use of the designs in terms of correctness, accuracy, +// reliability, or otherwise. +// +// LIMITATION OF LIABILITY. In no event will Xilinx or its +// licensors be liable for any loss of data, lost profits,cost +// or procurement of substitute goods or services, or for any +// special, incidental, consequential, or indirect damages +// arising from the use or operation of the designs or +// accompanying documentation, however caused and on any theory +// of liability. This limitation will apply even if Xilinx +// has been advised of the possibility of such damage. This +// limitation shall apply not-withstanding the failure of the +// essential purpose of any limited remedies herein. +// +// Copyright 2006 Xilinx, Inc. +// All rights reserved +// +////////////////////////////////////////////////////////////////////////////// +`timescale 1ns/1ps + +module encode ( + input clkin, // pixel clock input + input rstin, // async. reset input (active high) + input [7:0] din, // data inputs: expect registered + input c0, // c0 input + input c1, // c1 input + input de, // de input + output reg [9:0] dout // data outputs +); + + //////////////////////////////////////////////////////////// + // Counting number of 1s and 0s for each incoming pixel + // component. Pipe line the result. + // Register Data Input so it matches the pipe lined adder + // output + //////////////////////////////////////////////////////////// + reg [3:0] n1d; //number of 1s in din + reg [7:0] din_q; + + always @ (posedge clkin) begin + n1d <=#1 din[0] + din[1] + din[2] + din[3] + din[4] + din[5] + din[6] + din[7]; + + din_q <=#1 din; + end + + /////////////////////////////////////////////////////// + // Stage 1: 8 bit -> 9 bit + // Refer to DVI 1.0 Specification, page 29, Figure 3-5 + /////////////////////////////////////////////////////// + wire decision1; + + assign decision1 = (n1d > 4'h4) | ((n1d == 4'h4) & (din_q[0] == 1'b0)); +/* + reg [8:0] q_m; + always @ (posedge clkin) begin + q_m[0] <=#1 din_q[0]; + q_m[1] <=#1 (decision1) ? (q_m[0] ^~ din_q[1]) : (q_m[0] ^ din_q[1]); + q_m[2] <=#1 (decision1) ? (q_m[1] ^~ din_q[2]) : (q_m[1] ^ din_q[2]); + q_m[3] <=#1 (decision1) ? (q_m[2] ^~ din_q[3]) : (q_m[2] ^ din_q[3]); + q_m[4] <=#1 (decision1) ? (q_m[3] ^~ din_q[4]) : (q_m[3] ^ din_q[4]); + q_m[5] <=#1 (decision1) ? (q_m[4] ^~ din_q[5]) : (q_m[4] ^ din_q[5]); + q_m[6] <=#1 (decision1) ? (q_m[5] ^~ din_q[6]) : (q_m[5] ^ din_q[6]); + q_m[7] <=#1 (decision1) ? (q_m[6] ^~ din_q[7]) : (q_m[6] ^ din_q[7]); + q_m[8] <=#1 (decision1) ? 1'b0 : 1'b1; + end +*/ + wire [8:0] q_m; + assign q_m[0] = din_q[0]; + assign q_m[1] = (decision1) ? (q_m[0] ^~ din_q[1]) : (q_m[0] ^ din_q[1]); + assign q_m[2] = (decision1) ? (q_m[1] ^~ din_q[2]) : (q_m[1] ^ din_q[2]); + assign q_m[3] = (decision1) ? (q_m[2] ^~ din_q[3]) : (q_m[2] ^ din_q[3]); + assign q_m[4] = (decision1) ? (q_m[3] ^~ din_q[4]) : (q_m[3] ^ din_q[4]); + assign q_m[5] = (decision1) ? (q_m[4] ^~ din_q[5]) : (q_m[4] ^ din_q[5]); + assign q_m[6] = (decision1) ? (q_m[5] ^~ din_q[6]) : (q_m[5] ^ din_q[6]); + assign q_m[7] = (decision1) ? (q_m[6] ^~ din_q[7]) : (q_m[6] ^ din_q[7]); + assign q_m[8] = (decision1) ? 1'b0 : 1'b1; + + ///////////////////////////////////////////////////////// + // Stage 2: 9 bit -> 10 bit + // Refer to DVI 1.0 Specification, page 29, Figure 3-5 + ///////////////////////////////////////////////////////// + reg [3:0] n1q_m, n0q_m; // number of 1s and 0s for q_m + always @ (posedge clkin) begin + n1q_m <=#1 q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7]; + n0q_m <=#1 4'h8 - (q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7]); + end + + parameter CTRLTOKEN0 = 10'b1101010100; + parameter CTRLTOKEN1 = 10'b0010101011; + parameter CTRLTOKEN2 = 10'b0101010100; + parameter CTRLTOKEN3 = 10'b1010101011; + + reg [4:0] cnt; //disparity counter, MSB is the sign bit + wire decision2, decision3; + + assign decision2 = (cnt == 5'h0) | (n1q_m == n0q_m); + ///////////////////////////////////////////////////////////////////////// + // [(cnt > 0) and (N1q_m > N0q_m)] or [(cnt < 0) and (N0q_m > N1q_m)] + ///////////////////////////////////////////////////////////////////////// + assign decision3 = (~cnt[4] & (n1q_m > n0q_m)) | (cnt[4] & (n0q_m > n1q_m)); + + //////////////////////////////////// + // pipe line alignment + //////////////////////////////////// + reg de_q, de_reg; + reg c0_q, c1_q; + reg c0_reg, c1_reg; + reg [8:0] q_m_reg; + + always @ (posedge clkin) begin + de_q <=#1 de; + de_reg <=#1 de_q; + + c0_q <=#1 c0; + c0_reg <=#1 c0_q; + c1_q <=#1 c1; + c1_reg <=#1 c1_q; + + q_m_reg <=#1 q_m; + end + + /////////////////////////////// + // 10-bit out + // disparity counter + /////////////////////////////// + always @ (posedge clkin or posedge rstin) begin + if(rstin) begin + dout <= 10'h0; + cnt <= 5'h0; + end else begin + if (de_reg) begin + if(decision2) begin + dout[9] <=#1 ~q_m_reg[8]; + dout[8] <=#1 q_m_reg[8]; + dout[7:0] <=#1 (q_m_reg[8]) ? q_m_reg[7:0] : ~q_m_reg[7:0]; + + cnt <=#1 (~q_m_reg[8]) ? (cnt + n0q_m - n1q_m) : (cnt + n1q_m - n0q_m); + end else begin + if(decision3) begin + dout[9] <=#1 1'b1; + dout[8] <=#1 q_m_reg[8]; + dout[7:0] <=#1 ~q_m_reg[7:0]; + + cnt <=#1 cnt + {q_m_reg[8], 1'b0} + (n0q_m - n1q_m); + end else begin + dout[9] <=#1 1'b0; + dout[8] <=#1 q_m_reg[8]; + dout[7:0] <=#1 q_m_reg[7:0]; + + cnt <=#1 cnt - {~q_m_reg[8], 1'b0} + (n1q_m - n0q_m); + end + end + end else begin + case ({c1_reg, c0_reg}) + 2'b00: dout <=#1 CTRLTOKEN0; + 2'b01: dout <=#1 CTRLTOKEN1; + 2'b10: dout <=#1 CTRLTOKEN2; + default: dout <=#1 CTRLTOKEN3; + endcase + + cnt <=#1 5'h0; + end + end + end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/hdmi_tx_ip.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/hdmi_tx_ip.v new file mode 100644 index 0000000000000000000000000000000000000000..4180ea9dd175e8275ba2af2eb31817aa98f15eb3 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/hdmi_tx_ip.v @@ -0,0 +1,129 @@ +////////////////////////////////////////////////////////////////////////////// +// +// Xilinx, Inc. 2008 www.xilinx.com +// +////////////////////////////////////////////////////////////////////////////// +// File name : encode.v +// Description : TMDS encoder +// Author : Bob Feng +////////////////////////////////////////////////////////////////////////////// + + +`timescale 1 ps / 1ps +module hdmi_tx_ip +( + input pixelclk, // system clock + input pixelclk5x, // system clock x5 + input rstin, // reset + input[7:0] blue_din, // Blue data in + input[7:0] green_din, // Green data in + input[7:0] red_din, // Red data in + input hsync, // hsync data + input vsync, // vsync data + input de, // data enable +// output [2:0] dataout_h, +// output [2:0] dataout_l, +// output clk_h, +// output clk_l, + output [2:0] data_p_h, + output [2:0] data_p_l, + output clk_p_h , + output clk_p_l , + output [2:0] data_n_h, + output [2:0] data_n_l, + output clk_n_h , + output clk_n_l , + + output [9:0] txc_o, + output [9:0] txd0_o, + output [9:0] txd1_o, + output [9:0] txd2_o +); + +wire [9:0] red ; +wire [9:0] green ; +wire [9:0] blue ; + + + wire [3:0] w_ctl = 4'b0000; + + tmds_channel enc_0 ( + .clk_pixel (pixelclk), + .video_data (blue_din), + .data_island_data (0), + .control_data ({vsync, hsync}), + .mode ({3'b0, de}), // Mode select (0 = control, 1 = video, 2 = video guard, 3 = island, 4 = island guard) + .tmds (blue) + ); + tmds_channel enc_1 ( + .clk_pixel (pixelclk), + .video_data (green_din), + .data_island_data (0), + .control_data (w_ctl[1:0]), + .mode ({3'b0, de}), // Mode select (0 = control, 1 = video, 2 = video guard, 3 = island, 4 = island guard) + .tmds (green) + ); + tmds_channel enc_2 ( + .clk_pixel (pixelclk), + .video_data (red_din), + .data_island_data (0), + .control_data (w_ctl[3:2]), + .mode ({3'b0, de}), // Mode select (0 = control, 1 = video, 2 = video guard, 3 = island, 4 = island guard) + .tmds (red) + ); + + //encode encb ( + //.clkin (pixelclk), + //.rstin (rstin), + //.din (blue_din), + //.c0 (hsync), + //.c1 (vsync), + //.de (de), + //.dout (blue)) ; + // + //encode encr ( + //.clkin (pixelclk), + //.rstin (rstin), + //.din (green_din), + //.c0 (1'b0), + //.c1 (1'b0), + //.de (de), + //.dout (green)) ; + // + //encode encg ( + //.clkin (pixelclk), + //.rstin (rstin), + //.din (red_din), + //.c0 (1'b0), + //.c1 (1'b0), + //.de (de), + //.dout (red)) ; + +serdes_4b_10to1 serdes_4b_10to1_m0( + .clk (pixelclk ),// clock input + .clkx5 (pixelclk5x ),// 5x clock input + .data_b (blue ),// input data for serialisation + .data_g (green ),// input data for serialisation + .data_r (red ),// input data for serialisation + .data_c (10'b1111100000 ),// input data for serialisation + .dataout_h (),//(dataout_h ), + .dataout_l (),//(dataout_l ), + .clk_h (),//(clk_h ), + .clk_l (),//(clk_l ) + + .data_p_h (data_p_h), + .data_p_l (data_p_l), + .clk_p_h (clk_p_h ), + .clk_p_l (clk_p_l ), + .data_n_h (data_n_h), + .data_n_l (data_n_l), + .clk_n_h (clk_n_h ), + .clk_n_l (clk_n_l ) + ) ; + + assign txc_o = 10'b1111100000; + assign txd0_o = blue; + assign txd1_o = green; + assign txd2_o = red; + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/rgb2dvi.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/rgb2dvi.v new file mode 100644 index 0000000000000000000000000000000000000000..d097c10b24c8f17ef8d3b0378de61831f107d207 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/rgb2dvi.v @@ -0,0 +1,84 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Create Date: 11:23:23 02/27/2022 +// Module Name: rgb2dvi +////////////////////////////////////////////////////////////////////////////////// + +module rgb2dvi #( + parameter ENABLE_OSERDES = 1 +)( + // Pixel Clock (1X). + input PixelClk, + input aRst, + input aRst_n, + + input [3:0] bitflip_i, // LVDS Lane Flip. [3]TXC, [2:0]TXD + input oe_i, // Output Enable. + + // Video Timing Generator (With Data Valid Control) + input vid_pVSync, // VSync. High Valid. + input vid_pHSync, // HSync. High Valid. + input vid_pVDE, // DataValid (Timing). Must be WIDTH + 2. (de & ~dvalid) will send VLG. + input [23:0] vid_pData, // RGB Data. [7:0]B(0), [15:8]G(1), [23:16]R(2). + + // HDMI Serializer (5X). + input SerialClk, + output TMDS_Clk_p, + output TMDS_Clk_n, + output [2:0] TMDS_Data_p, + output [2:0] TMDS_Data_n, + + output [9:0] txc_o, + output [9:0] txd0_o, + output [9:0] txd1_o, + output [9:0] txd2_o +); + + wire w_rst = aRst || (~aRst_n); + + wire [3:0] w_ctl = 4'b0000; + + ////////////////////////////////////////////////////////////////////////////////// + // TMDS Encoder + ////////////////////////////////////////////////////////////////////////////////// + + wire [9:0] w_tmds_0_enc, w_tmds_1_enc, w_tmds_2_enc; + + tmds_channel enc_0 ( + .clk_pixel (PixelClk), + .video_data (vid_pData[ 7: 0]), + .data_island_data (0), + .control_data ({vid_pVSync, vid_pHSync}), + .mode ({3'b0, vid_pVDE}), // Mode select (0 = control, 1 = video, 2 = video guard, 3 = island, 4 = island guard) + .tmds (w_tmds_0_enc) + ); + tmds_channel enc_1 ( + .clk_pixel (PixelClk), + .video_data (vid_pData[15: 8]), + .data_island_data (0), + .control_data (w_ctl[1:0]), + .mode ({3'b0, vid_pVDE}), // Mode select (0 = control, 1 = video, 2 = video guard, 3 = island, 4 = island guard) + .tmds (w_tmds_1_enc) + ); + tmds_channel enc_2 ( + .clk_pixel (PixelClk), + .video_data (vid_pData[23:16]), + .data_island_data (0), + .control_data (w_ctl[3:2]), + .mode ({3'b0, vid_pVDE}), // Mode select (0 = control, 1 = video, 2 = video guard, 3 = island, 4 = island guard) + .tmds (w_tmds_2_enc) + ); + + + ////////////////////////////////////////////////////////////////////////////////// + // Serializer + ////////////////////////////////////////////////////////////////////////////////// + + assign txc_o = 10'b1111100000; + assign txd0_o = w_tmds_0_enc; + assign txd1_o = w_tmds_1_enc; + assign txd2_o = w_tmds_2_enc; + + + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/serdes_4b_10to1.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/serdes_4b_10to1.v new file mode 100644 index 0000000000000000000000000000000000000000..a432bc70f6112e9999c5a1faea4a85286076aa1f --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/serdes_4b_10to1.v @@ -0,0 +1,97 @@ +////////////////////////////////////////////////////////////////////////////// +// +// Xilinx, Inc. 2008 www.xilinx.com +// +////////////////////////////////////////////////////////////////////////////// +// File name : encode.v +// Description : TMDS encoder +// Author : Bob Feng +////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/1ps + +module serdes_4b_10to1 ( + input clk, // clock input + input clkx5, // 5x clock input + input [9:0] data_b, // input data for serialisation + input [9:0] data_g, // input data for serialisation + input [9:0] data_r, // input data for serialisation + input [9:0] data_c, // input data for serialisation + output [2:0] dataout_h, + output [2:0] dataout_l, + output clk_h, + output clk_l, + + output reg [2:0] data_p_h, + output reg [2:0] data_p_l, + output reg clk_p_h , + output reg clk_p_l , + output reg [2:0] data_n_h, + output reg [2:0] data_n_l, + output reg clk_n_h , + output reg clk_n_l +); + +reg [2:0] TMDS_mod5 = 0; // modulus 5 counter + +reg [4:0] TMDS_shift_0h = 0, TMDS_shift_0l = 0; +reg [4:0] TMDS_shift_1h = 0, TMDS_shift_1l = 0; +reg [4:0] TMDS_shift_2h = 0, TMDS_shift_2l = 0; +reg [4:0] TMDS_shift_3h = 0, TMDS_shift_3l = 0; +reg [9:0] datain_0; +reg [9:0] datain_1; +reg [9:0] datain_2; +reg [9:0] datain_3; +always @( posedge clk ) +begin + datain_0 <= data_b; + datain_1 <= data_g; + datain_2 <= data_r; + datain_3 <= data_c; +end + +wire [4:0] TMDS_0_l = {datain_0[9],datain_0[7],datain_0[5],datain_0[3],datain_0[1]}; +wire [4:0] TMDS_0_h = {datain_0[8],datain_0[6],datain_0[4],datain_0[2],datain_0[0]}; + +wire [4:0] TMDS_1_l = {datain_1[9],datain_1[7],datain_1[5],datain_1[3],datain_1[1]}; +wire [4:0] TMDS_1_h = {datain_1[8],datain_1[6],datain_1[4],datain_1[2],datain_1[0]}; + +wire [4:0] TMDS_2_l = {datain_2[9],datain_2[7],datain_2[5],datain_2[3],datain_3[1]}; +wire [4:0] TMDS_2_h = {datain_2[8],datain_2[6],datain_2[4],datain_2[2],datain_3[0]}; + +wire [4:0] TMDS_3_l = {datain_3[9],datain_3[7],datain_3[5],datain_3[3],datain_3[1]}; +wire [4:0] TMDS_3_h = {datain_3[8],datain_3[6],datain_3[4],datain_3[2],datain_3[0]}; + +always @(posedge clkx5) +begin + TMDS_shift_0h <= TMDS_mod5[2] ? TMDS_0_h : TMDS_shift_0h[4:1]; + TMDS_shift_0l <= TMDS_mod5[2] ? TMDS_0_l : TMDS_shift_0l[4:1]; + TMDS_shift_1h <= TMDS_mod5[2] ? TMDS_1_h : TMDS_shift_1h[4:1]; + TMDS_shift_1l <= TMDS_mod5[2] ? TMDS_1_l : TMDS_shift_1l[4:1]; + TMDS_shift_2h <= TMDS_mod5[2] ? TMDS_2_h : TMDS_shift_2h[4:1]; + TMDS_shift_2l <= TMDS_mod5[2] ? TMDS_2_l : TMDS_shift_2l[4:1]; + TMDS_shift_3h <= TMDS_mod5[2] ? TMDS_3_h : TMDS_shift_3h[4:1]; + TMDS_shift_3l <= TMDS_mod5[2] ? TMDS_3_l : TMDS_shift_3l[4:1]; + TMDS_mod5 <= (TMDS_mod5[2]) ? 3'd0 : TMDS_mod5 + 3'd1; +end + +assign dataout_h = {TMDS_shift_2h[0],TMDS_shift_1h[0],TMDS_shift_0h[0]}; +assign dataout_l = {TMDS_shift_2l[0],TMDS_shift_1l[0],TMDS_shift_0l[0]}; +assign clk_h = TMDS_shift_3h[0]; +assign clk_l = TMDS_shift_3l[0]; + +always @( posedge clkx5 ) +begin + data_p_h <= dataout_h; + data_p_l <= dataout_l; + clk_p_h <= clk_h; + clk_p_l <= clk_l; + + data_n_h <= ~dataout_h; + data_n_l <= ~dataout_l; + clk_n_h <= ~clk_h; + clk_n_l <= ~clk_l; +end + + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/tmds_channel.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/tmds_channel.v new file mode 100644 index 0000000000000000000000000000000000000000..053f9a0462e04537221ebe0798f1d6078255f2a9 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/hdmi_ip/tmds_channel.v @@ -0,0 +1,169 @@ +// Implementation of HDMI Spec v1.4a Section 5.4: Encoding, Section 5.2.2.1: Video Guard Band, Section 5.2.3.3: Data Island Guard Bands. +// By Sameer Puri https://github.com/sameer + +module tmds_channel +#( + // TMDS Channel number. + // There are only 3 possible channel numbers in HDMI 1.4a: 0, 1, 2. + parameter CN = 0 +) +( + input clk_pixel, + input [7:0] video_data, + input [3:0] data_island_data, + input [1:0] control_data, + input [2:0] mode, // Mode select (0 = control, 1 = video, 2 = video guard, 3 = island, 4 = island guard) + output reg [9:0] tmds = 10'b1101010100 +); + +// See Section 5.4.4.1 +// Below is a direct implementation of Figure 5-7, using the same variable names. + +reg signed [4:0] acc = 5'sd0; + +reg [8:0] q_m; +reg [9:0] q_out; +wire [9:0] video_coding; +assign video_coding = q_out; + +reg [3:0] N1D; +reg signed [4:0] N1q_m07; +reg signed [4:0] N0q_m07; +always @(*) +begin + N1D = video_data[0] + video_data[1] + video_data[2] + video_data[3] + video_data[4] + video_data[5] + video_data[6] + video_data[7]; + case(q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7]) + 4'b0000: N1q_m07 = 5'sd0; + 4'b0001: N1q_m07 = 5'sd1; + 4'b0010: N1q_m07 = 5'sd2; + 4'b0011: N1q_m07 = 5'sd3; + 4'b0100: N1q_m07 = 5'sd4; + 4'b0101: N1q_m07 = 5'sd5; + 4'b0110: N1q_m07 = 5'sd6; + 4'b0111: N1q_m07 = 5'sd7; + 4'b1000: N1q_m07 = 5'sd8; + default: N1q_m07 = 5'sd0; + endcase + N0q_m07 = 5'sd8 - N1q_m07; +end + +reg signed [4:0] acc_add; + +integer i; + +always @(*) +begin + if (N1D > 4'd4 || (N1D == 4'd4 && video_data[0] == 1'd0)) + begin + q_m[0] = video_data[0]; + for(i = 0; i < 7; i = i + 1) + q_m[i + 1] = q_m[i] ~^ video_data[i + 1]; + q_m[8] = 1'b0; + end + else + begin + q_m[0] = video_data[0]; + for(i = 0; i < 7; i = i + 1) + q_m[i + 1] = q_m[i] ^ video_data[i + 1]; + q_m[8] = 1'b1; + end + if (acc == 5'sd0 || (N1q_m07 == N0q_m07)) + begin + if (q_m[8]) + begin + acc_add = N1q_m07 - N0q_m07; + q_out = {~q_m[8], q_m[8], q_m[7:0]}; + end + else + begin + acc_add = N0q_m07 - N1q_m07; + q_out = {~q_m[8], q_m[8], ~q_m[7:0]}; + end + end + else + begin + if ((acc > 5'sd0 && N1q_m07 > N0q_m07) || (acc < 5'sd0 && N1q_m07 < N0q_m07)) + begin + q_out = {1'b1, q_m[8], ~q_m[7:0]}; + acc_add = (N0q_m07 - N1q_m07) + (q_m[8] ? 5'sd2 : 5'sd0); + end + else + begin + q_out = {1'b0, q_m[8], q_m[7:0]}; + acc_add = (N1q_m07 - N0q_m07) - (~q_m[8] ? 5'sd2 : 5'sd0); + end + end +end + +always @(posedge clk_pixel) acc <= mode != 3'd1 ? 5'sd0 : acc + acc_add; + +// See Section 5.4.2 +reg [9:0] control_coding; +always @(*) +begin + case(control_data) + 2'b00: control_coding = 10'b1101010100; + 2'b01: control_coding = 10'b0010101011; + 2'b10: control_coding = 10'b0101010100; + 2'b11: control_coding = 10'b1010101011; + endcase +end + +// See Section 5.4.3 +reg [9:0] terc4_coding; +always @(*) +begin + case(data_island_data) + 4'b0000 : terc4_coding = 10'b1010011100; + 4'b0001 : terc4_coding = 10'b1001100011; + 4'b0010 : terc4_coding = 10'b1011100100; + 4'b0011 : terc4_coding = 10'b1011100010; + 4'b0100 : terc4_coding = 10'b0101110001; + 4'b0101 : terc4_coding = 10'b0100011110; + 4'b0110 : terc4_coding = 10'b0110001110; + 4'b0111 : terc4_coding = 10'b0100111100; + 4'b1000 : terc4_coding = 10'b1011001100; + 4'b1001 : terc4_coding = 10'b0100111001; + 4'b1010 : terc4_coding = 10'b0110011100; + 4'b1011 : terc4_coding = 10'b1011000110; + 4'b1100 : terc4_coding = 10'b1010001110; + 4'b1101 : terc4_coding = 10'b1001110001; + 4'b1110 : terc4_coding = 10'b0101100011; + 4'b1111 : terc4_coding = 10'b1011000011; + endcase +end + +// See Section 5.2.2.1 +wire [9:0] video_guard_band; +generate + if (CN == 0 || CN == 2) + assign video_guard_band = 10'b1011001100; + else + assign video_guard_band = 10'b0100110011; +endgenerate + +// See Section 5.2.3.3 +wire [9:0] data_guard_band; +generate + if (CN == 1 || CN == 2) + assign data_guard_band = 10'b0100110011; + else + assign data_guard_band = control_data == 2'b00 ? 10'b1010001110 + : control_data == 2'b01 ? 10'b1001110001 + : control_data == 2'b10 ? 10'b0101100011 + : 10'b1011000011; +endgenerate + +// Apply selected mode. +always @(posedge clk_pixel) +begin + case (mode) + 3'd0: tmds <= control_coding; + 3'd1: tmds <= video_coding; + 3'd2: tmds <= video_guard_band; + 3'd3: tmds <= terc4_coding; + 3'd4: tmds <= data_guard_band; + endcase +end + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/lcd_driver.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/lcd_driver.v new file mode 100644 index 0000000000000000000000000000000000000000..3de95264a383d6c096e29b15ecf745a913d80292 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/lcd_driver.v @@ -0,0 +1,192 @@ +/*----------------------------------------------------------------------- + \\\|/// + \\ - - // + ( @ @ ) ++-----------------------------oOOo-(_)-oOOo-----------------------------+ +CONFIDENTIAL IN CONFIDENCE +This confidential and proprietary software may be only used as authorized +by a licensing agreement from CrazyBingo (Thereturnofbingo). +In the event of publication, the following notice is applicable: +Copyright (C) 2013-20xx CrazyBingo Corporation +The entire notice above must be reproduced on all authorized copies. +Author : CrazyBingo +Technology blogs : www.crazyfpga.com +Email Address : crazyfpga@vip.qq.com +Filename : lcd_driver.v +Date : 2012-02-18 +Description : LCD/VGA driver. +Modification History : +Date By Version Change Description +========================================================================= +12/02/18 CrazyBingo 1.0 Original +12/03/19 CrazyBingo 1.1 Modification +12/03/21 CrazyBingo 1.2 Modification +12/05/13 CrazyBingo 1.3 Modification +13/11/07 CrazyBingo 2.1 Modification +17/04/02 CrazyBingo 3.0 Modify for 12bit width logic +------------------------------------------------------------------------- +| Oooo | ++------------------------------oooO--( )-----------------------------+ + ( ) ) / + \ ( (_/ + \_) +----------------------------------------------------------------------*/ + +`timescale 1ns/1ps + +`include "lcd_para.v" + +module lcd_driver #( + // Setting up default timing + parameter H_FRONT = `H_FRONT, + H_SYNC = `H_SYNC, + H_BACK = `H_BACK, + H_DISP = `H_DISP, + H_TOTAL = `H_TOTAL, + + V_FRONT = `V_FRONT, + V_SYNC = `V_SYNC, + V_BACK = `V_BACK, + V_DISP = `V_DISP, + V_TOTAL = `V_TOTAL, + + DATA_WIDTH = 48 + + //H_REAL = 640, + //V_REAL = 480 +)( + //global clock + input clk, //system clock + input rst_n, //sync reset + + //lcd interface + output lcd_dclk, //lcd pixel clock + output lcd_blank, //lcd blank + output lcd_sync, //lcd sync + output reg lcd_hs, //lcd horizontal sync + output reg lcd_vs, //lcd vertical sync + output reg lcd_en, //lcd display enable + output [DATA_WIDTH-1:0] lcd_rgb, //lcd display data + + input [11:0] H_REAL, + input [11:0] V_REAL, + + //user interface + output reg lcd_request, //lcd data request + output reg [11:0] lcd_xpos, //lcd horizontal coordinate + output reg [11:0] lcd_ypos, //lcd vertical coordinate + input [DATA_WIDTH-1:0] lcd_data, //lcd data + + //output reg frame_count + //input [1:0]bf_process_vs + input trig_vs +); +reg en; +/******************************************* + SYNC--BACK--DISP--FRONT +*******************************************/ +//------------------------------------------ +//h_sync counter & generator +reg [13:0] hcnt; +always @ (posedge clk or negedge rst_n or negedge trig_vs) +begin + if ((!rst_n) || (!trig_vs))begin + hcnt <= 12'd0; +// frame_count <= 1'b0; + end + else + begin + if(hcnt < H_TOTAL - 1'b1) //line over + hcnt <= hcnt + 1'b1; + else + hcnt <= 12'd0; + + lcd_hs <= (en)? ((hcnt <= H_SYNC - 1'b1) ? 1'b0 : 1'b1) : 1'b0; + end +end + + +//------------------------------------------ +//v_sync counter & generator +reg [11:0] vcnt; +always@(posedge clk or negedge rst_n or negedge trig_vs) +begin + if (!rst_n)begin + vcnt <= 12'b0; + en <= 0; +// frame_count <= 1'b0; + end else if(!trig_vs)begin + vcnt <= 12'b0; + en <= 1; + end + else if(hcnt == H_TOTAL - 1'b1) //line over + begin + if(vcnt < V_TOTAL - 1'b1) //frame over + vcnt <= vcnt + 1'b1; + else begin + vcnt <= 12'd0; + en <= 0; +// frame_count <= ~frame_count; + end + + lcd_vs <= (en)? ((vcnt <= V_SYNC - 1'b1) ? 1'b0 : 1'b1) : 1'b0; + end +end + + +//------------------------------------------ +//LCELL LCELL(.in(clk),.out(lcd_dclk)); +assign lcd_dclk = ~clk; +assign lcd_blank = lcd_hs & lcd_vs; +assign lcd_sync = 1'b0; + + +//----------------------------------------- +reg [DATA_WIDTH-1:0] r_lcd_rgb = 0; +always@(posedge clk) begin + lcd_en <= (en)? ( (hcnt >= H_SYNC + H_BACK && hcnt < H_SYNC + H_BACK + H_DISP) && + (vcnt >= V_SYNC + V_BACK && vcnt < V_SYNC + V_BACK + V_DISP) + ? 1'b1 : 1'b0) : 1'b0; + // r_lcd_rgb <= lcd_data; + if(((hcnt >= H_SYNC + H_BACK && hcnt < H_SYNC + H_BACK + H_DISP/2)&&(vcnt >= V_SYNC + V_BACK && vcnt < V_SYNC + V_BACK + (V_DISP-V_REAL)/2)) + ||((hcnt >= H_SYNC + H_BACK && hcnt < H_SYNC + H_BACK + (H_DISP-H_REAL)/2)&&(vcnt >= V_SYNC + V_BACK + (V_DISP-V_REAL)/2 && vcnt < V_SYNC + V_BACK + V_DISP/2))) + begin + r_lcd_rgb <= 24'hFF0000; + end else if(((hcnt >= H_SYNC + H_BACK + H_DISP/2 && hcnt < H_SYNC + H_BACK + H_DISP) &&(vcnt >= V_SYNC + V_BACK && vcnt < V_SYNC + V_BACK + (V_DISP-V_REAL)/2)) + ||((hcnt >= H_SYNC + H_BACK + (H_DISP+H_REAL)/2 && hcnt < H_SYNC + H_BACK + H_DISP) &&(vcnt >= V_SYNC + V_BACK + (V_DISP-V_REAL)/2 && vcnt < V_SYNC + V_BACK + V_DISP/2))) + begin + r_lcd_rgb <= 24'h00FF00; + end else if(((hcnt >= H_SYNC + H_BACK && hcnt < H_SYNC + H_BACK + (H_DISP-H_REAL)/2) &&(vcnt >= V_SYNC + V_BACK + V_DISP/2 && vcnt < V_SYNC + V_BACK + (V_DISP+V_REAL)/2)) + ||((hcnt >= H_SYNC + H_BACK && hcnt < H_SYNC + H_BACK + H_DISP/2) &&(vcnt >= V_SYNC + V_BACK + (V_DISP+V_REAL)/2 && vcnt < V_SYNC + V_BACK + V_DISP))) + begin + r_lcd_rgb <= 24'h0000FF; + end else if(((hcnt >= H_SYNC + H_BACK + (H_DISP+H_REAL)/2 && hcnt < H_SYNC + H_BACK + H_DISP) &&(vcnt >= V_SYNC + V_BACK + V_DISP/2 && vcnt < V_SYNC + V_BACK + (V_DISP+V_REAL)/2)) + ||((hcnt >= H_SYNC + H_BACK + H_DISP/2 && hcnt < H_SYNC + H_BACK + H_DISP) &&(vcnt >= V_SYNC + V_BACK + (V_DISP+V_REAL)/2 && vcnt < V_SYNC + V_BACK + V_DISP))) + begin + r_lcd_rgb <= 24'hFFFFFF; + end else if((hcnt >= H_SYNC + H_BACK + (H_DISP-H_REAL)/2 && hcnt < H_SYNC + H_BACK + (H_DISP+H_REAL)/2) + &&(vcnt >= V_SYNC + V_BACK + (V_DISP-V_REAL)/2 && vcnt < V_SYNC + V_BACK + (V_DISP+V_REAL)/2)) + begin + r_lcd_rgb <= lcd_data; + end +end +assign lcd_rgb = (lcd_en ? r_lcd_rgb : 0); + +//------------------------------------------ +//ahead x clock +localparam H_AHEAD = 12'd1; + +// Standard FIFO Request Port + always@(posedge clk) begin + lcd_request <= (en)? ((hcnt >= H_SYNC + H_BACK - H_AHEAD + (H_DISP-H_REAL)/2 && hcnt < H_SYNC + H_BACK + (H_DISP+H_REAL)/2 - H_AHEAD) && + (vcnt >= V_SYNC + V_BACK + (V_DISP-V_REAL)/2 && vcnt < V_SYNC + V_BACK + (V_DISP+V_REAL)/2) + ? 1'b1 : 1'b0) : 1'b0; + + +// lcd xpos & ypos + lcd_xpos <= lcd_request ? (hcnt - (H_SYNC + H_BACK - H_AHEAD)) : 11'd0; + lcd_ypos <= lcd_request ? (vcnt - (V_SYNC + V_BACK)) : 12'd0; +end + + +endmodule diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/lcd_para.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/lcd_para.v new file mode 100644 index 0000000000000000000000000000000000000000..c24199f468068c858b61dfb167e88a225a6c6f52 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/src/lcd_para.v @@ -0,0 +1,200 @@ +/*----------------------------------------------------------------------- + \\\|/// + \\ - - // + ( @ @ ) ++-----------------------------oOOo-(_)-oOOo-----------------------------+ +CONFIDENTIAL IN CONFIDENCE +This confidential and proprietary software may be only used as authorized +by a licensing agreement from CrazyBingo (Thereturnofbingo). +In the event of publication, the following notice is applicable: +Copyright (C) 2013-20xx CrazyBingo Corporation +The entire notice above must be reproduced on all authorized copies. +Author : CrazyBingo +Technology blogs : www.crazyfpga.com +Email Address : crazyfpga@vip.qq.com +Filename : lcd_para.v +Date : 2012-02-18 +Description : LCD/VGA driver parameter. +Modification History : +Date By Version Change Description +========================================================================= +12/02/18 CrazyBingo 1.0 Original +12/03/19 CrazyBingo 1.1 Modification +12/03/21 CrazyBingo 1.2 Modification +12/05/13 CrazyBingo 1.3 Modification +13/11/07 CrazyBingo 2.1 Modification +17/04/02 CrazyBingo 3.0 Modify for 720P & 1080P & 800*480 +------------------------------------------------------------------------- +| Oooo | ++------------------------------oooO--( )-----------------------------+ + ( ) ) / + \ ( (_/ + \_) +----------------------------------------------------------------------*/ + +`timescale 1ns/1ps + +//----------------------------------------------------------------------- +//Define the color parameter RGB--8|8|8 +//define colors RGB--8|8|8 +`define RED 24'hFF0000 /*11111111,00000000,00000000 */ +`define GREEN 24'h00FF00 /*00000000,11111111,00000000 */ +`define BLUE 24'h0000FF /*00000000,00000000,11111111 */ +`define WHITE 24'hFFFFFF /*11111111,11111111,11111111 */ +`define BLACK 24'h000000 /*00000000,00000000,00000000 */ +`define YELLOW 24'hFFFF00 /*11111111,11111111,00000000 */ +`define CYAN 24'hFF00FF /*11111111,00000000,11111111 */ +`define ROYAL 24'h00FFFF /*00000000,11111111,11111111 */ + +//--------------------------------- +`define SYNC_POLARITY 1'b0 + +//------------------------------------ +//vga parameter define +//`define VGA_854_480_60FPS_30MHz +//`define VGA_640_480_60FPS_25MHz +//`define VGA_800_600_60FPS_40MHz +// `define VGA_1280_720_60FPS_74_25MHz +`define VGA_1920_1080_60FPS_148_5MHz +//`define VGA_1024_600_60FPS_50MHz +//`define DSI_1024_600_60FPS_50MHz + +//--------------------------------- +// 854 * 480 +`ifdef VGA_854_480_60FPS_30MHz +`define H_FRONT 10'd50 +`define H_SYNC 10'd16 +`define H_BACK 10'd40 +`define H_DISP 10'd854 +`define H_TOTAL 10'd960 + +`define V_FRONT 10'd30 +`define V_SYNC 10'd3 +`define V_BACK 10'd12 +`define V_DISP 10'd480 +`define V_TOTAL 10'd525 +`endif + + +//--------------------------------- +// 640 * 480 +`ifdef VGA_640_480_60FPS_25MHz +`define H_FRONT 12'd16 +`define H_SYNC 12'd96 +`define H_BACK 12'd48 +`define H_DISP 12'd640 +`define H_TOTAL 12'd800 + +`define V_FRONT 12'd10 +`define V_SYNC 12'd2 +`define V_BACK 12'd33 +`define V_DISP 12'd480 +`define V_TOTAL 12'd525 +`endif + +//--------------------------------- +// 800 * 600 +`ifdef VGA_800_600_60FPS_40MHz +`define H_FRONT 12'd40 +`define H_SYNC 12'd128 +`define H_BACK 12'd88 +`define H_DISP 12'd800 +`define H_TOTAL 12'd1056 + +`define V_FRONT 12'd1 +`define V_SYNC 12'd4 +`define V_BACK 12'd23 +`define V_DISP 12'd600 +`define V_TOTAL 12'd628 +`endif + + +//--------------------------------- +// 1024*600 DSI (Dual Output) +`ifdef DSI_1024_600_60FPS_50MHz +`define H_FRONT 151 +`define H_SYNC 1 +`define H_BACK 1 +`define H_DISP 512 +`define H_TOTAL 1330 + +`define V_FRONT 12'd32 +`define V_SYNC 12'd5 +`define V_BACK 12'd8 +`define V_DISP 12'd600 +`define V_TOTAL 12'd645 +`endif + + +//--------------------------------- +// 1280 * 720 +`ifdef VGA_1280_720_60FPS_74_25MHz +`define H_FRONT 12'd110 +`define H_SYNC 12'd40 +`define H_BACK 12'd220 +`define H_DISP 12'd1280 +`define H_DISP_REQ 12'd1280 +`define H_TOTAL 12'd1650 + +`define V_FRONT 12'd5 +`define V_SYNC 12'd5 +`define V_BACK 12'd20 +`define V_DISP 12'd720 +`define V_DISP_REQ 12'd720 +`define V_TOTAL 12'd750 +`endif + + +//--------------------------------- +// 1920 * 1080 +`ifdef VGA_1920_1080_60FPS_148_5MHz +`define H_FRONT 12'd88 +`define H_SYNC 12'd44 +`define H_BACK 12'd148 +`define H_DISP 12'd1920 +`define H_TOTAL 12'd2200 + +`define V_FRONT 12'd4 +`define V_SYNC 12'd5 +`define V_BACK 12'd36 +//`define V_FRONT 12'd3 +//`define V_SYNC 12'd2 +//`define V_BACK 12'd3 +`define V_DISP 12'd1080 +`define V_TOTAL 12'd1125 +//`define V_TOTAL 12'd1088 +`endif + + +//--------------------------------- +// 1024 * 600 +`ifdef VGA_1024_600_60FPS_50MHz +`define H_FRONT 11'd160 +`define H_SYNC 11'd40 +`define H_BACK 11'd120 +`define H_DISP 11'd1024 +`define H_TOTAL 11'd1344 + +`define V_FRONT 11'd12 +`define V_SYNC 11'd3 +`define V_BACK 11'd20 +`define V_DISP 11'd600 +`define V_TOTAL 11'd635 +`endif + + +`ifdef VGA_800_480_30FPS_16MHz +`define H_FRONT 11'd80 +`define H_SYNC 11'd32 +`define H_BACK 11'd48 +`define H_DISP 11'd800 +`define H_TOTAL 11'd960 + +`define V_FRONT 11'd12 +`define V_SYNC 11'd3 +`define V_BACK 11'd5 +`define V_DISP 11'd480 +`define V_TOTAL 11'd500 +`endif + + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/work_dbg/debug_top.v b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/work_dbg/debug_top.v new file mode 100644 index 0000000000000000000000000000000000000000..ed189fbd1eab1a98cd5b87610fdca3d2ccb8d083 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/work_dbg/debug_top.v @@ -0,0 +1,5833 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Auto-generated Efinix JTAG debugger top module. Do not modify. +// + +//`include "dbg_defines.v" +`define DR_WIDTH 82 + + +module edb_top ( + // debug core ports + input bscan_CAPTURE, + input bscan_DRCK, + input bscan_RESET, + input bscan_RUNTEST, + input bscan_SEL, + input bscan_SHIFT, + input bscan_TCK, + input bscan_TDI, + input bscan_TMS, + input bscan_UPDATE, + output bscan_TDO, + input la0_clk, + input [26:0] la0_probe0, + input [26:0] la0_probe1, + input [39:0] la0_probe2, + input [27:0] la0_probe3, + input [37:0] la0_probe4, + input [17:0] la0_probe5, + input [16:0] la0_probe6, + input la0_probe7, + input [7:0] la0_probe8 +); + + localparam HUB_CS_WIDTH = 15; + + wire [HUB_CS_WIDTH-1:0] edb_module_selects; + wire [HUB_CS_WIDTH-1:0] edb_module_inhibit; + wire [HUB_CS_WIDTH-1:0] edb_module_tdo; + wire [`DR_WIDTH-1:0] edb_user_dr; + + // debug core connections + + // Remarks: Require GBUFCE for JTAG TCK Clock + wire bscan_TCK_buffered; + EFX_GBUFCE #(.CE_POLARITY(1'b1)) CLKBUF_JTAG_TCK (.CE(1'b1), .I(bscan_TCK), .O(bscan_TCK_buffered )); + wire la0_module_select; + wire la0_module_inhibit; + wire la0_module_tdo; + + assign la0_module_select = edb_module_selects[0]; + assign edb_module_inhibit[0] = la0_module_inhibit; + assign edb_module_tdo[0] = la0_module_tdo; + assign edb_module_inhibit[1] = 1'b0; + assign edb_module_tdo[1] = 1'b0; + assign edb_module_inhibit[2] = 1'b0; + assign edb_module_tdo[2] = 1'b0; + assign edb_module_inhibit[3] = 1'b0; + assign edb_module_tdo[3] = 1'b0; + assign edb_module_inhibit[4] = 1'b0; + assign edb_module_tdo[4] = 1'b0; + assign edb_module_inhibit[5] = 1'b0; + assign edb_module_tdo[5] = 1'b0; + assign edb_module_inhibit[6] = 1'b0; + assign edb_module_tdo[6] = 1'b0; + assign edb_module_inhibit[7] = 1'b0; + assign edb_module_tdo[7] = 1'b0; + assign edb_module_inhibit[8] = 1'b0; + assign edb_module_tdo[8] = 1'b0; + assign edb_module_inhibit[9] = 1'b0; + assign edb_module_tdo[9] = 1'b0; + assign edb_module_inhibit[10] = 1'b0; + assign edb_module_tdo[10] = 1'b0; + assign edb_module_inhibit[11] = 1'b0; + assign edb_module_tdo[11] = 1'b0; + assign edb_module_inhibit[12] = 1'b0; + assign edb_module_tdo[12] = 1'b0; + assign edb_module_inhibit[13] = 1'b0; + assign edb_module_tdo[13] = 1'b0; + assign edb_module_inhibit[14] = 1'b0; + assign edb_module_tdo[14] = 1'b0; + + // debug core instances + edb_la_top #( + .NUM_PROBES ( 9 ), + .DATA_DEPTH ( 512 ), + .TRIGIN_EN ( 0 ), + .TRIGOUT_EN ( 0 ), + .INPUT_PIPE_STAGES ( 1 ), + .CAPTURE_CONTROL ( 0 ), + .UUID ( 128'hcdcdccf59d384126a349c4dc5e1c278d ), + .CNDTNL_STRG_EN ( 0 ), + .PROBE0_WIDTH ( 27 ), + .PROBE0_TYPE ( 2 ), + .PROBE1_WIDTH ( 27 ), + .PROBE1_TYPE ( 2 ), + .PROBE2_WIDTH ( 40 ), + .PROBE2_TYPE ( 2 ), + .PROBE3_WIDTH ( 28 ), + .PROBE3_TYPE ( 2 ), + .PROBE4_WIDTH ( 38 ), + .PROBE4_TYPE ( 2 ), + .PROBE5_WIDTH ( 18 ), + .PROBE5_TYPE ( 2 ), + .PROBE6_WIDTH ( 17 ), + .PROBE6_TYPE ( 2 ), + .PROBE7_WIDTH ( 1 ), + .PROBE7_TYPE ( 1 ), + .PROBE8_WIDTH ( 8 ), + .PROBE8_TYPE ( 2 ) + ) la0 ( + .bscan_CAPTURE ( bscan_CAPTURE ), + .bscan_DRCK ( bscan_DRCK ), + .bscan_RESET ( bscan_RESET ), + .bscan_RUNTEST ( bscan_RUNTEST ), + .bscan_SEL ( bscan_SEL ), + .bscan_SHIFT ( bscan_SHIFT ), + .bscan_TCK ( bscan_TCK_buffered ), + .bscan_TDI ( bscan_TDI ), + .bscan_TMS ( bscan_TMS ), + .bscan_UPDATE ( bscan_UPDATE ), + .edb_user_dr ( edb_user_dr ), + .edb_module_select ( la0_module_select ), + .edb_module_inhibit ( la0_module_inhibit ), + .edb_module_tdo ( la0_module_tdo ), + .clk ( la0_clk ), + .trig_in ( 1'b0 ), + .trig_in_ack ( ), + .trig_out ( ), + .trig_out_ack ( 1'b0 ), + .probe0 ( la0_probe0 ), + .probe1 ( la0_probe1 ), + .probe2 ( la0_probe2 ), + .probe3 ( la0_probe3 ), + .probe4 ( la0_probe4 ), + .probe5 ( la0_probe5 ), + .probe6 ( la0_probe6 ), + .probe7 ( la0_probe7 ), + .probe8 ( la0_probe8 ) + ); + + debug_hub debug_hub_inst ( + .bscan_CAPTURE ( bscan_CAPTURE ), + .bscan_DRCK ( bscan_DRCK ), + .bscan_RESET ( bscan_RESET ), + .bscan_RUNTEST ( bscan_RUNTEST ), + .bscan_SEL ( bscan_SEL ), + .bscan_SHIFT ( bscan_SHIFT ), + .bscan_TCK ( bscan_TCK_buffered ), + .bscan_TDI ( bscan_TDI ), + .bscan_TMS ( bscan_TMS ), + .bscan_UPDATE ( bscan_UPDATE ), + .bscan_TDO ( bscan_TDO ), + .edb_module_selects ( edb_module_selects ), + .edb_module_inhibit ( edb_module_inhibit ), + .edb_module_tdo ( edb_module_tdo ), + .edb_user_dr ( edb_user_dr ) + ); + +endmodule + + +////////////////////////////////////////////////////////////////////// +// File: CRC32.v +// Date: Thu Nov 27 13:56:49 2003 +// +// Copyright (C) 1999-2003 Easics NV. +// This source file may be used and distributed without restriction +// provided that this copyright statement is not removed from the file +// and that any derivative work contains the original copyright notice +// and the associated disclaimer. +// +// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +// +// Purpose: Verilog module containing a synthesizable CRC function +// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) +// * data width: 1 +// +// Info: janz@easics.be (Jan Zegers) +// http://www.easics.com +// +// Modified by Nathan Yawn for the Advanced Debug Module +// Changes (C) 2008 - 2010 Nathan Yawn +/////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adbg_crc32.v,v $ +// Revision 1.3 2011-10-24 02:25:11 natey +// Removed extraneous '#1' delays, which were a holdover from the original +// versions in the previous dbg_if core. +// +// Revision 1.2 2010-01-10 22:54:10 Nathan +// Update copyright dates +// +// Revision 1.1 2008/07/22 20:28:29 Nathan +// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes. +// +// Revision 1.3 2008/07/06 20:02:53 Nathan +// Fixes for synthesis with Xilinx ISE (also synthesizable with +// Quartus II 7.0). Ran through dos2unix. +// +// Revision 1.2 2008/06/20 19:22:10 Nathan +// Reversed the direction of the CRC computation shift, for a more +// hardware-efficient implementation. +// +// +// +// + + +module edb_adbg_crc32 (clk, data, enable, shift, clr, rstn, crc_out, serial_out); + input clk; + input data; + input enable; + input shift; + input clr; + input rstn; + output [31:0] crc_out; + output serial_out; + + reg [31:0] crc; + wire [31:0] new_crc; + + // You may notice that the 'poly' in this implementation is backwards. + // This is because the shift is also 'backwards', so that the data can + // be shifted out in the same direction, which saves on logic + routing. + assign new_crc[0] = crc[1]; + assign new_crc[1] = crc[2]; + assign new_crc[2] = crc[3]; + assign new_crc[3] = crc[4]; + assign new_crc[4] = crc[5]; + assign new_crc[5] = crc[6] ^ data ^ crc[0]; + assign new_crc[6] = crc[7]; + assign new_crc[7] = crc[8]; + assign new_crc[8] = crc[9] ^ data ^ crc[0]; + assign new_crc[9] = crc[10] ^ data ^ crc[0]; + assign new_crc[10] = crc[11]; + assign new_crc[11] = crc[12]; + assign new_crc[12] = crc[13]; + assign new_crc[13] = crc[14]; + assign new_crc[14] = crc[15]; + assign new_crc[15] = crc[16] ^ data ^ crc[0]; + assign new_crc[16] = crc[17]; + assign new_crc[17] = crc[18]; + assign new_crc[18] = crc[19]; + assign new_crc[19] = crc[20] ^ data ^ crc[0]; + assign new_crc[20] = crc[21] ^ data ^ crc[0]; + assign new_crc[21] = crc[22] ^ data ^ crc[0]; + assign new_crc[22] = crc[23]; + assign new_crc[23] = crc[24] ^ data ^ crc[0]; + assign new_crc[24] = crc[25] ^ data ^ crc[0]; + assign new_crc[25] = crc[26]; + assign new_crc[26] = crc[27] ^ data ^ crc[0]; + assign new_crc[27] = crc[28] ^ data ^ crc[0]; + assign new_crc[28] = crc[29]; + assign new_crc[29] = crc[30] ^ data ^ crc[0]; + assign new_crc[30] = crc[31] ^ data ^ crc[0]; + assign new_crc[31] = data ^ crc[0]; + + always @ (posedge clk or negedge rstn) + begin + if(~rstn) + crc[31:0] <= 32'hffffffff; + else if(clr) + crc[31:0] <= 32'hffffffff; + else if(enable) + crc[31:0] <= new_crc; + else if (shift) + crc[31:0] <= {1'b0, crc[31:1]}; + end + + //assign crc_match = (crc == 32'h0); + assign crc_out = crc; //[31]; + assign serial_out = crc[0]; +endmodule +// adbg_crc32 + + +//////////////////////////////////////////////////////////////////////////////// +// +// Efinix JTAG debugging debug hub core +// +// Dec 2018, samh +// + +//`include "dbg_defines.v" + + +module debug_hub #( + parameter ID_WIDTH = 4, + parameter CS_WIDTH = (1<= 1 + OP_WIDTH + ADDR_WIDTH + COUNT_WIDTH ) + localparam OP_WIDTH = 4; + localparam ADDR_WIDTH = 32; + localparam COUNT_WIDTH = 16; + + localparam REGSEL_WIDTH = 13; + localparam REG_WIDTH = 64; // max width for a single register + + localparam REG_MSB = `DR_WIDTH - (1 + OP_WIDTH + REGSEL_WIDTH) - 1; + + // Index coding for registers + localparam INTREG_R0 = 0; + localparam INTREG_TRIG_MASK0 = 1; + localparam INTREG_TRIG_MASK1 = 11; + localparam INTREG_TRIG_MASK2 = 12; + localparam INTREG_TRIG_MASK3 = 13; + localparam INTREG_CAP_MASK0 = 2; + localparam INTREG_CAP_MASK1 = 14; + localparam INTREG_CAP_MASK2 = 15; + localparam INTREG_CAP_MASK3 = 16; + localparam INTREG_WINDOW_PROP = 3; + localparam INEREG_SOFT_RESET = 4; + localparam INTREG_UUID_LOWER = 8; + localparam INTREG_UUID_UPPER = 9; + + localparam BUF_MAX_ADDR_W = 17; // max=131,072 =2^17 + + // | capture_pattern | tu_pattern | trig_pos | stop_trig | run_trig_imdt | run_trig | sample_cnt | cstate + // | 2-bit | 2-bit 17-bit | 1-bit 1-bit 1-bit | 17-bit 3-bit + localparam R0_WIDTH = 3 + 3 + BUF_MAX_ADDR_W * 2 + 2 + 2; + + // Layout for R3 (Window Properties) + // | num_trigger | window_depth | + // | 17 bit | 17 bit| + localparam R3_WIDTH = BUF_MAX_ADDR_W + 5; + + // Cmd coding for instructions + //localparam LA_CMD_BWRITE8 = 4'h1; + //localparam LA_CMD_BWRITE16 = 4'h2; + //localparam LA_CMD_BWRITE32 = 4'h3; + //localparam LA_CMD_BWRITE64 = 4'h4; + localparam LA_CMD_BREAD8 = 4'h5; + localparam LA_CMD_BREAD16 = 4'h6; + localparam LA_CMD_BREAD32 = 4'h7; + localparam LA_CMD_BREAD64 = 4'h8; + localparam LA_CMD_IREG_WR = 4'h9; + localparam LA_CMD_IREG_SEL = 4'hd; + + // FSM state coding + localparam STATE_idle = 4'h0; + localparam STATE_Rbegin = 4'h1; + localparam STATE_Rready = 4'h2; + localparam STATE_Rstatus = 4'h3; + localparam STATE_Rburst = 4'h4; + localparam STATE_Wready = 4'h5; + localparam STATE_Wwait = 4'h6; + localparam STATE_Wburst = 4'h7; + localparam STATE_Wstatus = 4'h8; + localparam STATE_Rcrc = 4'h9; + localparam STATE_Wcrc = 4'ha; + localparam STATE_Wmatch = 4'hb; + + localparam MAX_PROBES = 256; + + localparam PIPE_CU = 1; + localparam PIPE_TU = 1; + + + //////////////////////////////////////// + + localparam REG_USAGE_TRIG_PATTERN = 8'h01; + localparam REG_USAGE_TRIG_VALUE = 8'h02; + localparam REG_USAGE_TRIG_MASK = 8'h03; + localparam REG_USAGE_CAP_PATTERN = 8'h04; + localparam REG_USAGE_CAP_VALUE = 8'h05; + localparam REG_USAGE_CAP_MASK = 8'h06; + // No operation + localparam REG_USAGE_DEFAULT = 8'hff; + + localparam REG_TRIG_PATTERN_WIDTH = 8'd3; + localparam REG_TRIG_VALUE_WIDTH = 8'd64; + localparam REG_TRIG_MASK_WIDTH = 8'd64; + localparam REG_CAP_PATTERN_WIDTH = 8'd3; + localparam REG_CAP_VALUE_WIDTH = 8'd64; + localparam REG_CAP_MASK_WIDTH = 8'd64; + + localparam WINDOWS_ADDRESS_WIDTH = $clog2(BUF_MAX_ADDR_W); + + //wire [1023:0] probes [0:MAX_PROBES-1]; + localparam PROBES_WIDTH = MAX_PROBES + ALL_WIDTH - NUM_PROBES; + wire [PROBES_WIDTH-1:0] probes; + + // Registers to hold state etc. + wire [R0_WIDTH-1:0] internal_reg_r0; // module internal register. + // wire [R3_WIDTH-1:0] internal_reg_r3; + reg [REG_WIDTH-1:0] data_out_shift_reg; // widht-bits to accomodate the internal_reg_* + reg [REGSEL_WIDTH-1:0] internal_register_select; // Holds index of currently selected register + reg [OP_WIDTH-1:0] opcode; // holds the current command (rd/wr, word size) + reg [31:0] address_counter; // Holds address for next Wishbone access + reg [5:0] bit_count; // How many bits have been shifted in/out + reg [15:0] word_count; // bytes remaining in current burst command + + // Control signals for the various counters / registers / state machines + reg out_reg_ld_en; // Enable parallel load of data_out_shift_reg + reg out_reg_shift_en; // Enable shift of data_out_shift_reg + reg out_reg_data_sel; // 0 = BIU data, 1 = internal register data + reg regsel_ld_en; // Reg. select register load enable + reg intreg_ld_en; // load enable for internal registers + reg [1:0] tdo_output_sel; // Selects signal to send to TDO. 0 = ready bit, 1 = output register, 2 = CRC match, 3 = CRC shift reg. + reg addr_sel; // Selects data for address_counter. 0 = data_register_i, 1 = incremented address count + reg addr_ct_en; // Enable signal for address counter register + reg op_reg_en; // Enable signal for 'operation' register + reg bit_ct_rst; // reset (zero) bit count register + reg bit_ct_en; // enable bit counter + reg word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count + reg word_ct_en; // Enable byte counter register + reg crc_in_sel; // selects incoming write data (=0) or outgoing read data (=1)as input to CRC module + reg crc_en; // does 1-bit iteration in CRC module + reg crc_shift_en; // CRC reg is also it's own output shift register; this enables a shift + reg crc_clr; // resets CRC module + reg biu_strobe; // Indicates that the bus unit should latch data and start a transaction + + // Status signals + wire intreg_instruction; // True when the input_data_i reg has a valid internal register instruction + wire intreg_write; // True when the input_data_i reg has an internal register write op + wire burst_write; // True when the input_data_i reg has a valid burst write instruction for this module + wire burst_read; // True when the input_data_i reg has a valid burst read instruction for this module + // reg rd_op; // True when operation in the opcode reg is a read, false when a write + wire bit_count_max; // true when bit counter is equal to current word size + wire bit_count_32; // true when bit count register == 32, for CRC after burst writes + wire word_count_zero; // true when byte counter is zero + wire crc_match; // indicates whether data_register_i matches computed CRC + wire biu_ready; // indicates that the BIU has finished the last command + + // Intermediate signals + wire module_cmd; // inverse of MSB of data_register_i. 1 means current cmd not for top level (but is for us) + wire [OP_WIDTH-1:0] opcode_in; // from data_register_i + wire [ADDR_WIDTH-1:0] address_in; // from data_register_i + wire [COUNT_WIDTH-1:0] count_in; // from data_register_i + wire [REGSEL_WIDTH-1:0] reg_select; // from data_register_i, input to internal register select register + + wire [REG_WIDTH-1:0] out_reg_data; // parallel input to the output shift register + wire [REG_WIDTH-1:0] data_from_internal_reg; // data from internal reg. MUX to output shift register + reg [5:0] word_size_bits; // 8,16,32 or 64. Decoded from 'operation' + reg [3:0] word_size_bytes; // 1,2,4 or 8 + wire [31:0] data_to_addr_counter; // output of the mux in front of the address counter inputs + wire [32:0] incremented_address; // value of address counter plus 'word_size' + wire [15:0] decremented_word_count; + wire [15:0] data_to_word_counter; // output of the mux in front of the byte counter input + wire crc_serial_out; + wire crc_data_in; // input to CRC module, either data_register_i[52] or data_out_shift_reg[0] + wire [31:0] crc_data_out; // output of CRC module, to output shift register + wire [REG_WIDTH-1:0] data_to_biu; // from data_register_i + wire [REG_WIDTH-1:0] data_from_biu; // to data_out_shift_register + + reg [3:0] module_state, module_next_state; + + reg la_resetn_p1; + reg la_resetn; + wire [2:0] la_cstate; + reg la_run_trig; + reg la_run_trig_imdt; + reg la_stop_trig; + wire [BUF_MAX_ADDR_W-1:0] la_sample_cnt; + reg [BUF_MAX_ADDR_W-1:0] la_trig_pos; + wire tu_trigger; + wire [CAPTURE_WIDTH-1:0] cap_fifo_din; + reg [CAPTURE_WIDTH-1:0] cap_fifo_din_cu, cap_fifo_din_tu; + wire [TRIGGER_WIDTH-1:0] tu_data; + reg [1:0] la_trig_pattern; + reg [MAX_PROBES-1:0] la_trig_mask; // TODO fixed for MAX_PROBES = 64 + // reg cap_buf_read_done; + + wire capture_enable; + // Global Capture Condition Mask / Pattern + reg [1:0] la_capture_pattern; + wire la_capture_enable; + // wire [REG_WIDTH-1:0] register_conn [0:(1< REG_PER_PW*2+1 = 1024/64*2+1 = 33 + localparam REG_DEPTH = 128; + localparam integer ALL_LSB = PROBE_PBUS_LSB_ARRAY[(i*32) +: 32]; + localparam integer CAP_LSB = PROBE_DBUS_LSB_ARRAY[(i*32) +: 32]; + localparam integer TBUS_LSB = PROBE_TBUS_LSB_ARRAY[(i*32) +: 32]; + localparam integer CBUS_LSB = PROBE_CBUS_LSB_ARRAY[(i*32) +: 32]; + + wire [PROBE_WIDTH-1:0] this_probe; + reg [PROBE_WIDTH-1:0] this_probe_p1, this_probe_p2; + + reg [PROBE_WIDTH-1:0] this_probe_p3, this_probe_p4; + reg [PROBE_WIDTH-1:0] this_probe_p5, this_probe_p6; + + assign this_probe = probes[ALL_LSB +: PROBE_WIDTH]; + + if (INPUT_PIPE_STAGES >= 1) begin + always @(posedge clk) begin + this_probe_p1 <= this_probe; + end + end + else begin + always @(*) begin + this_probe_p1 = this_probe; + end + end + + if (INPUT_PIPE_STAGES >= 2) begin + always @(posedge clk) begin + this_probe_p2 <= this_probe_p1; + end + end + else begin + always @(*) begin + this_probe_p2 = this_probe_p1; + end + end + + if (INPUT_PIPE_STAGES >= 3) begin + always @(posedge clk) begin + this_probe_p3 <= this_probe_p2; + end + end + else begin + always @(*) begin + this_probe_p3 = this_probe_p2; + end + end + + if (INPUT_PIPE_STAGES >= 4) begin + always @(posedge clk) begin + this_probe_p4 <= this_probe_p3; + end + end + else begin + always @(*) begin + this_probe_p4 = this_probe_p3; + end + end + + if (INPUT_PIPE_STAGES >= 5) begin + always @(posedge clk) begin + this_probe_p5 <= this_probe_p4; + end + end + else begin + always @(*) begin + this_probe_p5 = this_probe_p4; + end + end + + if (INPUT_PIPE_STAGES >= 6) begin + always @(posedge clk) begin + this_probe_p6 <= this_probe_p5; + end + end + else begin + always @(*) begin + this_probe_p6 = this_probe_p5; + end + end + + + if (PROBE_TYPE != PROBE_TYPE_NOT_USED) begin + wire [(REG_PER_PW*REG_WIDTH)-1:0] probe_compared, probe_mask; + wire [2:0] probe_pattern; + + wire [(REG_PER_PW*REG_WIDTH)-1:0] cap_probe_compared, cap_probe_mask; + wire [2:0] cap_probe_pattern; + + // Setup logic for loading register when address selected + for (j = 0 ; j < REG_DEPTH; j = j + 1) begin : GEN_REGS + localparam REG_ADDR = (1 + i)*REG_DEPTH + j; // addr mapping + // localparam REG_USAGE = get_reg_usage_code(j, PROBE_WIDTH, REG_WIDTH); + // localparam REG_DATA_WIDTH = get_reg_data_width(REG_USAGE); + // localparam IS_REG_USING = is_reg_using(REG_USAGE, PROBE_TYPE); + + localparam num_reg_used = (PROBE_WIDTH - 1) / REG_WIDTH + 1; + localparam addr_offset = j; + + if (addr_offset == 0) + begin + reg [REG_TRIG_PATTERN_WIDTH -1 : 0] internal_reg_pr; + + // Load corresponding data width from dr when the reg addr is selected + always @(posedge bscan_TCK or posedge bscan_RESET) begin + if (bscan_RESET) begin + internal_reg_pr <= 'h0; + end + else if (intreg_ld_en && (reg_select == REG_ADDR)) begin + internal_reg_pr <= edb_user_dr[0 +: REG_TRIG_PATTERN_WIDTH]; + end + end + // Trigger Pattern + assign probe_pattern = internal_reg_pr; + end + else if (addr_offset < num_reg_used + 1) + begin + reg [REG_TRIG_VALUE_WIDTH -1 : 0] internal_reg_pr; + + // Load corresponding data width from dr when the reg addr is selected + always @(posedge bscan_TCK or posedge bscan_RESET) begin + if (bscan_RESET) begin + internal_reg_pr <= 'h0; + end + else if (intreg_ld_en && (reg_select == REG_ADDR)) begin + internal_reg_pr <= edb_user_dr[0 +: REG_TRIG_VALUE_WIDTH]; + end + end + // Trigger Value + assign probe_compared[(j-1)*REG_WIDTH +: REG_WIDTH] = internal_reg_pr; + end + else if (addr_offset < 2 * num_reg_used + 1) + begin + reg [REG_TRIG_MASK_WIDTH -1 : 0] internal_reg_pr; + + // Load corresponding data width from dr when the reg addr is selected + always @(posedge bscan_TCK or posedge bscan_RESET) begin + if (bscan_RESET) begin + internal_reg_pr <= 'h0; + end + else if (intreg_ld_en && (reg_select == REG_ADDR)) begin + internal_reg_pr <= edb_user_dr[0 +: REG_TRIG_MASK_WIDTH]; + end + end + // Trigger Mask + assign probe_mask[(j-REG_PER_PW-1)*REG_WIDTH +: REG_WIDTH] = internal_reg_pr; + end + else if (addr_offset == 2 * num_reg_used + 1) + begin + reg [REG_CAP_PATTERN_WIDTH -1 : 0] internal_reg_pr; + + // Load corresponding data width from dr when the reg addr is selected + always @(posedge bscan_TCK or posedge bscan_RESET) begin + if (bscan_RESET) begin + internal_reg_pr <= 'h0; + end + else if (intreg_ld_en && (reg_select == REG_ADDR)) begin + internal_reg_pr <= edb_user_dr[0 +: REG_CAP_PATTERN_WIDTH]; + end + end + // Capture Pattern + assign cap_probe_pattern = internal_reg_pr; + end + else if (addr_offset < 3 * num_reg_used + 2) + begin + reg [REG_CAP_VALUE_WIDTH -1 : 0] internal_reg_pr; + + // Load corresponding data width from dr when the reg addr is selected + always @(posedge bscan_TCK or posedge bscan_RESET) begin + if (bscan_RESET) begin + internal_reg_pr <= 'h0; + end + else if (intreg_ld_en && (reg_select == REG_ADDR)) begin + internal_reg_pr <= edb_user_dr[0 +: REG_CAP_VALUE_WIDTH]; + end + end + // Capture Value + assign cap_probe_compared[(j - 2* REG_PER_PW - 2)*REG_WIDTH +: REG_WIDTH] = internal_reg_pr; + end + else if (addr_offset < 4 * num_reg_used + 2) + begin + reg [REG_CAP_MASK_WIDTH -1 : 0] internal_reg_pr; + + // Load corresponding data width from dr when the reg addr is selected + always @(posedge bscan_TCK or posedge bscan_RESET) begin + if (bscan_RESET) begin + internal_reg_pr <= 'h0; + end + else if (intreg_ld_en && (reg_select == REG_ADDR)) begin + internal_reg_pr <= edb_user_dr[0 +: REG_CAP_MASK_WIDTH]; + end + end + + // Capture Mask + assign cap_probe_mask[(j - 3* REG_PER_PW - 2)*REG_WIDTH +: REG_WIDTH] = internal_reg_pr; + end + + end + + if (PROBE_TYPE == PROBE_TYPE_TRIGGER_AND_DATA || PROBE_TYPE == PROBE_TYPE_DATA_ONLY) begin + if (CAPTURE_CONTROL == 1) begin + wire cap_probe_cout; + + compare_unit #( + .WIDTH (PROBE_WIDTH), + .PIPE ( PIPE_CU ) + ) capture_cu ( + .clk ( clk ), + .data_in ( this_probe_p6 ), + .compared_in ( cap_probe_compared[0 +: PROBE_WIDTH] ), + .mask_in ( cap_probe_mask[0 +: PROBE_WIDTH] ), + .pattern_in ( cap_probe_pattern ), + .compare_out ( cap_probe_cout ) + ); + // Combine the output of compare unit into mux_capture_cmp + assign mux_capture_cmp[CBUS_LSB] = cap_probe_cout; + end + + assign cap_fifo_din[CAP_LSB +: PROBE_WIDTH] = this_probe_p6; + + end + + if (PROBE_TYPE == PROBE_TYPE_TRIGGER_AND_DATA || PROBE_TYPE == PROBE_TYPE_TRIGGER_ONLY) begin + wire probe_cout; + + compare_unit #( + .WIDTH ( PROBE_WIDTH ), + .PIPE ( PIPE_CU ) + ) trigger_cu ( + .clk ( clk ), + .data_in ( this_probe_p6 ), + .compared_in ( probe_compared[0 +: PROBE_WIDTH] ), + .mask_in ( probe_mask[0 +: PROBE_WIDTH] ), + .pattern_in ( probe_pattern ), + .compare_out ( probe_cout ) + ); + + assign tu_data[TBUS_LSB] = probe_cout; + end + end + end + endgenerate + + // Handle global trigger condition + trigger_unit #( + .WIDTH ( TRIGGER_WIDTH ), + .TRIGIN_EN ( TRIGIN_EN ), + .PIPE ( PIPE_TU ), + .TRIGGER_IF_MASK_ZERO ( 0 ) // Output low when mask is all zero + ) trigger_tu ( + .clk ( clk ), + .data_in ( tu_data ), + .mask_in ( la_trig_mask[0 +: TRIGGER_WIDTH] ), + .pattern_in ( la_trig_pattern ), + .trigger_in ( trig_in ), + .trigger_out ( tu_trigger ) + ); + + generate + if (CAPTURE_CONTROL == 1) begin + reg [MAX_PROBES - 1: 0] la_capture_mask; + // Register writes for R2 (Capture Mask: Which Probes has enabled capture conditions) + always @(posedge bscan_TCK or posedge bscan_RESET) begin + if (bscan_RESET) begin + la_capture_mask <= 256'b0; + end + else if (intreg_ld_en) begin + if (reg_select == INTREG_CAP_MASK0) begin + la_capture_mask[0 +: 64] <= edb_user_dr[REG_MSB -: 64]; + end + if (reg_select == INTREG_CAP_MASK1) begin + la_capture_mask[64 +: 64] <= edb_user_dr[REG_MSB -: 64]; + end + if (reg_select == INTREG_CAP_MASK2) begin + la_capture_mask[128 +: 64] <= edb_user_dr[REG_MSB -: 64]; + end + if (reg_select == INTREG_CAP_MASK3) begin + la_capture_mask[192 +: 64] <= edb_user_dr[REG_MSB -: 64]; + end + end + end + // assign register_conn[INTREG_CAP_MASK] = la_capture_mask; + + // Handle global capture condition + trigger_unit #( + .WIDTH ( NUM_DATA_PRB ), + .TRIGIN_EN ( 0 ), + .PIPE ( PIPE_TU ), + .TRIGGER_IF_MASK_ZERO ( 1 ) // Output high when mask is all zero + ) global_capture_inst ( + .clk ( clk ), + .data_in ( mux_capture_cmp ), + .mask_in ( la_capture_mask[0 +: NUM_DATA_PRB] ), + .pattern_in ( la_capture_pattern ), + .trigger_in ( 0 ), + .trigger_out ( capture_enable ) + ); + + assign la_capture_enable = capture_enable; + end else begin + assign capture_enable = 1'b1; + assign la_capture_enable = capture_enable; + assign la_capture_mask = 256'b0; + end + endgenerate + + generate + if (TRIGIN_EN) begin + always @(posedge clk) begin + if (!la_resetn) begin + trig_in_ack <= 1'b0; + end + else begin + trig_in_ack <= trig_in; + end + end + end + endgenerate + + generate + if (PIPE_CU == 1) begin + reg [CAPTURE_WIDTH-1:0] cap_fifo_din_p1; + + always @(posedge clk) begin + cap_fifo_din_p1 <= cap_fifo_din; + cap_fifo_din_cu <= cap_fifo_din_p1; + end + end + else begin + always @(*) begin + cap_fifo_din_cu = cap_fifo_din; + end + end + + // Added due to trigger unit now 1-cycle delayed + if (PIPE_TU == 1) begin + always @(posedge clk) begin + cap_fifo_din_tu <= cap_fifo_din_cu; + end + end + else begin + always @(*) begin + cap_fifo_din_tu = cap_fifo_din_cu; + end + end + endgenerate + + la_biu #( + .REG_WIDTH ( REG_WIDTH ), + .BUF_MAX_ADDR_W ( BUF_MAX_ADDR_W ), + .CAPTURE_WIDTH ( CAPTURE_WIDTH ), + .DATA_DEPTH ( DATA_DEPTH ), + .WINDOWS_ADDRESS_WIDTH (WINDOWS_ADDRESS_WIDTH), + .TRIGOUT_EN ( TRIGOUT_EN ), + .CAPTURE_CONTROL (CAPTURE_CONTROL) + ) la_biu_inst ( + .la_run_trig ( la_run_trig ), + .la_run_trig_imdt ( la_run_trig_imdt ), + .la_stop_trig ( la_stop_trig ), + .la_trig_pos ( la_trig_pos ), + .la_window_depth ( la_window_depth), + .la_num_trigger ( la_num_trigger), + .la_cstate ( la_cstate ), + .la_sample_cnt (la_sample_cnt), + .tck_i ( bscan_TCK ), + .reset_i ( bscan_RESET ), + .strobe_i ( biu_strobe ), + .rdy_o ( biu_ready ), + .addr_i ( address_counter ), + .data_o ( data_from_biu ), + .clk ( clk ), + .la_resetn ( la_resetn ), + .cap_fifo_din ( cap_fifo_din_tu ), + .capture_enable ( la_capture_enable ), + .tu_trigger ( tu_trigger ), + .trig_out ( trig_out ), + .trig_out_ack ( trig_out_ack ) + ); + +endmodule +// edb_la_top + +////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2019 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +///////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// +// A custom sync FIFO implementation with extra read port for reading a full +// buffer, with address 0 starting at the first word read pointer points to. +// +// May 2019, samh +// + +module fifo_address_trancode_unit #( + parameter TOTAL_ADDR_WIDTH = 10, + parameter CELL_ADDR_WIDTH = 11, // Additional 1 bit to indicate overflow + parameter BUFFER_DEPTH = 5, + parameter PIPE = 1 +)( + input clk, + + input [TOTAL_ADDR_WIDTH - 1:0] window_addr, + input [CELL_ADDR_WIDTH - 1:0] cell_addr, + input [BUFFER_DEPTH - 1:0] window_depth, // 2's power + + output reg [TOTAL_ADDR_WIDTH -1:0] phy_addr, + output reg cell_addr_msb +); + wire [TOTAL_ADDR_WIDTH - 1:0] out_phy_addr; + wire out_cell_addr_msb; + wire [BUFFER_DEPTH - 1:0] window_depth_plus_1; + wire [CELL_ADDR_WIDTH - 1:0] cell_addr_mask; + + wire [TOTAL_ADDR_WIDTH - 1:0] real_cell_addr; + assign real_cell_addr = cell_addr[TOTAL_ADDR_WIDTH-1:0]; + + // MSB LSB + // window_addr(window_addr width - window_depth bit) | cell_addr (window_depth bit) + // Example: + // window_depth = 4, addr_width = 10 + // MSP 6 bit = window_addr, 4 bit = cell_addr + assign out_phy_addr = (window_addr << window_depth) | (real_cell_addr & {{(TOTAL_ADDR_WIDTH){1'b1}} >> (TOTAL_ADDR_WIDTH - window_depth)}); + + // Get the most MSB bit of the cell addr, needed because the length of the cell addr depends on window_depth + assign window_depth_plus_1 = window_depth + 1'b1; + assign cell_addr_mask = 1'b1 << (window_depth); + assign out_cell_addr_msb = |{cell_addr & cell_addr_mask}; + + generate + if (PIPE == 1) begin + always @(posedge clk) begin + phy_addr <= out_phy_addr; + cell_addr_msb <= out_cell_addr_msb; + end + end else begin + always @(*) begin + phy_addr = out_phy_addr; + cell_addr_msb = out_cell_addr_msb; + end + end + endgenerate +endmodule + +module fifo_with_read #( + parameter DATA_WIDTH = 1, + parameter ADDR_WIDTH = 10, + parameter WINDOW_ADDR_WIDTH = 5, + parameter PIPE = 1 +)( + input clk, rstn, + input push, pop, + + input [WINDOW_ADDR_WIDTH - 1: 0] window_depth, + output reg full, + output [ADDR_WIDTH - 1: 0] curr_window_addr, + + input [DATA_WIDTH - 1:0] din, + output [DATA_WIDTH - 1: 0] dout, + input rd_mode, + input [ADDR_WIDTH-1:0] raddr, + + output prefull, + output preprefull, + output [ADDR_WIDTH -1: 0] curr_cnt, + output [ADDR_WIDTH: 0] total_cnt +); + + reg [ADDR_WIDTH - 1: 0] window_addr; + + localparam RAM_DEPTH = (1 << ADDR_WIDTH); + + wire [ADDR_WIDTH-1:0] wr_pointer; + wire [ADDR_WIDTH-1:0] rd_pointer; + + wire we, re; + wire [ADDR_WIDTH-1:0] phy_addr; + + wire segment_pointer_eq; + wire segment_msb_xor; + + reg [ADDR_WIDTH:0] segment_wr_pointer; + reg [ADDR_WIDTH:0] segment_rd_pointer; + + wire segment_wr_msb; + wire segment_rd_msb; + + reg [ADDR_WIDTH:0] counter; + reg [ADDR_WIDTH:0] total_counter; + + reg [ADDR_WIDTH:0] next_segment_wr_pointer; + wire next_segment_wr_msb; + wire [ADDR_WIDTH - 1: 0] next_phy_wr_addr; + wire [ADDR_WIDTH:0] max_counter; + + assign total_cnt = total_counter; + + // Stage 1: Increment Cell Address + always @(posedge clk) begin + if (!rstn) begin + counter <= 0; + window_addr <= 0; + segment_rd_pointer <= 0; + segment_wr_pointer <= 0; + next_segment_wr_pointer <= 1; + end else if (prefull && push && !pop) begin + window_addr <= window_addr + 1'b1; + segment_rd_pointer <= 0; + segment_wr_pointer <= 0; + next_segment_wr_pointer <= 1; + counter <= 0; + end else begin + if (pop) begin + segment_rd_pointer <= segment_rd_pointer + 1'b1; + end + + if (push) begin + segment_wr_pointer <= segment_wr_pointer + 1'b1; + next_segment_wr_pointer <= next_segment_wr_pointer + 1'b1; + end + + if (pop && !push) begin + counter <= counter - 1'b1; + end else if (push && !pop) begin + counter <= counter + 1'b1; + end else begin + counter <= counter; + end + end + end + + always @(posedge clk) begin + if (!rstn) begin + total_counter <= 0; + end else begin + if (pop && !push) begin + total_counter <= total_counter - 1'b1; + end else if (push && !pop) begin + total_counter <= total_counter + 1'b1; + end else begin + total_counter <= total_counter; + end + end + end + + assign curr_cnt = counter[ADDR_WIDTH-1:0]; + + // Stage 2: Translate the address to phyiscal address + fifo_address_trancode_unit #( + .TOTAL_ADDR_WIDTH(ADDR_WIDTH), + .CELL_ADDR_WIDTH(ADDR_WIDTH + 1), + .BUFFER_DEPTH(WINDOW_ADDR_WIDTH), + .PIPE(PIPE) + // .PIPE(0) + ) transcode_next_write_addr ( + .clk(clk), + .window_addr(window_addr), + .cell_addr(next_segment_wr_pointer), + .window_depth(window_depth), + + .phy_addr(next_phy_wr_addr), + .cell_addr_msb(next_segment_wr_msb) + ); + + fifo_address_trancode_unit #( + .TOTAL_ADDR_WIDTH(ADDR_WIDTH), + .CELL_ADDR_WIDTH(ADDR_WIDTH + 1), + .BUFFER_DEPTH(WINDOW_ADDR_WIDTH), + .PIPE(PIPE) + // .PIPE(0) + ) transcode_write_addr ( + .clk(clk), + .window_addr(window_addr), + .cell_addr(segment_wr_pointer), + .window_depth(window_depth), + + .phy_addr(wr_pointer), + .cell_addr_msb(segment_wr_msb) + ); + + fifo_address_trancode_unit #( + .TOTAL_ADDR_WIDTH(ADDR_WIDTH), + .CELL_ADDR_WIDTH(ADDR_WIDTH + 1), + .BUFFER_DEPTH(WINDOW_ADDR_WIDTH), + .PIPE(PIPE) + // .PIPE(0) + ) transcode_read_addr ( + .clk(clk), + .window_addr(window_addr), + .cell_addr(segment_rd_pointer), + .window_depth(window_depth), + + .phy_addr(rd_pointer), + .cell_addr_msb(segment_rd_msb) + ); + + reg [DATA_WIDTH - 1: 0] din_p2; + reg push_p2; + reg pop_p2; + + // We need to mark the MSP of the data of the last data block (for sw to reorder the data) + wire [DATA_WIDTH - 1:0] data_in_with_status_bit; + wire is_last_data = prefull && push && !pop; + assign data_in_with_status_bit = {is_last_data, din[DATA_WIDTH -2:0]}; + + generate + if (PIPE == 1) begin + always @(posedge clk) begin + din_p2 <= data_in_with_status_bit; + push_p2 <= push; + pop_p2 <= pop; + full <= prefull; + end + end else begin + always @(*) begin + din_p2 = data_in_with_status_bit; + push_p2 = push; + pop_p2 = pop; + end + end + endgenerate + + assign segment_pointer_eq = (rd_pointer == wr_pointer); + assign segment_msb_xor = segment_rd_msb ^ segment_wr_msb; + + assign next_segment_pointer_eq = (rd_pointer == next_phy_wr_addr); + assign next_segment_msb_xor = segment_rd_msb ^ next_segment_wr_msb; + + assign max_counter = (2 ** window_depth) & {ADDR_WIDTH+1{1'b1}}; + assign prefull = (counter == max_counter - 1'b1); + assign preprefull = (counter == max_counter - 2'b10); + + assign we = push_p2; + assign re = pop_p2; + assign curr_window_addr = window_addr; + + assign phy_addr = rd_mode ? raddr : rd_pointer[ADDR_WIDTH-1:0]; + edb_simple_dual_port_ram #( + .DATA_WIDTH ( DATA_WIDTH ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .RAM_INIT_FILE ( "" ) + ) simple_dual_port_ram_inst ( + .rclk ( clk ), + .re ( re | rd_mode ), + //.raddr ( rd_pointer[ADDR_WIDTH-1:0] ), + .raddr ( phy_addr ), + .rdata ( dout ), + .wclk ( clk ), + .we ( we ), + .waddr ( wr_pointer[ADDR_WIDTH-1:0] ), + .wdata ( din_p2 ) + ); +endmodule +// fifo_with_read + +////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2019 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +///////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// +// Modified from adbg AXI bus-interface-unit for LogicN logic analyzer +// +// May 2019, samh +// + + +module la_biu #( + parameter REG_WIDTH = 64, + parameter BUF_MAX_ADDR_W = 17, // max=131,072 =2^17 + parameter CAPTURE_WIDTH = 1, + parameter DATA_DEPTH = 1024, + parameter WINDOWS_ADDRESS_WIDTH = 5, // log2(max buffer width) ~= 4 + parameter TRIGOUT_EN = 0, + parameter CAPTURE_CONTROL = 0 +)( + input la_run_trig, + input la_run_trig_imdt, + input la_stop_trig, + input [BUF_MAX_ADDR_W-1:0] la_trig_pos, + input [WINDOWS_ADDRESS_WIDTH - 1:0] la_window_depth, + input [BUF_MAX_ADDR_W-1:0] la_num_trigger, + + output [2:0] la_cstate, + output [BUF_MAX_ADDR_W-1: 0] la_sample_cnt, + + input tck_i, + input reset_i, + input strobe_i, + output reg rdy_o, + input [31:0] addr_i, + output [REG_WIDTH-1:0] data_o, + //input [3:0] word_size_i, // 1,2, or 4 + + input clk, + input la_resetn, + input [CAPTURE_WIDTH-1:0] cap_fifo_din, + input capture_enable, // Set to high to capture the sampled data + input tu_trigger, + // input cap_buf_read_done, + + output reg trig_out, + input trig_out_ack +); + + // function integer least_pwr2; + // input integer target; + // integer i; + // begin + // least_pwr2 = 1; + // for (i = 31; i >= 0; i = i - 1) begin + // if ((1 << i) >= target) + // least_pwr2 = 1 << i; + // end + // end + // endfunction + + // State machine + localparam LA_IDLE = 4'h0; + localparam LA_PRE_TRIG = 4'h1; + localparam LA_WAIT_TRIG = 4'h2; + localparam LA_POST_TRIG = 4'h3; + localparam LA_FULL = 4'h4; + localparam LA_POST_TILL_FULL = 4'h5; + localparam LA_RE_TRIG = 4'h6; + localparam LA_POST_RE_TRIG_PHEAD = 4'h7; + localparam LA_POST_RE_TRIG = 4'h8; + localparam LA_POST_RE_TRIG_PHEAD_TRIGGED = 4'h9; + localparam LA_POST_REACH_FULL = 4'hA; + + // localparam BYTES_PER_WORD = (CAPTURE_WIDTH)/8 + 1; // Plus 1 bit status bit + // localparam BPW_LEAST_PWR2 = least_pwr2(BYTES_PER_WORD); + + localparam _64BIT_PER_WORD = (CAPTURE_WIDTH) / 64 + 1; + // localparam WPD_LEAST_PWR2 = least_pwr2(_64BIT_PER_WORD); + localparam WPD_LEAST_PWR2 = _64BIT_PER_WORD; + + // AXI4 FSM states + localparam S_IDLE = 2'h0, S_AXIADDR = 2'h1, S_AXIDATA = 2'h2, S_AXIRESP = 2'h3; + + reg [1:0] axi_fsm_state, next_fsm_state; + + reg [3:0] curr_state, next_state; + reg run_trig_p1, run_trig_p2; + reg run_trig_imdt_p1, run_trig_imdt_p2; + wire [BUF_MAX_ADDR_W-1:0] pos_counter; + wire trig_pos_reached; + wire fifo_full; + reg fifo_push, fifo_pop; + reg read_mode; + wire [CAPTURE_WIDTH:0] fifo_dout; + wire fifo_rstn; + // wire [(BPW_LEAST_PWR2*8)-1:0] dout_ceil; + // reg [7:0] conn8 [0:BPW_LEAST_PWR2-1]; + wire [(WPD_LEAST_PWR2) * 64 -1:0] dout_ceil; // Cell to store a data chunk + reg [63:0] conn64 [0:WPD_LEAST_PWR2-1]; + + reg triggering; + + // 1 free block in fifo for current window + wire fifo_free_one; + // 2 free block in fifo for current window + wire fifo_free_two; + + // 17-bits MSB from addr_i, + // actual used depends on BUF DATA_DEPTH + localparam ADDR_WIDTH = $clog2(DATA_DEPTH); + wire [ADDR_WIDTH-1:0] row_addr; + wire [14:0] col_addr; + + localparam MOD_ADDRESS = $clog2(ADDR_WIDTH); + // Number of bit for + // reg [WINDOWS_ADDRESS_WIDTH - 1:0] fifo_window_depth; + wire [BUF_MAX_ADDR_W - 1:0] fifo_window_cnt; + wire [ADDR_WIDTH-1:0] fifo_counter; + assign pos_counter = {{(BUF_MAX_ADDR_W - ADDR_WIDTH){1'b0}}, fifo_counter}; + + wire [ADDR_WIDTH:0] fifo_total_count; + assign la_sample_cnt = {{(BUF_MAX_ADDR_W - ADDR_WIDTH - 1){1'b0}}, fifo_total_count}; + + // Registers + reg [31:0] addr_reg; // Don't really need the two LSB, this info is in the SEL bits + reg [REG_WIDTH-1:0] data_out_reg; // AXI->dbg + reg str_sync; // This is 'active-toggle' rather than -high or -low. + reg rdy_sync; // ditto, active-toggle + + // Sync registers. TFF indicates TCK domain, WBFF indicates wb_clk domain + reg rdy_sync_tff1; + reg rdy_sync_tff2; + reg rdy_sync_tff2q; // used to detect toggles + reg str_sync_wbff1; + reg str_sync_wbff2; + reg str_sync_wbff2q; // used to detect toggles + + // Control Signals + reg data_o_en; // latch wb_data_i + reg rdy_sync_en; // toggle the rdy_sync signal, indicate ready to TCK domain + + // Internal signals + wire start_toggle; // AXI domain, indicates a toggle on the start strobe + wire [REG_WIDTH-1:0] swapped_data_out; + + // reg cap_buf_read_done_p1, cap_buf_read_done_p2, cap_buf_read_done_p3; + // wire cap_buf_read_done_negedge; + + // assign la_cstate = curr_state; + + localparam USER_LA_STATE_IDLE = 3'h0; + localparam USER_LA_STATE_PRE = 3'h1; + localparam USER_LA_STATE_WAIT = 3'h2; + localparam USER_LA_STATE_POST = 3'h3; + localparam USER_LA_STATE_FULL = 3'h4; + + reg[2:0] reg_la_cstate; + assign la_cstate = reg_la_cstate; + always @(*) begin + case (curr_state) + LA_IDLE: begin + reg_la_cstate = USER_LA_STATE_IDLE; + end + LA_PRE_TRIG: begin + reg_la_cstate = USER_LA_STATE_PRE; + end + LA_WAIT_TRIG: begin + reg_la_cstate = USER_LA_STATE_WAIT; + end + + LA_POST_TRIG: begin + reg_la_cstate = USER_LA_STATE_POST; + end + + LA_FULL: begin + reg_la_cstate = USER_LA_STATE_FULL; + end + + LA_POST_TILL_FULL: begin + reg_la_cstate = USER_LA_STATE_POST; + end + + LA_RE_TRIG: begin + reg_la_cstate = USER_LA_STATE_PRE; + end + + LA_POST_RE_TRIG_PHEAD: begin + reg_la_cstate = USER_LA_STATE_PRE; + end + + LA_POST_RE_TRIG: begin + reg_la_cstate = USER_LA_STATE_PRE; + end + LA_POST_RE_TRIG_PHEAD_TRIGGED: begin + reg_la_cstate = USER_LA_STATE_PRE; + end + LA_POST_REACH_FULL: begin + reg_la_cstate = USER_LA_STATE_POST; + end + default : + reg_la_cstate = USER_LA_STATE_IDLE; + endcase + end + + // Add one MSP bit to the captured data + wire [CAPTURE_WIDTH:0] fifo_data_with_dummy_bit; + assign fifo_data_with_dummy_bit = {1'b1, cap_fifo_din}; + + always @(posedge clk) begin + if (!la_resetn) begin + run_trig_p1 <= 1'b0; + run_trig_p2 <= 1'b0; + run_trig_imdt_p1 <= 1'b0; + run_trig_imdt_p2 <= 1'b0; + end + else begin + run_trig_p1 <= la_run_trig; + run_trig_p2 <= run_trig_p1; + run_trig_imdt_p1 <= la_run_trig_imdt; + run_trig_imdt_p2 <= run_trig_imdt_p1; + end + end + + assign trig_pos_reached = (pos_counter == la_trig_pos - 1); + + wire is_phead; + assign is_phead = la_trig_pos == 0; + + wire is_plast; + assign is_plast = la_trig_pos == 2 ** la_window_depth - 1; + + wire is_plast2; + assign is_plast2 = la_trig_pos == 2 ** la_window_depth - 2; + + wire is_last_window; + assign is_last_window = fifo_window_cnt == la_num_trigger - 1; + + always @(*) begin + case(curr_state) + LA_IDLE: begin + if (run_trig_p2 || run_trig_imdt_p2) begin + if (la_trig_pos == 0) begin + next_state = LA_WAIT_TRIG; + end else begin + next_state = LA_PRE_TRIG; + end + end else begin + next_state = LA_IDLE; + end + end + + LA_PRE_TRIG: begin + if (trig_pos_reached) begin + next_state = LA_WAIT_TRIG; + end else begin + next_state = LA_PRE_TRIG; + end + end + + LA_WAIT_TRIG: begin + if (tu_trigger || run_trig_imdt_p2) begin + if (is_plast) begin + next_state = LA_POST_RE_TRIG; + if (is_last_window) begin + next_state = LA_POST_REACH_FULL; + end + end else begin + next_state = LA_POST_TRIG; + if (is_last_window) begin + next_state = LA_POST_TILL_FULL; + end + end + end else if (la_stop_trig) begin + // Just buffer and stop + next_state = LA_POST_TILL_FULL; + end else begin + next_state = LA_WAIT_TRIG; + end + end + + LA_FULL: begin + next_state = LA_FULL; + end + + // Push until fifo is real-full (all windows are full) + LA_POST_TILL_FULL: begin + if (fifo_free_one) begin + next_state = LA_POST_REACH_FULL; + end else begin + next_state = LA_POST_TILL_FULL; + end + end + + LA_POST_REACH_FULL: begin + next_state = LA_FULL; + end + + LA_POST_RE_TRIG_PHEAD: begin + if (tu_trigger || run_trig_imdt_p2) begin + next_state = LA_POST_RE_TRIG_PHEAD_TRIGGED; + if (is_last_window) begin + next_state = LA_POST_TILL_FULL; + end + end else begin + next_state = LA_WAIT_TRIG; + end + end + + LA_POST_RE_TRIG_PHEAD_TRIGGED: begin + next_state = LA_POST_TRIG; + end + + LA_POST_RE_TRIG: begin + if (trig_pos_reached) begin + next_state = LA_WAIT_TRIG; + end else begin + next_state = LA_PRE_TRIG; + end + end + + LA_POST_TRIG: begin + if (fifo_free_two || (fifo_free_one && is_plast2)) begin + if (is_last_window) begin + next_state = LA_POST_TILL_FULL; + end else begin + if (is_phead) begin + next_state = LA_POST_RE_TRIG_PHEAD; + end else begin + next_state = LA_POST_RE_TRIG; + end + end + end else begin + next_state = LA_POST_TRIG; + end + end + + default: next_state = LA_IDLE; + endcase + end + + // Control whether go to next state or not + reg state_load; + always @(*) begin + fifo_push = 1'b0; + fifo_pop = 1'b0; + read_mode = 1'b0; + triggering = 1'b0; + state_load = 1'b1; + case(curr_state) + LA_PRE_TRIG: begin + state_load = capture_enable; + fifo_push = 1'b1 & capture_enable; + end + + LA_WAIT_TRIG: begin + state_load = capture_enable; + if (tu_trigger || run_trig_imdt_p2) begin + triggering = 1'b1; + fifo_push = 1'b1 & capture_enable; + fifo_pop = 1'b0; + end + else begin + fifo_pop = 1'b1 & capture_enable; + fifo_push = 1'b1 & capture_enable; + end + end + + LA_POST_TRIG: begin + state_load = capture_enable; + fifo_push = 1'b1 & capture_enable; + end + + LA_FULL: begin + read_mode = 1'b1; + end + + LA_POST_TILL_FULL: begin + state_load = capture_enable; + fifo_push = 1'b1 & capture_enable; + end + + LA_RE_TRIG: begin + state_load = capture_enable; + fifo_push = 1'b1 & capture_enable; + end + + LA_POST_REACH_FULL: begin + // The fifo is fulled already, not pushing / poping + end + + LA_POST_RE_TRIG_PHEAD: begin + state_load = capture_enable; + fifo_push = 1'b1 & capture_enable; + end + + LA_POST_RE_TRIG_PHEAD_TRIGGED: begin + state_load = capture_enable; + fifo_push = 1'b1 & capture_enable; + end + + LA_POST_RE_TRIG: begin + state_load = capture_enable; + fifo_push = 1'b1 & capture_enable; + end + + default: begin + fifo_push = 1'b0; + fifo_pop = 1'b0; + end + endcase + end + + always @(posedge clk) begin + if (!la_resetn) begin + curr_state <= LA_IDLE; + end + else if (la_stop_trig) begin + curr_state <= next_state; + end else if (state_load) begin + curr_state <= next_state; + end + end + + generate + if (TRIGOUT_EN) begin + always @(posedge clk) begin + if (!la_resetn || trig_out_ack || (curr_state == LA_IDLE)) begin + trig_out <= 1'b0; + end + else if (triggering) begin + trig_out <= 1'b1; + end + end + end + endgenerate + + // Create toggle-active strobe signal for clock sync. This will start a transaction + // on the AXI once the toggle propagates to the FSM in the AXI domain. + always @(posedge tck_i or posedge reset_i) begin + if (reset_i) + str_sync <= 1'b0; + else if (strobe_i && rdy_o) + str_sync <= ~str_sync; + end + + // synchronize the start strobe + always @(posedge clk) begin + if (!la_resetn) begin + str_sync_wbff1 <= 1'b0; + str_sync_wbff2 <= 1'b0; + str_sync_wbff2q <= 1'b0; + end + else begin + str_sync_wbff1 <= str_sync; + str_sync_wbff2 <= str_sync_wbff1; + str_sync_wbff2q <= str_sync_wbff2; // used to detect toggles + end + end + + assign start_toggle = (str_sync_wbff2 != str_sync_wbff2q); + + // Create a toggle-active ready signal to send to the TCK domain + always @(posedge clk) begin + if (!la_resetn) + rdy_sync <= 1'b0; + else if (rdy_sync_en) + rdy_sync <= ~rdy_sync; + end + + // Create rdy_o output. Set on reset, clear on strobe (if set), set on input toggle + always @(posedge tck_i or posedge reset_i) begin + if (reset_i) begin + rdy_sync_tff1 <= 1'b0; + rdy_sync_tff2 <= 1'b0; + rdy_sync_tff2q <= 1'b0; + end + else begin + rdy_sync_tff1 <= rdy_sync; // Synchronize the ready signal across clock domains + rdy_sync_tff2 <= rdy_sync_tff1; + rdy_sync_tff2q <= rdy_sync_tff2; // used to detect toggles + end + end + + always @(posedge tck_i or posedge reset_i) begin + if (reset_i) begin + rdy_o <= 1'b1; + end + else begin + if (strobe_i && rdy_o) + rdy_o <= 1'b0; + else if (rdy_sync_tff2 != rdy_sync_tff2q) + rdy_o <= 1'b1; + end + end + + // Latch input data on 'start' strobe, if ready. + always @(posedge tck_i or posedge reset_i) begin + if (reset_i) begin + addr_reg <= 0; + end + else if (strobe_i && rdy_o) begin + addr_reg <= addr_i; + end + end + + // WB->dbg data register + always @(posedge clk) begin + if (!la_resetn) + data_out_reg <= 0; + else if (data_o_en) + data_out_reg <= swapped_data_out; + end + + assign data_o = data_out_reg; + + // assign fifo_rstn = la_resetn && !(curr_state == LA_IDLE || curr_state == LA_RE_TRIG); + assign fifo_rstn = la_resetn && !(curr_state == LA_IDLE); + + assign row_addr = addr_reg[15 +: ADDR_WIDTH]; + // Because col_addr is incremented by 8, we need to divided it by 8 here to locate the correct 64bit part of the whole words + assign col_addr = addr_reg[14:0] >> 3; + + wire [ADDR_WIDTH -1:0] la_window_fill_cnt; + + assign fifo_window_cnt = {{(BUF_MAX_ADDR_W - ADDR_WIDTH){1'b0}},la_window_fill_cnt}; + + fifo_with_read #( + .DATA_WIDTH ( CAPTURE_WIDTH + 1), + .WINDOW_ADDR_WIDTH (WINDOWS_ADDRESS_WIDTH), + .ADDR_WIDTH ( ADDR_WIDTH ), + .PIPE (1) + ) fifo_with_read_inst ( + .clk ( clk ), + .rstn ( fifo_rstn ), + .push ( fifo_push ), + .pop ( fifo_pop ), + .window_depth (la_window_depth), + .full ( fifo_full ), + .curr_window_addr (la_window_fill_cnt), + .rd_mode ( read_mode ), + .raddr ( row_addr ), + .din ( fifo_data_with_dummy_bit ), + .dout ( fifo_dout ), + .prefull(fifo_free_one), + .preprefull(fifo_free_two), + .curr_cnt(fifo_counter), + .total_cnt(fifo_total_count) + ); + + // assign dout_ceil = fifo_dout; + // always @(*) begin + // for (i = 0; i < BYTES_PER_WORD; i = i + 1) begin + // conn8[i] = dout_ceil[i*8 +: 8]; + // end + // end + // //assign swapped_data_out = conn8[col_addr[0 +: $clog2(BPW_LEAST_PWR2)]]; + // assign swapped_data_out = conn8[col_addr]; + + assign dout_ceil = fifo_dout; + genvar i; + generate + for (i = 0; i < _64BIT_PER_WORD; i = i + 1) begin + always @(*) begin + conn64[i] = dout_ceil[i * 64 +: 64]; + end + end + endgenerate + assign swapped_data_out = conn64[col_addr]; + + // Determination of next state (combinatorial) + always @(*) begin + //axi_master_ar_valid = 1'b0; + //axi_master_r_ready = 1'b0; + next_fsm_state = axi_fsm_state; + rdy_sync_en = 1'b0; + data_o_en = 1'b0; + + case (axi_fsm_state) + S_IDLE: begin + if (start_toggle) + next_fsm_state = S_AXIADDR; // Don't go to next state for 1-cycle transfer + else + next_fsm_state = S_IDLE; + end + S_AXIADDR: begin + //axi_master_ar_valid = 1'b1; + //if (!wr_reg && axi_master_ar_ready) + next_fsm_state = S_AXIRESP; + end + S_AXIRESP: begin + //axi_master_r_ready = 1'b1; + //if (!wr_reg && axi_master_r_valid) begin + data_o_en = 1'b1; + next_fsm_state = S_IDLE; + rdy_sync_en = 1'b1; + //end + end + endcase + end + + // Sequential bit + always @(posedge clk) begin + if (!la_resetn) axi_fsm_state <= S_IDLE; + else axi_fsm_state <= next_fsm_state; + end + +endmodule +// la_biu + +////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2019 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +///////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// +// Compare unit for each probe of the Efinix LogicN logic analyzer +// +// May 2019, samh +// + + +module compare_unit #( + parameter WIDTH = 1, + parameter PIPE = 0 +)( + input clk, + input [WIDTH-1:0] data_in, + input [WIDTH-1:0] compared_in, + input [WIDTH-1:0] mask_in, + input [2:0] pattern_in, + output reg compare_out +); + + localparam NOP = 3'h0; + localparam LOGIC_ZERO = 3'h1; + localparam LOGIC_ONE = 3'h2; + localparam DONT_CARE = 3'h3; + localparam RISE_EDGE = 3'h4; + localparam FALL_EDGE = 3'h5; + localparam BOTH_EDGE = 3'h6; + localparam NO_TRAN = 3'h7; + + localparam EQ = 3'h1; + localparam NOT_EQ = 3'h2; + localparam LESS_THAN = 3'h3; + localparam LESS_EQ = 3'h4; + localparam GRTR_THAN = 3'h5; + localparam GRTR_EQ = 3'h6; + + generate + if (WIDTH == 1) begin + reg data_in_p1; + reg enable; + wire rise, fall; + + always @(posedge clk) begin + data_in_p1 <= data_in; + enable <= 1'b1; + end + + assign rise = (data_in == 1'b1 && data_in_p1 == 1'b0); + assign fall = (data_in == 1'b0 && data_in_p1 == 1'b1); + + if (PIPE == 0) begin + always @(*) begin + case (pattern_in) + LOGIC_ZERO: + compare_out = (data_in == 1'b0); + LOGIC_ONE: + compare_out = (data_in == 1'b1); + DONT_CARE: + compare_out = (data_in == 1'bx); + RISE_EDGE: + compare_out = enable && rise; + FALL_EDGE: + compare_out = enable && fall; + BOTH_EDGE: + compare_out = enable && (rise || fall); + NO_TRAN: + compare_out = enable && (data_in == data_in_p1); + default: // NOP + compare_out = 1'b0; + endcase + end + end + else begin // PIPE != 0 + reg exp1, exp2, exp3, exp4, exp5, exp6; + + always @(posedge clk) begin + exp1 <= (data_in == 1'b0); + exp2 <= (data_in == 1'b1); + exp3 <= enable && rise; + exp4 <= enable && fall; + exp5 <= enable && (rise || fall); + exp6 <= enable && (data_in == data_in_p1); + case (pattern_in) + LOGIC_ZERO: + //compare_out <= (data_in == 1'b0); + compare_out <= exp1; + LOGIC_ONE: + //compare_out <= (data_in == 1'b1); + compare_out <= exp2; + DONT_CARE: + compare_out <= 1'b1; + RISE_EDGE: + //compare_out <= enable && rise; + compare_out <= exp3; + FALL_EDGE: + //compare_out <= enable && fall; + compare_out <= exp4; + BOTH_EDGE: + //compare_out <= enable && (rise || fall); + compare_out <= exp5; + NO_TRAN: + //compare_out <= enable && (data_in == data_in_p1); + compare_out <= exp6; + default: // NOP + compare_out <= 1'b0; + endcase + end + end + end + else begin // WIDTH != 1 + if (PIPE == 0) begin + always @(*) begin + case (pattern_in) + EQ: + compare_out = (data_in | ~mask_in) == (compared_in | ~mask_in); + NOT_EQ: + compare_out = (data_in | ~mask_in) != (compared_in | ~mask_in); + LESS_THAN: + compare_out = (data_in < compared_in); + LESS_EQ: + compare_out = (data_in <= compared_in); + GRTR_THAN: + compare_out = (data_in > compared_in); + GRTR_EQ: + compare_out = (data_in >= compared_in); + default: // NOP + compare_out = 1'b0; + endcase + end + end + else begin // PIPE != 0 + reg [WIDTH-1:0] exp1, exp2; + reg exp_gt; + reg exp_eq; + + always @(posedge clk) begin + exp1 <= (data_in | ~mask_in); + exp2 <= (compared_in | ~mask_in); + exp_gt <= (data_in > compared_in); + exp_eq <= (data_in == compared_in); + + case (pattern_in) + EQ: + compare_out <= exp1 == exp2; + NOT_EQ: + compare_out <= exp1 != exp2; + LESS_THAN: + compare_out <= !exp_gt && !exp_eq; + LESS_EQ: + compare_out <= !exp_gt; + GRTR_THAN: + compare_out <= exp_gt; + GRTR_EQ: + compare_out <= exp_gt || exp_eq; + default: // NOP + compare_out <= 1'b0; + endcase + end + end + end + endgenerate + +endmodule +// compare_unit + +////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2019 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +///////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// +// Trigger unit for the trigger condition (reduction logic) on all compare unit +// outputs in Efinix LogicN logic analyzer +// +// May 2019, samh +// + + +module trigger_unit #( + parameter WIDTH = 1, + parameter TRIGIN_EN = 0, + parameter PIPE = 0, + parameter TRIGGER_IF_MASK_ZERO = 0 /* Output High / Low when mask_in is all zero, + only apply when TRIGIN_EN is disabled + */ +)( + input clk, + input [WIDTH-1:0] data_in, + input [WIDTH-1:0] mask_in, // Enable mask, set bit hi to enable trigger + input [1:0] pattern_in, + input trigger_in, + output reg trigger_out +); + + localparam AND = 'h0; + localparam OR = 'h1; + localparam NAND = 'h2; + localparam NOR = 'h3; + + generate + if (TRIGIN_EN == 1) begin + reg mux_out; + always @(*) begin + case (pattern_in) + OR: + mux_out = |{(data_in & mask_in), trigger_in}; + NAND: + mux_out = ~&{(data_in | ~mask_in), trigger_in}; + NOR: + mux_out = ~|{(data_in & mask_in), trigger_in}; + default: // AND + mux_out = &{(data_in | ~mask_in), trigger_in}; + endcase + end + // When TRIGIN_EN is set, it is considered that the mask for comparasion would never be empty + if (PIPE == 0) begin + always @(*) begin + trigger_out = mux_out; + end + end else begin + always @(posedge clk) begin + trigger_out <= mux_out; + end + end + end else begin + reg mux_out; + always @(*) begin + case (pattern_in) + OR: + mux_out = |(data_in & mask_in); + NAND: + mux_out = ~&(data_in | ~mask_in); + NOR: + mux_out = ~|(data_in & mask_in); + default: // AND + mux_out = &(data_in | ~mask_in); + endcase + end + if (PIPE == 0) begin + if (TRIGGER_IF_MASK_ZERO == 0) begin + always @(*) begin + trigger_out = mux_out && (|mask_in); + end + end else begin + always @(*) begin + trigger_out = mux_out || (~|mask_in); + end + end + end else begin + if (TRIGGER_IF_MASK_ZERO == 0) begin + always @(posedge clk) begin + trigger_out <= mux_out && (|mask_in); + end + end else begin + always @(posedge clk) begin + trigger_out <= mux_out || (~|mask_in); + end + end + end + end + endgenerate +endmodule +// trigger_unit + +////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2019 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +///////////////////////////////////////////////////////////////////////////// + diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/work_pt/peri_res.json b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/work_pt/peri_res.json new file mode 100644 index 0000000000000000000000000000000000000000..da6bd0eecb6de8647b2c9670e4829cf923e1185a --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/1080p@60/work_pt/peri_res.json @@ -0,0 +1,3 @@ +{ + "migration_launch_pt": "normal" +} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/README.md b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/README.md new file mode 100644 index 0000000000000000000000000000000000000000..23b1167eed1613b6f8d8779d0c2747b74345d0a1 --- /dev/null +++ b/Floatkyun_Ultra-Vision/FPGA/Architecture2(1080P@60Hz)/README.md @@ -0,0 +1,18 @@ +工程使用 Efinity 2023.2.307 进行开发以及烧录，同样可以使用更高版本的 Efinity，2024版本的 Efinity 修复了一下bug，可能会更好一些（maybe）。 +硬件平台：Ti60F225核心板，底板V1.0，ADV7611 HDMI转LVDS模块。 + +打开Efinity->open project->选择工程文件Ti60_Demo.xml 以打开工程。 + +.v文件： + 顶层文件：1080@60/example_top.v + 功能模块：1080@60/src 中 + 算法以及单片机控制模块： 1080@60/data_in_uart_control_new/rtl 中 + +bit流文件： + 1080@60/outflow 中（使用Efinity进行烧录）bicubic_32_small.bit 为最新验证可用的bit流文件。 + +.sdc文件： + 1080@60/Ti60_Demo.pt.sdc + + +（可能存在一些未使用的冗余文件） \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/CMakeLists.txt b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..7e686668995be4fe1e26cbc3d0283e889672936f --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/CMakeLists.txt @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: MIT + +cmake_minimum_required(VERSION 3.20.0) + +project(gui_guider) + +FILE(GLOB_RECURSE SOURCES ./custom/*.c ./generated/*.c ports/linux/main.c) + +find_package(PkgConfig) +pkg_check_modules(PKG_WAYLAND wayland-client wayland-cursor wayland-protocols xkbcommon) + +add_executable (gui_guider ${SOURCES}) +target_link_libraries (gui_guider PUBLIC lvgl lv_drivers ${PKG_WAYLAND_LIBRARIES}) +target_include_directories(gui_guider PRIVATE generated custom generated/guider_customer_fonts generated/guider_fonts generated/images) + +install(PROGRAMS ${CMAKE_CURRENT_BINARY_DIR}/gui_guider DESTINATION bin) + +if(EXISTS ${CMAKE_SOURCE_DIR}/lvgl AND EXISTS ${CMAKE_SOURCE_DIR}/ports/linux/lv_drivers) +add_subdirectory(lvgl) +add_subdirectory(ports/linux/lv_drivers ${CMAKE_CURRENT_BINARY_DIR}/lv_drivers) +target_include_directories(gui_guider PRIVATE lvgl/src lvgl/src/font ports/linux/lv_drivers) +endif() + diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/LICENSE.txt b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/LICENSE.txt new file mode 100644 index 0000000000000000000000000000000000000000..e11e96948166bf3d7bc06b81d9430f201f784ccb --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/LICENSE.txt @@ -0,0 +1,211 @@ +LA_OPT_NXP_Software_License v47 July 2023  +IMPORTANT.  Read the following NXP Software License Agreement (“Agreement”) completely. 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You agree to provide all assistance reasonably requested by NXP to establish, preserve or enforce such right. +6.       ESSENTIAL PATENTS.    NXP has no obligation to identify or obtain any license to any Intellectual Property Right of a third-party that may be necessary for use in connection with technology that is incorporated into the Authorized System (whether or not as part of the Licensed Software). +7.       TERM AND TERMINATION.   This Agreement will remain in effect unless terminated as provided in this Section. +7.1.         You may terminate this Agreement immediately upon written notice to NXP at the address provided below. +7.2.         Either party may terminate this Agreement if the other party is in default of any of the terms and conditions of this Agreement, and termination is effective if the defaulting party fails to correct such default within 30 days after written notice thereof by the non-defaulting party to the defaulting party at the address below. +7.3.         Notwithstanding the foregoing, NXP may terminate this Agreement immediately upon written notice if you: breach any of your confidentiality obligations or the license restrictions under this Agreement;  become bankrupt, insolvent, or file a petition for bankruptcy or insolvency; make an assignment for the benefit of its creditors; enter proceedings for winding up or dissolution; are dissolved; or are nationalized or become subject to the expropriation of all or substantially all of your business or assets. +7.4.         Upon termination of this Agreement, all licenses granted under Section 2 will expire. +7.5.         After termination of this Agreement by either party you will destroy all parts of Licensed Software and its Derivative Works (if any) and will provide to NXP a statement certifying the same. +7.6.         Notwithstanding the termination of this Agreement for any reason, the terms of Sections 1 and 3 through 24 will survive.   +8.        SUPPORT.  NXP is not obligated to provide any support, upgrades or new releases of the Licensed Software under this Agreement. If you wish, you may contact NXP and report problems and provide suggestions regarding the Licensed Software. NXP has no obligation to respond to such a problem report or suggestion. NXP may make changes to the Licensed Software at any time, without any obligation to notify or provide updated versions of the Licensed Software to you. +9.        NO WARRANTY.  To the maximum extent permitted by law, NXP expressly disclaims any warranty for the Licensed Software. The Licensed Software is provided “AS IS”, without warranty of any kind, either express or implied, including without limitation the implied warranties of merchantability, fitness for a particular purpose, or non-infringement. You assume the entire risk arising out of the use or performance of the licensed software, or any systems you design using the licensed software (if any). +10.        INDEMNITY. You agree to fully defend and indemnify NXP from all claims, liabilities, and costs (including reasonable attorney’s fees) related to (1) your use (including your subcontractor’s or distributee’s use, if permitted) of the Licensed Software or (2) your violation of the terms and conditions of this Agreement. +11.        LIMITATION OF LIABILITY.  EXCLUDING LIABILITY FOR A BREACH OF SECTION 2 (LICENSE GRANTS), SECTION 3 (LICENSE LIMITATIONS AND RESTRICTIONS), SECTION 16 (CONFIDENTIAL INFORMATION), OR CLAIMS UNDER SECTION 10 (INDEMNITY), IN NO EVENT WILL EITHER PARTY BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. NXP’S TOTAL LIABILITY FOR ALL COSTS, DAMAGES, CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT OR PRODUCT(S) SUPPLIED UNDER THIS AGREEMENT IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP IN CONNECTION WITH THE LICENSED SOFTWARE PROVIDED UNDER THIS AGREEMENT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. +12.        EXPORT COMPLIANCE. Each party shall comply with all applicable export and import control laws and regulations including but not limited to the US Export Administration Regulation (including restrictions on certain military end uses and military end users as specified in Section 15 C.F.R. § 744.21 and prohibited party lists issued by other federal governments), Catch-all regulations and all national and international embargoes. Each party further agrees that it will not knowingly transfer, divert, export or re-export, directly or indirectly, any product, software, including software source code, or technology restricted by such regulations or by other applicable national regulations, received from the other party under this Agreement, or any direct product of such software or technical data to any person, firm, entity, country or destination to which such transfer, diversion, export or re-export is restricted or prohibited, without obtaining prior written authorization from the applicable competent government authorities to the extent required by those laws. +13.   GOVERNMENT CONTRACT COMPLIANCE +13.1.      If you sell Authorized Systems directly to any government or public entity, including U.S., state, local, foreign or international governments or public entities, or indirectly via a prime contractor or subcontractor of such governments or entities, NXP makes no representations, certifications, or warranties whatsoever about compliance with government or public entity acquisition statutes or regulations, including, without limitation, statutes or regulations that may relate to pricing, quality, origin or content. +13.2.      The Licensed Software has been developed at private expense and is a “Commercial Item” as defined in 48 C.F.R. Section 2.101, consisting of “Commercial Computer Software”, and/or “Commercial Computer Software Documentation,” as such terms are used in 48 C.F.R. Section 12.212 (or 48 C.F.R. Section 227.7202, as applicable) and may only be licensed to or shared with U.S. Government end users in object code form as part of, or embedded within, Authorized Systems. Any agreement pursuant to which you share the Licensed Software will include a provision that reiterates the limitations of this document and requires all sub-agreements to similarly contain such limitations.  +14.        CRITICAL APPLICATIONS. In some cases, NXP may promote certain software for use in the development of, or for incorporation into, products or services (a) used in applications requiring fail-safe performance or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (these products and services are referred to as “Critical Applications”). NXP’s goal is to educate customers so that they can design their own end-product solutions to meet applicable functional safety standards and requirements. Licensee makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, Licensee assumes all risk related to use of the Licensed Software in Critical Applications and NXP SHALL NOT BE LIABLE FOR ANY SUCH USE IN CRITICAL APPLICATIONS BY LICENSEE. Accordingly, Licensee will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to Licensee’s incorporation of the Licensed Software in a Critical Application. +15.        CHOICE OF LAW; VENUE.  This Agreement will be governed by, construed, and enforced in accordance with the laws of The Netherlands, without regard to conflicts of laws principles, will apply to all matters relating to this Agreement or the Licensed Software, and you agree that any litigation will be subject to the exclusive jurisdiction of the courts of Amsterdam, The Netherlands. The United Nations Convention on Contracts for the International Sale of Goods will not apply to this document.  +16.        CONFIDENTIAL INFORMATION.  Subject to the license grants and restrictions contained herein, you must treat the Licensed Software as confidential information and you agree to retain the Licensed Software in confidence perpetually. You may not disclose any part of the Licensed Software to anyone other than distributees in accordance with Section 2.3 and employees, or subcontractors in accordance with Section 2.5, who have a need to know of the Licensed Software and who have executed written agreements obligating them to protect such Licensed Software to at least the same degree of confidentiality as in this Agreement. You agree to use the same degree of care, but no less than a reasonable degree of care, with the Licensed Software as you do with your own confidential information. You may disclose Licensed Software to the extent required by a court or under operation of law or order provided that you notify NXP of such requirement prior to disclosure, which you only disclose the minimum of the required information, and that you allow NXP the opportunity to object to such court or other legal body requiring such disclosure. +17.       TRADEMARKS.  You are not authorized to use any NXP trademarks, brand names, or logos. +18.        ENTIRE AGREEMENT.  This Agreement constitutes the entire agreement between you and NXP regarding the subject matter of this Agreement, and supersedes all prior communications, negotiations, understandings, agreements or representations, either written or oral, if any. This Agreement may only be amended in written form, signed by you and NXP. +19.        SEVERABILITY.  If any provision of this Agreement is held for any reason to be invalid or unenforceable, then the remaining provisions of this Agreement will be unimpaired and, unless a modification or replacement of the invalid or unenforceable provision is further held to deprive you or NXP of a material benefit, in which case the Agreement will immediately terminate, the invalid or unenforceable provision will be replaced with a provision that is valid and enforceable and that comes closest to the intention underlying the invalid or unenforceable provision. +20.        NO WAIVER.  The waiver by NXP of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision. +21.        AUDIT.  You will keep full, clear and accurate records with respect to your compliance with the limited license rights granted under this Agreement for three years following expiration or termination of this Agreement. NXP will have the right, either itself or through an independent certified public accountant to examine and audit, at NXP’s expense, not more than once a year, and during normal business hours, all such records that may bear upon your compliance with the limited license rights granted above. You must make prompt adjustment to compensate for any errors and/or omissions disclosed by such examination or audit. +22.        NOTICES.             All notices and communications under this Agreement will be made in writing, and will be effective when received at the following addresses:  + NXP: + NXP B.V. + High Tech Campus 60 + 5656 AG Eindhoven + The Netherlands + ATTN: Legal Department +  + You: + The address provided at registration will be used. + +23.        RELATIONSHIP OF THE PARTIES.     The parties are independent contractors. Nothing in this Agreement will be construed to create any partnership, joint venture, or similar relationship. Neither party is authorized to bind the other to any obligations with third parties. +24.        SUCCESSION AND ASSIGNMENT.   This Agreement will be binding upon and inure to the benefit of the parties and their permitted successors and assigns.  You may not assign this Agreement, or any part of this Agreement, without the prior written approval of NXP, which approval will not be unreasonably withheld or delayed. NXP may assign this Agreement, or any part of this Agreement, in its sole discretion. +25. PRIVACY. By agreeing to this Agreement and/or utilizing the Licensed Software, Licensee consents to use of certain personal information, including but not limited to name, email address, and location, for the purpose of NXP’s internal analysis regarding future software offerings. NXP’s complete Privacy Statement can be found at: https://www.nxp.com/company/our-company/about-nxp/privacy-statement:PRIVACYPRACTICES. + + +  +  + + +APPENDIX A +Other License Grants and Restrictions: + +The Licensed Software may include some or all of the following software, which is either 1) Third Party Software or 2) NXP proprietary software subject to different terms than those in the Agreement. If the Software Content Register that accompanies the Licensed Software identifies any of the following Third Party Software or specific components of the NXP proprietary software, the following terms apply to the extent they deviate from the terms in the Agreement: + +Airbiquity Inc.: The Airbiquity software may only be used in object code and Licensee may not sublicense the Airbiquity software to any third party. Licensee’s license to use the Airbiquity software expires on June 30, 2024. + +Amazon: Use of the Amazon software constitutes your acceptance of the terms of the Amazon Program Materials License Agreement (including the AVS Component Schedule, if applicable), located at https://developer.amazon.com/support/legal/pml. All Amazon software is hereby designated “Amazon confidential”. With the exception of the binary library of the Amazon Wake Word Engine for “Alexa”, all Amazon software is also hereby designated as “Restricted Program Materials”. Amazon is a third-party beneficiary to this Agreement with respect to the Amazon software. + +Amazon Web Services, Inc.: AWS is an intended third-party beneficiary to this Agreement with respect to the Greengrass software. If you have an account with AWS that is not in good standing, you may not download, install, use or distribute the Greengrass software. You will comply with all instructions and requirements in any integration documents, guidelines, or other documentation AWS provides. The license to the Greengrass software will immediately terminate without notice if you (a) fail to comply with this Agreement or any other agreement with AWS, (b) fail to make timely payment for any AWS service, (c) fail to implement AWS updates, or (d) bring any action for intellectual property infringement against AWS or any AWS customer utilizing AWS services. Any dispute or claim relating to your use of the Greengrass software will be resolved by binding arbitration, rather than in court, except that you may assert claims in small claims court if your claims qualify. + +Amazon: AWS Fleetwise software must be used consistent with the terms found here: https://github.com/aws/aws-iot-fleetwise-edge/blob/main/LICENSE. + +Amphion Semiconductor Ltd.: Distribution of Amphion software must be a part of, or embedded within, Authorized Systems that include an Amphion Video Decoder. + +Apple MFi Software Development Kit: Use of Apple MFi Software and associated documentation is restricted to current Apple MFi licensees in accordance with the terms of their own valid and in-effect license from Apple. + +Aquantia Corp.: You may use Aquantia's API binaries solely to flash the API software to an NXP Product which mates with an Aquantia device. + +Argus Cyber Security: The Argus software may only be used in object code and only for evaluation and demonstration purposes. + +Atheros: Use of Atheros software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from Atheros. + +ATI (AMD): Distribution of ATI software must be a part of, or embedded within, Authorized Systems that include a ATI graphics processor core. + +Au-Zone Technologies: eIQ Portal, Model Tool, DeepViewRT and ModelRunner are distributed by NXP under license from Au-Zone Technologies.  Your use of the Licensed Software, examples and related documentation is subject to the following: +(1)          Use of Software is limited to Authorized System only +(2)          In no event may Licensee Sublicense the Software +(3)          AU-ZONE TECHNOLOGIES SHALL NOT BE LIABLE FOR USE OF LICENSED SOFTWARE IN CRITICAL APPLICATIONS BY LICENSEE + + +Broadcom Corporation: Your use of Broadcom Corporation software is restricted to Authorized Systems that incorporate a compatible integrated circuit device manufactured or sold by Broadcom. + +Cadence Design Systems: Use of Cadence audio codec software is limited to distribution only of one copy per single NXP Product. The license granted herein to the Cadence Design Systems HiFi aacPlus Audio Decoder software does not include a license to the AAC family of technologies which you or your customer may need to obtain. Configuration tool outputs may only be distributed by licensees of the relevant Cadence SDK and distribution is limited to distribution of one copy embedded in a single NXP Product. Your use of Cadence NatureDSP Libraries whether in source code or in binary is restricted to NXP SoC based systems or emulation enablement based on NXP SoC. + +CEVA D.S.P. Ltd. And CEVA Technologies Inc. (“CEVA”): The CEVA-SPF2 linear algebra, CEVA-SPF2 Neural Network Libraries, CEVA-SPF2 Core Libraries, CEVA-SPF2 OpenAMP and CEVA-SPF2 STL licensed modules are owned by CEVA and such materials may only be used in connection with an NXP product containing the S250 or S125 integrated circuits, whether or not the CEVA-SPF2 Core is physically implemented and/or enabled on such NXP product + +Cirque Corporation: Use of Cirque Corporation technology is limited to evaluation, demonstration, or certification testing only. Permitted distributions must be similarly limited. Further rights, including but not limited to ANY commercial distribution rights, must be obtained directly from Cirque Corporation. + +Coding Technologies (Dolby Labs): Use of CTS software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained from Dolby Laboratories. + +Coremark: Use of the Coremark benchmarking software is subject to the following terms and conditions: https://github.com/eembc/coremark/blob/main/LICENSE.md + +CSR: Use of Cambridge Silicon Radio, Inc. ("CSR") software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from CSR. + +Crank: Use of Crank Software Inc. software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from Crank Software Inc. + +Cypress Semiconductor Corporation: WWD RTOS source code may only be used in accordance with the Cypress IOT Community License Agreement obtained directly from Cypress Semiconductor Corporation. + +Elektrobit Automotive GmbH (“EB”): EB software must be used consistent with the EB License Terms and Conditions, Version 1.4 (Dec 2019) found here: https://www.elektrobit.com/legal-notice/ .  Licensee is only granted an evaluation license for the EB software, defined as license to use the EB software internally for own evaluation purposes, limited to three (3) months. Production deployment of the EB software using this license is prohibited. See additionally Section 2.1.1 EB EULA. + +Embedded Systems Academy GmbH (EmSA): Any use of Micro CANopen Plus is subject to the acceptance of the license conditions described in the LICENSE.INFO file distributed with all example projects and in the documentation and the additional clause described below. +Clause 1: Micro CANopen Plus may not be used for any competitive or comparative purpose, including the publication of any form of run time or compile time metric, without the express permission of EmSA. + +Fenopix Technologies Private Limited: Under no circumstances may the CanvasJS software product be used in any way that would compete with any product from Fenopix.  License to the CanvasJS software will terminate immediately without notice if Licensee fail to comply with any provision of this Agreement. + +Fraunhofer IIS: Fraunhofer MPEG Audio Decoder (Fraunhofer copyright) - If you are provided MPEG-H decoding functionality, you understand that NXP will provide Fraunhofer your name and contact information. + +Future Technology Devices International Ltd.: Future Technology Devices International software must be used consistent with the terms found here: http://www.ftdichip.com/Drivers/FTDriverLicenceTerms.htm + +Global Locate (Broadcom Corporation): Use of Global Locate, Inc. software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained from Global Locate. + +IAR Systems: Use of IAR flashloader or any IAR source code is subject to the terms of the IAR Source License located within the IAR zip package. The IAR Source License applies to linker command files, example projects unless another license is explicitly stated, the cstartup code, low_level_init.c, and some other low-level runtime library files. + +LC3plus: the LC3plus Low Complexity Communication Codec Plus (LC3plus) per ETSI TS 103 634 V1.3.1, is subject to ETSI Intellectual Property Rights Policy, See https://portal.etsi.org/directives/45_directives_jun_2022.pdf. For application in an End Product, Fraunhofer communication applies, see https://www.iis.fraunhofer.de/en/ff/amm/communication/lc3.html + +Microsoft: Except for Microsoft PlayReady software, if the Licensed Software includes software owned by Microsoft Corporation ("Microsoft"), it is subject to the terms of your license with Microsoft (the "Microsoft Underlying Licensed Software") and as such, NXP grants no license to you, beyond evaluation and demonstration in connection with NXP processors, in the Microsoft Underlying Licensed Software. You must separately obtain rights beyond evaluation and demonstration in connection with the Microsoft Underlying Licensed Software from Microsoft. Microsoft does not provide support services for the components provided to you through this Agreement. If you have any questions or require technical assistance, please contact NXP. Microsoft Corporation is a third party beneficiary to this Agreement with the right to enforce the terms of this Agreement. TO THE MAXIMUM EXTENT PERMITTED BY LAW, MICROSOFT AND ITS AFFILIATES DISCLAIM ANY WARRANTIES FOR THE MICROSOFT UNDERLYING LICENSED SOFTWARE. TO THE MAXIMUM EXTENT PERMITTED BY LAW, NEITHER MICROSOFT NOR ITS AFFILIATES WILL BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY DIRECT, INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, ARISING FROM THE FROM THE USE OF THE MICROSOFT UNDERLYING LICENSED SOFTWARE. With respect to the Microsoft PlayReady software, you will have the license rights granted in Section 2, provided that you may not use the Microsoft PlayReady software unless you have entered into a Microsoft PlayReady Master Agreement and license directly with Microsoft. + +MindTree: Notwithstanding the terms contained in Section 2.3 (a), if the Licensed Software includes proprietary software of MindTree in source code format, Licensee may make modifications and create derivative works only to the extent necessary for debugging of the Licensed Software. + +MM SOLUTIONS AD: Use of MM SOLUTIONS AEC (Auto Exposure Control) and AWB (Auto White Balance) software is limited to demonstration, testing, and evaluation only. In no event may Licensee distribute or sublicense the MM SOLUTIONS software. Further rights must be obtained directly from MM SOLUTIONS. + +MPEG LA: Use of MPEG LA audio or video codec technology is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from MPEG LA. + +MQX RTOS Code: MQX RTOS source code may not be re-distributed by any NXP Licensee under any circumstance, even by a signed written amendment to this Agreement. + +NXP Voice Software: VoiceSpot, VoiceSeeker (including AEC), VIT Speech to Intent, and Conversa may be used for evaluation or demonstration purposes only. Any commercial distribution rights are subject to a separate royalty agreement obtained from NXP. + +NXP Wireless Charging Library: License to the Software is limited to use in inductive coupling or wireless charging applications + +Opus: Use of Opus software must be consistent with the terms of the Opus license which can be found at: http://www.opus-codec.org/license/ + +Oracle JRE (Java): The Oracle JRE must be used consistent with terms found here: http://java.com/license + +P&E Micro: P&E Software must be used consistent with the terms found here: http://www.pemicro.com/licenses/gdbserver/license_gdb.pdf + +Pro Design Electronic: Licensee may not modify, create derivative works based on, or copy the Pro Design software, documentation, hardware execution key or the accompanying materials. Licensee shall not use Pro Design's or any of its licensors names, logos or trademarks to market the Authorized System. Only NXP customers and distributors are permitted to further redistribute the Pro Design software and only as part of an Authorized System which contains the Pro Design software. + +Qualcomm Atheros, Inc.: Notwithstanding anything in this Agreement, Qualcomm Atheros, Inc. Wi-Fi software must be used strictly in accordance with the Qualcomm Atheros, Inc. Technology License Agreement that accompanies such software. Any other use is expressly prohibited. + +Real Networks - GStreamer Optimized Real Format Client Code implementation or OpenMax Optimized Real Format Client Code: Use of the GStreamer Optimized Real Format Client Code, or OpenMax Optimized Real Format Client code is restricted to applications in the automotive market. Licensee must be a final manufacturer in good standing with a current license with Real Networks for the commercial use and distribution of products containing the GStreamer Optimized Real Format Client Code implementation or OpenMax Optimized Real Format Client Code + +Real-Time Innovations, Inc.: Not withstanding anything in this Agreement, Real-Time Innovations, Inc. software must be used strictly in accordance with Real-Time Innovations, Inc.'s Automotive Software Evaluation License Agreement, available here: https://www.rti.com/hubfs/_Collateral/Services_and_Support/Automotive_Evaluation_SLA_90_dayNXP.pdf .  Any other use is expressly prohibited. + +RivieraWaves SAS (a member of the CEVA, Inc. family of companies): You may not use the RivieraWaves intellectual property licensed under this Agreement if you develop, market, and/or license products similar to such RivieraWaves intellectual property. Such use constitutes a breach of this Agreement. Any such use rights must be obtained directly from RivieraWaves. + +SanDisk Corporation: If the Licensed Software includes software developed by SanDisk Corporation ("SanDisk"), you must separately obtain the rights to reproduce and distribute this software in source code form from SanDisk. Please follow these easy steps to obtain the license and software: +(1) Contact your local SanDisk sales representative to obtain the SanDisk License Agreement. +(2) Sign the license agreement. Fax the signed agreement to SanDisk USA marketing department at 408-542-0403. The license will be valid when fully executed by SanDisk. +(3) If you have specific questions, please send an email to sales@sandisk.com +You may only use the SanDisk Corporation Licensed Software on products compatible with a SanDisk Secure Digital Card. You may not use the SanDisk Corporation Licensed Software on any memory device product. SanDisk retains all rights to any modifications or derivative works to the SanDisk Corporation Licensed Software that you may create. + +SEGGER Microcontroller - emWin Software: Your use of SEGGER emWin software and components is restricted for development of NXP ARM7, ARM9, Cortex-M0, Cortex-M3, Cortex-M4, Cortex-M33, Cortex-M7, and Cortex-A7 based products only. + +SEGGER Microcontroller - J-Link/J-Trace Software: Segger software must be used consistent with the terms found here: http://www.segger.com/jlink-software.html + +Synopsys/BLE Software: Your use of the Synopsys/BLE Software and related documentation is subject to the following: +(1) Synopsys is third-party beneficiaries of, and thus may enforce against you, the license restrictions and confidentiality obligations in this agreement with respect to their intellectual property and proprietary information. +(2) Your distribution of the Licensed Software shall subject any recipient to a written agreement at least as protective of the Licensed Software as provided in this Agreement. + +Synopsys/Target Compiler Technologies: Your use of the Synopsys/Target Compiler Technologies Licensed Software and related documentation is subject to the following: +(1) Duration of the license for the Licensed Software is limited to 12 months, unless otherwise specified in the license file. +(2) The Licensed Software is usable by one user at a time on a single designated computer, unless otherwise agreed by Synopsys. +(3) Licensed Software and documentation are to be used only on a designated computer at the designated physical address provided by you on the APEX license form. +(4) The Licensed Software is not sub-licensable. + +T2 Labs / T2 Software: As a condition to the grant of any license under this Agreement, you represent and warrant that you will comply with all licenses, agreements, rules and bylaws of the Bluetooth SIG (Special Interest Group ) applicable to the licensed software and documentation and its use which may affect when and if you may take certain actions under licenses granted hereunder. + +The license grant under this Agreement is conditional to you being (i) a Bluetooth SIG Associate member until such time as the specifications for the software are made public to Bluetooth SIG members of any level and (ii) thereafter a Bluetooth SIG member of any level. + +Notwithstanding the terms contained in Section 2.3 (a), if the licensed software includes proprietary software in source code format, you may make modifications and create derivative works only to the extent necessary for improving the performance of the source code with the NXP products or your products and for creating enhancements of such products. You may not further sublicense or otherwise distribute the source code, or any modifications or derivatives thereof as stand-alone products. You will be responsible for qualifying any modifications or derivatives with the Bluetooth SIG and any other qualifying bodies. +TARA Systems: Use of TARA Systems GUI technology Embedded Wizard is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from TARA Systems. + +Texas Instruments: Your use of Texas Instruments Inc. WiLink8 Licensed Software is restricted to NXP SoC based systems that include a compatible connectivity device manufactured by TI. + +TES Electronic Solutions Germany (TES): TES 3D Surround View software and associated data and documentation may only be used for evaluation purposes and for demonstration to third parties in integrated form on a board package containing an NXP S32V234 device. Licensee may not distribute or sublicense the TES software. Your license to the TES software may be terminated at any time upon notice. + +Vivante: Distribution of Vivante software must be a part of, or embedded within, Authorized Systems that include a Vivante Graphics Processing Unit. diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/README.md b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/README.md new file mode 100644 index 0000000000000000000000000000000000000000..7b678d99d662540a5dd1ce75c8a669795388c046 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/README.md @@ -0,0 +1,9 @@ +## 如何查看该GUI工程 +在恩智浦的[GUIguider官网](https://www.nxp.com.cn/design/design-center/software/development-software/gui-guider:GUI-GUIDER)下载1.7.2版本的GUIguider，并导入该工程即可查看。 + +## 为什么我打开的工程和展示出的图形界面不一致 +由于GUIguider中的部分控件不能调整颜色和字体，只能在移植到STM32后再对代码进行更改。 + +出现以下工程界面是正常的 + +![工程界面](https://github.com/Floatkyun/Ultra-Vision/blob/main/GUI/GUIguider_Project/img/工程界面.png) diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/SCR.txt b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/SCR.txt new file mode 100644 index 0000000000000000000000000000000000000000..351c2b14487e20a26e55992da0ce3a12eef3b224 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/SCR.txt @@ -0,0 +1,484 @@ +Software Content Register + +Package: +Version: +Outgoing License: +License File: +Description and comments: +Release Location: +Origin: NXP (BSD-3-Clause) + NXP (Apache License 2.0) + NXP (MIT) + Amazon (MIT) + Electronic Lives Mfg. by ChaN of Ageo city, Japan (FatFs License) + CMSIS - ARM (Apache-2.0) - https://github.com/ARM-software/CMSIS_5/ + CMSIS_ICCARM - IAR Systems, ARM (Apache-2.0) - https://github.com/ARM-software/CMSIS_5/ + Samsung - https://github.com/libsdl-org/SDL + Samsung - https://github.com/Samsung/rlottie + freertos - Amazon (MIT) - https://aws.amazon.com/freertos/ + Petteri Aimonen (https://github.com/PetteriAimonen) + VeriSilicon (MIT), Raph Levien, Nicolas Silva (Apache-2.0) + lvgl - Gabor Kiss-Vamosi (MIT) - https://github.com/lvgl/lvgl + lvgl_tlsf- Matthew Conte (BSD-3-Clause) - https://github.com/lvgl/lvgl + Cisco (BSD-2-Clause) - https://github.com/cisco/openh264/tree/v2.1.1 + https://lvgl.io/assets/others/FontAwesome5-Solid+Brands+Regular.woff + https://fonts.google.com/specimen/Montserrat/about + https://github.com/micmro/Stylify-Me/blob/main/.fonts + https://www.cufonfonts.com/ + https://www.fontsquirrel.com/ + ArchitectsDaughter font file + +Folder Name: custom +CUSTOM CODE FOLDER Name: custom + Version: NA + Outgoing License: LA_OPT_NXP_Software_License.txt v45 May 2023 + License File: LICENSE.txt + Format: source code + Description: custom code function file. + Location: custom + Origin: MIT - NXP created + +------------------------------------------------------------- +Folder Name: generated +GENERATED CODE FOLDER Name: generated + Version: NA + Outgoing License: LA_OPT_NXP_Software_License.txt v45 May 2023 + License File: LICENSE.txt + Format: source code + Description: Gui Guider generate application code. + Location: generated + Origin: MIT - NXP created + +------------------------------------------------------------- +Folder Name: lib +GENERATED CODE FOLDER Name: lib + Version: NA + Outgoing License: LA_OPT_NXP_Software_License.txt v45 May 2023 + License File: LICENSE.txt + Format: binary + Description: Libraries for GUI Guider advanced widgets. + Location: lib + Origin: MIT - NXP created + +------------------------------------------------------------- + +------------------------------------------------------------- +Import Fonts packages +------------------------------------------------------------- + +Package: arial.TTF +Outgoing License: Free for commercial use - https://www.cufonfonts.com/font/arial +License File: https://www.cufonfonts.com/font/arial - License +Package Category: font +Type of Content: ttf +Description and comments: Arial font file +Location: import/font +Origin: https://www.cufonfonts.com/ + +Package: Abel-regular.ttf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: import\font\Licenses\License-abel.txt +Package Category: font +Type of Content: ttf +Description and comments: abel-regular font file +Location: import/font +Origin: https://www.fontsquirrel.com/ + +Package: Acme-Regular.ttf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: import\font\Licenses\License-Acme.txt +Package Category: font +Type of Content: ttf +Description and comments: Acme-Regular font file +Location: import/font +Origin: https://www.fontsquirrel.com/ + +Package: Adventpro-regular.ttf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: import\font\Licenses\License-adventpro.txt +Package Category: font +Type of Content: ttf +Description and comments: adventpro-regular font file +Location: import/font +Origin: https://www.fontsquirrel.com/ + +Package: AguafinaScript-Regular.ttf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: import\font\Licenses\License-AguafinaScript.txt +Package Category: font +Type of Content: ttf +Description and comments: AguafinaScript-Regular font file +Location: import/font +Origin: https://www.fontsquirrel.com/ + +Package: Alatsi-Regular.ttf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: import\font\Licenses\License-Alatsi.txt +Package Category: font +Type of Content: ttf +Description and comments: Alatsi-Regular font file +Location: import/font +Origin: https://www.fontsquirrel.com/ + +Package: AlexBrush-Regular.ttf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: import\font\Licenses\License-AlexBrush.txt +Package Category: font +Type of Content: ttf +Description and comments: AlexBrush-Regular font file +Location: import/font +Origin: https://www.fontsquirrel.com/ + +Package: AmaticSC-Regular.ttf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: import\font\Licenses\License-AmaticSC.txt +Package Category: font +Type of Content: ttf +Description and comments: AmaticSC-Regular font file +Location: import/font +Origin: https://www.fontsquirrel.com/ + +Package: Amiko-Regular.ttf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: import\font\Licenses\License-Amiko.txt +Package Category: font +Type of Content: ttf +Description and comments: Amiko-Regular font file +Location: import/font +Origin: https://www.fontsquirrel.com/ + +Package: Antonio-Regular.ttf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: import\font\Licenses\License-Antonio.txt +Package Category: font +Type of Content: ttf +Description and comments: Antonio-Regular font file +Location: import/font +Origin: https://www.fontsquirrel.com/ + +Package: ArchitectsDaughter.ttf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: import\font\Licenses\License-ArchitectsDaughter.txt +Package Category: font +Type of Content: ttf +Description and comments: ArchitectsDaughter font file +Location: import/font +Origin: ArchitectsDaughter font file + +Package: FontAwesome5.woff +Outgoing License: For free. +License File: https://fontawesome.com/docs +Package Category: font +Type of Content: woff +Description and comments: FontAwesome5 font file +Location: import/font +Origin: https://lvgl.io/assets/others/FontAwesome5-Solid+Brands+Regular.woff + +Package: montserratMedium.ttf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: https://github.com/JulietaUla/Montserrat/blob/master/OFL.txt +Package Category: font +Type of Content: ttf +Description and comments: montserratMedium font file +Location: import/font +Origin: https://fonts.google.com/specimen/Montserrat/about + +Package: SourceHanSerifSC-Regular.otf +Outgoing License: SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +License File: https://github.com/adobe-fonts/source-han-serif/blob/release/LICENSE.txt +Package Category: font +Type of Content: otf +Description and comments: SourceHanSerifSC simplifiedChinese file +Location: import/font +Origin: https://github.com/adobe-fonts/source-han-serif/blob/release/OTF/SimplifiedChinese/SourceHanSerifSC-Regular.otf + +------------------------------------------------------------- + +------------------------------------------------------------- +Folder Name: lvgl +lvgl Name: LVGL + Version: 8.3.10 + Outgoing License: MIT + License File: lvgl/LICENSE + Format: source code + Description: Light and Versatile Graphics Library + (LVGL) + Location: lvgl + Origin: Gabor Kiss-Vamosi + Url: https://github.com/lvgl/lvgl + +lvgl_tlsf Name: LVGL tlsf + Version: 8.3.10 + Outgoing License: BSD-3-Clause + License File: BSD-3-Clause + Format: source code + Description and comments: Light and Versatile Graphics Library (LVGL) + Release location: + Origin: Matthew Conte - https://github.com/lvgl/lvgl + +lv_printf Name: LVGL printf + Version: 8.3.10 + Outgoing License: MIT + License File: MIT + Format: source code + Description and comments: LVGL print function + Release location: + Origin: Marco Paland - https://github.com/lvgl/lvgl + +qrcode Name: QR Code + Version: 8.3.10 + Outgoing License: MIT + License File: MIT + Format: source code + Description and comments: QR Code function + Release location: + Origin: Project Nayuki - https://github.com/lvgl/lvgl + +png Name: png + Version: 8.3.10 + Outgoing License: MIT + License File: MIT + Format: source code + Description and comments: png function + Release location: + Origin: Lode Vandevenne - https://github.com/lvgl/lvgl + +jpg Name: jpg + Version: 8.3.10 + Outgoing License: MIT + License File: MIT + Format: source code + Description and comments: jpg function + Release location: + Origin: ChaN - https://github.com/lvgl/lvgl + +------------------------------------------------------------- +Folder Name: lvgl-simulator +lv_drivers Name: LVGL Simulator drivers + Version: NA + Outgoing License: MIT + License File: lvgl-simulator/lv_drivers/LICENSE + Format: source code + Description: Light and Versatile Graphics Library + (LVGL) + Location: lvgl-simulator/lv_drivers + Origin: Gabor Kiss-Vamosi + Url: https://github.com/lvgl/lvgl + + +rlottie Name: rlottie H files + Version: NA + Outgoing License: MIT + License File: https://github.com/Samsung/rlottie/blob/master/COPYING + Format: source code + Description: rlottie is a platform independent standalone c++ library + for rendering vector based animations and art in realtime. + Location: lvgl-simulator/rlottie + Origin: Samsung + Url: https://github.com/Samsung/rlottie + +SDL2 Name: SDL2 + Version: NA + Outgoing License: zlib License + License File: https://github.com/libsdl-org/SDL/blob/main/LICENSE.txt + Format: source code + Description: It is used by video playback software, emulators, + and popular games including Valve's award winning catalog and many Humble Bundle games + Location: lvgl-simulator/SDL2 + Origin: Samsung + Url: https://github.com/libsdl-org/SDL + +wels Name: openh264 H file + Version: 2.1.1 + Outgoing License: BSD-2-Clause + License File: https://github.com/cisco/openh264/blob/master/LICENSE + Format: source code + Description: Codec library which supports H.264 + encoding and decoding + Location: lvgl-simulator/wels + Origin: Cisco (BSD-2-Clause) - + https://github.com/cisco/openh264/tree/v2.1.1 + +------------------------------------------------------------- +Folder Name: temp +GENERATED CODE FOLDER Name: temp + Version: NA + Outgoing License: LA_OPT_NXP_Software_License.txt v45 May 2023 + License File: LICENSE.txt + Format: source code + Description: Gui Guider generate temporary lv_conf file. + Location: generated + Origin: MIT - NXP created + +------------------------------------------------------------- +Folder Name: ports +PORTS OS TEMPLATE FOLDER Name: ports + Version: NA + Outgoing License: LA_OPT_NXP_Software_License.txt v45 May 2023 + License File: LICENSE.txt + Format: source code + Description: custom code added. + Location: custom + Origin: MIT - NXP created + +------------------------------------------------------------- +Folder Name: sdk/Core +Package License: LA_OPT_NXP_Software_License.txt v45 May 2023 +SDK_Peripheral_Driver Name: SDK Peripheral Driver + Version: 2.x.x + Outgoing License: BSD-3-clause + License File: COPYING-BSD-3 + Format: source code + Description: Peripheral drivers are designed for + the most common use cases identified for the + underlying hardware block. + Location: sdk/Core/drivers + Origin: NXP (BSD-3-Clause) + +SDK_Device Name: SDK SoC files + Version: NA + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code, linker files + Description: Device system files, template files, + IDE related startup and linker files. + Location: sdk/Core/device + Origin: NXP (BSD-3-Clause) + +SDK_Components Name: SDK components and board peripheral drivers + Version: NA + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code + Description: SDK components and board peripheral + drivers, for example, flash and codec drivers. + Location: sdk/Core/component + Origin: NXP (BSD-3-Clause), ITE (BSD-3-Clause) + +cmsis_drivers Name: SDK CMSIS Peripheral Drivers + Version: 2.x.x + Outgoing License: Apache License 2.0 + License File: sdk/Core/CMSIS_driver/LICENSE.txt + Format: source code + Description: CMSIS Peripheral drivers are designed + to provide hardware independent APIs which make + application reusable across a wide range of + supported microcontroller devices. + Location: sdk/Core/CMSIS_driver + Origin: NXP (Apache License 2.0) + +cmsis Name: SDK CMSIS Peripheral Drivers + Version: 2.x.x + Outgoing License: Apache License 2.0 + License File: sdk/Core/CMSIS/LICENSE.txt + Format: source code + Description: CMSIS Peripheral drivers are designed + to provide hardware independent APIs which make + application reusable across a wide range of + supported microcontroller devices. + Location: sdk/Core/CMSIS + Origin: NXP (Apache License 2.0) + +fatfs Name: FatFs + Version: 0.14b + Outgoing License: FatFs License + Approved open source license: Yes + License File: sdk/Core/fatfs/LICENSE.txt + Format: source code + Description: Generic FAT file system for small + embedded devices. + Location: sdk/Core/fatfs + Origin: Electronic Lives Mfg. by ChaN of Ageo + city, Japan (FatFs License) + Url: http://elm-chan.org/fsw/ff/00index_e.html + +freertos-kernel Name: FreeRTOS kernel + Version: 10.5.1 + Outgoing License: MIT + License File: + sdk/Core/freertos/freertos-kernel/LICENSE.md + Format: source code + Description: Open source RTOS kernel for small + devices + Location: rtos/freertos/freertos-kernel + Origin: Amazon (MIT) + Url: https://github.com/FreeRTOS/FreeRTOS-Kernel + +openh264 Name: OpenH264 + Version: 2.1.1 + Outgoing License: BSD-2-Clause + License File: sdk/Core/openh264/LICENSE + Format: source code + Description: Codec library which supports H.264 + encoding and decoding + Location: sdk/Core/openh264 + Origin: Cisco (BSD-2-Clause) - + https://github.com/cisco/openh264/tree/v2.1.1 + +sdmmc Name: SD MMC SDIO Card middleware + Version: 2.2.7 + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code + Description: A software component support SD card, + eMMC card, SDIO card. + Location: sdk/Core/sdmmc + Origin: NXP (BSD-3-Clause) + +lvgl Name: LVGL + Version: 8.3.5 + Outgoing License: MIT + License File: sdk/Core/lvgl/lvgl/LICENCE.txt + Format: source code + Description: Light and Versatile Graphics Library + (LVGL) + Location: sdk/Core/lvgl + Origin: Gabor Kiss-Vamosi + Url: https://github.com/lvgl/lvgl + +rlottie Name: rlottie + Version: NA + Outgoing License: MIT + License File: https://github.com/Samsung/rlottie/blob/master/COPYING + Format: source code + Description: rlottie is a platform independent standalone c++ library + for rendering vector based animations and art in realtime. + Location: sdk/Core/rlottie + Origin: Samsung + Url: https://github.com/Samsung/rlottie + +board Name: board + Version: NA + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code + Description: SDK out of box examples to show how + to use peripheral drivers and integrate middleware. + Location: sdk/Core/board + Origin: NXP (BSD-3-Clause) + +vglite Name: vglite + Version: 3.0.15_rev7 + Outgoing License: MIT + License File: sdk/Core/vglite/LICENSE.txt + Format: source code + Description: VeriSilicon's platform independent + VGLite Graphics library + Location: sdk/Core/vglite + Origin: VeriSilicon (MIT), Raph Levien, Nicolas + Silva (Apache-2.0) + Url: http://www.verisilicon.com/, + https://github.com/linebender/kurbo + +vglite_mcufont Name: mcufont + Version: 1.0 + Outgoing License: MIT + License File: + sdk/Core/vglite/font/mcufont/LICENSE + Format: source code + Description: Font rendering library for + microcontrollers + Location: sdk/Core/vglite/font + Origin: Petteri Aimonen + (https://github.com/PetteriAimonen) + Url: https://github.com/mcufont/mcufont \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/custom/custom.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/custom/custom.c new file mode 100644 index 0000000000000000000000000000000000000000..ed3f1d9bbb34c46ccd1c7d05c147a3cf7e3ed202 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/custom/custom.c @@ -0,0 +1,42 @@ +/* +* Copyright 2023 NXP +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in +* accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, +* activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license +* terms, then you may not retain, install, activate or otherwise use the software. +*/ + + +/********************* + * INCLUDES + *********************/ +#include +#include "lvgl.h" +#include "custom.h" + +/********************* + * DEFINES + *********************/ + +/********************** + * TYPEDEFS + **********************/ + +/********************** + * STATIC PROTOTYPES + **********************/ + +/********************** + * STATIC VARIABLES + **********************/ + +/** + * Create a demo application + */ + +void custom_init(lv_ui *ui) +{ + /* Add your codes here */ +} + diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/custom/custom.h b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/custom/custom.h new file mode 100644 index 0000000000000000000000000000000000000000..63395064f65bca2a370aa9d23f6e2ddc226fc4d1 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/custom/custom.h @@ -0,0 +1,23 @@ +/* +* Copyright 2023 NXP +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in +* accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, +* activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license +* terms, then you may not retain, install, activate or otherwise use the software. +*/ + +#ifndef __CUSTOM_H_ +#define __CUSTOM_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "gui_guider.h" + +void custom_init(lv_ui *ui); + +#ifdef __cplusplus +} +#endif +#endif /* EVENT_CB_H_ */ diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/custom/lv_conf_ext.h b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/custom/lv_conf_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..9a1270e1290b7edf0039065a7ebd24d8bd88669d --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/custom/lv_conf_ext.h @@ -0,0 +1,42 @@ +/* +* Copyright 2023 NXP +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in +* accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, +* activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license +* terms, then you may not retain, install, activate or otherwise use the software. +*/ + +/* + * lv_conf_ext.h for custom lvconf file. + * Created on: Feb 8, 2023 + * example : + * #undef LV_FONT_FMT_TXT_LARGE + * #define LV_FONT_FMT_TXT_LARGE 1 + */ + +#ifndef LV_CONF_EXT_H +#define LV_CONF_EXT_H + + +/* common code begin */ + + +/* common code end */ + + +#if LV_USE_GUIDER_SIMULATOR +/* code for simulator begin */ + + +/* code for simulator end */ +#else +/* code for board begin */ + + +/* code for board end */ +#endif + + + +#endif /* LV_CONF_EXT_H */ \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/events_init.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/events_init.c new file mode 100644 index 0000000000000000000000000000000000000000..8017d6add215fdb4c55b3dee318ee428bd474ee9 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/events_init.c @@ -0,0 +1,329 @@ +/* +* Copyright 2024 NXP +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in +* accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, +* activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license +* terms, then you may not retain, install, activate or otherwise use the software. +*/ + +#include "events_init.h" +#include +#include "lvgl.h" + +#if LV_USE_FREEMASTER +#include "freemaster_client.h" +#endif + + +static void screen_slider_x_pix_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_PRESSED: + { + ui_move_animation(guider_ui.screen_btn_select, 300, 0, 65, 40, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + ui_scale_animation(guider_ui.screen_btn_select, 400, 0, 125, 70, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + break; + } + case LV_EVENT_VALUE_CHANGED: + { + lv_obj_clear_flag(guider_ui.screen_slider_x_pix, LV_OBJ_FLAG_HIDDEN); + break; + } + default: + break; + } +} +static void screen_btn_hand_set_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_SHORT_CLICKED: + { + ui_move_animation(guider_ui.screen_btn_select, 300, 0, 65, 40, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + ui_scale_animation(guider_ui.screen_btn_select, 400, 0, 125, 70, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + break; + } + default: + break; + } +} +static void screen_btn_demo_linear_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_SHORT_CLICKED: + { + ui_move_animation(guider_ui.screen_btn_select, 300, 0, 450, 15, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + ui_scale_animation(guider_ui.screen_btn_select, 400, 0, 263, 50, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + break; + } + default: + break; + } +} +static void screen_btn_demo_nonlinear_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_SHORT_CLICKED: + { + ui_move_animation(guider_ui.screen_btn_select, 300, 0, 450, 85, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + ui_scale_animation(guider_ui.screen_btn_select, 400, 0, 265, 50, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + break; + } + default: + break; + } +} +static void screen_ddlist_nonlinear_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_VALUE_CHANGED: + { + lv_obj_clear_flag(guider_ui.screen_ddlist_nonlinear, LV_OBJ_FLAG_HIDDEN); + uint16_t id = lv_dropdown_get_selected(guider_ui.screen_ddlist_nonlinear); + switch(id) { + default: + break; + } + break; + } + default: + break; + } +} +static void screen_img_1_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_CLICKED: + { + lv_obj_clear_flag(guider_ui.screen_Alpha_cont, LV_OBJ_FLAG_HIDDEN); + break; + } + default: + break; + } +} +static void screen_ddlist_min_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_VALUE_CHANGED: + { + lv_obj_clear_flag(guider_ui.screen_ddlist_min, LV_OBJ_FLAG_HIDDEN); + uint16_t id = lv_dropdown_get_selected(guider_ui.screen_ddlist_min); + switch(id) { + default: + break; + } + break; + } + default: + break; + } +} +static void screen_ddlist_max_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_VALUE_CHANGED: + { + lv_obj_clear_flag(guider_ui.screen_ddlist_max, LV_OBJ_FLAG_HIDDEN); + uint16_t id = lv_dropdown_get_selected(guider_ui.screen_ddlist_max); + switch(id) { + default: + break; + } + break; + } + default: + break; + } +} +static void screen_slider_y_pix_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_VALUE_CHANGED: + { + lv_obj_clear_flag(guider_ui.screen_slider_y_pix, LV_OBJ_FLAG_HIDDEN); + break; + } + case LV_EVENT_PRESSED: + { + ui_move_animation(guider_ui.screen_btn_select, 300, 0, 65, 40, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + ui_scale_animation(guider_ui.screen_btn_select, 400, 0, 125, 70, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + break; + } + default: + break; + } +} +static void screen_btnm_x_pic_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_PRESSED: + { + lv_obj_t * obj = lv_event_get_target(e); + uint32_t id = lv_btnmatrix_get_selected_btn(obj); + switch(id) { + case 0: + { + lv_obj_clear_flag(guider_ui.screen_btnm_x_pic, LV_OBJ_FLAG_HIDDEN); + ui_move_animation(guider_ui.screen_btn_select, 300, 0, 65, 40, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + ui_scale_animation(guider_ui.screen_btn_select, 400, 0, 125, 70, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + break; + } + case 1: + { + lv_obj_clear_flag(guider_ui.screen_btnm_x_pic, LV_OBJ_FLAG_HIDDEN); + ui_move_animation(guider_ui.screen_btn_select, 300, 0, 65, 40, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + ui_scale_animation(guider_ui.screen_btn_select, 400, 0, 125, 70, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + break; + } + default: + break; + } + break; + } + default: + break; + } +} +static void screen_btnm_y_pic_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_PRESSED: + { + lv_obj_t * obj = lv_event_get_target(e); + uint32_t id = lv_btnmatrix_get_selected_btn(obj); + switch(id) { + case 0: + { + lv_obj_clear_flag(guider_ui.screen_btnm_x_pic, LV_OBJ_FLAG_HIDDEN); + ui_move_animation(guider_ui.screen_btn_select, 300, 0, 65, 40, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + ui_scale_animation(guider_ui.screen_btn_select, 400, 0, 125, 70, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + break; + } + case 1: + { + lv_obj_clear_flag(guider_ui.screen_btnm_x_pic, LV_OBJ_FLAG_HIDDEN); + ui_move_animation(guider_ui.screen_btn_select, 300, 0, 65, 40, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + ui_scale_animation(guider_ui.screen_btn_select, 400, 0, 125, 70, &lv_anim_path_bounce, 0, 0, 0, 0, NULL, NULL, NULL); + break; + } + default: + break; + } + break; + } + default: + break; + } +} +static void screen_ddlist_vid_format_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_VALUE_CHANGED: + { + lv_obj_clear_flag(guider_ui.screen_ddlist_vid_format, LV_OBJ_FLAG_HIDDEN); + uint16_t id = lv_dropdown_get_selected(guider_ui.screen_ddlist_vid_format); + switch(id) { + default: + break; + } + break; + } + default: + break; + } +} +static void screen_ddlist_algorithm_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_VALUE_CHANGED: + { + lv_obj_clear_flag(guider_ui.screen_ddlist_algorithm, LV_OBJ_FLAG_HIDDEN); + uint16_t id = lv_dropdown_get_selected(guider_ui.screen_ddlist_algorithm); + switch(id) { + default: + break; + } + break; + } + default: + break; + } +} +static void screen_slider_a_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_VALUE_CHANGED: + { + lv_obj_clear_flag(guider_ui.screen_slider_a, LV_OBJ_FLAG_HIDDEN); + break; + } + default: + break; + } +} +static void screen_btn_1_event_handler (lv_event_t *e) +{ + lv_event_code_t code = lv_event_get_code(e); + + switch (code) { + case LV_EVENT_CLICKED: + { + lv_obj_add_flag(guider_ui.screen_Alpha_cont, LV_OBJ_FLAG_HIDDEN); + break; + } + default: + break; + } +} +void events_init_screen(lv_ui *ui) +{ + lv_obj_add_event_cb(ui->screen_slider_x_pix, screen_slider_x_pix_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_btn_hand_set, screen_btn_hand_set_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_btn_demo_linear, screen_btn_demo_linear_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_btn_demo_nonlinear, screen_btn_demo_nonlinear_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_ddlist_nonlinear, screen_ddlist_nonlinear_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_img_1, screen_img_1_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_ddlist_min, screen_ddlist_min_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_ddlist_max, screen_ddlist_max_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_slider_y_pix, screen_slider_y_pix_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_btnm_x_pic, screen_btnm_x_pic_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_btnm_y_pic, screen_btnm_y_pic_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_ddlist_vid_format, screen_ddlist_vid_format_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_ddlist_algorithm, screen_ddlist_algorithm_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_slider_a, screen_slider_a_event_handler, LV_EVENT_ALL, ui); + lv_obj_add_event_cb(ui->screen_btn_1, screen_btn_1_event_handler, LV_EVENT_ALL, ui); +} + +void events_init(lv_ui *ui) +{ + +} diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/events_init.h b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/events_init.h new file mode 100644 index 0000000000000000000000000000000000000000..c41097eaa3e7b94df56df9807f28f8424869f759 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/events_init.h @@ -0,0 +1,26 @@ +/* +* Copyright 2024 NXP +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in +* accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, +* activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license +* terms, then you may not retain, install, activate or otherwise use the software. +*/ + + +#ifndef EVENTS_INIT_H_ +#define EVENTS_INIT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "gui_guider.h" + +void events_init(lv_ui *ui); + +void events_init_screen(lv_ui *ui); + +#ifdef __cplusplus +} +#endif +#endif /* EVENT_CB_H_ */ diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/gui_guider.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/gui_guider.c new file mode 100644 index 0000000000000000000000000000000000000000..415dde7df21f8fc475e50136811b522c5b3b67c5 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/gui_guider.c @@ -0,0 +1,153 @@ +/* +* Copyright 2024 NXP +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in +* accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, +* activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license +* terms, then you may not retain, install, activate or otherwise use the software. +*/ + +#include "lvgl.h" +#include +#include "gui_guider.h" +#if LV_USE_FREEMASTER +#include "gg_external_data.h" +#endif + +void ui_init_style(lv_style_t * style) +{ + if (style->prop_cnt > 1) + lv_style_reset(style); + else + lv_style_init(style); +} + +void ui_load_scr_animation(lv_ui *ui, lv_obj_t ** new_scr, bool new_scr_del, bool * old_scr_del, ui_setup_scr_t setup_scr, + lv_scr_load_anim_t anim_type, uint32_t time, uint32_t delay, bool is_clean, bool auto_del) +{ + lv_obj_t * act_scr = lv_scr_act(); + +#if LV_USE_FREEMASTER + if(auto_del) { + gg_edata_task_clear(act_scr); + } +#endif + if (auto_del && is_clean) { + lv_obj_clean(act_scr); + } + if (new_scr_del) { + setup_scr(ui); + } + lv_scr_load_anim(*new_scr, anim_type, time, delay, auto_del); + *old_scr_del = auto_del; +} + +void ui_move_animation(void * var, int32_t duration, int32_t delay, int32_t x_end, int32_t y_end, lv_anim_path_cb_t path_cb, + uint16_t repeat_cnt, uint32_t repeat_delay, uint32_t playback_time, uint32_t playback_delay, + lv_anim_start_cb_t start_cb, lv_anim_ready_cb_t ready_cb, lv_anim_deleted_cb_t deleted_cb) +{ + lv_anim_t anim; + lv_anim_init(&anim); + lv_anim_set_var(&anim, var); + lv_anim_set_time(&anim, duration); + lv_anim_set_delay(&anim, delay); + lv_anim_set_path_cb(&anim, path_cb); + lv_anim_set_repeat_count(&anim, repeat_cnt); + lv_anim_set_repeat_delay(&anim, repeat_delay); + lv_anim_set_playback_time(&anim, playback_time); + lv_anim_set_playback_delay(&anim, playback_delay); + + lv_anim_set_exec_cb(&anim, (lv_anim_exec_xcb_t)lv_obj_set_x); + lv_anim_set_values(&anim, lv_obj_get_x(var), x_end); + lv_anim_start(&anim); + lv_anim_set_exec_cb(&anim, (lv_anim_exec_xcb_t)lv_obj_set_y); + lv_anim_set_values(&anim, lv_obj_get_y(var), y_end); + lv_anim_set_start_cb(&anim, start_cb); + lv_anim_set_ready_cb(&anim, ready_cb); + lv_anim_set_deleted_cb(&anim, deleted_cb); + lv_anim_start(&anim); +} + +void ui_scale_animation(void * var, int32_t duration, int32_t delay, int32_t width, int32_t height, lv_anim_path_cb_t path_cb, + uint16_t repeat_cnt, uint32_t repeat_delay, uint32_t playback_time, uint32_t playback_delay, + lv_anim_start_cb_t start_cb, lv_anim_ready_cb_t ready_cb, lv_anim_deleted_cb_t deleted_cb) +{ + lv_anim_t anim; + lv_anim_init(&anim); + lv_anim_set_var(&anim, var); + lv_anim_set_time(&anim, duration); + lv_anim_set_delay(&anim, delay); + lv_anim_set_path_cb(&anim, path_cb); + lv_anim_set_repeat_count(&anim, repeat_cnt); + lv_anim_set_repeat_delay(&anim, repeat_delay); + lv_anim_set_playback_time(&anim, playback_time); + lv_anim_set_playback_delay(&anim, playback_delay); + + lv_anim_set_exec_cb(&anim, (lv_anim_exec_xcb_t)lv_obj_set_width); + lv_anim_set_values(&anim, lv_obj_get_width(var), width); + lv_anim_start(&anim); + lv_anim_set_exec_cb(&anim, (lv_anim_exec_xcb_t)lv_obj_set_height); + lv_anim_set_values(&anim, lv_obj_get_height(var), height); + lv_anim_set_start_cb(&anim, start_cb); + lv_anim_set_ready_cb(&anim, ready_cb); + lv_anim_set_deleted_cb(&anim, deleted_cb); + lv_anim_start(&anim); +} + +void ui_img_zoom_animation(void * var, int32_t duration, int32_t delay, int32_t zoom, lv_anim_path_cb_t path_cb, + uint16_t repeat_cnt, uint32_t repeat_delay, uint32_t playback_time, uint32_t playback_delay, + lv_anim_start_cb_t start_cb, lv_anim_ready_cb_t ready_cb, lv_anim_deleted_cb_t deleted_cb) +{ + lv_anim_t anim; + lv_anim_init(&anim); + lv_anim_set_var(&anim, var); + lv_anim_set_time(&anim, duration); + lv_anim_set_delay(&anim, delay); + lv_anim_set_exec_cb(&anim, (lv_anim_exec_xcb_t)lv_img_set_zoom); + lv_anim_set_values(&anim, lv_img_get_zoom(var), zoom); + lv_anim_set_path_cb(&anim, path_cb); + lv_anim_set_repeat_count(&anim, repeat_cnt); + lv_anim_set_repeat_delay(&anim, repeat_delay); + lv_anim_set_playback_time(&anim, playback_time); + lv_anim_set_playback_delay(&anim, playback_delay); + lv_anim_set_start_cb(&anim, start_cb); + lv_anim_set_ready_cb(&anim, ready_cb); + lv_anim_set_deleted_cb(&anim, deleted_cb); + lv_anim_start(&anim); +} + +void ui_img_rotate_animation(void * var, int32_t duration, int32_t delay, lv_coord_t x, lv_coord_t y, int32_t rotate, + lv_anim_path_cb_t path_cb, uint16_t repeat_cnt, uint32_t repeat_delay, uint32_t playback_time, uint32_t playback_delay, + lv_anim_start_cb_t start_cb, lv_anim_ready_cb_t ready_cb, lv_anim_deleted_cb_t deleted_cb) +{ + lv_anim_t anim; + lv_anim_init(&anim); + lv_anim_set_var(&anim, var); + lv_anim_set_time(&anim, duration); + lv_anim_set_delay(&anim, delay); + lv_img_set_pivot(var, x, y); + lv_anim_set_exec_cb(&anim, (lv_anim_exec_xcb_t)lv_img_set_angle); + lv_anim_set_values(&anim, 0, rotate*10); + lv_anim_set_path_cb(&anim, path_cb); + lv_anim_set_repeat_count(&anim, repeat_cnt); + lv_anim_set_repeat_delay(&anim, repeat_delay); + lv_anim_set_playback_time(&anim, playback_time); + lv_anim_set_playback_delay(&anim, playback_delay); + lv_anim_set_start_cb(&anim, start_cb); + lv_anim_set_ready_cb(&anim, ready_cb); + lv_anim_set_deleted_cb(&anim, deleted_cb); + lv_anim_start(&anim); +} + +void init_scr_del_flag(lv_ui *ui) +{ + + ui->screen_del = true; +} + +void setup_ui(lv_ui *ui) +{ + init_scr_del_flag(ui); + setup_scr_screen(ui); + lv_scr_load(ui->screen); +} diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/gui_guider.h b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/gui_guider.h new file mode 100644 index 0000000000000000000000000000000000000000..013683aacc9c1cedae682bc7a0a72e8a7537bf3c --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/gui_guider.h @@ -0,0 +1,107 @@ +/* +* Copyright 2024 NXP +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in +* accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, +* activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license +* terms, then you may not retain, install, activate or otherwise use the software. +*/ + +#ifndef GUI_GUIDER_H +#define GUI_GUIDER_H +#ifdef __cplusplus +extern "C" { +#endif + +#include "lvgl.h" + +typedef struct +{ + + lv_obj_t *screen; + bool screen_del; + lv_obj_t *screen_slider_x_pix; + lv_obj_t *screen_cont_mode_control; + lv_obj_t *screen_label_1; + lv_obj_t *screen_btn_hand_set; + lv_obj_t *screen_btn_hand_set_label; + lv_obj_t *screen_btn_demo_linear; + lv_obj_t *screen_btn_demo_linear_label; + lv_obj_t *screen_btn_demo_nonlinear; + lv_obj_t *screen_btn_demo_nonlinear_label; + lv_obj_t *screen_cont_1; + lv_obj_t *screen_ddlist_nonlinear; + lv_obj_t *screen_label_2; + lv_obj_t *screen_btn_select; + lv_obj_t *screen_btn_select_label; + lv_obj_t *screen_label_x_pix_; + lv_obj_t *screen_label_y_pix_len_; + lv_obj_t *screen_label_y_pix; + lv_obj_t *screen_label_x_pix; + lv_obj_t *screen_img_1; + lv_obj_t *screen_ddlist_min; + lv_obj_t *screen_ddlist_max; + lv_obj_t *screen_label_3; + lv_obj_t *screen_label_4; + lv_obj_t *screen_slider_y_pix; + lv_obj_t *screen_btnm_x_pic; + lv_obj_t *screen_btnm_y_pic; + lv_obj_t *screen_label_vid_format; + lv_obj_t *screen_label_6; + lv_obj_t *screen_ddlist_vid_format; + lv_obj_t *screen_ddlist_algorithm; + lv_obj_t *screen_Alpha_cont; + lv_obj_t *screen_slider_a; + lv_obj_t *screen_label_a; + lv_obj_t *screen_label_a_value; + lv_obj_t *screen_btn_1; + lv_obj_t *screen_btn_1_label; +}lv_ui; + +typedef void (*ui_setup_scr_t)(lv_ui * ui); + +void ui_init_style(lv_style_t * style); + +void ui_load_scr_animation(lv_ui *ui, lv_obj_t ** new_scr, bool new_scr_del, bool * old_scr_del, ui_setup_scr_t setup_scr, + lv_scr_load_anim_t anim_type, uint32_t time, uint32_t delay, bool is_clean, bool auto_del); + +void ui_move_animation(void * var, int32_t duration, int32_t delay, int32_t x_end, int32_t y_end, lv_anim_path_cb_t path_cb, + uint16_t repeat_cnt, uint32_t repeat_delay, uint32_t playback_time, uint32_t playback_delay, + lv_anim_start_cb_t start_cb, lv_anim_ready_cb_t ready_cb, lv_anim_deleted_cb_t deleted_cb); + +void ui_scale_animation(void * var, int32_t duration, int32_t delay, int32_t width, int32_t height, lv_anim_path_cb_t path_cb, + uint16_t repeat_cnt, uint32_t repeat_delay, uint32_t playback_time, uint32_t playback_delay, + lv_anim_start_cb_t start_cb, lv_anim_ready_cb_t ready_cb, lv_anim_deleted_cb_t deleted_cb); + +void ui_img_zoom_animation(void * var, int32_t duration, int32_t delay, int32_t zoom, lv_anim_path_cb_t path_cb, + uint16_t repeat_cnt, uint32_t repeat_delay, uint32_t playback_time, uint32_t playback_delay, + lv_anim_start_cb_t start_cb, lv_anim_ready_cb_t ready_cb, lv_anim_deleted_cb_t deleted_cb); + +void ui_img_rotate_animation(void * var, int32_t duration, int32_t delay, lv_coord_t x, lv_coord_t y, int32_t rotate, + lv_anim_path_cb_t path_cb, uint16_t repeat_cnt, uint32_t repeat_delay, uint32_t playback_time, + uint32_t playback_delay, lv_anim_start_cb_t start_cb, lv_anim_ready_cb_t ready_cb, lv_anim_deleted_cb_t deleted_cb); + +void init_scr_del_flag(lv_ui *ui); + +void setup_ui(lv_ui *ui); + + +extern lv_ui guider_ui; + + +void setup_scr_screen(lv_ui *ui); +LV_IMG_DECLARE(_cbf040c3eda1f28470a3ec0f5384e18e1334bea0_alpha_242x106); + +LV_FONT_DECLARE(lv_font_MI_LanTing_Regular_28) +LV_FONT_DECLARE(lv_font_MI_LanTing_Regular_16) +LV_FONT_DECLARE(lv_font_montserratMedium_16) +LV_FONT_DECLARE(lv_font_montserratMedium_12) +LV_FONT_DECLARE(lv_font_MI_LanTing_Regular_24) +LV_FONT_DECLARE(lv_font_MI_LanTing_Regular_12) +LV_FONT_DECLARE(lv_font_MI_LanTing_Regular_18) + + +#ifdef __cplusplus +} +#endif +#endif diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_customer_fonts/guider_customer_fonts.h b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_customer_fonts/guider_customer_fonts.h new file mode 100644 index 0000000000000000000000000000000000000000..dde2676a3450349e3260c092547f4d5757484df1 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_customer_fonts/guider_customer_fonts.h @@ -0,0 +1,21 @@ +/* +* Copyright 2023 NXP +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in +* accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, +* activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license +* terms, then you may not retain, install, activate or otherwise use the software. +*/ + +#ifndef GUIDER_CUSTOMER_FONTS_H +#define GUIDER_CUSTOMER_FONTS_H +#ifdef __cplusplus +extern "C" { +#endif + +#include "lv_font.h" + +#ifdef __cplusplus +} +#endif +#endif \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_12.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_12.c new file mode 100644 index 0000000000000000000000000000000000000000..79b99f29f804732245ca2f7d89690715848d5235 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_12.c @@ -0,0 +1,1514 @@ +/* + * Copyright 2024 NXP + * NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in + * accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, + * activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to + * comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license + * terms, then you may not retain, install, activate or otherwise use the software. + */ +/******************************************************************************* + * Size: 12 px + * Bpp: 4 + * Opts: --user-data-dir=C:\Users\hp\AppData\Roaming\gui-guider --app-path=C:\NXP\GUI-Guider-1.7.2-GA\resources\app.asar --no-sandbox --no-zygote --lang=zh-CN --device-scale-factor=1.5 --num-raster-threads=4 --enable-main-frame-before-activation --renderer-client-id=5 --time-ticks-at-unix-epoch=-1732015070561205 --launch-time-ticks=65380923608 --mojo-platform-channel-handle=3108 --field-trial-handle=1864,i,17219279099561217522,18026807573185265005,131072 --disable-features=SpareRendererForSitePerProcess,WinRetrieveSuggestionsOnlyOnDemand /prefetch:1 + ******************************************************************************/ + +#ifdef LV_LVGL_H_INCLUDE_SIMPLE +#include "lvgl.h" +#else +#include "lvgl.h" +#endif + +#ifndef LV_FONT_MI_LANTING_REGULAR_12 +#define LV_FONT_MI_LANTING_REGULAR_12 1 +#endif + +#if LV_FONT_MI_LANTING_REGULAR_12 + +/*----------------- + * BITMAPS + *----------------*/ + +/*Store the image of the glyphs*/ +static LV_ATTRIBUTE_LARGE_CONST const uint8_t glyph_bitmap[] = { + /* U+0020 " " */ + + /* U+0021 "!" */ + 0xd5, 0xc5, 0xc4, 0xb4, 0xa3, 0xa2, 0x51, 0xc5, + + /* U+0022 "\"" */ + 0x5c, 0x4d, 0x4b, 0x3c, 0x29, 0x2a, 0x0, 0x0, + + /* U+0023 "#" */ + 0x0, 0x57, 0xc, 0x0, 0x9, 0x32, 0x90, 0x2b, + 0xeb, 0xcc, 0x80, 0xc, 0x9, 0x20, 0x3, 0x90, + 0xb0, 0x9, 0xdd, 0xbe, 0xb2, 0xa, 0x23, 0x90, + 0x0, 0xc0, 0x75, 0x0, + + /* U+0024 "$" */ + 0x0, 0x4, 0x0, 0x0, 0x5, 0xd6, 0x0, 0xc, + 0x8b, 0x7d, 0x12, 0xb0, 0x90, 0x85, 0x1d, 0x29, + 0x0, 0x0, 0x3c, 0xf7, 0x10, 0x0, 0x9, 0x6d, + 0x33, 0x30, 0x90, 0x3a, 0x3b, 0x9, 0x4, 0x90, + 0x6a, 0xc8, 0x91, 0x0, 0x9, 0x0, 0x0, + + /* U+0025 "%" */ + 0x9, 0xbb, 0x10, 0x9, 0x40, 0x2, 0x90, 0x47, + 0x3, 0xa0, 0x0, 0x1a, 0x5, 0x70, 0xc1, 0x0, + 0x0, 0x6a, 0x90, 0x76, 0x6a, 0x80, 0x0, 0x0, + 0x2b, 0x1a, 0x7, 0x40, 0x0, 0xb, 0x24, 0x70, + 0x47, 0x0, 0x5, 0x80, 0x2a, 0x7, 0x50, 0x1, + 0xc0, 0x0, 0x8b, 0xb0, + + /* U+0026 "&" */ + 0x0, 0x8b, 0xc5, 0x0, 0x0, 0x3a, 0x1, 0xd0, + 0x0, 0x1, 0xb0, 0x5a, 0x0, 0x0, 0x8, 0xe8, + 0x0, 0x30, 0xb, 0x74, 0xb1, 0x2b, 0x5, 0x80, + 0x2, 0xcb, 0x60, 0x4b, 0x0, 0x8, 0xe9, 0x0, + 0x7c, 0xcc, 0x70, 0x79, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+0027 "'" */ + 0x6b, 0x4a, 0x39, 0x0, + + /* U+0028 "(" */ + 0x0, 0x14, 0x0, 0xa2, 0x4, 0x80, 0xb, 0x20, + 0xd, 0x0, 0x2c, 0x0, 0x1c, 0x0, 0xc, 0x0, + 0x8, 0x40, 0x1, 0xb0, 0x0, 0x56, + + /* U+0029 ")" */ + 0x23, 0x0, 0xb, 0x10, 0x3, 0x80, 0x0, 0xc0, + 0x0, 0x94, 0x0, 0x76, 0x0, 0x85, 0x0, 0xa2, + 0x0, 0xb0, 0x7, 0x40, 0x29, 0x0, + + /* U+002A "*" */ + 0x0, 0xe0, 0x7, 0x9b, 0x87, 0x5, 0xc5, 0x0, + 0xb0, 0xb0, 0x0, 0x0, 0x0, + + /* U+002B "+" */ + 0x0, 0x8, 0x30, 0x0, 0x0, 0x94, 0x0, 0x0, + 0x9, 0x40, 0x3, 0xcc, 0xed, 0xcb, 0x0, 0x9, + 0x40, 0x0, 0x0, 0x94, 0x0, + + /* U+002C "," */ + 0x6, 0x40, 0xb2, 0xb, 0x0, + + /* U+002D "-" */ + 0x4d, 0xdd, 0xd5, + + /* U+002E "." */ + 0x32, 0xd9, + + /* U+002F "/" */ + 0x0, 0x84, 0x0, 0xc0, 0x2, 0x90, 0x7, 0x40, + 0xc, 0x0, 0x2a, 0x0, 0x75, 0x0, 0xc0, 0x0, + + /* U+0030 "0" */ + 0x2, 0xcc, 0xc2, 0x0, 0xd3, 0x3, 0xd0, 0x4a, + 0x0, 0xa, 0x46, 0x70, 0x0, 0x76, 0x67, 0x0, + 0x7, 0x64, 0xa0, 0x0, 0xa4, 0xd, 0x30, 0x2d, + 0x0, 0x2c, 0xcc, 0x20, + + /* U+0031 "1" */ + 0x3, 0xbc, 0x1a, 0x3c, 0x0, 0x1c, 0x0, 0x1c, + 0x0, 0x1c, 0x0, 0x1c, 0x0, 0x1c, 0x0, 0x1c, + + /* U+0032 "2" */ + 0x5, 0xcd, 0xb2, 0x2, 0xc0, 0x3, 0xc0, 0x23, + 0x0, 0xd, 0x0, 0x0, 0x8, 0x70, 0x0, 0x7, + 0x90, 0x0, 0x7, 0x90, 0x0, 0x8, 0x90, 0x0, + 0x5, 0xfc, 0xcc, 0xc1, + + /* U+0033 "3" */ + 0x5, 0xcc, 0xb4, 0x0, 0x90, 0x0, 0xd0, 0x0, + 0x0, 0x2e, 0x0, 0x6, 0xdf, 0x50, 0x0, 0x0, + 0x3c, 0x0, 0x0, 0x0, 0xa4, 0x3a, 0x0, 0x1d, + 0x10, 0x7c, 0xcc, 0x40, + + /* U+0034 "4" */ + 0x0, 0x0, 0xc4, 0x0, 0x0, 0xad, 0x40, 0x0, + 0x86, 0x94, 0x0, 0x69, 0x9, 0x40, 0x4b, 0x0, + 0x94, 0xb, 0xcc, 0xce, 0xd9, 0x0, 0x0, 0x94, + 0x0, 0x0, 0x9, 0x40, + + /* U+0035 "5" */ + 0xb, 0xcc, 0xca, 0x0, 0xd0, 0x0, 0x0, 0xe, + 0xac, 0x91, 0x1, 0xb1, 0x5, 0xb0, 0x0, 0x0, + 0xc, 0x10, 0x0, 0x0, 0xc1, 0x28, 0x0, 0x3c, + 0x0, 0x7c, 0xcb, 0x20, + + /* U+0036 "6" */ + 0x2, 0xcc, 0xd7, 0x0, 0xb1, 0x0, 0x50, 0x3a, + 0xac, 0xa1, 0x5, 0xf3, 0x3, 0xc0, 0x69, 0x0, + 0xa, 0x35, 0x80, 0x0, 0xa3, 0x1d, 0x10, 0x2d, + 0x0, 0x4c, 0xcb, 0x30, + + /* U+0037 "7" */ + 0x3c, 0xcc, 0xcf, 0x10, 0x0, 0x3, 0xb0, 0x0, + 0x0, 0xb3, 0x0, 0x0, 0x3b, 0x0, 0x0, 0xa, + 0x40, 0x0, 0x2, 0xc0, 0x0, 0x0, 0xa4, 0x0, + 0x0, 0x2c, 0x0, 0x0, + + /* U+0038 "8" */ + 0x4, 0xcc, 0xc4, 0x0, 0xd1, 0x1, 0xe0, 0xc, + 0x20, 0x2d, 0x0, 0x4f, 0xdf, 0x40, 0x2c, 0x10, + 0x1c, 0x27, 0x70, 0x0, 0x76, 0x4b, 0x0, 0xb, + 0x30, 0x6c, 0xcc, 0x50, + + /* U+0039 "9" */ + 0x4, 0xcc, 0xb3, 0x2, 0xc1, 0x2, 0xc0, 0x58, + 0x0, 0xb, 0x32, 0xc1, 0x3, 0xf4, 0x4, 0xbb, + 0x9b, 0x30, 0x0, 0x0, 0xc1, 0x39, 0x0, 0x5c, + 0x0, 0x7c, 0xcc, 0x10, + + /* U+003A ":" */ + 0xd8, 0x42, 0x0, 0x0, 0x42, 0xd8, + + /* U+003B ";" */ + 0xd8, 0x42, 0x0, 0x0, 0x42, 0xd8, 0x36, 0x81, + 0x0, + + /* U+003C "<" */ + 0x0, 0x0, 0x0, 0x60, 0x0, 0x5, 0xd7, 0x0, + 0x4c, 0x81, 0x1, 0xb9, 0x10, 0x0, 0x2c, 0x50, + 0x0, 0x0, 0x8, 0xc4, 0x0, 0x0, 0x1, 0xab, + 0x30, 0x0, 0x0, 0x3a, + + /* U+003D "=" */ + 0x3c, 0xcc, 0xcc, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3, 0xcc, 0xcc, 0xc8, + + /* U+003E ">" */ + 0x23, 0x0, 0x0, 0x1, 0xba, 0x20, 0x0, 0x0, + 0x3b, 0x91, 0x0, 0x0, 0x4, 0xb7, 0x0, 0x0, + 0x19, 0xa0, 0x0, 0x8c, 0x40, 0x6, 0xd6, 0x0, + 0x4, 0x80, 0x0, 0x0, + + /* U+003F "?" */ + 0x4, 0xbb, 0xc6, 0x2, 0xd1, 0x0, 0xd3, 0x2, + 0x0, 0xc, 0x40, 0x0, 0x8, 0xa0, 0x0, 0xb, + 0x60, 0x0, 0x0, 0xc0, 0x0, 0x0, 0x1, 0x0, + 0x0, 0x3, 0xe0, 0x0, + + /* U+0040 "@" */ + 0x0, 0x5, 0xbb, 0xbb, 0x70, 0x0, 0xa, 0x60, + 0x0, 0x6, 0xc0, 0x8, 0x40, 0x8a, 0xad, 0x8, + 0x60, 0xb0, 0x77, 0x1, 0xd0, 0x2a, 0x39, 0xd, + 0x0, 0x2a, 0x2, 0x94, 0x90, 0xc1, 0x9, 0x90, + 0x93, 0x1d, 0x2, 0x99, 0x29, 0x94, 0x0, 0xa4, + 0x0, 0x0, 0x0, 0x20, 0x1, 0xc5, 0x0, 0x1, + 0x7a, 0x0, 0x0, 0x6a, 0xaa, 0x83, 0x0, + + /* U+0041 "A" */ + 0x0, 0x8, 0xd0, 0x0, 0x0, 0x0, 0xb5, 0x70, + 0x0, 0x0, 0x74, 0xb, 0x0, 0x0, 0xa, 0x0, + 0x56, 0x0, 0x5, 0xdc, 0xcc, 0xc0, 0x0, 0xb0, + 0x0, 0x7, 0x50, 0x49, 0x0, 0x0, 0x1c, 0xb, + 0x30, 0x0, 0x0, 0xb4, + + /* U+0042 "B" */ + 0xf, 0xdd, 0xdc, 0x50, 0xe, 0x0, 0x0, 0xd3, + 0xe, 0x0, 0x2, 0xd1, 0xf, 0xee, 0xee, 0x50, + 0xe, 0x0, 0x1, 0xc4, 0xe, 0x0, 0x0, 0x5a, + 0xe, 0x0, 0x0, 0xa7, 0xf, 0xcc, 0xcc, 0x80, + + /* U+0043 "C" */ + 0x0, 0x5c, 0xcc, 0xa1, 0x0, 0x6c, 0x10, 0x6, + 0xe1, 0xe, 0x20, 0x0, 0x4, 0x13, 0xd0, 0x0, + 0x0, 0x0, 0x3c, 0x0, 0x0, 0x0, 0x0, 0xe1, + 0x0, 0x0, 0x85, 0x6, 0xc1, 0x0, 0x5e, 0x10, + 0x4, 0xbc, 0xca, 0x20, + + /* U+0044 "D" */ + 0xf, 0xcc, 0xdd, 0x70, 0x0, 0xf0, 0x0, 0x9, + 0xa0, 0xf, 0x0, 0x0, 0xd, 0x30, 0xf0, 0x0, + 0x0, 0x96, 0xf, 0x0, 0x0, 0x9, 0x60, 0xf0, + 0x0, 0x0, 0xc3, 0xf, 0x0, 0x0, 0x8b, 0x0, + 0xfc, 0xcc, 0xd8, 0x0, + + /* U+0045 "E" */ + 0xfc, 0xcc, 0xcc, 0x6f, 0x0, 0x0, 0x0, 0xf0, + 0x0, 0x0, 0xf, 0xcc, 0xcc, 0xc2, 0xf0, 0x0, + 0x0, 0xf, 0x0, 0x0, 0x0, 0xf0, 0x0, 0x0, + 0xf, 0xcc, 0xcc, 0xc9, + + /* U+0046 "F" */ + 0xfd, 0xdd, 0xdd, 0x2f, 0x0, 0x0, 0x0, 0xf0, + 0x0, 0x0, 0xf, 0xcc, 0xcc, 0x50, 0xf0, 0x0, + 0x0, 0xf, 0x0, 0x0, 0x0, 0xf0, 0x0, 0x0, + 0xf, 0x0, 0x0, 0x0, + + /* U+0047 "G" */ + 0x0, 0x5c, 0xcb, 0xc7, 0x0, 0x5, 0xa1, 0x0, + 0xa, 0xa0, 0xd, 0x0, 0x0, 0x0, 0x0, 0x2c, + 0x0, 0xa, 0xcc, 0xe0, 0x3f, 0x0, 0x0, 0x0, + 0xe0, 0xe, 0x50, 0x0, 0x0, 0xe0, 0x4, 0xe4, + 0x0, 0x7, 0xd0, 0x0, 0x2a, 0xcc, 0xc8, 0x10, + + /* U+0048 "H" */ + 0xf0, 0x0, 0x0, 0xe1, 0xf0, 0x0, 0x0, 0xe1, + 0xf0, 0x0, 0x0, 0xe1, 0xfc, 0xcc, 0xcc, 0xf1, + 0xf0, 0x0, 0x0, 0xe1, 0xf0, 0x0, 0x0, 0xe1, + 0xf0, 0x0, 0x0, 0xe1, 0xf0, 0x0, 0x0, 0xe1, + + /* U+0049 "I" */ + 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, + + /* U+004A "J" */ + 0x0, 0x0, 0xa5, 0x0, 0x0, 0xa5, 0x0, 0x0, + 0xa5, 0x0, 0x0, 0xa5, 0x0, 0x0, 0xa5, 0x32, + 0x0, 0xa5, 0x7a, 0x0, 0xd2, 0xa, 0xdd, 0x70, + + /* U+004B "K" */ + 0x1e, 0x0, 0x0, 0xb9, 0x1, 0xe0, 0x1, 0xc7, + 0x0, 0x1e, 0x2, 0xd5, 0x0, 0x1, 0xe3, 0xe9, + 0x0, 0x0, 0x1f, 0xc2, 0xa6, 0x0, 0x1, 0xf1, + 0x0, 0xd4, 0x0, 0x1e, 0x0, 0x2, 0xe2, 0x1, + 0xe0, 0x0, 0x5, 0xd1, + + /* U+004C "L" */ + 0x1e, 0x0, 0x0, 0x1, 0xe0, 0x0, 0x0, 0x1e, + 0x0, 0x0, 0x1, 0xe0, 0x0, 0x0, 0x1e, 0x0, + 0x0, 0x1, 0xe0, 0x0, 0x0, 0x1e, 0x0, 0x0, + 0x1, 0xfc, 0xcc, 0xc7, + + /* U+004D "M" */ + 0xf, 0x70, 0x0, 0x0, 0xda, 0xe, 0xd0, 0x0, + 0x5, 0xda, 0xe, 0x76, 0x0, 0xb, 0x6a, 0xe, + 0x1c, 0x0, 0x3a, 0x4a, 0xe, 0x9, 0x40, 0xa3, + 0x4a, 0xe, 0x2, 0xb1, 0xb0, 0x4a, 0xe, 0x0, + 0xab, 0x40, 0x4a, 0xe, 0x0, 0x3d, 0x0, 0x4a, + + /* U+004E "N" */ + 0xf, 0x70, 0x0, 0xe, 0x10, 0xeb, 0x30, 0x0, + 0xe1, 0xe, 0x1c, 0x0, 0xe, 0x10, 0xe0, 0x4a, + 0x0, 0xe1, 0xe, 0x0, 0x86, 0xe, 0x10, 0xe0, + 0x0, 0xc2, 0xe1, 0xe, 0x0, 0x2, 0xce, 0x10, + 0xe0, 0x0, 0x6, 0xf1, + + /* U+004F "O" */ + 0x0, 0x58, 0x66, 0x95, 0x0, 0x7, 0x90, 0x0, + 0xa, 0x60, 0x1e, 0x0, 0x0, 0x1, 0xf0, 0x4c, + 0x0, 0x0, 0x0, 0xd4, 0x4c, 0x0, 0x0, 0x0, + 0xd3, 0xf, 0x10, 0x0, 0x2, 0xf0, 0x7, 0xc2, + 0x0, 0x2c, 0x70, 0x0, 0x7d, 0xdd, 0xc6, 0x0, + + /* U+0050 "P" */ + 0xfc, 0xcc, 0xd9, 0xf, 0x0, 0x0, 0x89, 0xf0, + 0x0, 0x2, 0xdf, 0x0, 0x0, 0x98, 0xfd, 0xdd, + 0xc8, 0xf, 0x0, 0x0, 0x0, 0xf0, 0x0, 0x0, + 0xf, 0x0, 0x0, 0x0, + + /* U+0051 "Q" */ + 0x0, 0x6c, 0xbc, 0xb4, 0x0, 0x7, 0xb1, 0x0, + 0x2d, 0x40, 0x1e, 0x10, 0x0, 0x4, 0xd0, 0x5b, + 0x0, 0x0, 0x0, 0xf1, 0x6a, 0x0, 0x0, 0x0, + 0xf2, 0x2e, 0x10, 0x0, 0x3, 0xe0, 0x9, 0xb1, + 0x0, 0x2d, 0x50, 0x0, 0x7d, 0xde, 0xc4, 0x0, + 0x0, 0x0, 0x7, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x9b, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, + + /* U+0052 "R" */ + 0xfc, 0xcc, 0xcc, 0x50, 0xf0, 0x0, 0x1, 0xe1, + 0xf0, 0x0, 0x3, 0xe1, 0xfd, 0xdd, 0xec, 0x50, + 0xf0, 0x2, 0xd1, 0x0, 0xf0, 0x0, 0x5c, 0x0, + 0xf0, 0x0, 0x9, 0xa0, 0xf0, 0x0, 0x0, 0xc7, + + /* U+0053 "S" */ + 0x3, 0xbc, 0xcc, 0x50, 0xe, 0x30, 0x2, 0xe3, + 0xe, 0x20, 0x0, 0x21, 0x3, 0xbb, 0x84, 0x0, + 0x0, 0x0, 0x48, 0xc2, 0x26, 0x0, 0x0, 0x5a, + 0x1e, 0x40, 0x0, 0x98, 0x2, 0xac, 0xcc, 0x80, + + /* U+0054 "T" */ + 0x8c, 0xce, 0xdc, 0xc6, 0x0, 0x9, 0x60, 0x0, + 0x0, 0x9, 0x60, 0x0, 0x0, 0x9, 0x60, 0x0, + 0x0, 0x9, 0x60, 0x0, 0x0, 0x9, 0x60, 0x0, + 0x0, 0x9, 0x60, 0x0, 0x0, 0x9, 0x60, 0x0, + + /* U+0055 "U" */ + 0xf0, 0x0, 0x0, 0xd2, 0xf0, 0x0, 0x0, 0xd2, + 0xf0, 0x0, 0x0, 0xd2, 0xf0, 0x0, 0x0, 0xd2, + 0xf0, 0x0, 0x0, 0xd2, 0xd2, 0x0, 0x0, 0xf0, + 0x8a, 0x0, 0x8, 0xa0, 0x8, 0xcc, 0xc9, 0x0, + + /* U+0056 "V" */ + 0x87, 0x0, 0x0, 0xc, 0x41, 0xd0, 0x0, 0x3, + 0xd0, 0xa, 0x50, 0x0, 0xa5, 0x0, 0x3c, 0x0, + 0x1d, 0x0, 0x0, 0xb3, 0x8, 0x70, 0x0, 0x4, + 0xa0, 0xd0, 0x0, 0x0, 0xc, 0x78, 0x0, 0x0, + 0x0, 0x6f, 0x10, 0x0, + + /* U+0057 "W" */ + 0xa5, 0x0, 0xa, 0xa0, 0x0, 0x5a, 0x5a, 0x0, + 0xa, 0x90, 0x0, 0x95, 0xe, 0x0, 0x56, 0x55, + 0x0, 0xe0, 0xb, 0x30, 0xa1, 0xa, 0x3, 0xb0, + 0x6, 0x70, 0xb0, 0xa, 0x7, 0x60, 0x1, 0xc5, + 0x60, 0x6, 0x4c, 0x10, 0x0, 0xcb, 0x10, 0x2, + 0xbb, 0x0, 0x0, 0x7c, 0x0, 0x0, 0xd6, 0x0, + + /* U+0058 "X" */ + 0x2d, 0x20, 0x0, 0x7a, 0x0, 0x4c, 0x0, 0x4c, + 0x0, 0x0, 0x6a, 0x1c, 0x10, 0x0, 0x0, 0x9e, + 0x30, 0x0, 0x0, 0xc, 0xb6, 0x0, 0x0, 0xb, + 0x50, 0xc3, 0x0, 0x9, 0x80, 0x2, 0xd2, 0x7, + 0xb0, 0x0, 0x4, 0xd1, + + /* U+0059 "Y" */ + 0x88, 0x0, 0x0, 0x3d, 0x10, 0xc4, 0x0, 0x1d, + 0x20, 0x1, 0xd1, 0xb, 0x50, 0x0, 0x3, 0xc8, + 0x80, 0x0, 0x0, 0x8, 0xc0, 0x0, 0x0, 0x0, + 0x5a, 0x0, 0x0, 0x0, 0x5, 0xa0, 0x0, 0x0, + 0x0, 0x5a, 0x0, 0x0, + + /* U+005A "Z" */ + 0x2c, 0xcc, 0xcd, 0xf2, 0x0, 0x0, 0xa, 0x60, + 0x0, 0x0, 0x89, 0x0, 0x0, 0x5, 0xb0, 0x0, + 0x0, 0x3c, 0x0, 0x0, 0x2, 0xd1, 0x0, 0x0, + 0x1c, 0x30, 0x0, 0x0, 0xae, 0xcc, 0xcc, 0xc5, + + /* U+005B "[" */ + 0x1b, 0x92, 0x2a, 0x0, 0x2a, 0x0, 0x2a, 0x0, + 0x2a, 0x0, 0x2a, 0x0, 0x2a, 0x0, 0x2a, 0x0, + 0x2a, 0x0, 0x2a, 0x0, 0x1b, 0x93, + + /* U+005C "\\" */ + 0xc0, 0x0, 0x74, 0x0, 0x2a, 0x0, 0xc, 0x0, + 0x7, 0x40, 0x2, 0x90, 0x0, 0xc0, 0x0, 0x84, + + /* U+005D "]" */ + 0x7a, 0x70, 0x39, 0x3, 0x90, 0x39, 0x3, 0x90, + 0x39, 0x3, 0x90, 0x39, 0x3, 0x90, 0x39, 0x8a, + 0x70, + + /* U+005E "^" */ + 0x0, 0x43, 0x0, 0x0, 0xcb, 0x0, 0x6, 0x87, + 0x50, 0xd, 0x10, 0xc0, 0x69, 0x0, 0x85, + + /* U+005F "_" */ + 0xaa, 0xaa, 0xaa, 0xa5, + + /* U+0060 "`" */ + 0x1e, 0x20, 0x48, + + /* U+0061 "a" */ + 0x6, 0xcb, 0xc6, 0x1, 0xb0, 0x0, 0xe1, 0x0, + 0x35, 0x7e, 0x21, 0xc8, 0x52, 0xc2, 0x68, 0x0, + 0x2f, 0x21, 0xbb, 0xa9, 0xa5, + + /* U+0062 "b" */ + 0x2c, 0x0, 0x0, 0x2, 0xc0, 0x0, 0x0, 0x2c, + 0x9b, 0xc4, 0x2, 0xf2, 0x0, 0xc1, 0x2c, 0x0, + 0x7, 0x62, 0xc0, 0x0, 0x77, 0x2f, 0x10, 0xb, + 0x22, 0xc8, 0x8b, 0x60, + + /* U+0063 "c" */ + 0x4, 0xcb, 0xc4, 0x1, 0xd0, 0x1, 0xb0, 0x68, + 0x0, 0x0, 0x6, 0x80, 0x0, 0x10, 0x2d, 0x10, + 0x1e, 0x0, 0x5c, 0xcc, 0x40, + + /* U+0064 "d" */ + 0x0, 0x0, 0xd, 0x20, 0x0, 0x0, 0xd2, 0x5, + 0xcb, 0x8d, 0x22, 0xc0, 0x3, 0xf2, 0x77, 0x0, + 0xd, 0x27, 0x60, 0x0, 0xd2, 0x2b, 0x0, 0x1f, + 0x20, 0x5a, 0x98, 0xd2, + + /* U+0065 "e" */ + 0x3, 0xbb, 0xb5, 0x2, 0xc0, 0x0, 0xb3, 0x6d, + 0xbb, 0xbc, 0x65, 0x90, 0x0, 0x0, 0x1d, 0x10, + 0x1d, 0x40, 0x3b, 0xcd, 0x70, + + /* U+0066 "f" */ + 0x9, 0xc8, 0xf, 0x0, 0xbf, 0xb4, 0xf, 0x0, + 0xf, 0x0, 0xf, 0x0, 0xf, 0x0, 0xf, 0x0, + + /* U+0067 "g" */ + 0x4, 0xbb, 0x9b, 0x32, 0xc0, 0x2, 0xf3, 0x76, + 0x0, 0xb, 0x38, 0x60, 0x0, 0xb3, 0x3b, 0x0, + 0x1f, 0x30, 0x7c, 0xa9, 0xb3, 0x0, 0x0, 0xc, + 0x30, 0x40, 0x3, 0xe0, 0x9, 0xbc, 0xc4, 0x0, + + /* U+0068 "h" */ + 0x2c, 0x0, 0x0, 0x2, 0xc0, 0x0, 0x0, 0x2c, + 0x8b, 0xd7, 0x2, 0xf3, 0x0, 0xe1, 0x2c, 0x0, + 0xc, 0x22, 0xc0, 0x0, 0xc2, 0x2c, 0x0, 0xc, + 0x22, 0xc0, 0x0, 0xc2, + + /* U+0069 "i" */ + 0x2c, 0x1, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, + + /* U+006A "j" */ + 0x2, 0xd0, 0x1, 0x2, 0xd0, 0x2d, 0x2, 0xd0, + 0x2d, 0x2, 0xd0, 0x2d, 0x2, 0xd0, 0x2c, 0x5c, + 0x70, + + /* U+006B "k" */ + 0x2c, 0x0, 0x0, 0x2, 0xc0, 0x0, 0x0, 0x2c, + 0x0, 0xc7, 0x2, 0xc1, 0xc5, 0x0, 0x2d, 0xcb, + 0x0, 0x2, 0xe2, 0x96, 0x0, 0x2c, 0x0, 0xd2, + 0x2, 0xc0, 0x3, 0xd0, + + /* U+006C "l" */ + 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, 0x2c, + + /* U+006D "m" */ + 0x2c, 0x8a, 0xc3, 0x9a, 0xc2, 0x2f, 0x10, 0x5e, + 0x10, 0x5a, 0x2c, 0x0, 0x3b, 0x0, 0x3b, 0x2c, + 0x0, 0x3b, 0x0, 0x3b, 0x2c, 0x0, 0x3b, 0x0, + 0x3b, 0x2c, 0x0, 0x3b, 0x0, 0x3b, + + /* U+006E "n" */ + 0x2c, 0x8b, 0xc7, 0x2, 0xf3, 0x0, 0xe1, 0x2c, + 0x0, 0xb, 0x22, 0xc0, 0x0, 0xb3, 0x2c, 0x0, + 0xb, 0x32, 0xc0, 0x0, 0xb3, + + /* U+006F "o" */ + 0x4, 0xbb, 0xc5, 0x2, 0xc0, 0x1, 0xe2, 0x77, + 0x0, 0x8, 0x77, 0x70, 0x0, 0x77, 0x2c, 0x0, + 0xc, 0x30, 0x5b, 0xbb, 0x50, + + /* U+0070 "p" */ + 0x2c, 0x89, 0xb4, 0x2, 0xf1, 0x0, 0xc1, 0x2c, + 0x0, 0x7, 0x62, 0xc0, 0x0, 0x76, 0x2f, 0x20, + 0xc, 0x22, 0xc9, 0xbc, 0x50, 0x2c, 0x0, 0x0, + 0x2, 0xc0, 0x0, 0x0, 0x2c, 0x0, 0x0, 0x0, + + /* U+0071 "q" */ + 0x5, 0xcb, 0x8d, 0x12, 0xc0, 0x2, 0xf1, 0x76, + 0x0, 0xd, 0x17, 0x60, 0x0, 0xd1, 0x2c, 0x0, + 0x3f, 0x10, 0x5c, 0xb8, 0xd1, 0x0, 0x0, 0xd, + 0x10, 0x0, 0x0, 0xd1, 0x0, 0x0, 0xd, 0x10, + + /* U+0072 "r" */ + 0x2c, 0xac, 0x22, 0xf1, 0x0, 0x2c, 0x0, 0x2, + 0xc0, 0x0, 0x2c, 0x0, 0x2, 0xc0, 0x0, + + /* U+0073 "s" */ + 0x9, 0xcc, 0xb1, 0x3c, 0x0, 0x74, 0xb, 0x95, + 0x10, 0x0, 0x25, 0xb7, 0x59, 0x0, 0x3c, 0x9, + 0xcb, 0xb3, + + /* U+0074 "t" */ + 0x0, 0x0, 0xd, 0x0, 0xf, 0x0, 0x9f, 0xb2, + 0xf, 0x0, 0xf, 0x0, 0xf, 0x0, 0xe, 0x0, + 0xa, 0xb2, + + /* U+0075 "u" */ + 0x3b, 0x0, 0xc, 0x23, 0xb0, 0x0, 0xc2, 0x3b, + 0x0, 0xc, 0x23, 0xb0, 0x0, 0xc2, 0x1e, 0x0, + 0x3f, 0x20, 0x7c, 0xb8, 0xc2, + + /* U+0076 "v" */ + 0x96, 0x0, 0xe, 0x3, 0xc0, 0x6, 0x80, 0xc, + 0x20, 0xc1, 0x0, 0x68, 0x3a, 0x0, 0x0, 0xca, + 0x30, 0x0, 0x9, 0xc0, 0x0, + + /* U+0077 "w" */ + 0xc2, 0x1, 0xf2, 0x0, 0xd0, 0x67, 0x5, 0xa7, + 0x5, 0x80, 0x1c, 0x9, 0x2b, 0xa, 0x20, 0xb, + 0x1b, 0xb, 0x1c, 0x0, 0x6, 0x98, 0x7, 0x97, + 0x0, 0x1, 0xf4, 0x3, 0xf1, 0x0, + + /* U+0078 "x" */ + 0x3c, 0x0, 0x6a, 0x0, 0x69, 0x2c, 0x0, 0x0, + 0x9c, 0x10, 0x0, 0xa, 0xb3, 0x0, 0x9, 0x61, + 0xc1, 0x6, 0xa0, 0x4, 0xc0, + + /* U+0079 "y" */ + 0x96, 0x0, 0xe, 0x3, 0xc0, 0x5, 0xa0, 0xc, + 0x20, 0xa3, 0x0, 0x67, 0x1d, 0x0, 0x1, 0xc6, + 0x70, 0x0, 0xa, 0xd1, 0x0, 0x0, 0x5a, 0x0, + 0x0, 0xb, 0x40, 0x0, 0x4c, 0x90, 0x0, 0x0, + + /* U+007A "z" */ + 0x5c, 0xcc, 0xeb, 0x0, 0x0, 0x2c, 0x10, 0x0, + 0x1c, 0x20, 0x0, 0x1c, 0x30, 0x0, 0xc, 0x40, + 0x0, 0x9, 0xeb, 0xbb, 0xb0, + + /* U+007B "{" */ + 0x0, 0x78, 0x3, 0x90, 0x4, 0x70, 0x4, 0x70, + 0x6, 0x60, 0x6c, 0x0, 0x6, 0x60, 0x4, 0x70, + 0x4, 0x70, 0x3, 0x90, 0x0, 0x88, + + /* U+007C "|" */ + 0x6c, 0xcc, 0xcc, 0xcc, 0xcc, 0xc0, + + /* U+007D "}" */ + 0x69, 0x10, 0x5, 0x70, 0x3, 0x80, 0x3, 0x80, + 0x2, 0xa0, 0x0, 0x9a, 0x2, 0xa0, 0x3, 0x80, + 0x3, 0x80, 0x5, 0x70, 0x69, 0x10, + + /* U+007E "~" */ + 0x3b, 0xda, 0x42, 0x64, 0x10, 0x5c, 0xd7, + + /* U+4E09 "三" */ + 0x4, 0xcc, 0xcc, 0xcc, 0xcc, 0x80, 0x0, 0x11, + 0x11, 0x11, 0x11, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xbd, 0xdd, 0xdd, 0xdd, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1d, 0xdd, 0xdd, 0xdd, 0xdd, 0xd5, + + /* U+4E34 "临" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0x0, + 0x77, 0x0, 0x0, 0x70, 0xc0, 0xe, 0x20, 0x0, + 0xb, 0xc, 0x7, 0xdb, 0xbb, 0xb4, 0xb0, 0xc3, + 0xd0, 0x76, 0x0, 0xb, 0xc, 0x32, 0x0, 0x91, + 0x0, 0xb0, 0xc0, 0x9b, 0xbb, 0xba, 0xb, 0xc, + 0xc, 0x2, 0x90, 0xb0, 0xb0, 0xc0, 0xc0, 0x29, + 0xb, 0xb, 0xc, 0xc, 0x2, 0x90, 0xb0, 0x90, + 0xc0, 0xdb, 0xce, 0xbd, 0x0, 0xc, 0xb, 0x0, + 0x0, 0xa0, + + /* U+53CC "双" */ + 0x2c, 0xcc, 0xc7, 0xcc, 0xcc, 0x90, 0x0, 0x0, + 0xb2, 0xb0, 0x3, 0xa0, 0xb, 0x0, 0xc0, 0xc0, + 0x6, 0x60, 0x6, 0x81, 0xb0, 0xb1, 0xa, 0x20, + 0x0, 0xb9, 0x60, 0x66, 0xc, 0x0, 0x0, 0x2f, + 0x10, 0x1c, 0x76, 0x0, 0x0, 0x6e, 0x70, 0x8, + 0xd0, 0x0, 0x2, 0xd1, 0xd2, 0x2d, 0xc5, 0x0, + 0x1d, 0x30, 0x27, 0xd3, 0xc, 0x80, 0x14, 0x0, + 0x5a, 0x10, 0x0, 0x82, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+6027 "性" */ + 0x0, 0xc0, 0x0, 0x8, 0x40, 0x0, 0x0, 0xc0, + 0x9, 0x28, 0x50, 0x0, 0x0, 0xc6, 0xd, 0x8, + 0x50, 0x0, 0x9, 0xca, 0x6e, 0xce, 0xdc, 0xc0, + 0x37, 0xc0, 0xa4, 0x8, 0x50, 0x0, 0x33, 0xc0, + 0x30, 0x8, 0x50, 0x0, 0x0, 0xc0, 0x3c, 0xce, + 0xdc, 0xa0, 0x0, 0xc0, 0x0, 0x8, 0x50, 0x0, + 0x0, 0xc0, 0x0, 0x8, 0x50, 0x0, 0x0, 0xc0, + 0x1, 0x18, 0x51, 0x10, 0x0, 0xc0, 0xbb, 0xbb, + 0xbb, 0xb4, + + /* U+6700 "最" */ + 0x0, 0x9a, 0x99, 0x99, 0x9e, 0x10, 0x0, 0x99, + 0x77, 0x77, 0x7d, 0x10, 0x0, 0x9a, 0x99, 0x99, + 0x9e, 0x10, 0x3, 0x33, 0x33, 0x33, 0x33, 0x32, + 0x6, 0xd6, 0x6d, 0x66, 0x66, 0x63, 0x0, 0xe9, + 0x9d, 0x4b, 0x99, 0xa0, 0x0, 0xb0, 0xc, 0xb, + 0x3, 0x80, 0x0, 0xe9, 0x9d, 0x3, 0x9b, 0x10, + 0x4, 0xd7, 0x8e, 0x73, 0xcb, 0x20, 0x5, 0x42, + 0xc, 0x69, 0x12, 0x94, + + /* U+6B21 "次" */ + 0x0, 0x0, 0x1, 0x50, 0x0, 0x0, 0x8, 0x20, + 0x6, 0x70, 0x0, 0x0, 0x2, 0xc0, 0xc, 0xdc, + 0xcc, 0xc1, 0x0, 0x66, 0x4a, 0x4, 0x0, 0xc0, + 0x0, 0x0, 0xc2, 0xc, 0x6, 0x70, 0x0, 0x26, + 0x0, 0x3f, 0x1, 0x0, 0x0, 0xa4, 0x0, 0x7c, + 0x50, 0x0, 0x2, 0xc0, 0x0, 0xd2, 0xc0, 0x0, + 0xa, 0x50, 0xa, 0x60, 0x89, 0x0, 0xa, 0x1, + 0xb8, 0x0, 0xa, 0xa0, 0x0, 0xb, 0x50, 0x0, + 0x0, 0x74, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+7EBF "线" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x93, + 0x0, 0xc0, 0x80, 0x0, 0x1, 0xc0, 0x0, 0xc0, + 0x49, 0x0, 0x9, 0x42, 0x0, 0xc4, 0x57, 0x80, + 0x3b, 0xb, 0x7c, 0xe9, 0x74, 0x20, 0x5b, 0xd7, + 0x0, 0x92, 0x0, 0x10, 0x1, 0xb0, 0x26, 0xcc, + 0xbb, 0x91, 0xb, 0x42, 0x35, 0x68, 0x5, 0x40, + 0x2b, 0x97, 0x0, 0xc, 0x6a, 0x0, 0x0, 0x1, + 0x0, 0x1e, 0x90, 0x62, 0x4b, 0xcb, 0x59, 0xc7, + 0xa0, 0xb0, 0x1, 0x0, 0x84, 0x0, 0x7d, 0x90, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+8FD1 "近" */ + 0x3, 0x10, 0x0, 0x0, 0x0, 0x0, 0x4, 0xb0, + 0xa, 0xbb, 0xcc, 0x60, 0x0, 0x83, 0xd, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xd, 0x0, 0x0, 0x0, + 0x3c, 0xb0, 0xf, 0xbb, 0xdb, 0xb2, 0x0, 0xc0, + 0x1c, 0x0, 0xd0, 0x0, 0x0, 0xc0, 0x3a, 0x0, + 0xd0, 0x0, 0x0, 0xc0, 0x95, 0x0, 0xd0, 0x0, + 0x1, 0xe2, 0xc0, 0x0, 0xd0, 0x0, 0xb, 0x7c, + 0x40, 0x0, 0x20, 0x0, 0x47, 0x2, 0x8b, 0xbb, + 0xcc, 0xc2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F001 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x12, 0x0, 0x0, + 0x0, 0x3, 0x7c, 0xff, 0x0, 0x0, 0x59, 0xef, + 0xff, 0xff, 0x0, 0xe, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xf, 0xff, 0xfd, 0x84, 0x8f, 0x0, 0xf, + 0xd7, 0x20, 0x0, 0x8f, 0x0, 0xf, 0x80, 0x0, + 0x0, 0x8f, 0x0, 0xf, 0x80, 0x0, 0x0, 0x8f, + 0x0, 0xf, 0x80, 0x0, 0x7b, 0xdf, 0x2, 0x3f, + 0x80, 0x6, 0xff, 0xff, 0xaf, 0xff, 0x80, 0x2, + 0xef, 0xf9, 0xef, 0xff, 0x60, 0x0, 0x2, 0x10, + 0x29, 0xa7, 0x0, 0x0, 0x0, 0x0, + + /* U+F008 "" */ + 0xb4, 0xdf, 0xff, 0xff, 0xfd, 0x4b, 0xe8, 0xe7, + 0x22, 0x22, 0x7e, 0x8e, 0xc0, 0xc5, 0x0, 0x0, + 0x6c, 0xc, 0xfc, 0xf6, 0x11, 0x11, 0x7f, 0xcf, + 0xc0, 0xcf, 0xff, 0xff, 0xfb, 0xc, 0xfc, 0xf6, + 0x11, 0x11, 0x7f, 0xcf, 0xc0, 0xc5, 0x0, 0x0, + 0x6c, 0xc, 0xe8, 0xe7, 0x22, 0x22, 0x7e, 0x8e, + 0xb4, 0xdf, 0xff, 0xff, 0xfd, 0x4b, + + /* U+F00B "" */ + 0xdf, 0xf6, 0x9f, 0xff, 0xff, 0xfd, 0xff, 0xf8, + 0xcf, 0xff, 0xff, 0xff, 0xef, 0xf6, 0xaf, 0xff, + 0xff, 0xfe, 0x13, 0x20, 0x3, 0x33, 0x33, 0x31, + 0xff, 0xf7, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xcf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xbf, 0xff, + 0xff, 0xff, 0x13, 0x20, 0x3, 0x33, 0x33, 0x31, + 0xef, 0xf6, 0xaf, 0xff, 0xff, 0xfe, 0xff, 0xf8, + 0xcf, 0xff, 0xff, 0xff, 0xdf, 0xf6, 0xaf, 0xff, + 0xff, 0xfd, + + /* U+F00C "" */ + 0x0, 0x0, 0x0, 0x0, 0x3, 0xd4, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0xfe, 0x0, 0x0, 0x0, 0x3, + 0xff, 0xf4, 0x4d, 0x30, 0x0, 0x3f, 0xff, 0x40, + 0xef, 0xf3, 0x3, 0xff, 0xf4, 0x0, 0x4f, 0xff, + 0x6f, 0xff, 0x40, 0x0, 0x4, 0xff, 0xff, 0xf4, + 0x0, 0x0, 0x0, 0x4f, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x3, 0xd3, 0x0, 0x0, 0x0, + + /* U+F00D "" */ + 0x14, 0x0, 0x0, 0x22, 0xd, 0xf7, 0x0, 0x4f, + 0xf1, 0x9f, 0xf7, 0x4f, 0xfd, 0x0, 0xaf, 0xff, + 0xfd, 0x10, 0x0, 0xbf, 0xfe, 0x10, 0x0, 0x4f, + 0xff, 0xf7, 0x0, 0x4f, 0xfd, 0xaf, 0xf7, 0xe, + 0xfd, 0x10, 0xaf, 0xf2, 0x5b, 0x10, 0x0, 0x99, + 0x0, + + /* U+F011 "" */ + 0x0, 0x0, 0x7, 0x70, 0x0, 0x0, 0x0, 0x32, + 0xf, 0xf0, 0x24, 0x0, 0x5, 0xfc, 0xf, 0xf0, + 0xcf, 0x50, 0x1f, 0xf4, 0xf, 0xf0, 0x5f, 0xf1, + 0x7f, 0x80, 0xf, 0xf0, 0x8, 0xf7, 0xbf, 0x20, + 0xf, 0xf0, 0x2, 0xfb, 0xcf, 0x10, 0xe, 0xe0, + 0x1, 0xfc, 0xaf, 0x40, 0x1, 0x10, 0x4, 0xfa, + 0x5f, 0xb0, 0x0, 0x0, 0xb, 0xf6, 0xd, 0xfa, + 0x10, 0x1, 0xaf, 0xd0, 0x2, 0xdf, 0xfc, 0xcf, + 0xfd, 0x20, 0x0, 0x8, 0xef, 0xfe, 0x91, 0x0, + 0x0, 0x0, 0x1, 0x10, 0x0, 0x0, + + /* U+F013 "" */ + 0x0, 0x0, 0x14, 0x41, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xf7, 0x0, 0x0, 0x3, 0x43, 0xdf, 0xfd, + 0x34, 0x30, 0xe, 0xff, 0xff, 0xff, 0xff, 0xe0, + 0x6f, 0xff, 0xfb, 0xbf, 0xff, 0xf6, 0x1b, 0xff, + 0x70, 0x7, 0xff, 0xb1, 0x7, 0xff, 0x20, 0x2, + 0xff, 0x70, 0x1b, 0xff, 0x70, 0x7, 0xff, 0xb1, + 0x6f, 0xff, 0xfb, 0xbf, 0xff, 0xf6, 0xe, 0xff, + 0xff, 0xff, 0xff, 0xe0, 0x3, 0x42, 0xcf, 0xfc, + 0x23, 0x30, 0x0, 0x0, 0x7f, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x4, 0x41, 0x0, 0x0, + + /* U+F015 "" */ + 0x0, 0x0, 0x0, 0x73, 0x3, 0x83, 0x0, 0x0, + 0x0, 0x1d, 0xff, 0x67, 0xf7, 0x0, 0x0, 0x3, + 0xee, 0x5a, 0xfe, 0xf7, 0x0, 0x0, 0x6f, 0xd3, + 0xb5, 0x7f, 0xf7, 0x0, 0x9, 0xfb, 0x3d, 0xff, + 0x85, 0xfe, 0x30, 0xbf, 0x95, 0xff, 0xff, 0xfb, + 0x3e, 0xf4, 0x76, 0x6f, 0xff, 0xff, 0xff, 0xd2, + 0xa1, 0x0, 0xcf, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0xcf, 0xfa, 0x2, 0xff, 0xf4, 0x0, 0x0, + 0xcf, 0xfa, 0x2, 0xff, 0xf4, 0x0, 0x0, 0xaf, + 0xf8, 0x1, 0xff, 0xf3, 0x0, + + /* U+F019 "" */ + 0x0, 0x0, 0x27, 0x72, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xf8, 0x0, 0x0, 0x0, 0xdf, + 0xff, 0xff, 0xfd, 0x0, 0x0, 0x4f, 0xff, 0xff, + 0xf4, 0x0, 0x0, 0x4, 0xff, 0xff, 0x40, 0x0, + 0x23, 0x33, 0x5f, 0xf5, 0x33, 0x32, 0xff, 0xff, + 0xa4, 0x4a, 0xff, 0xff, 0xff, 0xff, 0xfc, 0xcf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5c, 0x8f, + 0x9a, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, + + /* U+F01C "" */ + 0x0, 0x4f, 0xff, 0xff, 0xff, 0xb0, 0x0, 0x1, + 0xed, 0x88, 0x88, 0x89, 0xf8, 0x0, 0xa, 0xf2, + 0x0, 0x0, 0x0, 0xaf, 0x30, 0x5f, 0x70, 0x0, + 0x0, 0x0, 0x1e, 0xc0, 0xef, 0x88, 0x60, 0x0, + 0x28, 0x8b, 0xf6, 0xff, 0xff, 0xf3, 0x0, 0xbf, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + + /* U+F021 "" */ + 0x0, 0x0, 0x1, 0x10, 0x0, 0x59, 0x0, 0x19, + 0xef, 0xfd, 0x70, 0x9f, 0x3, 0xef, 0xda, 0x9d, + 0xfe, 0xbf, 0xe, 0xf6, 0x0, 0x0, 0x5f, 0xff, + 0x7f, 0x70, 0x0, 0x3f, 0xff, 0xff, 0x69, 0x0, + 0x0, 0x2a, 0xaa, 0xa9, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaa, 0xaa, 0xa2, 0x0, 0x0, 0xa6, + 0xff, 0xfe, 0xf3, 0x0, 0x7, 0xf7, 0xff, 0xf5, + 0x0, 0x0, 0x7f, 0xe0, 0xfb, 0xef, 0xd9, 0xad, + 0xfe, 0x30, 0xfa, 0x8, 0xef, 0xfe, 0x91, 0x0, + 0x95, 0x0, 0x1, 0x10, 0x0, 0x0, + + /* U+F026 "" */ + 0x0, 0x0, 0x2a, 0x0, 0x2, 0xef, 0x78, 0x8e, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xdf, 0xff, 0xff, 0x0, 0x7, 0xff, + 0x0, 0x0, 0x7f, 0x0, 0x0, 0x1, + + /* U+F027 "" */ + 0x0, 0x0, 0x2a, 0x0, 0x0, 0x0, 0x2e, 0xf0, + 0x0, 0x78, 0x8e, 0xff, 0x3, 0xf, 0xff, 0xff, + 0xf0, 0xba, 0xff, 0xff, 0xff, 0x3, 0xff, 0xff, + 0xff, 0xf0, 0xaa, 0xdf, 0xff, 0xff, 0x4, 0x0, + 0x0, 0x8f, 0xf0, 0x0, 0x0, 0x0, 0x8f, 0x0, + 0x0, 0x0, 0x0, 0x10, 0x0, + + /* U+F028 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xd2, 0x0, 0x0, 0x0, + 0x2a, 0x0, 0x11, 0x8e, 0x10, 0x0, 0x2, 0xef, + 0x0, 0x7d, 0x2b, 0x90, 0x78, 0x8e, 0xff, 0x3, + 0xa, 0xb3, 0xf0, 0xff, 0xff, 0xff, 0xb, 0xa1, + 0xf1, 0xe3, 0xff, 0xff, 0xff, 0x3, 0xf0, 0xe3, + 0xc5, 0xff, 0xff, 0xff, 0xb, 0xa1, 0xf1, 0xe3, + 0xdf, 0xff, 0xff, 0x3, 0xa, 0xb3, 0xf0, 0x0, + 0x7, 0xff, 0x0, 0x7d, 0x2b, 0x90, 0x0, 0x0, + 0x7f, 0x0, 0x11, 0x9e, 0x10, 0x0, 0x0, 0x1, + 0x0, 0x6, 0xd2, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+F03E "" */ + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xfd, 0x5b, + 0xff, 0xff, 0xff, 0xff, 0xf5, 0x1, 0xff, 0xff, + 0xef, 0xff, 0xfb, 0x18, 0xff, 0xf6, 0x1c, 0xff, + 0xff, 0xfc, 0xff, 0x60, 0x1, 0xdf, 0xff, 0x60, + 0x96, 0x0, 0x0, 0x8f, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xfc, 0x88, 0x88, 0x88, 0x88, 0xcf, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xfb, + + /* U+F043 "" */ + 0x0, 0x2, 0x40, 0x0, 0x0, 0x0, 0xcf, 0x10, + 0x0, 0x0, 0x3f, 0xf7, 0x0, 0x0, 0xa, 0xff, + 0xe0, 0x0, 0x4, 0xff, 0xff, 0x80, 0x0, 0xef, + 0xff, 0xff, 0x30, 0x8f, 0xff, 0xff, 0xfc, 0xe, + 0xff, 0xff, 0xff, 0xf2, 0xf9, 0xcf, 0xff, 0xff, + 0x3d, 0xc5, 0xff, 0xff, 0xf1, 0x6f, 0xa3, 0xbf, + 0xfa, 0x0, 0x8f, 0xff, 0xfb, 0x0, 0x0, 0x26, + 0x74, 0x0, 0x0, + + /* U+F048 "" */ + 0x58, 0x0, 0x0, 0x35, 0x9f, 0x10, 0x5, 0xfe, + 0x9f, 0x10, 0x6f, 0xfe, 0x9f, 0x17, 0xff, 0xfe, + 0x9f, 0x9f, 0xff, 0xfe, 0x9f, 0xff, 0xff, 0xfe, + 0x9f, 0xef, 0xff, 0xfe, 0x9f, 0x2d, 0xff, 0xfe, + 0x9f, 0x10, 0xcf, 0xfe, 0x9f, 0x10, 0xb, 0xfe, + 0x8f, 0x0, 0x0, 0x9b, 0x0, 0x0, 0x0, 0x0, + + /* U+F04B "" */ + 0x46, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0x40, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xa1, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf7, 0x0, 0x0, 0xff, 0xff, + 0xff, 0xfd, 0x50, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xb1, 0xff, 0xff, 0xff, 0xff, 0xff, 0x6f, 0xff, + 0xff, 0xff, 0xff, 0xb1, 0xff, 0xff, 0xff, 0xfd, + 0x40, 0xf, 0xff, 0xff, 0xf7, 0x0, 0x0, 0xff, + 0xff, 0xa1, 0x0, 0x0, 0xf, 0xfd, 0x40, 0x0, + 0x0, 0x0, 0x36, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F04C "" */ + 0xaf, 0xfe, 0x30, 0xaf, 0xfe, 0x3f, 0xff, 0xf7, + 0xf, 0xff, 0xf7, 0xff, 0xff, 0x80, 0xff, 0xff, + 0x8f, 0xff, 0xf8, 0xf, 0xff, 0xf8, 0xff, 0xff, + 0x80, 0xff, 0xff, 0x8f, 0xff, 0xf8, 0xf, 0xff, + 0xf8, 0xff, 0xff, 0x80, 0xff, 0xff, 0x8f, 0xff, + 0xf8, 0xf, 0xff, 0xf8, 0xff, 0xff, 0x80, 0xff, + 0xff, 0x8f, 0xff, 0xf7, 0xf, 0xff, 0xf7, 0x48, + 0x98, 0x10, 0x48, 0x98, 0x10, + + /* U+F04D "" */ + 0x48, 0x88, 0x88, 0x88, 0x88, 0x1f, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xaf, + 0xff, 0xff, 0xff, 0xfe, 0x30, + + /* U+F051 "" */ + 0x26, 0x0, 0x0, 0x58, 0x7f, 0xa0, 0x0, 0xbf, + 0x8f, 0xfb, 0x0, 0xbf, 0x8f, 0xff, 0xc1, 0xbf, + 0x8f, 0xff, 0xfd, 0xcf, 0x8f, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xef, 0x8f, 0xff, 0xf4, 0xbf, + 0x8f, 0xff, 0x40, 0xbf, 0x8f, 0xe3, 0x0, 0xbf, + 0x5d, 0x20, 0x0, 0xae, 0x0, 0x0, 0x0, 0x0, + + /* U+F052 "" */ + 0x0, 0x0, 0x3, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xfa, 0x0, 0x0, 0x0, 0x2, 0xef, 0xff, + 0x90, 0x0, 0x0, 0x1e, 0xff, 0xff, 0xf8, 0x0, + 0x1, 0xdf, 0xff, 0xff, 0xff, 0x70, 0xc, 0xff, + 0xff, 0xff, 0xff, 0xf4, 0xd, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0x1, 0x34, 0x44, 0x44, 0x44, 0x30, + 0xd, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0xc, 0xff, 0xff, 0xff, + 0xff, 0xf5, + + /* U+F053 "" */ + 0x0, 0x0, 0x3, 0x10, 0x0, 0x5, 0xfb, 0x0, + 0x5, 0xff, 0x40, 0x5, 0xff, 0x40, 0x5, 0xff, + 0x50, 0x3, 0xff, 0x50, 0x0, 0xb, 0xfc, 0x10, + 0x0, 0xb, 0xfc, 0x10, 0x0, 0xc, 0xfc, 0x10, + 0x0, 0xc, 0xfb, 0x0, 0x0, 0xa, 0x50, + + /* U+F054 "" */ + 0x3, 0x10, 0x0, 0x3, 0xfc, 0x10, 0x0, 0xb, + 0xfc, 0x10, 0x0, 0xb, 0xfc, 0x10, 0x0, 0xb, + 0xfc, 0x10, 0x0, 0xd, 0xfb, 0x0, 0x5, 0xff, + 0x50, 0x5, 0xff, 0x50, 0x5, 0xff, 0x50, 0x3, + 0xff, 0x50, 0x0, 0xa, 0x50, 0x0, 0x0, + + /* U+F067 "" */ + 0x0, 0x0, 0x69, 0x10, 0x0, 0x0, 0x0, 0xd, + 0xf5, 0x0, 0x0, 0x0, 0x0, 0xef, 0x60, 0x0, + 0x0, 0x0, 0xe, 0xf6, 0x0, 0x0, 0x58, 0x88, + 0xff, 0xb8, 0x88, 0x1f, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x9b, 0xbb, 0xff, 0xdb, 0xbb, 0x30, 0x0, + 0xe, 0xf6, 0x0, 0x0, 0x0, 0x0, 0xef, 0x60, + 0x0, 0x0, 0x0, 0xe, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x9d, 0x20, 0x0, 0x0, + + /* U+F068 "" */ + 0x46, 0x66, 0x66, 0x66, 0x66, 0x1f, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0xad, 0xdd, 0xdd, 0xdd, 0xdd, + 0x40, + + /* U+F06E "" */ + 0x0, 0x3, 0xad, 0xff, 0xc7, 0x0, 0x0, 0x0, + 0x9f, 0xe6, 0x24, 0xaf, 0xe3, 0x0, 0xb, 0xff, + 0x20, 0x77, 0x9, 0xff, 0x40, 0x7f, 0xf9, 0x0, + 0xcf, 0xa1, 0xff, 0xe1, 0xef, 0xf6, 0x7f, 0xff, + 0xf0, 0xef, 0xf7, 0x8f, 0xf9, 0x3f, 0xff, 0xc1, + 0xff, 0xe1, 0xb, 0xff, 0x26, 0xca, 0x19, 0xff, + 0x40, 0x0, 0x9f, 0xe6, 0x24, 0xaf, 0xe3, 0x0, + 0x0, 0x3, 0x9d, 0xff, 0xc7, 0x0, 0x0, + + /* U+F070 "" */ + 0x32, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1c, 0xf8, 0x4a, 0xef, 0xeb, 0x50, 0x0, 0x0, + 0x0, 0x9f, 0xfd, 0x52, 0x5d, 0xfc, 0x10, 0x0, + 0x0, 0x5, 0xfe, 0x4a, 0x70, 0xcf, 0xe1, 0x0, + 0xb, 0x80, 0x2d, 0xff, 0xf7, 0x4f, 0xfb, 0x0, + 0x2f, 0xfb, 0x0, 0xaf, 0xfb, 0x2f, 0xff, 0x30, + 0xb, 0xff, 0x50, 0x7, 0xfe, 0x7f, 0xfb, 0x0, + 0x1, 0xdf, 0xc0, 0x0, 0x3e, 0xff, 0xe1, 0x0, + 0x0, 0x1b, 0xfc, 0x42, 0x1, 0xbf, 0xa0, 0x0, + 0x0, 0x0, 0x5b, 0xef, 0xb0, 0x8, 0xfc, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x40, + + /* U+F071 "" */ + 0x0, 0x0, 0x0, 0x3, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xef, 0xf7, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x2f, 0xfd, 0xef, 0xa0, 0x0, 0x0, 0x0, 0xb, + 0xfb, 0x3, 0xff, 0x30, 0x0, 0x0, 0x4, 0xff, + 0xc0, 0x4f, 0xfc, 0x0, 0x0, 0x0, 0xdf, 0xfd, + 0x5, 0xff, 0xf6, 0x0, 0x0, 0x7f, 0xff, 0xf8, + 0xcf, 0xff, 0xe1, 0x0, 0x1f, 0xff, 0xfc, 0x4, + 0xff, 0xff, 0x90, 0xa, 0xff, 0xff, 0xd2, 0x7f, + 0xff, 0xff, 0x20, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf6, 0x4, 0x78, 0x88, 0x88, 0x88, 0x88, + 0x87, 0x0, + + /* U+F074 "" */ + 0x0, 0x0, 0x0, 0x0, 0x6, 0x10, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xc1, 0xff, 0xf8, 0x0, 0x2e, + 0xff, 0xfc, 0xcd, 0xff, 0x62, 0xef, 0xdf, 0xf9, + 0x0, 0x2c, 0x4e, 0xf9, 0xf, 0x90, 0x0, 0x2, + 0xef, 0x90, 0x7, 0x0, 0x0, 0x2e, 0xf8, 0x88, + 0xf, 0xa0, 0xcd, 0xff, 0x80, 0xdf, 0xdf, 0xf9, + 0xff, 0xf8, 0x0, 0x1e, 0xff, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x6, 0x10, + + /* U+F077 "" */ + 0x0, 0x0, 0x27, 0x0, 0x0, 0x0, 0x0, 0x2e, + 0xf9, 0x0, 0x0, 0x0, 0x2e, 0xff, 0xf9, 0x0, + 0x0, 0x2e, 0xf9, 0x2e, 0xf9, 0x0, 0x2e, 0xf9, + 0x0, 0x2e, 0xf9, 0xb, 0xf9, 0x0, 0x0, 0x2e, + 0xf4, 0x27, 0x0, 0x0, 0x0, 0x27, 0x0, + + /* U+F078 "" */ + 0x27, 0x0, 0x0, 0x0, 0x27, 0xb, 0xf9, 0x0, + 0x0, 0x2e, 0xf4, 0x2e, 0xf9, 0x0, 0x2e, 0xf9, + 0x0, 0x2e, 0xf9, 0x2e, 0xf9, 0x0, 0x0, 0x2e, + 0xff, 0xf9, 0x0, 0x0, 0x0, 0x2e, 0xf9, 0x0, + 0x0, 0x0, 0x0, 0x26, 0x0, 0x0, 0x0, + + /* U+F079 "" */ + 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3f, 0xc0, 0x7, 0x77, 0x77, 0x72, 0x0, + 0x3, 0xff, 0xfc, 0x2e, 0xff, 0xff, 0xf9, 0x0, + 0xf, 0xcf, 0xcf, 0xa0, 0x0, 0x0, 0xe9, 0x0, + 0x4, 0x1e, 0x93, 0x20, 0x0, 0x0, 0xe9, 0x0, + 0x0, 0xe, 0x90, 0x0, 0x0, 0x0, 0xe9, 0x0, + 0x0, 0xe, 0x90, 0x0, 0x0, 0xb5, 0xe9, 0x97, + 0x0, 0xe, 0xc7, 0x77, 0x73, 0xbf, 0xff, 0xf6, + 0x0, 0xd, 0xff, 0xff, 0xfd, 0xb, 0xff, 0x70, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa6, 0x0, + + /* U+F07B "" */ + 0xbf, 0xff, 0xf6, 0x0, 0x0, 0x0, 0xff, 0xff, + 0xff, 0x98, 0x88, 0x74, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xfb, + + /* U+F093 "" */ + 0x0, 0x0, 0x2, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x3e, 0xe3, 0x0, 0x0, 0x0, 0x3, 0xef, 0xfe, + 0x30, 0x0, 0x0, 0x3e, 0xff, 0xff, 0xe3, 0x0, + 0x0, 0xef, 0xff, 0xff, 0xfe, 0x0, 0x0, 0x0, + 0x8f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xf8, 0x0, 0x0, + 0x23, 0x32, 0x8f, 0xf8, 0x23, 0x32, 0xff, 0xfe, + 0x39, 0x93, 0xef, 0xff, 0xff, 0xff, 0xc9, 0x9c, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5c, 0x8f, + 0x9a, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, + + /* U+F095 "" */ + 0x0, 0x0, 0x0, 0x0, 0x3, 0x62, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x3f, 0xff, 0xe0, 0x0, 0x0, 0x0, 0x9, + 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x2d, 0xff, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xfd, 0x0, 0x0, 0x1, + 0x0, 0x9, 0xff, 0x40, 0x1, 0x8e, 0xe1, 0x1a, + 0xff, 0x70, 0x0, 0xef, 0xff, 0xde, 0xff, 0x90, + 0x0, 0xc, 0xff, 0xff, 0xff, 0x60, 0x0, 0x0, + 0x8f, 0xff, 0xe9, 0x10, 0x0, 0x0, 0x2, 0x76, + 0x30, 0x0, 0x0, 0x0, 0x0, + + /* U+F0C4 "" */ + 0x7, 0x93, 0x0, 0x0, 0x22, 0xa, 0xff, 0xf2, + 0x0, 0x8f, 0xf5, 0xf9, 0x1f, 0x70, 0x8f, 0xf9, + 0xc, 0xfc, 0xf8, 0x8f, 0xf9, 0x0, 0x1a, 0xef, + 0xff, 0xf9, 0x0, 0x0, 0x0, 0xef, 0xfc, 0x0, + 0x0, 0x7, 0xbf, 0xff, 0xf6, 0x0, 0xa, 0xff, + 0xfa, 0xbf, 0xf6, 0x0, 0xf9, 0x1f, 0x70, 0xbf, + 0xf6, 0xc, 0xfc, 0xf4, 0x0, 0xbf, 0xf4, 0x1a, + 0xc6, 0x0, 0x0, 0x56, 0x0, + + /* U+F0C5 "" */ + 0x0, 0x3, 0x44, 0x41, 0x20, 0x0, 0x0, 0xff, + 0xff, 0x5e, 0x40, 0x24, 0x1f, 0xff, 0xf5, 0xee, + 0x2f, 0xf4, 0xff, 0xff, 0xc8, 0x82, 0xff, 0x4f, + 0xff, 0xff, 0xff, 0x5f, 0xf4, 0xff, 0xff, 0xff, + 0xf5, 0xff, 0x4f, 0xff, 0xff, 0xff, 0x5f, 0xf4, + 0xff, 0xff, 0xff, 0xf5, 0xff, 0x4f, 0xff, 0xff, + 0xff, 0x5f, 0xf4, 0xff, 0xff, 0xff, 0xf4, 0xff, + 0x93, 0x44, 0x44, 0x43, 0xf, 0xff, 0xff, 0xff, + 0x50, 0x0, 0x68, 0x88, 0x88, 0x71, 0x0, 0x0, + + /* U+F0C7 "" */ + 0x48, 0x88, 0x88, 0x87, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xfb, 0x0, 0xf8, 0x0, 0x0, 0xb, 0xfb, + 0xf, 0x80, 0x0, 0x0, 0xbf, 0xf3, 0xfb, 0x77, + 0x77, 0x7d, 0xff, 0x4f, 0xff, 0xff, 0xff, 0xff, + 0xf4, 0xff, 0xff, 0x42, 0xdf, 0xff, 0x4f, 0xff, + 0xc0, 0x8, 0xff, 0xf4, 0xff, 0xfe, 0x0, 0xaf, + 0xff, 0x4f, 0xff, 0xfc, 0xaf, 0xff, 0xf4, 0xaf, + 0xff, 0xff, 0xff, 0xfd, 0x10, + + /* U+F0C9 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0x9a, 0xaa, 0xaa, 0xaa, 0xaa, + 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x89, 0x99, + 0x99, 0x99, 0x99, 0x3f, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x12, 0x22, 0x22, 0x22, 0x22, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x9a, 0xaa, 0xaa, 0xaa, + 0xaa, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F0E0 "" */ + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x4e, 0xff, 0xff, 0xff, + 0xff, 0xe4, 0xc3, 0xbf, 0xff, 0xff, 0xfb, 0x3c, + 0xff, 0x57, 0xff, 0xff, 0x75, 0xff, 0xff, 0xf9, + 0x3d, 0xd3, 0x9f, 0xff, 0xff, 0xff, 0xd5, 0x5d, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xfb, + + /* U+F0E7 "" */ + 0x1, 0xbb, 0xba, 0x10, 0x0, 0x5f, 0xff, 0xf1, + 0x0, 0x7, 0xff, 0xfb, 0x0, 0x0, 0x9f, 0xff, + 0x60, 0x0, 0xb, 0xff, 0xff, 0xff, 0x60, 0xef, + 0xff, 0xff, 0xf1, 0xe, 0xff, 0xff, 0xf8, 0x0, + 0x0, 0xc, 0xfe, 0x0, 0x0, 0x0, 0xff, 0x50, + 0x0, 0x0, 0x3f, 0xc0, 0x0, 0x0, 0x7, 0xf3, + 0x0, 0x0, 0x0, 0xa9, 0x0, 0x0, 0x0, 0x2, + 0x0, 0x0, 0x0, + + /* U+F0EA "" */ + 0x0, 0x2a, 0x50, 0x0, 0x0, 0xe, 0xff, 0x8f, + 0xff, 0x20, 0x0, 0xff, 0xf8, 0xff, 0xf4, 0x0, + 0xf, 0xff, 0xeb, 0xbb, 0x30, 0x0, 0xff, 0xf4, + 0x99, 0x92, 0x60, 0xf, 0xff, 0x5f, 0xff, 0x4f, + 0xa0, 0xff, 0xf5, 0xff, 0xf5, 0x56, 0x1f, 0xff, + 0x5f, 0xff, 0xff, 0xf4, 0xff, 0xf5, 0xff, 0xff, + 0xff, 0x4e, 0xff, 0x5f, 0xff, 0xff, 0xf4, 0x0, + 0x5, 0xff, 0xff, 0xff, 0x40, 0x0, 0x5f, 0xff, + 0xff, 0xf4, 0x0, 0x0, 0x44, 0x44, 0x44, 0x0, + + /* U+F0F3 "" */ + 0x0, 0x0, 0x15, 0x0, 0x0, 0x0, 0x0, 0x9, + 0xf1, 0x0, 0x0, 0x0, 0x2d, 0xff, 0xf9, 0x0, + 0x0, 0xe, 0xff, 0xff, 0xf7, 0x0, 0x5, 0xff, + 0xff, 0xff, 0xd0, 0x0, 0x8f, 0xff, 0xff, 0xff, + 0x0, 0xa, 0xff, 0xff, 0xff, 0xf2, 0x0, 0xdf, + 0xff, 0xff, 0xff, 0x50, 0x6f, 0xff, 0xff, 0xff, + 0xfd, 0xe, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x24, + 0x44, 0x44, 0x44, 0x43, 0x0, 0x0, 0x2f, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x46, 0x0, 0x0, 0x0, + + /* U+F11C "" */ + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0xfc, + 0x8e, 0x8e, 0x8e, 0x88, 0xe8, 0xf7, 0xf8, 0xc, + 0xc, 0xb, 0x0, 0xb0, 0xf8, 0xff, 0xec, 0xfc, + 0xec, 0xee, 0xcf, 0xf8, 0xff, 0xa0, 0xc0, 0xa0, + 0x77, 0x2f, 0xf8, 0xff, 0xec, 0xfc, 0xec, 0xee, + 0xcf, 0xf8, 0xf8, 0xc, 0x0, 0x0, 0x0, 0xb0, + 0xf8, 0xfc, 0x8e, 0x88, 0x88, 0x88, 0xe8, 0xf7, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + + /* U+F124 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x18, 0xef, 0xe0, 0x0, 0x0, + 0x0, 0x29, 0xff, 0xff, 0xb0, 0x0, 0x0, 0x3a, + 0xff, 0xff, 0xff, 0x30, 0x0, 0x4c, 0xff, 0xff, + 0xff, 0xfc, 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, + 0xf5, 0x0, 0xe, 0xff, 0xff, 0xff, 0xff, 0xd0, + 0x0, 0x1, 0x34, 0x44, 0xdf, 0xff, 0x60, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0xf8, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x26, + 0x0, 0x0, 0x0, + + /* U+F15B "" */ + 0x9b, 0xbb, 0xb2, 0x70, 0xf, 0xff, 0xff, 0x4f, + 0x90, 0xff, 0xff, 0xf4, 0xff, 0x9f, 0xff, 0xff, + 0x54, 0x44, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x34, 0x44, + 0x44, 0x44, 0x30, + + /* U+F1EB "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5, 0x9b, 0xcb, 0x95, 0x0, 0x0, 0x0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0x80, 0x3, 0xef, + 0xfa, 0x53, 0x23, 0x5a, 0xff, 0xe3, 0xdf, 0xa1, + 0x0, 0x0, 0x0, 0x1, 0xaf, 0xd2, 0x60, 0x5, + 0xbe, 0xfe, 0xb5, 0x0, 0x52, 0x0, 0x1c, 0xff, + 0xfe, 0xff, 0xfc, 0x10, 0x0, 0x2, 0xec, 0x40, + 0x0, 0x4c, 0xe2, 0x0, 0x0, 0x1, 0x0, 0x1, + 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0xa, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xd6, 0x0, + 0x0, 0x0, + + /* U+F240 "" */ + 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x75, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf8, + 0x34, 0x44, 0x44, 0x44, 0x44, 0x4f, 0xdf, 0x8c, + 0xff, 0xff, 0xff, 0xff, 0xf2, 0xcf, 0xf8, 0xcf, + 0xff, 0xff, 0xff, 0xff, 0x8, 0xff, 0x89, 0xcc, + 0xcc, 0xcc, 0xcc, 0xc3, 0xff, 0xfb, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x9f, 0x9c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F241 "" */ + 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x75, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf8, + 0x34, 0x44, 0x44, 0x43, 0x0, 0x4f, 0xdf, 0x8c, + 0xff, 0xff, 0xff, 0xc0, 0x2, 0xcf, 0xf8, 0xcf, + 0xff, 0xff, 0xfc, 0x0, 0x8, 0xff, 0x89, 0xcc, + 0xcc, 0xcc, 0x90, 0x3, 0xff, 0xfb, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x9f, 0x9c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F242 "" */ + 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x75, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf8, + 0x34, 0x44, 0x42, 0x0, 0x0, 0x4f, 0xdf, 0x8c, + 0xff, 0xff, 0x80, 0x0, 0x2, 0xcf, 0xf8, 0xcf, + 0xff, 0xf8, 0x0, 0x0, 0x8, 0xff, 0x89, 0xcc, + 0xcc, 0x60, 0x0, 0x3, 0xff, 0xfb, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x9f, 0x9c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F243 "" */ + 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x75, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf8, + 0x34, 0x41, 0x0, 0x0, 0x0, 0x4f, 0xdf, 0x8c, + 0xff, 0x40, 0x0, 0x0, 0x2, 0xcf, 0xf8, 0xcf, + 0xf4, 0x0, 0x0, 0x0, 0x8, 0xff, 0x89, 0xcc, + 0x30, 0x0, 0x0, 0x3, 0xff, 0xfb, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x9f, 0x9c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F244 "" */ + 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x75, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xdf, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xcf, 0xf8, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0x80, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xff, 0xfb, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x9f, 0x9c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F287 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x25, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xcb, 0xfe, 0x0, 0x0, 0x0, + 0x1, 0x0, 0xd, 0x10, 0x42, 0x0, 0x0, 0x0, + 0x9f, 0xd1, 0x68, 0x0, 0x0, 0x0, 0x68, 0x0, + 0xff, 0xfe, 0xee, 0xed, 0xdd, 0xdd, 0xef, 0xc0, + 0x9f, 0xd1, 0x0, 0xb3, 0x0, 0x0, 0x68, 0x0, + 0x1, 0x0, 0x0, 0x3b, 0x5, 0x74, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xbe, 0xfb, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2d, 0xfb, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F293 "" */ + 0x0, 0x0, 0x34, 0x20, 0x0, 0x0, 0x6e, 0xfe, + 0xfd, 0x20, 0x4, 0xff, 0xf3, 0xff, 0xd0, 0xc, + 0xff, 0xf0, 0x4f, 0xf5, 0xf, 0xd5, 0xf2, 0x95, + 0xf8, 0x2f, 0xf7, 0x41, 0x3c, 0xfa, 0x3f, 0xff, + 0x60, 0xaf, 0xfb, 0x3f, 0xfe, 0x20, 0x4f, 0xfb, + 0x2f, 0xe2, 0x92, 0x75, 0xfa, 0xf, 0xeb, 0xf1, + 0x49, 0xf8, 0x9, 0xff, 0xf0, 0x9f, 0xf2, 0x1, + 0xdf, 0xf9, 0xff, 0x90, 0x0, 0x6, 0xab, 0x95, + 0x0, + + /* U+F2ED "" */ + 0x0, 0x4, 0x88, 0x70, 0x0, 0xb, 0xcc, 0xff, + 0xff, 0xdc, 0xc5, 0xbc, 0xcc, 0xcc, 0xcc, 0xcc, + 0x52, 0x88, 0x88, 0x88, 0x88, 0x60, 0x4f, 0xff, + 0xff, 0xff, 0xfc, 0x4, 0xfa, 0xae, 0x6f, 0x5f, + 0xc0, 0x4f, 0xaa, 0xe6, 0xf4, 0xfc, 0x4, 0xfa, + 0xae, 0x6f, 0x4f, 0xc0, 0x4f, 0xaa, 0xe6, 0xf4, + 0xfc, 0x4, 0xfa, 0xae, 0x6f, 0x4f, 0xc0, 0x4f, + 0xaa, 0xe6, 0xf5, 0xfc, 0x3, 0xff, 0xff, 0xff, + 0xff, 0xb0, 0x6, 0x88, 0x88, 0x88, 0x72, 0x0, + + /* U+F304 "" */ + 0x0, 0x0, 0x0, 0x0, 0x1, 0x71, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xef, 0xd1, 0x0, 0x0, 0x0, + 0x1, 0x5f, 0xff, 0xc0, 0x0, 0x0, 0x2, 0xea, + 0x5f, 0xfd, 0x0, 0x0, 0x2, 0xef, 0xfa, 0x5d, + 0x20, 0x0, 0x2, 0xef, 0xff, 0xf8, 0x0, 0x0, + 0x2, 0xef, 0xff, 0xfe, 0x20, 0x0, 0x2, 0xef, + 0xff, 0xfe, 0x20, 0x0, 0x2, 0xef, 0xff, 0xfe, + 0x20, 0x0, 0x0, 0xbf, 0xff, 0xfe, 0x20, 0x0, + 0x0, 0xd, 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, + 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, 0x6, 0x64, + 0x10, 0x0, 0x0, 0x0, 0x0, + + /* U+F55A "" */ + 0x0, 0x5, 0xef, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5, + 0xff, 0xff, 0x91, 0xdd, 0x19, 0xff, 0xf5, 0xff, + 0xff, 0xfd, 0x11, 0x11, 0xdf, 0xff, 0xef, 0xff, + 0xff, 0xfb, 0x0, 0xbf, 0xff, 0xf5, 0xff, 0xff, + 0xfd, 0x11, 0x11, 0xdf, 0xff, 0x5, 0xff, 0xff, + 0x91, 0xdd, 0x19, 0xff, 0xf0, 0x5, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0x4, 0xef, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F7C2 "" */ + 0x0, 0x17, 0x88, 0x87, 0x20, 0x2d, 0xff, 0xff, + 0xfd, 0x2e, 0xa0, 0xb3, 0x78, 0xfe, 0xfa, 0xb, + 0x37, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfc, 0xff, 0xff, 0xff, 0xfc, 0x4, 0x44, + 0x44, 0x44, 0x0, + + /* U+F8A2 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4, 0xf0, 0x0, 0x69, 0x0, + 0x0, 0x0, 0xdf, 0x0, 0x7f, 0xc0, 0x0, 0x0, + 0xd, 0xf0, 0x8f, 0xff, 0xdd, 0xdd, 0xdd, 0xff, + 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xb, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xc0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0 +}; + + +/*--------------------- + * GLYPH DESCRIPTION + *--------------------*/ + +static const lv_font_fmt_txt_glyph_dsc_t glyph_dsc[] = { + {.bitmap_index = 0, .adv_w = 0, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0} /* id = 0 reserved */, + {.bitmap_index = 0, .adv_w = 48, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 0, .adv_w = 56, .box_w = 2, .box_h = 8, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 8, .adv_w = 71, .box_w = 4, .box_h = 4, .ofs_x = 0, .ofs_y = 4}, + {.bitmap_index = 16, .adv_w = 111, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 44, .adv_w = 117, .box_w = 7, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 83, .adv_w = 179, .box_w = 11, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 127, .adv_w = 143, .box_w = 9, .box_h = 9, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 168, .adv_w = 38, .box_w = 2, .box_h = 4, .ofs_x = 0, .ofs_y = 4}, + {.bitmap_index = 172, .adv_w = 66, .box_w = 4, .box_h = 11, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 194, .adv_w = 66, .box_w = 4, .box_h = 11, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 216, .adv_w = 81, .box_w = 5, .box_h = 5, .ofs_x = 0, .ofs_y = 3}, + {.bitmap_index = 229, .adv_w = 121, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 250, .adv_w = 57, .box_w = 3, .box_h = 3, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 255, .adv_w = 97, .box_w = 6, .box_h = 1, .ofs_x = 0, .ofs_y = 3}, + {.bitmap_index = 258, .adv_w = 58, .box_w = 2, .box_h = 2, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 260, .adv_w = 54, .box_w = 4, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 276, .adv_w = 110, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 304, .adv_w = 90, .box_w = 4, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 320, .adv_w = 108, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 348, .adv_w = 109, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 376, .adv_w = 110, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 404, .adv_w = 109, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 432, .adv_w = 110, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 460, .adv_w = 109, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 488, .adv_w = 112, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 516, .adv_w = 110, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 544, .adv_w = 57, .box_w = 2, .box_h = 6, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 550, .adv_w = 57, .box_w = 2, .box_h = 9, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 559, .adv_w = 121, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 587, .adv_w = 118, .box_w = 7, .box_h = 4, .ofs_x = 0, .ofs_y = 2}, + {.bitmap_index = 601, .adv_w = 119, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 629, .adv_w = 111, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 657, .adv_w = 183, .box_w = 11, .box_h = 10, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 712, .adv_w = 136, .box_w = 9, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 748, .adv_w = 134, .box_w = 8, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 780, .adv_w = 147, .box_w = 9, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 816, .adv_w = 145, .box_w = 9, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 852, .adv_w = 134, .box_w = 7, .box_h = 8, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 880, .adv_w = 124, .box_w = 7, .box_h = 8, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 908, .adv_w = 156, .box_w = 10, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 948, .adv_w = 145, .box_w = 8, .box_h = 8, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 980, .adv_w = 53, .box_w = 2, .box_h = 8, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 988, .adv_w = 101, .box_w = 6, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1012, .adv_w = 134, .box_w = 9, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1048, .adv_w = 113, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1076, .adv_w = 168, .box_w = 10, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1116, .adv_w = 145, .box_w = 9, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1152, .adv_w = 157, .box_w = 10, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1192, .adv_w = 134, .box_w = 7, .box_h = 8, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1220, .adv_w = 157, .box_w = 10, .box_h = 11, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 1275, .adv_w = 145, .box_w = 8, .box_h = 8, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1307, .adv_w = 134, .box_w = 8, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1339, .adv_w = 124, .box_w = 8, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1371, .adv_w = 147, .box_w = 8, .box_h = 8, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1403, .adv_w = 137, .box_w = 9, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1439, .adv_w = 191, .box_w = 12, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1487, .adv_w = 136, .box_w = 9, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1523, .adv_w = 134, .box_w = 9, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1559, .adv_w = 124, .box_w = 8, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1591, .adv_w = 54, .box_w = 4, .box_h = 11, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 1613, .adv_w = 54, .box_w = 4, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1629, .adv_w = 54, .box_w = 3, .box_h = 11, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 1646, .adv_w = 95, .box_w = 6, .box_h = 5, .ofs_x = 0, .ofs_y = 4}, + {.bitmap_index = 1661, .adv_w = 119, .box_w = 8, .box_h = 1, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 1665, .adv_w = 64, .box_w = 3, .box_h = 2, .ofs_x = 0, .ofs_y = 6}, + {.bitmap_index = 1668, .adv_w = 113, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1689, .adv_w = 111, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1717, .adv_w = 102, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1738, .adv_w = 111, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1766, .adv_w = 113, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1787, .adv_w = 56, .box_w = 4, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1803, .adv_w = 113, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 1835, .adv_w = 111, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1863, .adv_w = 42, .box_w = 2, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1871, .adv_w = 42, .box_w = 3, .box_h = 11, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 1888, .adv_w = 101, .box_w = 7, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1916, .adv_w = 42, .box_w = 2, .box_h = 8, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1924, .adv_w = 167, .box_w = 10, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1954, .adv_w = 113, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1975, .adv_w = 113, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1996, .adv_w = 111, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 2028, .adv_w = 111, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 2060, .adv_w = 70, .box_w = 5, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2075, .adv_w = 104, .box_w = 6, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2093, .adv_w = 56, .box_w = 4, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2111, .adv_w = 111, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2132, .adv_w = 101, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2153, .adv_w = 145, .box_w = 10, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2183, .adv_w = 101, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2204, .adv_w = 101, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 2236, .adv_w = 101, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2257, .adv_w = 66, .box_w = 4, .box_h = 11, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 2279, .adv_w = 50, .box_w = 1, .box_h = 11, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 2285, .adv_w = 66, .box_w = 4, .box_h = 11, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 2307, .adv_w = 118, .box_w = 7, .box_h = 2, .ofs_x = 0, .ofs_y = 3}, + {.bitmap_index = 2314, .adv_w = 192, .box_w = 12, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2368, .adv_w = 192, .box_w = 11, .box_h = 12, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2434, .adv_w = 192, .box_w = 12, .box_h = 11, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 2500, .adv_w = 192, .box_w = 12, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 2566, .adv_w = 192, .box_w = 12, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 2626, .adv_w = 192, .box_w = 12, .box_h = 12, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 2698, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 2776, .adv_w = 192, .box_w = 12, .box_h = 12, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 2848, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 2926, .adv_w = 192, .box_w = 12, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2980, .adv_w = 192, .box_w = 12, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3046, .adv_w = 192, .box_w = 12, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3100, .adv_w = 132, .box_w = 9, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3141, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3219, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3297, .adv_w = 216, .box_w = 14, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3374, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3452, .adv_w = 216, .box_w = 14, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3515, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3593, .adv_w = 96, .box_w = 6, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3623, .adv_w = 144, .box_w = 9, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3668, .adv_w = 216, .box_w = 14, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3759, .adv_w = 192, .box_w = 12, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3813, .adv_w = 132, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3872, .adv_w = 168, .box_w = 8, .box_h = 12, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 3920, .adv_w = 168, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3992, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4053, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4114, .adv_w = 168, .box_w = 8, .box_h = 12, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 4162, .adv_w = 168, .box_w = 12, .box_h = 11, .ofs_x = -1, .ofs_y = -1}, + {.bitmap_index = 4228, .adv_w = 120, .box_w = 7, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4267, .adv_w = 120, .box_w = 7, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4306, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4367, .adv_w = 168, .box_w = 11, .box_h = 3, .ofs_x = 0, .ofs_y = 3}, + {.bitmap_index = 4384, .adv_w = 216, .box_w = 14, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 4447, .adv_w = 240, .box_w = 16, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 4551, .adv_w = 216, .box_w = 15, .box_h = 13, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 4649, .adv_w = 192, .box_w = 12, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4715, .adv_w = 168, .box_w = 11, .box_h = 7, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 4754, .adv_w = 168, .box_w = 11, .box_h = 7, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 4793, .adv_w = 240, .box_w = 16, .box_h = 10, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 4873, .adv_w = 192, .box_w = 12, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 4927, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5005, .adv_w = 192, .box_w = 13, .box_h = 13, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 5090, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5151, .adv_w = 168, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5223, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5284, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5345, .adv_w = 192, .box_w = 12, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 5399, .adv_w = 120, .box_w = 9, .box_h = 13, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 5458, .adv_w = 168, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5530, .adv_w = 168, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5602, .adv_w = 216, .box_w = 14, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 5665, .adv_w = 192, .box_w = 14, .box_h = 13, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 5756, .adv_w = 144, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5815, .adv_w = 240, .box_w = 15, .box_h = 12, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5905, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 5973, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 6041, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 6109, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 6177, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 6245, .adv_w = 240, .box_w = 16, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6333, .adv_w = 168, .box_w = 10, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6398, .adv_w = 168, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6470, .adv_w = 192, .box_w = 13, .box_h = 13, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 6555, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 6623, .adv_w = 144, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6682, .adv_w = 193, .box_w = 13, .box_h = 9, .ofs_x = 0, .ofs_y = 0} +}; + +/*--------------------- + * CHARACTER MAPPING + *--------------------*/ + +static const uint16_t unicode_list_1[] = { + 0x0, 0x2b, 0x5c3, 0x121e, 0x18f7, 0x1d18, 0x30b6, 0x41c8, + 0xa1f8, 0xa1ff, 0xa202, 0xa203, 0xa204, 0xa208, 0xa20a, 0xa20c, + 0xa210, 0xa213, 0xa218, 0xa21d, 0xa21e, 0xa21f, 0xa235, 0xa23a, + 0xa23f, 0xa242, 0xa243, 0xa244, 0xa248, 0xa249, 0xa24a, 0xa24b, + 0xa25e, 0xa25f, 0xa265, 0xa267, 0xa268, 0xa26b, 0xa26e, 0xa26f, + 0xa270, 0xa272, 0xa28a, 0xa28c, 0xa2bb, 0xa2bc, 0xa2be, 0xa2c0, + 0xa2d7, 0xa2de, 0xa2e1, 0xa2ea, 0xa313, 0xa31b, 0xa352, 0xa3e2, + 0xa437, 0xa438, 0xa439, 0xa43a, 0xa43b, 0xa47e, 0xa48a, 0xa4e4, + 0xa4fb, 0xa751, 0xa9b9, 0xaa99 +}; + +/*Collect the unicode lists and glyph_id offsets*/ +static const lv_font_fmt_txt_cmap_t cmaps[] = +{ + { + .range_start = 32, .range_length = 95, .glyph_id_start = 1, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 19977, .range_length = 43674, .glyph_id_start = 96, + .unicode_list = unicode_list_1, .glyph_id_ofs_list = NULL, .list_length = 68, .type = LV_FONT_FMT_TXT_CMAP_SPARSE_TINY + } +}; + + + +/*-------------------- + * ALL CUSTOM DATA + *--------------------*/ + +#if LV_VERSION_CHECK(8, 0, 0) +/*Store all the custom data of the font*/ +static lv_font_fmt_txt_glyph_cache_t cache; +static const lv_font_fmt_txt_dsc_t font_dsc = { +#else +static lv_font_fmt_txt_dsc_t font_dsc = { +#endif + .glyph_bitmap = glyph_bitmap, + .glyph_dsc = glyph_dsc, + .cmaps = cmaps, + .kern_dsc = NULL, + .kern_scale = 0, + .cmap_num = 2, + .bpp = 4, + .kern_classes = 0, + .bitmap_format = 0, +#if LV_VERSION_CHECK(8, 0, 0) + .cache = &cache +#endif +}; + + +/*----------------- + * PUBLIC FONT + *----------------*/ + +/*Initialize a public general font descriptor*/ +#if LV_VERSION_CHECK(8, 0, 0) +const lv_font_t lv_font_MI_LanTing_Regular_12 = { +#else +lv_font_t lv_font_MI_LanTing_Regular_12 = { +#endif + .get_glyph_dsc = lv_font_get_glyph_dsc_fmt_txt, /*Function pointer to get glyph's data*/ + .get_glyph_bitmap = lv_font_get_bitmap_fmt_txt, /*Function pointer to get glyph's bitmap*/ + .line_height = 12, /*The maximum line height required by the font default: (f.src.ascent - f.src.descent)*/ + .base_line = 2, /*Baseline measured from the bottom of the line*/ +#if !(LVGL_VERSION_MAJOR == 6 && LVGL_VERSION_MINOR == 0) + .subpx = LV_FONT_SUBPX_NONE, +#endif +#if LV_VERSION_CHECK(7, 4, 0) || LVGL_VERSION_MAJOR >= 8 + .underline_position = -1, + .underline_thickness = 1, +#endif + .dsc = &font_dsc /*The custom font data. Will be accessed by `get_glyph_bitmap/dsc` */ +}; + + + +#endif /*#if LV_FONT_MI_LANTING_REGULAR_12*/ + diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_16.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_16.c new file mode 100644 index 0000000000000000000000000000000000000000..2c5b71cd27ab6b5268f371500e237d53c9af4690 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_16.c @@ -0,0 +1,2618 @@ +/* + * Copyright 2024 NXP + * NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in + * accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, + * activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to + * comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license + * terms, then you may not retain, install, activate or otherwise use the software. + */ +/******************************************************************************* + * Size: 16 px + * Bpp: 4 + * Opts: --user-data-dir=C:\Users\hp\AppData\Roaming\gui-guider --app-path=C:\NXP\GUI-Guider-1.7.2-GA\resources\app.asar --no-sandbox --no-zygote --lang=zh-CN --device-scale-factor=1.5 --num-raster-threads=4 --enable-main-frame-before-activation --renderer-client-id=5 --time-ticks-at-unix-epoch=-1732015070561205 --launch-time-ticks=65380923608 --mojo-platform-channel-handle=3108 --field-trial-handle=1864,i,17219279099561217522,18026807573185265005,131072 --disable-features=SpareRendererForSitePerProcess,WinRetrieveSuggestionsOnlyOnDemand /prefetch:1 + ******************************************************************************/ + +#ifdef LV_LVGL_H_INCLUDE_SIMPLE +#include "lvgl.h" +#else +#include "lvgl.h" +#endif + +#ifndef LV_FONT_MI_LANTING_REGULAR_16 +#define LV_FONT_MI_LANTING_REGULAR_16 1 +#endif + +#if LV_FONT_MI_LANTING_REGULAR_16 + +/*----------------- + * BITMAPS + *----------------*/ + +/*Store the image of the glyphs*/ +static LV_ATTRIBUTE_LARGE_CONST const uint8_t glyph_bitmap[] = { + /* U+0020 " " */ + + /* U+0021 "!" */ + 0x7f, 0x26, 0xf2, 0x6f, 0x15, 0xf0, 0x5f, 0x4, + 0xf0, 0x4f, 0x3, 0xe0, 0x3e, 0x1, 0x60, 0x0, + 0x4, 0xc0, 0x6f, 0x10, + + /* U+0022 "\"" */ + 0x2f, 0x56, 0xf1, 0x1f, 0x45, 0xf0, 0xf, 0x34, + 0xf0, 0xe, 0x23, 0xe0, 0x7, 0x11, 0x70, + + /* U+0023 "#" */ + 0x0, 0x5, 0xa0, 0x2e, 0x0, 0x0, 0x8, 0x70, + 0x5b, 0x0, 0x0, 0xb, 0x50, 0x78, 0x0, 0x0, + 0xe, 0x20, 0xa5, 0x0, 0xd, 0xef, 0xee, 0xff, + 0xe1, 0x1, 0x5c, 0x12, 0xf1, 0x10, 0x0, 0x79, + 0x3, 0xc0, 0x0, 0x0, 0xa6, 0x6, 0x90, 0x0, + 0xaf, 0xff, 0xff, 0xff, 0x50, 0x12, 0xf2, 0x2d, + 0x52, 0x0, 0x3, 0xd0, 0xf, 0x0, 0x0, 0x6, + 0xa0, 0x2d, 0x0, 0x0, 0x9, 0x70, 0x6a, 0x0, + 0x0, + + /* U+0024 "$" */ + 0x0, 0x0, 0x42, 0x0, 0x0, 0x0, 0x0, 0x84, + 0x0, 0x0, 0x0, 0x6d, 0xff, 0xb2, 0x0, 0x6, + 0xf6, 0x97, 0xbe, 0x10, 0xc, 0x60, 0x84, 0xe, + 0x70, 0xe, 0x40, 0x84, 0x6, 0x50, 0xc, 0xb0, + 0x84, 0x0, 0x0, 0x2, 0xed, 0xc6, 0x0, 0x0, + 0x0, 0x17, 0xdf, 0xd3, 0x0, 0x0, 0x0, 0x87, + 0x9f, 0x30, 0x0, 0x0, 0x84, 0x7, 0xc0, 0x3e, + 0x0, 0x84, 0x3, 0xf0, 0xf, 0x40, 0x84, 0x6, + 0xd0, 0x8, 0xe4, 0x85, 0x4e, 0x60, 0x0, 0x7d, + 0xff, 0xe6, 0x0, 0x0, 0x0, 0x85, 0x0, 0x0, + 0x0, 0x0, 0x84, 0x0, 0x0, + + /* U+0025 "%" */ + 0x2c, 0xfc, 0x20, 0x0, 0xe, 0x20, 0xb, 0x81, + 0x7c, 0x0, 0x8, 0xa0, 0x0, 0xe0, 0x0, 0xf0, + 0x1, 0xe2, 0x0, 0xe, 0x10, 0xf, 0x0, 0x8a, + 0x0, 0x0, 0xa8, 0x7, 0xc0, 0x1e, 0x20, 0x0, + 0x1, 0xbf, 0xc2, 0x8, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x1, 0xf1, 0x1b, 0xeb, 0x10, 0x0, 0x0, + 0x99, 0xa, 0x80, 0x99, 0x0, 0x0, 0x1f, 0x10, + 0xf0, 0x2, 0xd0, 0x0, 0x9, 0x90, 0xf, 0x0, + 0xf, 0x0, 0x2, 0xf1, 0x0, 0xe1, 0x2, 0xe0, + 0x0, 0x98, 0x0, 0x9, 0x92, 0xa9, 0x0, 0x2f, + 0x10, 0x0, 0x1a, 0xfb, 0x10, + + /* U+0026 "&" */ + 0x0, 0x7, 0xee, 0xa0, 0x0, 0x0, 0x0, 0x5d, + 0x21, 0xc9, 0x0, 0x0, 0x0, 0xa7, 0x0, 0x5d, + 0x0, 0x0, 0x0, 0x88, 0x0, 0x7c, 0x0, 0x0, + 0x0, 0x2e, 0x13, 0xe4, 0x0, 0x0, 0x0, 0x9, + 0xee, 0x50, 0x0, 0x0, 0x0, 0x7e, 0xcb, 0x0, + 0xb, 0x50, 0x7, 0xd2, 0xb, 0xa0, 0xe, 0x40, + 0x1f, 0x30, 0x0, 0xcb, 0x4f, 0x0, 0x3f, 0x0, + 0x0, 0xc, 0xf9, 0x0, 0x1f, 0x20, 0x0, 0x6, + 0xfd, 0x10, 0xa, 0xd5, 0x24, 0xaf, 0x5b, 0xe3, + 0x0, 0x8d, 0xfe, 0x92, 0x0, 0xa7, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+0027 "'" */ + 0x3f, 0x52, 0xf4, 0xf, 0x30, 0xf2, 0x7, 0x0, + + /* U+0028 "(" */ + 0x0, 0x4b, 0x0, 0xd, 0x20, 0x7, 0x90, 0x0, + 0xe2, 0x0, 0x4d, 0x0, 0x8, 0x90, 0x0, 0xb7, + 0x0, 0xd, 0x50, 0x0, 0xd5, 0x0, 0xb, 0x60, + 0x0, 0x88, 0x0, 0x4, 0xc0, 0x0, 0xe, 0x20, + 0x0, 0x78, 0x0, 0x1, 0xd2, 0x0, 0x5, 0xb0, + + /* U+0029 ")" */ + 0x1d, 0x10, 0x0, 0x6a, 0x0, 0x0, 0xe2, 0x0, + 0x7, 0x90, 0x0, 0x2f, 0x0, 0x0, 0xe3, 0x0, + 0xc, 0x60, 0x0, 0xa8, 0x0, 0xa, 0x80, 0x0, + 0xb6, 0x0, 0xd, 0x30, 0x1, 0xe0, 0x0, 0x69, + 0x0, 0xd, 0x20, 0x6, 0xa0, 0x1, 0xd1, 0x0, + + /* U+002A "*" */ + 0x0, 0x4f, 0x0, 0x1, 0x22, 0xd0, 0x30, 0x6f, + 0xad, 0xbf, 0x20, 0x8, 0xe5, 0x0, 0x5, 0xd3, + 0xe2, 0x0, 0x76, 0xa, 0x40, 0x0, 0x0, 0x0, + 0x0, + + /* U+002B "+" */ + 0x0, 0x0, 0x58, 0x0, 0x0, 0x0, 0x0, 0x7a, + 0x0, 0x0, 0x0, 0x0, 0x7a, 0x0, 0x0, 0x0, + 0x0, 0x7a, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xf3, 0x3, 0x33, 0x9b, 0x33, 0x30, 0x0, 0x0, + 0x7a, 0x0, 0x0, 0x0, 0x0, 0x7a, 0x0, 0x0, + 0x0, 0x0, 0x7a, 0x0, 0x0, + + /* U+002C "," */ + 0x2f, 0x44, 0xf0, 0x79, 0xb, 0x30, + + /* U+002D "-" */ + 0x0, 0x0, 0x0, 0x0, 0x1f, 0xff, 0xff, 0xf3, + 0x3, 0x33, 0x33, 0x30, + + /* U+002E "." */ + 0x6f, 0x66, 0xf6, + + /* U+002F "/" */ + 0x0, 0x9, 0x70, 0x0, 0xd2, 0x0, 0x2e, 0x0, + 0x6, 0xa0, 0x0, 0xa5, 0x0, 0xe, 0x10, 0x3, + 0xd0, 0x0, 0x79, 0x0, 0xc, 0x40, 0x0, 0xf0, + 0x0, 0x4c, 0x0, 0x9, 0x70, 0x0, 0xd3, 0x0, + 0x0, + + /* U+0030 "0" */ + 0x0, 0x3c, 0xfd, 0x60, 0x0, 0x1e, 0x93, 0x6f, + 0x50, 0x9, 0xb0, 0x0, 0x6e, 0x0, 0xe5, 0x0, + 0x0, 0xf4, 0x1f, 0x10, 0x0, 0xb, 0x72, 0xf0, + 0x0, 0x0, 0x98, 0x3e, 0x0, 0x0, 0x8, 0x93, + 0xf0, 0x0, 0x0, 0x98, 0x1f, 0x10, 0x0, 0xb, + 0x70, 0xe5, 0x0, 0x0, 0xf4, 0x9, 0xb0, 0x0, + 0x5e, 0x0, 0x1f, 0x93, 0x5f, 0x60, 0x0, 0x3c, + 0xfd, 0x60, 0x0, + + /* U+0031 "1" */ + 0x1, 0xaf, 0x5, 0xec, 0xf0, 0xb5, 0x2f, 0x0, + 0x2, 0xf0, 0x0, 0x2f, 0x0, 0x2, 0xf0, 0x0, + 0x2f, 0x0, 0x2, 0xf0, 0x0, 0x2f, 0x0, 0x2, + 0xf0, 0x0, 0x2f, 0x0, 0x2, 0xf0, 0x0, 0x2f, + 0x0, + + /* U+0032 "2" */ + 0x0, 0x6d, 0xfd, 0x50, 0x0, 0x7e, 0x74, 0x7f, + 0x40, 0xf, 0x40, 0x0, 0x7c, 0x1, 0xc0, 0x0, + 0x3, 0xf0, 0x0, 0x0, 0x0, 0x5d, 0x0, 0x0, + 0x0, 0xd, 0x70, 0x0, 0x0, 0x9, 0xc0, 0x0, + 0x0, 0x6, 0xe2, 0x0, 0x0, 0x4, 0xf4, 0x0, + 0x0, 0x2, 0xf6, 0x0, 0x0, 0x1, 0xd9, 0x0, + 0x0, 0x0, 0xcd, 0x32, 0x22, 0x20, 0x3f, 0xff, + 0xff, 0xff, 0x20, + + /* U+0033 "3" */ + 0x0, 0x6d, 0xfd, 0x70, 0x0, 0x7e, 0x53, 0x4c, + 0x80, 0x9, 0x30, 0x0, 0x2f, 0x0, 0x0, 0x0, + 0x2, 0xf1, 0x0, 0x0, 0x2, 0xbd, 0x0, 0x0, + 0xbf, 0xfe, 0x30, 0x0, 0x1, 0x36, 0xd4, 0x0, + 0x0, 0x0, 0x4, 0xe0, 0x0, 0x0, 0x0, 0xe, + 0x40, 0x10, 0x0, 0x0, 0xd5, 0x2f, 0x20, 0x0, + 0x2f, 0x30, 0xae, 0x63, 0x5d, 0xa0, 0x0, 0x7d, + 0xfe, 0x70, 0x0, + + /* U+0034 "4" */ + 0x0, 0x0, 0x3, 0xf0, 0x0, 0x0, 0x0, 0xdf, + 0x0, 0x0, 0x0, 0x8d, 0xf0, 0x0, 0x0, 0x2f, + 0x4f, 0x0, 0x0, 0xc, 0x82, 0xf0, 0x0, 0x7, + 0xd0, 0x2f, 0x0, 0x2, 0xf3, 0x2, 0xf0, 0x0, + 0xb9, 0x0, 0x2f, 0x0, 0x5e, 0x0, 0x2, 0xf0, + 0xc, 0xff, 0xff, 0xff, 0xff, 0x22, 0x22, 0x24, + 0xf3, 0x20, 0x0, 0x0, 0x2f, 0x0, 0x0, 0x0, + 0x2, 0xf0, 0x0, + + /* U+0035 "5" */ + 0x4, 0xff, 0xff, 0xfc, 0x0, 0x5d, 0x22, 0x22, + 0x20, 0x7, 0xb0, 0x0, 0x0, 0x0, 0x89, 0x0, + 0x0, 0x0, 0x9, 0x80, 0x0, 0x0, 0x0, 0xba, + 0xcf, 0xd5, 0x0, 0xc, 0xd5, 0x36, 0xe6, 0x0, + 0x51, 0x0, 0x5, 0xe0, 0x0, 0x0, 0x0, 0xf, + 0x30, 0x0, 0x0, 0x0, 0xf3, 0x5, 0x0, 0x0, + 0x5e, 0x0, 0xcb, 0x43, 0x6e, 0x60, 0x1, 0x9e, + 0xfd, 0x50, 0x0, + + /* U+0036 "6" */ + 0x0, 0x2b, 0xfe, 0x90, 0x0, 0x1e, 0x93, 0x4c, + 0xb0, 0x8, 0xb0, 0x0, 0x1e, 0x20, 0xd5, 0x0, + 0x0, 0x0, 0xf, 0x10, 0x0, 0x0, 0x2, 0xf3, + 0xbf, 0xd7, 0x0, 0x3f, 0xe7, 0x35, 0xe8, 0x3, + 0xf6, 0x0, 0x2, 0xf2, 0x3f, 0x0, 0x0, 0xd, + 0x50, 0xf0, 0x0, 0x0, 0xd6, 0xd, 0x50, 0x0, + 0x2f, 0x20, 0x4e, 0x63, 0x5d, 0x90, 0x0, 0x4d, + 0xfe, 0x70, 0x0, + + /* U+0037 "7" */ + 0x1f, 0xff, 0xff, 0xff, 0x20, 0x22, 0x22, 0x26, + 0xe0, 0x0, 0x0, 0x0, 0xa8, 0x0, 0x0, 0x0, + 0x1f, 0x20, 0x0, 0x0, 0x7, 0xc0, 0x0, 0x0, + 0x0, 0xd6, 0x0, 0x0, 0x0, 0x4f, 0x0, 0x0, + 0x0, 0xa, 0x90, 0x0, 0x0, 0x1, 0xf3, 0x0, + 0x0, 0x0, 0x7c, 0x0, 0x0, 0x0, 0xd, 0x60, + 0x0, 0x0, 0x3, 0xf0, 0x0, 0x0, 0x0, 0xaa, + 0x0, 0x0, 0x0, + + /* U+0038 "8" */ + 0x0, 0x5c, 0xfd, 0x80, 0x0, 0x4f, 0x72, 0x5d, + 0xa0, 0xb, 0x80, 0x0, 0x3f, 0x0, 0xb7, 0x0, + 0x3, 0xf0, 0x4, 0xe3, 0x2, 0xc9, 0x0, 0x8, + 0xff, 0xfd, 0x0, 0x6, 0xe6, 0x35, 0xda, 0x0, + 0xf4, 0x0, 0x1, 0xe4, 0x4e, 0x0, 0x0, 0xa, + 0x84, 0xe0, 0x0, 0x0, 0x99, 0x1f, 0x30, 0x0, + 0xe, 0x50, 0x8e, 0x63, 0x4c, 0xc0, 0x0, 0x6d, + 0xfe, 0x80, 0x0, + + /* U+0039 "9" */ + 0x0, 0x4d, 0xfd, 0x60, 0x0, 0x5f, 0x73, 0x6e, + 0x60, 0xe, 0x60, 0x0, 0x4e, 0x2, 0xf1, 0x0, + 0x0, 0xf3, 0x2f, 0x0, 0x0, 0xe, 0x50, 0xf4, + 0x0, 0x3, 0xf6, 0x8, 0xd3, 0x3, 0xdf, 0x60, + 0x9, 0xff, 0xf7, 0xd4, 0x0, 0x0, 0x20, 0xe, + 0x30, 0x0, 0x0, 0x2, 0xf1, 0x1c, 0x10, 0x0, + 0x9c, 0x0, 0xad, 0x43, 0x8f, 0x40, 0x0, 0x8e, + 0xfd, 0x50, 0x0, + + /* U+003A ":" */ + 0x7f, 0x57, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0x57, 0xf5, + + /* U+003B ";" */ + 0x7f, 0x57, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6e, 0x57, 0xf5, 0x8, + 0x40, 0xc1, 0x57, 0x0, 0x0, + + /* U+003C "<" */ + 0x0, 0x0, 0x0, 0x0, 0x21, 0x0, 0x0, 0x0, + 0x7, 0xf2, 0x0, 0x0, 0x3, 0xdd, 0x50, 0x0, + 0x1, 0x9f, 0x70, 0x0, 0x0, 0x6e, 0xa1, 0x0, + 0x0, 0xc, 0xd4, 0x0, 0x0, 0x0, 0xf, 0x80, + 0x0, 0x0, 0x0, 0x2, 0xce, 0x50, 0x0, 0x0, + 0x0, 0x6, 0xeb, 0x20, 0x0, 0x0, 0x0, 0x1a, + 0xf8, 0x0, 0x0, 0x0, 0x0, 0x4d, 0xe1, 0x0, + 0x0, 0x0, 0x0, 0x82, + + /* U+003D "=" */ + 0xf, 0xff, 0xff, 0xff, 0xe0, 0x22, 0x22, 0x22, + 0x22, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, 0xf0, 0x22, + 0x22, 0x22, 0x22, + + /* U+003E ">" */ + 0x3, 0x0, 0x0, 0x0, 0x0, 0xf, 0x80, 0x0, + 0x0, 0x0, 0x3, 0xde, 0x40, 0x0, 0x0, 0x0, + 0x6, 0xeb, 0x10, 0x0, 0x0, 0x0, 0x19, 0xf7, + 0x0, 0x0, 0x0, 0x0, 0x3c, 0xc0, 0x0, 0x0, + 0x0, 0x7, 0xf1, 0x0, 0x0, 0x4, 0xdd, 0x30, + 0x0, 0x1, 0xaf, 0x70, 0x0, 0x0, 0x7f, 0xb2, + 0x0, 0x0, 0xd, 0xe5, 0x0, 0x0, 0x0, 0x9, + 0x10, 0x0, 0x0, 0x0, + + /* U+003F "?" */ + 0x0, 0x4b, 0xee, 0x91, 0x0, 0x5f, 0x72, 0x3c, + 0xd0, 0xe, 0x70, 0x0, 0x1f, 0x51, 0x91, 0x0, + 0x0, 0xe7, 0x0, 0x0, 0x0, 0x1f, 0x40, 0x0, + 0x0, 0x1c, 0xc0, 0x0, 0x0, 0x1d, 0xb0, 0x0, + 0x0, 0xb, 0xa0, 0x0, 0x0, 0x0, 0xf2, 0x0, + 0x0, 0x0, 0x1b, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2a, 0x20, 0x0, 0x0, 0x4, + 0xf3, 0x0, 0x0, + + /* U+0040 "@" */ + 0x0, 0x0, 0x17, 0xcf, 0xfd, 0x92, 0x0, 0x0, + 0x0, 0x5e, 0xa4, 0x11, 0x38, 0xf5, 0x0, 0x0, + 0x4e, 0x30, 0x0, 0x0, 0x3, 0xf3, 0x0, 0xe, + 0x30, 0x8, 0xed, 0x8b, 0x7, 0xb0, 0x7, 0xa0, + 0xc, 0x91, 0x2f, 0x90, 0x1f, 0x10, 0xc5, 0x5, + 0xd0, 0x0, 0xb6, 0x0, 0xd3, 0xf, 0x10, 0xa7, + 0x0, 0xb, 0x40, 0xc, 0x30, 0xf1, 0xd, 0x50, + 0x0, 0xe3, 0x0, 0xe1, 0xf, 0x20, 0xc5, 0x0, + 0x5f, 0x10, 0x3c, 0x0, 0xb6, 0x7, 0xa0, 0x3a, + 0xd3, 0x2c, 0x30, 0x5, 0xc0, 0x9, 0xeb, 0x15, + 0xec, 0x40, 0x0, 0xc, 0x80, 0x0, 0x0, 0x0, + 0x2, 0x0, 0x0, 0x1c, 0xc5, 0x10, 0x1, 0x49, + 0xb2, 0x0, 0x0, 0x5, 0xbe, 0xff, 0xd9, 0x30, + 0x0, + + /* U+0041 "A" */ + 0x0, 0x0, 0x4f, 0x80, 0x0, 0x0, 0x0, 0x0, + 0xad, 0xe0, 0x0, 0x0, 0x0, 0x0, 0xf3, 0xe4, + 0x0, 0x0, 0x0, 0x6, 0xd0, 0x9a, 0x0, 0x0, + 0x0, 0xc, 0x80, 0x3f, 0x10, 0x0, 0x0, 0x2f, + 0x20, 0xe, 0x60, 0x0, 0x0, 0x8d, 0x0, 0x8, + 0xc0, 0x0, 0x0, 0xe7, 0x0, 0x3, 0xf3, 0x0, + 0x4, 0xff, 0xff, 0xff, 0xf9, 0x0, 0xa, 0xc3, + 0x33, 0x33, 0x8e, 0x0, 0xf, 0x50, 0x0, 0x0, + 0x1f, 0x50, 0x6e, 0x0, 0x0, 0x0, 0xa, 0xb0, + 0xc8, 0x0, 0x0, 0x0, 0x4, 0xf2, + + /* U+0042 "B" */ + 0xbf, 0xff, 0xfe, 0x91, 0x0, 0xba, 0x44, 0x45, + 0xbe, 0x10, 0xb8, 0x0, 0x0, 0xd, 0x80, 0xb8, + 0x0, 0x0, 0xa, 0xb0, 0xb8, 0x0, 0x0, 0xd, + 0x80, 0xb8, 0x0, 0x2, 0xad, 0x10, 0xbf, 0xff, + 0xff, 0xd3, 0x0, 0xb9, 0x33, 0x34, 0x8e, 0x50, + 0xb8, 0x0, 0x0, 0x6, 0xf0, 0xb8, 0x0, 0x0, + 0x1, 0xf3, 0xb8, 0x0, 0x0, 0x5, 0xf1, 0xb9, + 0x22, 0x23, 0x6e, 0x90, 0xbf, 0xff, 0xff, 0xd6, + 0x0, + + /* U+0043 "C" */ + 0x0, 0x2, 0xae, 0xfd, 0x81, 0x0, 0x0, 0x3f, + 0xb4, 0x25, 0xed, 0x10, 0x1, 0xea, 0x0, 0x0, + 0x1e, 0xb0, 0x7, 0xe0, 0x0, 0x0, 0x5, 0xc1, + 0xc, 0x90, 0x0, 0x0, 0x0, 0x0, 0xf, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x1f, 0x40, 0x0, 0x0, + 0x0, 0x0, 0xf, 0x50, 0x0, 0x0, 0x0, 0x0, + 0xd, 0x80, 0x0, 0x0, 0x0, 0x71, 0x8, 0xe0, + 0x0, 0x0, 0x5, 0xf3, 0x1, 0xe9, 0x0, 0x0, + 0x1e, 0xc0, 0x0, 0x4f, 0xb5, 0x36, 0xee, 0x20, + 0x0, 0x1, 0x9d, 0xfe, 0x91, 0x0, + + /* U+0044 "D" */ + 0xbf, 0xff, 0xfe, 0xb4, 0x0, 0xb, 0xa3, 0x33, + 0x49, 0xf7, 0x0, 0xb9, 0x0, 0x0, 0x4, 0xf4, + 0xb, 0x90, 0x0, 0x0, 0x9, 0xc0, 0xb9, 0x0, + 0x0, 0x0, 0x4f, 0x1b, 0x90, 0x0, 0x0, 0x1, + 0xf3, 0xb9, 0x0, 0x0, 0x0, 0xf, 0x4b, 0x90, + 0x0, 0x0, 0x1, 0xf3, 0xb9, 0x0, 0x0, 0x0, + 0x3f, 0x1b, 0x90, 0x0, 0x0, 0x9, 0xc0, 0xb9, + 0x0, 0x0, 0x3, 0xf5, 0xb, 0xa3, 0x33, 0x49, + 0xf8, 0x0, 0xbf, 0xff, 0xfe, 0xb4, 0x0, 0x0, + + /* U+0045 "E" */ + 0xaf, 0xff, 0xff, 0xff, 0xf0, 0xab, 0x33, 0x33, + 0x33, 0x30, 0xaa, 0x0, 0x0, 0x0, 0x0, 0xaa, + 0x0, 0x0, 0x0, 0x0, 0xaa, 0x0, 0x0, 0x0, + 0x0, 0xaa, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, + 0xff, 0xff, 0x90, 0xab, 0x33, 0x33, 0x33, 0x10, + 0xaa, 0x0, 0x0, 0x0, 0x0, 0xaa, 0x0, 0x0, + 0x0, 0x0, 0xaa, 0x0, 0x0, 0x0, 0x0, 0xab, + 0x33, 0x33, 0x33, 0x31, 0xaf, 0xff, 0xff, 0xff, + 0xf5, + + /* U+0046 "F" */ + 0x9f, 0xff, 0xff, 0xff, 0x89, 0xb3, 0x33, 0x33, + 0x31, 0x9a, 0x0, 0x0, 0x0, 0x9, 0xa0, 0x0, + 0x0, 0x0, 0x9a, 0x0, 0x0, 0x0, 0x9, 0xa0, + 0x0, 0x0, 0x0, 0x9f, 0xff, 0xff, 0xfa, 0x9, + 0xb3, 0x33, 0x33, 0x10, 0x9a, 0x0, 0x0, 0x0, + 0x9, 0xa0, 0x0, 0x0, 0x0, 0x9a, 0x0, 0x0, + 0x0, 0x9, 0xa0, 0x0, 0x0, 0x0, 0x9a, 0x0, + 0x0, 0x0, 0x0, + + /* U+0047 "G" */ + 0x0, 0x1, 0x9e, 0xfe, 0xb5, 0x0, 0x0, 0x3, + 0xfc, 0x52, 0x39, 0xf9, 0x0, 0x0, 0xea, 0x0, + 0x0, 0x5, 0xf7, 0x0, 0x6f, 0x0, 0x0, 0x0, + 0x8, 0x80, 0xb, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0x50, 0x0, 0x1f, 0xff, 0xff, 0x0, 0xf7, 0x0, + 0x0, 0x22, 0x25, 0xf0, 0xb, 0xb0, 0x0, 0x0, + 0x0, 0x3f, 0x0, 0x6f, 0x20, 0x0, 0x0, 0x3, + 0xf0, 0x0, 0xdc, 0x0, 0x0, 0x0, 0x8f, 0x0, + 0x1, 0xdd, 0x62, 0x25, 0xcf, 0x50, 0x0, 0x0, + 0x6c, 0xff, 0xd9, 0x20, 0x0, + + /* U+0048 "H" */ + 0xaa, 0x0, 0x0, 0x0, 0x8c, 0xaa, 0x0, 0x0, + 0x0, 0x8c, 0xaa, 0x0, 0x0, 0x0, 0x8c, 0xaa, + 0x0, 0x0, 0x0, 0x8c, 0xaa, 0x0, 0x0, 0x0, + 0x8c, 0xaa, 0x0, 0x0, 0x0, 0x8c, 0xaf, 0xff, + 0xff, 0xff, 0xfc, 0xab, 0x33, 0x33, 0x33, 0x9c, + 0xaa, 0x0, 0x0, 0x0, 0x8c, 0xaa, 0x0, 0x0, + 0x0, 0x8c, 0xaa, 0x0, 0x0, 0x0, 0x8c, 0xaa, + 0x0, 0x0, 0x0, 0x8c, 0xaa, 0x0, 0x0, 0x0, + 0x8c, + + /* U+0049 "I" */ + 0x6e, 0x6e, 0x6e, 0x6e, 0x6e, 0x6e, 0x6e, 0x6e, + 0x6e, 0x6e, 0x6e, 0x6e, 0x6e, + + /* U+004A "J" */ + 0x0, 0x0, 0x3, 0xf2, 0x0, 0x0, 0x3, 0xf2, + 0x0, 0x0, 0x3, 0xf2, 0x0, 0x0, 0x3, 0xf2, + 0x0, 0x0, 0x3, 0xf2, 0x0, 0x0, 0x3, 0xf2, + 0x0, 0x0, 0x3, 0xf2, 0x0, 0x0, 0x3, 0xf2, + 0x0, 0x0, 0x3, 0xf1, 0x5c, 0x0, 0x3, 0xf1, + 0x5f, 0x10, 0x7, 0xf0, 0xe, 0xc5, 0x6f, 0x90, + 0x2, 0xcf, 0xe9, 0x0, + + /* U+004B "K" */ + 0xc8, 0x0, 0x0, 0x6, 0xf6, 0xc, 0x80, 0x0, + 0x5, 0xf7, 0x0, 0xc8, 0x0, 0x4, 0xf8, 0x0, + 0xc, 0x80, 0x3, 0xf9, 0x0, 0x0, 0xc8, 0x2, + 0xe9, 0x0, 0x0, 0xc, 0x81, 0xef, 0x0, 0x0, + 0x0, 0xc9, 0xdb, 0xc9, 0x0, 0x0, 0xc, 0xfc, + 0x2, 0xf4, 0x0, 0x0, 0xcc, 0x0, 0x7, 0xe1, + 0x0, 0xc, 0x80, 0x0, 0xd, 0xb0, 0x0, 0xc8, + 0x0, 0x0, 0x3f, 0x60, 0xc, 0x80, 0x0, 0x0, + 0x9f, 0x20, 0xc8, 0x0, 0x0, 0x0, 0xec, 0x0, + + /* U+004C "L" */ + 0xc8, 0x0, 0x0, 0x0, 0xc8, 0x0, 0x0, 0x0, + 0xc8, 0x0, 0x0, 0x0, 0xc8, 0x0, 0x0, 0x0, + 0xc8, 0x0, 0x0, 0x0, 0xc8, 0x0, 0x0, 0x0, + 0xc8, 0x0, 0x0, 0x0, 0xc8, 0x0, 0x0, 0x0, + 0xc8, 0x0, 0x0, 0x0, 0xc8, 0x0, 0x0, 0x0, + 0xc8, 0x0, 0x0, 0x0, 0xc9, 0x33, 0x33, 0x32, + 0xcf, 0xff, 0xff, 0xfc, + + /* U+004D "M" */ + 0xbf, 0x30, 0x0, 0x0, 0x1, 0xfd, 0xbf, 0x90, + 0x0, 0x0, 0x6, 0xfd, 0xbb, 0xe0, 0x0, 0x0, + 0xc, 0xbd, 0xb8, 0xd4, 0x0, 0x0, 0x2f, 0x6d, + 0xb8, 0x7a, 0x0, 0x0, 0x8a, 0x5d, 0xb8, 0x1f, + 0x10, 0x0, 0xe4, 0x5d, 0xb8, 0xb, 0x60, 0x3, + 0xe0, 0x5d, 0xb8, 0x5, 0xc0, 0x9, 0x80, 0x5d, + 0xb8, 0x0, 0xf2, 0xf, 0x20, 0x5d, 0xb8, 0x0, + 0x98, 0x5c, 0x0, 0x5d, 0xb8, 0x0, 0x4e, 0xb6, + 0x0, 0x5d, 0xb8, 0x0, 0xd, 0xf1, 0x0, 0x5d, + 0xb8, 0x0, 0x8, 0xa0, 0x0, 0x5d, + + /* U+004E "N" */ + 0xbf, 0x20, 0x0, 0x0, 0x8c, 0xbf, 0xb0, 0x0, + 0x0, 0x8c, 0xb9, 0xe4, 0x0, 0x0, 0x8c, 0xb9, + 0x5d, 0x0, 0x0, 0x8c, 0xb9, 0xb, 0x70, 0x0, + 0x8c, 0xb9, 0x2, 0xf2, 0x0, 0x8c, 0xb9, 0x0, + 0x8b, 0x0, 0x8c, 0xb9, 0x0, 0xe, 0x40, 0x8c, + 0xb9, 0x0, 0x5, 0xd0, 0x8c, 0xb9, 0x0, 0x0, + 0xc7, 0x8c, 0xb9, 0x0, 0x0, 0x3f, 0x9c, 0xb9, + 0x0, 0x0, 0x9, 0xfc, 0xb9, 0x0, 0x0, 0x1, + 0xec, + + /* U+004F "O" */ + 0x0, 0x1, 0x9d, 0xfe, 0xb4, 0x0, 0x0, 0x4, + 0xfb, 0x41, 0x39, 0xf8, 0x0, 0x1, 0xea, 0x0, + 0x0, 0x6, 0xf4, 0x0, 0x8e, 0x0, 0x0, 0x0, + 0xc, 0xc0, 0xd, 0x90, 0x0, 0x0, 0x0, 0x6f, + 0x10, 0xf5, 0x0, 0x0, 0x0, 0x2, 0xf5, 0x2f, + 0x30, 0x0, 0x0, 0x0, 0xf, 0x61, 0xf5, 0x0, + 0x0, 0x0, 0x1, 0xf5, 0xe, 0x80, 0x0, 0x0, + 0x0, 0x4f, 0x20, 0x9e, 0x0, 0x0, 0x0, 0xa, + 0xd0, 0x2, 0xfa, 0x0, 0x0, 0x5, 0xf6, 0x0, + 0x5, 0xfd, 0x63, 0x49, 0xfa, 0x0, 0x0, 0x3, + 0xae, 0xfe, 0xb5, 0x0, 0x0, + + /* U+0050 "P" */ + 0xaf, 0xff, 0xff, 0xd8, 0x0, 0xab, 0x33, 0x33, + 0x6d, 0xb0, 0xaa, 0x0, 0x0, 0x2, 0xf4, 0xaa, + 0x0, 0x0, 0x0, 0xe7, 0xaa, 0x0, 0x0, 0x1, + 0xf5, 0xaa, 0x0, 0x0, 0x3c, 0xd0, 0xaf, 0xff, + 0xff, 0xfb, 0x20, 0xab, 0x33, 0x32, 0x0, 0x0, + 0xaa, 0x0, 0x0, 0x0, 0x0, 0xaa, 0x0, 0x0, + 0x0, 0x0, 0xaa, 0x0, 0x0, 0x0, 0x0, 0xaa, + 0x0, 0x0, 0x0, 0x0, 0xaa, 0x0, 0x0, 0x0, + 0x0, + + /* U+0051 "Q" */ + 0x0, 0x2, 0xae, 0xfe, 0xa3, 0x0, 0x0, 0x5, + 0xfb, 0x41, 0x4b, 0xf6, 0x0, 0x2, 0xf8, 0x0, + 0x0, 0x9, 0xf2, 0x0, 0xad, 0x0, 0x0, 0x0, + 0xe, 0xa0, 0xf, 0x70, 0x0, 0x0, 0x0, 0x8f, + 0x2, 0xf3, 0x0, 0x0, 0x0, 0x4, 0xf2, 0x4f, + 0x20, 0x0, 0x0, 0x0, 0x2f, 0x43, 0xf3, 0x0, + 0x0, 0x0, 0x3, 0xf2, 0xf, 0x60, 0x0, 0x0, + 0x0, 0x6f, 0x0, 0xbc, 0x0, 0x0, 0x0, 0xb, + 0xa0, 0x3, 0xf7, 0x0, 0x0, 0x6, 0xf3, 0x0, + 0x7, 0xfb, 0x53, 0x4a, 0xf8, 0x0, 0x0, 0x4, + 0xbe, 0xff, 0xc5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xea, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0xf9, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3, 0x10, 0x0, + + /* U+0052 "R" */ + 0xaf, 0xff, 0xff, 0xeb, 0x30, 0xa, 0xb2, 0x22, + 0x24, 0x9f, 0x30, 0xaa, 0x0, 0x0, 0x0, 0xab, + 0xa, 0xa0, 0x0, 0x0, 0x6, 0xe0, 0xaa, 0x0, + 0x0, 0x0, 0x9d, 0xa, 0xa0, 0x0, 0x1, 0x7f, + 0x70, 0xaf, 0xff, 0xff, 0xff, 0x90, 0xa, 0xb3, + 0x33, 0xdb, 0x0, 0x0, 0xaa, 0x0, 0x3, 0xf5, + 0x0, 0xa, 0xa0, 0x0, 0x7, 0xf2, 0x0, 0xaa, + 0x0, 0x0, 0xb, 0xd1, 0xa, 0xa0, 0x0, 0x0, + 0x1e, 0xb0, 0xaa, 0x0, 0x0, 0x0, 0x4f, 0x70, + + /* U+0053 "S" */ + 0x0, 0x2a, 0xef, 0xd9, 0x20, 0x0, 0x2f, 0xa4, + 0x35, 0xce, 0x20, 0x9, 0xc0, 0x0, 0x0, 0xdb, + 0x0, 0xca, 0x0, 0x0, 0x5, 0x70, 0x8, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xfc, 0x73, 0x0, + 0x0, 0x0, 0x3, 0x8d, 0xfe, 0x70, 0x0, 0x0, + 0x0, 0x1, 0x7f, 0xa0, 0x1, 0x0, 0x0, 0x0, + 0x4f, 0x31, 0xf4, 0x0, 0x0, 0x1, 0xf5, 0xc, + 0xc0, 0x0, 0x0, 0x5f, 0x10, 0x2e, 0xc5, 0x23, + 0x7f, 0x80, 0x0, 0x18, 0xdf, 0xec, 0x50, 0x0, + + /* U+0054 "T" */ + 0x9f, 0xff, 0xff, 0xff, 0xff, 0x13, 0x33, 0x8d, + 0x33, 0x33, 0x0, 0x0, 0x7d, 0x0, 0x0, 0x0, + 0x0, 0x7d, 0x0, 0x0, 0x0, 0x0, 0x7d, 0x0, + 0x0, 0x0, 0x0, 0x7d, 0x0, 0x0, 0x0, 0x0, + 0x7d, 0x0, 0x0, 0x0, 0x0, 0x7d, 0x0, 0x0, + 0x0, 0x0, 0x7d, 0x0, 0x0, 0x0, 0x0, 0x7d, + 0x0, 0x0, 0x0, 0x0, 0x7d, 0x0, 0x0, 0x0, + 0x0, 0x7d, 0x0, 0x0, 0x0, 0x0, 0x7d, 0x0, + 0x0, + + /* U+0055 "U" */ + 0xaa, 0x0, 0x0, 0x0, 0x7d, 0xaa, 0x0, 0x0, + 0x0, 0x7d, 0xaa, 0x0, 0x0, 0x0, 0x7d, 0xaa, + 0x0, 0x0, 0x0, 0x7d, 0xaa, 0x0, 0x0, 0x0, + 0x7d, 0xaa, 0x0, 0x0, 0x0, 0x7d, 0xaa, 0x0, + 0x0, 0x0, 0x7d, 0xaa, 0x0, 0x0, 0x0, 0x7d, + 0x9b, 0x0, 0x0, 0x0, 0x8c, 0x6e, 0x0, 0x0, + 0x0, 0xba, 0x2f, 0x50, 0x0, 0x3, 0xf4, 0x8, + 0xf8, 0x33, 0x7e, 0xb0, 0x0, 0x6c, 0xff, 0xd7, + 0x0, + + /* U+0056 "V" */ + 0x8d, 0x0, 0x0, 0x0, 0x3, 0xf2, 0x2f, 0x30, + 0x0, 0x0, 0x9, 0xc0, 0xc, 0x80, 0x0, 0x0, + 0xe, 0x60, 0x6, 0xe0, 0x0, 0x0, 0x5f, 0x10, + 0x1, 0xf4, 0x0, 0x0, 0xaa, 0x0, 0x0, 0xa9, + 0x0, 0x1, 0xf4, 0x0, 0x0, 0x4f, 0x0, 0x6, + 0xe0, 0x0, 0x0, 0xe, 0x50, 0xc, 0x80, 0x0, + 0x0, 0x8, 0xb0, 0x1f, 0x20, 0x0, 0x0, 0x2, + 0xf1, 0x7c, 0x0, 0x0, 0x0, 0x0, 0xc6, 0xd6, + 0x0, 0x0, 0x0, 0x0, 0x6e, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x1f, 0xa0, 0x0, 0x0, + + /* U+0057 "W" */ + 0x9b, 0x0, 0x0, 0xc, 0xe0, 0x0, 0x0, 0xaa, + 0x5f, 0x0, 0x0, 0x1f, 0xf2, 0x0, 0x0, 0xe6, + 0x1f, 0x30, 0x0, 0x5d, 0xb6, 0x0, 0x2, 0xf2, + 0xd, 0x60, 0x0, 0x98, 0x7a, 0x0, 0x6, 0xd0, + 0x9, 0xa0, 0x0, 0xd3, 0x2e, 0x0, 0xa, 0x90, + 0x5, 0xe0, 0x2, 0xf0, 0xe, 0x20, 0xe, 0x50, + 0x1, 0xf1, 0x6, 0xa0, 0xa, 0x60, 0x2f, 0x10, + 0x0, 0xd5, 0xb, 0x60, 0x6, 0xa0, 0x6c, 0x0, + 0x0, 0x99, 0xf, 0x10, 0x1, 0xe0, 0x98, 0x0, + 0x0, 0x5d, 0x3d, 0x0, 0x0, 0xd3, 0xd4, 0x0, + 0x0, 0x1f, 0x98, 0x0, 0x0, 0x99, 0xf0, 0x0, + 0x0, 0xc, 0xf4, 0x0, 0x0, 0x5f, 0xb0, 0x0, + 0x0, 0x8, 0xf0, 0x0, 0x0, 0x1f, 0x70, 0x0, + + /* U+0058 "X" */ + 0x1e, 0x80, 0x0, 0x0, 0x2f, 0x60, 0x4, 0xf3, + 0x0, 0x0, 0xbb, 0x0, 0x0, 0x9d, 0x0, 0x6, + 0xe1, 0x0, 0x0, 0xe, 0x70, 0x1e, 0x50, 0x0, + 0x0, 0x4, 0xf2, 0xaa, 0x0, 0x0, 0x0, 0x0, + 0x9e, 0xe1, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0xd8, 0xf4, 0x0, 0x0, + 0x0, 0xa, 0xb0, 0x6e, 0x10, 0x0, 0x0, 0x5f, + 0x20, 0xc, 0xb0, 0x0, 0x2, 0xf6, 0x0, 0x2, + 0xf6, 0x0, 0xc, 0xb0, 0x0, 0x0, 0x7f, 0x20, + 0x8f, 0x10, 0x0, 0x0, 0xd, 0xc0, + + /* U+0059 "Y" */ + 0x9d, 0x0, 0x0, 0x0, 0xc, 0xc0, 0xe, 0x70, + 0x0, 0x0, 0x6f, 0x20, 0x5, 0xf2, 0x0, 0x1, + 0xe7, 0x0, 0x0, 0xbb, 0x0, 0xa, 0xc0, 0x0, + 0x0, 0x1f, 0x50, 0x4f, 0x20, 0x0, 0x0, 0x6, + 0xe1, 0xd8, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xd0, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x1f, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x1f, 0x20, 0x0, 0x0, 0x0, 0x0, 0x1f, 0x20, + 0x0, 0x0, 0x0, 0x0, 0x1f, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x1f, 0x20, 0x0, 0x0, + + /* U+005A "Z" */ + 0xf, 0xff, 0xff, 0xff, 0xfa, 0x3, 0x33, 0x33, + 0x37, 0xf3, 0x0, 0x0, 0x0, 0x1e, 0x80, 0x0, + 0x0, 0x0, 0xac, 0x0, 0x0, 0x0, 0x5, 0xf2, + 0x0, 0x0, 0x0, 0x1e, 0x60, 0x0, 0x0, 0x0, + 0xbb, 0x0, 0x0, 0x0, 0x6, 0xe1, 0x0, 0x0, + 0x0, 0x2f, 0x50, 0x0, 0x0, 0x0, 0xca, 0x0, + 0x0, 0x0, 0x7, 0xe0, 0x0, 0x0, 0x0, 0x2f, + 0x62, 0x22, 0x22, 0x22, 0xaf, 0xff, 0xff, 0xff, + 0xfe, + + /* U+005B "[" */ + 0xce, 0xe5, 0xd3, 0x0, 0xd3, 0x0, 0xd3, 0x0, + 0xd3, 0x0, 0xd3, 0x0, 0xd3, 0x0, 0xd3, 0x0, + 0xd3, 0x0, 0xd3, 0x0, 0xd3, 0x0, 0xd3, 0x0, + 0xd3, 0x0, 0xd3, 0x0, 0xd3, 0x0, 0xce, 0xe5, + + /* U+005C "\\" */ + 0xd3, 0x0, 0x9, 0x70, 0x0, 0x4b, 0x0, 0x0, + 0xf0, 0x0, 0xc, 0x40, 0x0, 0x78, 0x0, 0x3, + 0xd0, 0x0, 0xe, 0x10, 0x0, 0xa5, 0x0, 0x6, + 0x90, 0x0, 0x2e, 0x0, 0x0, 0xd2, 0x0, 0x9, + 0x60, + + /* U+005D "]" */ + 0xae, 0xe7, 0x0, 0x97, 0x0, 0x97, 0x0, 0x97, + 0x0, 0x97, 0x0, 0x97, 0x0, 0x97, 0x0, 0x97, + 0x0, 0x97, 0x0, 0x97, 0x0, 0x97, 0x0, 0x97, + 0x0, 0x97, 0x0, 0x97, 0x0, 0x97, 0xbe, 0xf7, + + /* U+005E "^" */ + 0x0, 0xb, 0xa0, 0x0, 0x0, 0x2f, 0xe2, 0x0, + 0x0, 0x99, 0x88, 0x0, 0x0, 0xf2, 0x2e, 0x0, + 0x7, 0xc0, 0xb, 0x60, 0xd, 0x60, 0x5, 0xd0, + 0x4f, 0x0, 0x0, 0xe4, + + /* U+005F "_" */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + + /* U+0060 "`" */ + 0xd, 0xb0, 0x3, 0xf2, 0x0, 0x78, + + /* U+0061 "a" */ + 0x0, 0x7d, 0xfe, 0xa1, 0x0, 0x8e, 0x51, 0x2b, + 0xb0, 0xd, 0x50, 0x0, 0x2f, 0x10, 0x0, 0x0, + 0x1, 0xf3, 0x0, 0x16, 0x9b, 0xef, 0x30, 0x6f, + 0xc9, 0x72, 0xf3, 0x1f, 0x50, 0x0, 0x1f, 0x34, + 0xf0, 0x0, 0x6, 0xf3, 0x1f, 0x70, 0x15, 0xdf, + 0x40, 0x4c, 0xfe, 0xa2, 0xb7, + + /* U+0062 "b" */ + 0xe5, 0x0, 0x0, 0x0, 0xe5, 0x0, 0x0, 0x0, + 0xe5, 0x0, 0x0, 0x0, 0xe5, 0x8e, 0xe9, 0x0, + 0xed, 0x92, 0x3c, 0xa0, 0xec, 0x0, 0x1, 0xf2, + 0xe7, 0x0, 0x0, 0xb7, 0xe5, 0x0, 0x0, 0x99, + 0xe5, 0x0, 0x0, 0x9a, 0xe7, 0x0, 0x0, 0xa8, + 0xea, 0x0, 0x0, 0xe4, 0xed, 0x50, 0x9, 0xd0, + 0xe6, 0x9d, 0xfb, 0x20, + + /* U+0063 "c" */ + 0x0, 0x4d, 0xfd, 0x70, 0x0, 0x3f, 0x62, 0x5e, + 0x80, 0xc, 0x70, 0x0, 0x5e, 0x1, 0xf2, 0x0, + 0x0, 0x0, 0x4f, 0x0, 0x0, 0x0, 0x4, 0xf0, + 0x0, 0x0, 0x0, 0x2f, 0x20, 0x0, 0x8, 0x10, + 0xd8, 0x0, 0x4, 0xf0, 0x5, 0xf7, 0x35, 0xe8, + 0x0, 0x6, 0xdf, 0xd7, 0x0, + + /* U+0064 "d" */ + 0x0, 0x0, 0x0, 0x1f, 0x20, 0x0, 0x0, 0x1, + 0xf2, 0x0, 0x0, 0x0, 0x1f, 0x20, 0x7, 0xef, + 0xb2, 0xf2, 0x6, 0xf5, 0x26, 0xcf, 0x20, 0xe5, + 0x0, 0x7, 0xf2, 0x3f, 0x0, 0x0, 0x2f, 0x25, + 0xe0, 0x0, 0x1, 0xf2, 0x5e, 0x0, 0x0, 0x1f, + 0x22, 0xf0, 0x0, 0x3, 0xf2, 0xd, 0x50, 0x0, + 0x7f, 0x20, 0x5e, 0x52, 0x6c, 0xf2, 0x0, 0x6d, + 0xfa, 0x2f, 0x20, + + /* U+0065 "e" */ + 0x0, 0x2b, 0xfe, 0x90, 0x0, 0x2e, 0x83, 0x3c, + 0xa0, 0xb, 0x80, 0x0, 0x1e, 0x31, 0xf2, 0x0, + 0x0, 0xb8, 0x4f, 0xff, 0xff, 0xff, 0xb4, 0xf2, + 0x22, 0x22, 0x21, 0x2f, 0x30, 0x0, 0x2, 0x0, + 0xd8, 0x0, 0x1, 0xe7, 0x4, 0xf8, 0x34, 0xce, + 0x10, 0x4, 0xcf, 0xea, 0x20, + + /* U+0066 "f" */ + 0x2, 0xcf, 0xe1, 0x8, 0xd1, 0x20, 0x9, 0xa0, + 0x0, 0xff, 0xff, 0x70, 0x1a, 0xa1, 0x0, 0x9, + 0xa0, 0x0, 0x9, 0xa0, 0x0, 0x9, 0xa0, 0x0, + 0x9, 0xa0, 0x0, 0x9, 0xa0, 0x0, 0x9, 0xa0, + 0x0, 0x9, 0xa0, 0x0, 0x9, 0xa0, 0x0, + + /* U+0067 "g" */ + 0x0, 0x4c, 0xfb, 0x2f, 0x50, 0x4e, 0x51, 0x6d, + 0xf5, 0xc, 0x40, 0x0, 0x5f, 0x52, 0xf0, 0x0, + 0x0, 0xf5, 0x5d, 0x0, 0x0, 0xf, 0x56, 0xd0, + 0x0, 0x0, 0xf5, 0x3f, 0x0, 0x0, 0xf, 0x50, + 0xf4, 0x0, 0x5, 0xf5, 0x8, 0xe3, 0x14, 0xcf, + 0x40, 0x9, 0xef, 0xb2, 0xf3, 0x0, 0x0, 0x0, + 0x2f, 0x10, 0x95, 0x21, 0x4d, 0xa0, 0x3, 0xbf, + 0xfd, 0x80, 0x0, + + /* U+0068 "h" */ + 0xe6, 0x0, 0x0, 0x0, 0xe6, 0x0, 0x0, 0x0, + 0xe6, 0x0, 0x0, 0x0, 0xe6, 0x7e, 0xfb, 0x20, + 0xec, 0xa3, 0x3c, 0xc0, 0xec, 0x0, 0x3, 0xf1, + 0xe7, 0x0, 0x0, 0xf3, 0xe6, 0x0, 0x0, 0xf3, + 0xe6, 0x0, 0x0, 0xf3, 0xe6, 0x0, 0x0, 0xf3, + 0xe6, 0x0, 0x0, 0xf3, 0xe6, 0x0, 0x0, 0xf3, + 0xe6, 0x0, 0x0, 0xf3, + + /* U+0069 "i" */ + 0xd6, 0x94, 0x0, 0xd6, 0xd6, 0xd6, 0xd6, 0xd6, + 0xd6, 0xd6, 0xd6, 0xd6, 0xd6, + + /* U+006A "j" */ + 0x0, 0xd6, 0x0, 0x94, 0x0, 0x0, 0x0, 0xd6, + 0x0, 0xd6, 0x0, 0xd6, 0x0, 0xd6, 0x0, 0xd6, + 0x0, 0xd6, 0x0, 0xd6, 0x0, 0xd6, 0x0, 0xd6, + 0x0, 0xd6, 0x0, 0xd6, 0x1, 0xf5, 0xbf, 0xb0, + + /* U+006B "k" */ + 0xe6, 0x0, 0x0, 0x0, 0xe6, 0x0, 0x0, 0x0, + 0xe6, 0x0, 0x0, 0x0, 0xe6, 0x0, 0x3f, 0x90, + 0xe6, 0x1, 0xea, 0x0, 0xe6, 0xc, 0xb0, 0x0, + 0xe6, 0xbd, 0x0, 0x0, 0xed, 0xef, 0x10, 0x0, + 0xee, 0x2a, 0xa0, 0x0, 0xe6, 0x2, 0xf4, 0x0, + 0xe6, 0x0, 0x8d, 0x0, 0xe6, 0x0, 0x1e, 0x70, + 0xe6, 0x0, 0x6, 0xf2, + + /* U+006C "l" */ + 0xe5, 0xe5, 0xe5, 0xe5, 0xe5, 0xe5, 0xe5, 0xe5, + 0xe5, 0xe5, 0xe5, 0xe5, 0xe5, + + /* U+006D "m" */ + 0xe5, 0x8f, 0xe7, 0x5, 0xee, 0xa0, 0xe, 0xc7, + 0x15, 0xf7, 0xa2, 0x2d, 0x90, 0xea, 0x0, 0xb, + 0xe0, 0x0, 0x6d, 0xe, 0x60, 0x0, 0x9b, 0x0, + 0x4, 0xf0, 0xe5, 0x0, 0x9, 0xa0, 0x0, 0x4f, + 0xe, 0x50, 0x0, 0x9a, 0x0, 0x4, 0xf0, 0xe5, + 0x0, 0x9, 0xa0, 0x0, 0x4f, 0xe, 0x50, 0x0, + 0x9a, 0x0, 0x4, 0xf0, 0xe5, 0x0, 0x9, 0xa0, + 0x0, 0x4f, 0xe, 0x50, 0x0, 0x9a, 0x0, 0x4, + 0xf0, + + /* U+006E "n" */ + 0xe5, 0x7e, 0xfb, 0x20, 0xec, 0xa3, 0x2c, 0xc0, + 0xec, 0x0, 0x2, 0xf1, 0xe6, 0x0, 0x0, 0xf3, + 0xe5, 0x0, 0x0, 0xf4, 0xe5, 0x0, 0x0, 0xf4, + 0xe5, 0x0, 0x0, 0xf4, 0xe5, 0x0, 0x0, 0xf4, + 0xe5, 0x0, 0x0, 0xf4, 0xe5, 0x0, 0x0, 0xf4, + + /* U+006F "o" */ + 0x0, 0x4c, 0xfe, 0x90, 0x0, 0x5e, 0x51, 0x4e, + 0xb0, 0xd, 0x60, 0x0, 0x3f, 0x43, 0xf0, 0x0, + 0x0, 0xd9, 0x5e, 0x0, 0x0, 0xa, 0xb5, 0xe0, + 0x0, 0x0, 0x9b, 0x2f, 0x0, 0x0, 0xb, 0x90, + 0xe6, 0x0, 0x1, 0xf4, 0x5, 0xf5, 0x13, 0xcc, + 0x0, 0x6, 0xdf, 0xe9, 0x10, + + /* U+0070 "p" */ + 0xe6, 0x9e, 0xe9, 0x0, 0xee, 0x60, 0x1b, 0x90, + 0xea, 0x0, 0x1, 0xf1, 0xe6, 0x0, 0x0, 0xb6, + 0xe5, 0x0, 0x0, 0x99, 0xe5, 0x0, 0x0, 0x99, + 0xe7, 0x0, 0x0, 0xb7, 0xeb, 0x0, 0x1, 0xf3, + 0xec, 0x82, 0x3c, 0xb0, 0xe5, 0x8e, 0xfa, 0x0, + 0xe5, 0x0, 0x0, 0x0, 0xe5, 0x0, 0x0, 0x0, + 0xe5, 0x0, 0x0, 0x0, + + /* U+0071 "q" */ + 0x0, 0x7e, 0xfa, 0x2f, 0x20, 0x7e, 0x52, 0x6c, + 0xf2, 0xe, 0x50, 0x0, 0x7f, 0x23, 0xf0, 0x0, + 0x3, 0xf2, 0x5d, 0x0, 0x0, 0x1f, 0x25, 0xd0, + 0x0, 0x1, 0xf2, 0x2f, 0x0, 0x0, 0x3f, 0x20, + 0xd5, 0x0, 0x8, 0xf2, 0x5, 0xe5, 0x26, 0xcf, + 0x20, 0x6, 0xef, 0xa3, 0xf2, 0x0, 0x0, 0x0, + 0x1f, 0x20, 0x0, 0x0, 0x1, 0xf2, 0x0, 0x0, + 0x0, 0x1f, 0x20, + + /* U+0072 "r" */ + 0xe6, 0xaf, 0x9e, 0xd7, 0x22, 0xeb, 0x0, 0xe, + 0x60, 0x0, 0xe5, 0x0, 0xe, 0x50, 0x0, 0xe5, + 0x0, 0xe, 0x50, 0x0, 0xe5, 0x0, 0xe, 0x50, + 0x0, + + /* U+0073 "s" */ + 0x1, 0xae, 0xfc, 0x40, 0xb, 0xb3, 0x2a, 0xf2, + 0xf, 0x40, 0x0, 0xa2, 0xd, 0xa0, 0x0, 0x0, + 0x3, 0xde, 0xa6, 0x0, 0x0, 0x4, 0x8d, 0xe2, + 0x1, 0x0, 0x0, 0xba, 0x3f, 0x10, 0x0, 0x8b, + 0xc, 0xc3, 0x14, 0xe6, 0x1, 0x9e, 0xfd, 0x60, + + /* U+0074 "t" */ + 0x0, 0x10, 0x0, 0x7a, 0x0, 0x9, 0xa0, 0x0, + 0x9a, 0x0, 0xcf, 0xff, 0x40, 0xaa, 0x10, 0x9, + 0xa0, 0x0, 0x9a, 0x0, 0x9, 0xa0, 0x0, 0x9a, + 0x0, 0x9, 0xa0, 0x0, 0x9a, 0x0, 0x8, 0xc0, + 0x0, 0x2d, 0xe5, + + /* U+0075 "u" */ + 0xf4, 0x0, 0x0, 0xf2, 0xf4, 0x0, 0x0, 0xf2, + 0xf4, 0x0, 0x0, 0xf2, 0xf4, 0x0, 0x0, 0xf2, + 0xf4, 0x0, 0x0, 0xf2, 0xf4, 0x0, 0x0, 0xf2, + 0xe5, 0x0, 0x2, 0xf2, 0xd7, 0x0, 0x7, 0xf2, + 0x8e, 0x42, 0x7c, 0xf2, 0x9, 0xef, 0xa1, 0xf2, + + /* U+0076 "v" */ + 0x9c, 0x0, 0x0, 0x4f, 0x14, 0xf1, 0x0, 0x9, + 0xb0, 0xe, 0x50, 0x0, 0xe6, 0x0, 0x9a, 0x0, + 0x3f, 0x0, 0x4, 0xe0, 0x8, 0xb0, 0x0, 0xe, + 0x30, 0xd5, 0x0, 0x0, 0xa8, 0x2f, 0x0, 0x0, + 0x4, 0xd8, 0xa0, 0x0, 0x0, 0xf, 0xe4, 0x0, + 0x0, 0x0, 0xae, 0x0, 0x0, + + /* U+0077 "w" */ + 0xc7, 0x0, 0xa, 0xd0, 0x0, 0x4f, 0x8, 0xb0, + 0x0, 0xee, 0x0, 0x8, 0xa0, 0x3e, 0x0, 0x2d, + 0xb4, 0x0, 0xd6, 0x0, 0xf3, 0x5, 0x97, 0x70, + 0x1f, 0x10, 0xb, 0x70, 0x96, 0x4b, 0x5, 0xc0, + 0x0, 0x6b, 0xc, 0x21, 0xe0, 0x98, 0x0, 0x2, + 0xf0, 0xe0, 0xd, 0x2d, 0x30, 0x0, 0xd, 0x7b, + 0x0, 0xa7, 0xe0, 0x0, 0x0, 0x9e, 0x80, 0x7, + 0xea, 0x0, 0x0, 0x4, 0xf4, 0x0, 0x3f, 0x50, + 0x0, + + /* U+0078 "x" */ + 0x2f, 0x40, 0x0, 0xac, 0x0, 0x8d, 0x0, 0x4f, + 0x20, 0x0, 0xd6, 0xd, 0x70, 0x0, 0x3, 0xe7, + 0xc0, 0x0, 0x0, 0x9, 0xf3, 0x0, 0x0, 0x0, + 0xbf, 0x40, 0x0, 0x0, 0x6d, 0x4e, 0x10, 0x0, + 0x2f, 0x30, 0xaa, 0x0, 0xc, 0x90, 0x2, 0xf4, + 0x7, 0xe1, 0x0, 0x8, 0xe1, + + /* U+0079 "y" */ + 0x8d, 0x0, 0x0, 0x3f, 0x12, 0xf2, 0x0, 0x8, + 0xc0, 0xd, 0x70, 0x0, 0xd6, 0x0, 0x7c, 0x0, + 0x3f, 0x0, 0x1, 0xf2, 0x8, 0xa0, 0x0, 0xb, + 0x70, 0xe4, 0x0, 0x0, 0x5c, 0x3e, 0x0, 0x0, + 0x0, 0xfa, 0x90, 0x0, 0x0, 0xa, 0xf3, 0x0, + 0x0, 0x0, 0x6d, 0x0, 0x0, 0x0, 0xc, 0x70, + 0x0, 0x0, 0x6, 0xf1, 0x0, 0x0, 0x3e, 0xe5, + 0x0, 0x0, 0x0, + + /* U+007A "z" */ + 0x4f, 0xff, 0xff, 0xfd, 0x0, 0x22, 0x22, 0x5f, + 0x40, 0x0, 0x0, 0xd, 0x90, 0x0, 0x0, 0x9, + 0xd0, 0x0, 0x0, 0x4, 0xf3, 0x0, 0x0, 0x1, + 0xe7, 0x0, 0x0, 0x0, 0xbc, 0x0, 0x0, 0x0, + 0x6f, 0x20, 0x0, 0x0, 0x2f, 0x71, 0x11, 0x11, + 0xa, 0xff, 0xff, 0xff, 0xf1, + + /* U+007B "{" */ + 0x0, 0x9, 0xd3, 0x0, 0x8a, 0x0, 0x0, 0xb5, + 0x0, 0x0, 0xb4, 0x0, 0x0, 0xb4, 0x0, 0x0, + 0xb4, 0x0, 0x0, 0xc4, 0x0, 0x3, 0xe0, 0x0, + 0x8f, 0x40, 0x0, 0x3, 0xe1, 0x0, 0x0, 0xc4, + 0x0, 0x0, 0xb4, 0x0, 0x0, 0xb4, 0x0, 0x0, + 0xb4, 0x0, 0x0, 0x9a, 0x0, 0x0, 0x1a, 0xd3, + + /* U+007C "|" */ + 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, + 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, + + /* U+007D "}" */ + 0x7c, 0x50, 0x0, 0x2, 0xe2, 0x0, 0x0, 0xa5, + 0x0, 0x0, 0xa6, 0x0, 0x0, 0xa6, 0x0, 0x0, + 0xa6, 0x0, 0x0, 0x96, 0x0, 0x0, 0x5c, 0x10, + 0x0, 0xa, 0xf2, 0x0, 0x6b, 0x10, 0x0, 0xa6, + 0x0, 0x0, 0xa6, 0x0, 0x0, 0xa6, 0x0, 0x0, + 0xa6, 0x0, 0x2, 0xe4, 0x0, 0x7d, 0x70, 0x0, + + /* U+007E "~" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1a, 0xff, 0xc6, + 0x11, 0x72, 0x49, 0x44, 0x9e, 0xff, 0xd1, 0x0, + 0x0, 0x0, 0x22, 0x0, + + /* U+503C "值" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x87, 0x0, 0x0, 0xe3, 0x0, 0x0, 0x0, + 0xe, 0x42, 0x22, 0x2e, 0x52, 0x22, 0x10, 0x4, + 0xd1, 0xbb, 0xbb, 0xfc, 0xbb, 0xb7, 0x0, 0xb7, + 0x0, 0x0, 0xe, 0x30, 0x0, 0x0, 0x3f, 0x40, + 0x5f, 0xdd, 0xdd, 0xde, 0xa0, 0xc, 0xf4, 0x5, + 0xa0, 0x0, 0x0, 0x6a, 0x5, 0xed, 0x40, 0x5e, + 0xdd, 0xdd, 0xde, 0xa0, 0x44, 0xc4, 0x5, 0xa0, + 0x0, 0x0, 0x6a, 0x0, 0xc, 0x40, 0x5e, 0xbb, + 0xbb, 0xbd, 0xa0, 0x0, 0xc4, 0x5, 0xa1, 0x11, + 0x11, 0x6a, 0x0, 0xc, 0x40, 0x5a, 0x11, 0x11, + 0x16, 0xa0, 0x0, 0xc4, 0x5, 0xec, 0xcc, 0xcc, + 0xda, 0x0, 0xc, 0x40, 0x5a, 0x0, 0x0, 0x6, + 0xa0, 0x0, 0xc4, 0xae, 0xfe, 0xee, 0xee, 0xef, + 0xd0, + + /* U+50CF "像" */ + 0x0, 0x1, 0xb0, 0x4, 0xc0, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xa0, 0x1e, 0xec, 0xcc, 0x50, 0x0, + 0x0, 0xb, 0x32, 0xd6, 0x0, 0x4d, 0x10, 0x0, + 0x0, 0x2d, 0x1e, 0xeb, 0xbb, 0xfd, 0xbb, 0x30, + 0x0, 0x9c, 0x3, 0xe1, 0x17, 0x81, 0x1c, 0x40, + 0x1, 0xfc, 0x1, 0xe0, 0xa, 0x50, 0xb, 0x40, + 0xa, 0xcc, 0x1, 0xcc, 0xde, 0xcc, 0xcc, 0x30, + 0xd, 0x3c, 0x0, 0x6, 0xdb, 0x0, 0x6c, 0x0, + 0x1, 0x3c, 0x19, 0xd7, 0x4e, 0xad, 0xb1, 0x0, + 0x0, 0x3c, 0x4, 0x18, 0xb3, 0xf4, 0xc0, 0x0, + 0x0, 0x3c, 0x1a, 0xc5, 0x3c, 0xe2, 0xb5, 0x0, + 0x0, 0x3c, 0x3, 0x19, 0xc2, 0xc3, 0x2e, 0x30, + 0x0, 0x3c, 0x2a, 0xd7, 0x12, 0xe1, 0x3, 0xa0, + 0x0, 0x3c, 0x5, 0x2, 0xdc, 0x60, 0x0, 0x0, + + /* U+51FA "出" */ + 0x0, 0x0, 0x0, 0xc5, 0x0, 0x0, 0x0, 0x1, + 0x0, 0x0, 0xc5, 0x0, 0x0, 0x10, 0xb, 0x60, + 0x0, 0xc5, 0x0, 0x3, 0xe0, 0xb, 0x60, 0x0, + 0xc5, 0x0, 0x3, 0xe0, 0xb, 0x60, 0x0, 0xc5, + 0x0, 0x3, 0xe0, 0xb, 0x71, 0x11, 0xd6, 0x11, + 0x14, 0xe0, 0xa, 0xee, 0xee, 0xff, 0xee, 0xee, + 0xd0, 0x0, 0x0, 0x0, 0xc5, 0x0, 0x0, 0x0, + 0x19, 0x0, 0x0, 0xc5, 0x0, 0x0, 0x73, 0x2f, + 0x0, 0x0, 0xc5, 0x0, 0x0, 0xc5, 0x2f, 0x0, + 0x0, 0xc5, 0x0, 0x0, 0xc5, 0x2f, 0x0, 0x0, + 0xc5, 0x0, 0x0, 0xc5, 0x2f, 0x44, 0x44, 0xd7, + 0x44, 0x44, 0xd5, 0x1c, 0xcc, 0xcc, 0xcc, 0xcc, + 0xcc, 0xf5, + + /* U+51FD "函" */ + 0x0, 0xef, 0xff, 0xff, 0xff, 0xff, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x29, 0xc7, 0x0, 0x16, 0x4, + 0x0, 0x1c, 0xb4, 0x2, 0x25, 0x2e, 0xc, 0xa0, + 0x2f, 0x0, 0xbb, 0x5c, 0x2e, 0x0, 0xab, 0x2f, + 0xd, 0x90, 0x5c, 0x2e, 0x0, 0x1, 0x2f, 0x2, + 0x0, 0x5c, 0x2e, 0x0, 0x3c, 0x4f, 0x49, 0x0, + 0x5c, 0x2e, 0x9, 0xe6, 0x2f, 0xa, 0xd3, 0x5c, + 0x2e, 0x8a, 0x10, 0x2f, 0x0, 0x6e, 0x6c, 0x2e, + 0x0, 0x0, 0x5e, 0x0, 0x0, 0x5c, 0x2e, 0x0, + 0x8f, 0xe6, 0x0, 0x0, 0x5c, 0x2e, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x6c, 0x2d, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xec, + + /* U+52A8 "动" */ + 0x0, 0x0, 0x0, 0x0, 0x1, 0xe0, 0x0, 0x0, + 0x5c, 0xcc, 0xcc, 0x40, 0x1e, 0x0, 0x0, 0x1, + 0x33, 0x33, 0x31, 0x2, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1f, 0xff, 0xff, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0x3, 0xd0, 0x2, 0xe0, 0xcc, 0xcc, + 0xcc, 0x90, 0x3d, 0x0, 0x2e, 0x3, 0x3c, 0x93, + 0x32, 0x4, 0xc0, 0x2, 0xe0, 0x1, 0xf2, 0x0, + 0x0, 0x6a, 0x0, 0x3d, 0x0, 0x6b, 0xa, 0x40, + 0x8, 0x80, 0x3, 0xd0, 0xd, 0x30, 0x6b, 0x0, + 0xc5, 0x0, 0x4d, 0x4, 0xc0, 0x0, 0xe2, 0x2f, + 0x10, 0x5, 0xc0, 0xdd, 0xcd, 0xef, 0x89, 0x90, + 0x0, 0x6b, 0x5, 0x53, 0x20, 0x17, 0xf2, 0x22, + 0x2b, 0x80, 0x0, 0x0, 0x0, 0xd7, 0x9, 0xff, + 0xc1, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, + 0x0, + + /* U+5782 "垂" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x11, 0x0, + 0x0, 0xdd, 0xde, 0xee, 0xee, 0xed, 0xc9, 0x0, + 0x0, 0x11, 0x10, 0x8, 0x80, 0x0, 0x0, 0x0, + 0x1, 0x22, 0x22, 0x29, 0x92, 0x22, 0x22, 0x10, + 0x7, 0xcd, 0xfc, 0xce, 0xec, 0xcf, 0xcc, 0x70, + 0x0, 0x4, 0xc0, 0x8, 0x80, 0xd, 0x30, 0x0, + 0x0, 0x4, 0xc0, 0x8, 0x80, 0xd, 0x30, 0x0, + 0x1e, 0xee, 0xfe, 0xef, 0xfe, 0xef, 0xee, 0xe1, + 0x0, 0x4, 0xc0, 0x8, 0x80, 0xd, 0x30, 0x0, + 0x0, 0x4, 0xc0, 0x8, 0x80, 0xd, 0x30, 0x0, + 0x9, 0xee, 0xfe, 0xef, 0xfe, 0xef, 0xee, 0x90, + 0x0, 0x0, 0x0, 0x8, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0x80, 0x0, 0x0, 0x0, + 0x0, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x0, + + /* U+578B "型" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0x30, + 0x7, 0xef, 0xee, 0xff, 0xe0, 0xc3, 0xc, 0x30, + 0x0, 0xe, 0x10, 0x87, 0x0, 0xc3, 0xc, 0x30, + 0x0, 0xe, 0x10, 0x87, 0x0, 0xc3, 0xc, 0x30, + 0xe, 0xef, 0xee, 0xff, 0xe6, 0xc3, 0xc, 0x30, + 0x0, 0x1e, 0x0, 0x87, 0x0, 0x92, 0xc, 0x30, + 0x0, 0x8a, 0x0, 0x87, 0x0, 0x0, 0xd, 0x30, + 0x5, 0xf3, 0x0, 0x87, 0x0, 0x4c, 0xde, 0x0, + 0x3, 0x60, 0x0, 0x2, 0x10, 0x3, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x8, 0x90, 0x0, 0x0, 0x0, + 0x0, 0xce, 0xee, 0xef, 0xfe, 0xee, 0xec, 0x0, + 0x0, 0x0, 0x0, 0x8, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0x90, 0x0, 0x0, 0x0, + 0x1e, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xe1, + + /* U+5927 "大" */ + 0x0, 0x0, 0x0, 0x8, 0xa0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0xa0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0x90, 0x0, 0x0, 0x0, + 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe0, + 0x2, 0x22, 0x22, 0x2c, 0xb2, 0x22, 0x22, 0x20, + 0x0, 0x0, 0x0, 0xf, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4c, 0xb4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xb7, 0x6c, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xe1, 0xd, 0x60, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0x50, 0x3, 0xf5, 0x0, 0x0, + 0x0, 0x5, 0xf8, 0x0, 0x0, 0x5f, 0x80, 0x0, + 0x2, 0xaf, 0x60, 0x0, 0x0, 0x3, 0xde, 0x60, + 0xb, 0xc2, 0x0, 0x0, 0x0, 0x0, 0x8, 0x90, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+5BBD "宽" */ + 0x0, 0x0, 0x0, 0x64, 0x0, 0x0, 0x0, 0x1, + 0x33, 0x33, 0x3a, 0xb3, 0x33, 0x33, 0x10, 0x9d, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xd9, 0x8, 0x70, + 0xf, 0x10, 0x1, 0xf0, 0x8, 0x80, 0xbc, 0xcc, + 0xfd, 0xcc, 0xdf, 0xcc, 0xcc, 0x1, 0x11, 0x1f, + 0x31, 0x13, 0xf1, 0x11, 0x10, 0x0, 0x0, 0x10, + 0x0, 0x1, 0x0, 0x0, 0x0, 0x4f, 0xee, 0xee, + 0xee, 0xee, 0xf1, 0x0, 0x4, 0xd0, 0x0, 0x41, + 0x0, 0xf, 0x10, 0x0, 0x4d, 0x0, 0xd, 0x50, + 0x0, 0xf1, 0x0, 0x4, 0xd0, 0x2, 0xff, 0x20, + 0xf, 0x11, 0x0, 0x16, 0x1, 0xc7, 0xe2, 0x0, + 0x51, 0xf0, 0x0, 0x28, 0xe9, 0xd, 0x50, 0x0, + 0x5c, 0x9, 0xef, 0xa3, 0x0, 0x6e, 0xff, 0xfd, + 0x40, 0x33, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+5C0F "小" */ + 0x0, 0x0, 0x0, 0x4d, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4, 0xd0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4d, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xa1, 0x4, 0xd0, 0x8, 0x10, 0x0, 0x0, 0x6d, + 0x0, 0x4d, 0x0, 0xb8, 0x0, 0x0, 0xb, 0x70, + 0x4, 0xd0, 0x4, 0xf1, 0x0, 0x2, 0xf1, 0x0, + 0x4d, 0x0, 0xc, 0x80, 0x0, 0x8b, 0x0, 0x4, + 0xd0, 0x0, 0x5f, 0x10, 0x1f, 0x40, 0x0, 0x4d, + 0x0, 0x0, 0xe7, 0x8, 0xc0, 0x0, 0x4, 0xd0, + 0x0, 0x7, 0xe0, 0x95, 0x0, 0x0, 0x4d, 0x0, + 0x0, 0x9, 0x10, 0x0, 0x0, 0x4, 0xd0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0x32, 0x9c, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xfd, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+5E73 "平" */ + 0x5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, + 0x0, 0x0, 0x0, 0x9, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x46, 0x0, 0x9, 0x90, 0x0, 0x74, 0x0, + 0x0, 0x2f, 0x40, 0x9, 0x90, 0x4, 0xe2, 0x0, + 0x0, 0x5, 0xe2, 0x9, 0x90, 0x3e, 0x30, 0x0, + 0x0, 0x0, 0x98, 0x9, 0x90, 0xb5, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0x90, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf1, + 0x2, 0x22, 0x22, 0x29, 0xa2, 0x22, 0x22, 0x20, + 0x0, 0x0, 0x0, 0x9, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0x90, 0x0, 0x0, 0x0, + + /* U+5EA6 "度" */ + 0x0, 0x0, 0x0, 0x1, 0x90, 0x0, 0x0, 0x0, + 0x1, 0x11, 0x11, 0x1e, 0x51, 0x11, 0x11, 0x0, + 0xed, 0xde, 0xfd, 0xdd, 0xdf, 0xdd, 0xb0, 0xe, + 0x20, 0x3c, 0x0, 0x0, 0xf1, 0x0, 0x0, 0xe7, + 0xef, 0xfe, 0xee, 0xef, 0xee, 0x90, 0xe, 0x20, + 0x3c, 0x0, 0x0, 0xf1, 0x0, 0x0, 0xe1, 0x3, + 0xea, 0xaa, 0xaf, 0x10, 0x0, 0xe, 0x10, 0x2, + 0x22, 0x22, 0x20, 0x0, 0x0, 0xf1, 0x23, 0x33, + 0x33, 0x33, 0x30, 0x0, 0xf, 0xa, 0xfd, 0xbb, + 0xbb, 0xcf, 0x10, 0x1, 0xe0, 0x4, 0xe2, 0x0, + 0x3e, 0x50, 0x0, 0x5b, 0x0, 0x4, 0xe7, 0x8d, + 0x30, 0x0, 0xa, 0x70, 0x0, 0x4b, 0xff, 0x93, + 0x0, 0x2, 0xf1, 0x8b, 0xfc, 0x71, 0x17, 0xcf, + 0xd8, 0x4, 0x5, 0x51, 0x0, 0x0, 0x0, 0x14, + 0x30, + + /* U+5F0F "式" */ + 0x0, 0x0, 0x0, 0x0, 0x2f, 0x4, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1f, 0x3, 0xe6, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1f, 0x0, 0x36, 0x0, + 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0x20, 0x0, 0x0, + 0x1, 0x33, 0x33, 0x33, 0xc, 0x40, 0x0, 0x0, + 0x7, 0xdd, 0xfd, 0xdd, 0xb, 0x60, 0x0, 0x0, + 0x0, 0x0, 0xd4, 0x0, 0x8, 0x80, 0x0, 0x0, + 0x0, 0x0, 0xd4, 0x0, 0x5, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0xd4, 0x0, 0x0, 0xf0, 0x0, 0x81, + 0x1, 0x24, 0xea, 0x9b, 0x90, 0xa6, 0x0, 0xf0, + 0xe, 0xca, 0x86, 0x43, 0x10, 0x2d, 0x15, 0xb0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xdd, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+6027 "性" */ + 0x0, 0x1f, 0x0, 0x0, 0x1, 0xf0, 0x0, 0x0, + 0x0, 0x1f, 0x0, 0xd, 0x21, 0xf0, 0x0, 0x0, + 0x0, 0x1f, 0x50, 0x2e, 0x1, 0xf0, 0x0, 0x0, + 0x7, 0x4f, 0xd5, 0x7f, 0xdd, 0xfd, 0xdd, 0xa0, + 0xc, 0x3f, 0x26, 0xd6, 0x23, 0xf3, 0x22, 0x20, + 0xe, 0x1f, 0x4, 0xd0, 0x1, 0xf0, 0x0, 0x0, + 0x1c, 0x1f, 0x4, 0x50, 0x1, 0xf0, 0x0, 0x0, + 0x1, 0x1f, 0x0, 0x0, 0x2, 0xf1, 0x0, 0x0, + 0x0, 0x1f, 0x0, 0xcf, 0xff, 0xff, 0xff, 0x70, + 0x0, 0x1f, 0x0, 0x0, 0x1, 0xf0, 0x0, 0x0, + 0x0, 0x1f, 0x0, 0x0, 0x1, 0xf0, 0x0, 0x0, + 0x0, 0x1f, 0x0, 0x0, 0x1, 0xf0, 0x0, 0x0, + 0x0, 0x1f, 0x1, 0x22, 0x23, 0xf2, 0x22, 0x20, + 0x0, 0x1f, 0xa, 0xee, 0xee, 0xee, 0xee, 0xe1, + + /* U+62E9 "择" */ + 0x0, 0x3d, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3d, 0x1, 0xef, 0xee, 0xee, 0xef, 0x50, + 0x0, 0x3d, 0x0, 0xc, 0x70, 0x0, 0x7d, 0x0, + 0x1f, 0xff, 0xf8, 0x1, 0xd7, 0x8, 0xd1, 0x0, + 0x0, 0x3d, 0x0, 0x0, 0x2e, 0xfd, 0x10, 0x0, + 0x0, 0x3d, 0x2, 0x8c, 0xea, 0x5a, 0xec, 0x91, + 0x0, 0x3d, 0x34, 0x94, 0x1, 0xb0, 0x3, 0x60, + 0x5, 0xaf, 0xf5, 0x0, 0x2, 0xe0, 0x0, 0x0, + 0x2e, 0xbd, 0x0, 0xef, 0xff, 0xff, 0xff, 0x90, + 0x0, 0x3d, 0x0, 0x0, 0x2, 0xe0, 0x0, 0x0, + 0x0, 0x3d, 0x0, 0x0, 0x2, 0xe0, 0x0, 0x0, + 0x0, 0x3d, 0xc, 0xee, 0xee, 0xfe, 0xee, 0xe4, + 0x0, 0x5c, 0x0, 0x0, 0x2, 0xe0, 0x0, 0x0, + 0xf, 0xf7, 0x0, 0x0, 0x2, 0xe0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+653E "放" */ + 0x0, 0x2, 0x90, 0x0, 0x3, 0x90, 0x0, 0x0, + 0x0, 0x1, 0xf1, 0x0, 0x8, 0x90, 0x0, 0x0, + 0x2, 0x22, 0xc6, 0x21, 0xe, 0x40, 0x0, 0x0, + 0xd, 0xef, 0xdd, 0xda, 0x5f, 0xff, 0xff, 0xf2, + 0x0, 0x5a, 0x0, 0x0, 0xd8, 0x0, 0x2e, 0x0, + 0x0, 0x6a, 0x0, 0x8, 0xdb, 0x0, 0x4c, 0x0, + 0x0, 0x6f, 0xff, 0xe7, 0x2e, 0x0, 0x78, 0x0, + 0x0, 0x78, 0x2, 0xe0, 0xd, 0x20, 0xc4, 0x0, + 0x0, 0x96, 0x1, 0xe0, 0x8, 0x82, 0xe0, 0x0, + 0x0, 0xb5, 0x2, 0xd0, 0x1, 0xeb, 0x80, 0x0, + 0x0, 0xd2, 0x2, 0xd0, 0x0, 0xaf, 0x0, 0x0, + 0x3, 0xe0, 0x3, 0xc0, 0x6, 0xfc, 0xb0, 0x0, + 0x9, 0x80, 0x7, 0xb0, 0x9f, 0x30, 0xcc, 0x20, + 0x1f, 0x17, 0xfd, 0x4d, 0xd2, 0x0, 0x9, 0xe0, + 0x2, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x20, + + /* U+6570 "数" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, 0x0, + 0x1, 0x20, 0x87, 0x2, 0x0, 0xa5, 0x0, 0x0, + 0x3, 0xd2, 0x87, 0x3d, 0x20, 0xf1, 0x0, 0x0, + 0x0, 0x47, 0x87, 0x93, 0x5, 0xe8, 0x88, 0x80, + 0xa, 0xbb, 0xdd, 0xbb, 0x4b, 0xa8, 0x9f, 0x80, + 0x2, 0x25, 0xf8, 0x22, 0x5f, 0x20, 0x3c, 0x0, + 0x0, 0x6c, 0x9c, 0xc2, 0xcd, 0x50, 0x5a, 0x0, + 0xc, 0xa1, 0x76, 0x4c, 0x55, 0x80, 0x87, 0x0, + 0x1, 0x3, 0x90, 0x0, 0x2, 0xd0, 0xc3, 0x0, + 0xb, 0xbd, 0xdb, 0xba, 0x0, 0xd4, 0xe0, 0x0, + 0x2, 0x9a, 0x22, 0x7c, 0x0, 0x7f, 0x70, 0x0, + 0x0, 0xca, 0x30, 0xd4, 0x0, 0x5f, 0x50, 0x0, + 0x0, 0x4, 0xde, 0xb0, 0x3, 0xe7, 0xe4, 0x0, + 0x0, 0x5a, 0xe6, 0xbb, 0x5f, 0x50, 0x5f, 0x60, + 0xe, 0xc6, 0x0, 0x2, 0xe4, 0x0, 0x3, 0xb0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+6700 "最" */ + 0x0, 0x1f, 0xcc, 0xcc, 0xcc, 0xcc, 0xf2, 0x0, + 0x0, 0x1f, 0x44, 0x44, 0x44, 0x44, 0xf2, 0x0, + 0x0, 0x1f, 0x55, 0x55, 0x55, 0x55, 0xf2, 0x0, + 0x0, 0x1f, 0xcc, 0xcc, 0xcc, 0xcc, 0xf2, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1d, 0xed, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xd2, + 0x0, 0xa5, 0x0, 0x6a, 0x1, 0x11, 0x11, 0x0, + 0x0, 0xad, 0xcc, 0xda, 0x6f, 0xbb, 0xbf, 0x20, + 0x0, 0xa5, 0x0, 0x6a, 0xa, 0x40, 0x3c, 0x0, + 0x0, 0xad, 0xcc, 0xda, 0x3, 0xd1, 0xc3, 0x0, + 0x0, 0xa5, 0x0, 0x6a, 0x30, 0x7f, 0x80, 0x0, + 0x9, 0xed, 0xbb, 0xdd, 0x76, 0xd8, 0xd8, 0x20, + 0x3, 0x10, 0x0, 0x6a, 0x98, 0x10, 0x6, 0xb0, + + /* U+683C "格" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xf, 0x0, 0x0, 0x89, 0x0, 0x0, 0x0, + 0x0, 0xf, 0x0, 0x1, 0xfa, 0x77, 0x77, 0x20, + 0x0, 0xf, 0x0, 0x9, 0xd9, 0x99, 0x9f, 0x40, + 0xd, 0xef, 0xea, 0x6f, 0xe1, 0x0, 0x8b, 0x0, + 0x0, 0x3f, 0x1, 0xf4, 0x8a, 0x6, 0xe1, 0x0, + 0x0, 0x9f, 0x40, 0x20, 0xb, 0xce, 0x20, 0x0, + 0x0, 0xcf, 0xe6, 0x0, 0x5d, 0xde, 0x60, 0x0, + 0x6, 0x8f, 0x2d, 0x8d, 0xd4, 0x4, 0xdf, 0xa1, + 0xd, 0x3f, 0x3, 0xa3, 0x0, 0x0, 0x3, 0x80, + 0x3b, 0xf, 0x0, 0x2f, 0xff, 0xff, 0xff, 0x10, + 0x2, 0xf, 0x0, 0x2e, 0x0, 0x0, 0xf, 0x10, + 0x0, 0xf, 0x0, 0x2e, 0x0, 0x0, 0xf, 0x10, + 0x0, 0xf, 0x0, 0x2f, 0x33, 0x33, 0x3f, 0x10, + 0x0, 0xf, 0x0, 0x2f, 0xcc, 0xcc, 0xcf, 0x10, + + /* U+6A21 "模" */ + 0x0, 0x3c, 0x0, 0x1, 0xe0, 0xe, 0x10, 0x0, + 0x3, 0xc0, 0x8b, 0xbf, 0xbb, 0xfb, 0xb7, 0x1, + 0x5c, 0x22, 0x34, 0xe3, 0x3e, 0x43, 0x10, 0xff, + 0xff, 0x40, 0x4, 0x0, 0x30, 0x0, 0x0, 0x6c, + 0x0, 0xcd, 0xcc, 0xcc, 0xdb, 0x0, 0xb, 0xc0, + 0xc, 0x40, 0x0, 0x3, 0xc0, 0x1, 0xef, 0xa0, + 0xcd, 0xbb, 0xbb, 0xcc, 0x0, 0x89, 0xc9, 0x9c, + 0x40, 0x0, 0x3, 0xc0, 0x1e, 0x4c, 0x1, 0xbd, + 0xdd, 0xdd, 0xdb, 0x1, 0x73, 0xc0, 0x0, 0x0, + 0x76, 0x0, 0x0, 0x0, 0x3c, 0xd, 0xdd, 0xde, + 0xed, 0xdd, 0x90, 0x3, 0xc0, 0x0, 0x3, 0xcc, + 0x20, 0x0, 0x0, 0x3c, 0x0, 0x4a, 0xd2, 0x2d, + 0x94, 0x10, 0x3, 0xc1, 0xeb, 0x50, 0x0, 0x5, + 0xa9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+6C34 "水" */ + 0x0, 0x0, 0x0, 0x5, 0xc0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xc0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xc0, 0x0, 0x1, 0x0, + 0x0, 0x11, 0x11, 0x5, 0xf2, 0x0, 0x4f, 0x20, + 0xb, 0xff, 0xff, 0x5, 0xf8, 0x4, 0xf6, 0x0, + 0x0, 0x0, 0x4d, 0x5, 0xde, 0x6e, 0x40, 0x0, + 0x0, 0x0, 0x89, 0x5, 0xc8, 0xe3, 0x0, 0x0, + 0x0, 0x0, 0xe3, 0x5, 0xc1, 0xe4, 0x0, 0x0, + 0x0, 0x7, 0xc0, 0x5, 0xc0, 0x4e, 0x10, 0x0, + 0x0, 0x1f, 0x40, 0x5, 0xc0, 0x8, 0xd1, 0x0, + 0x0, 0xc9, 0x0, 0x5, 0xc0, 0x0, 0xae, 0x20, + 0xa, 0xd0, 0x0, 0x5, 0xc0, 0x0, 0x9, 0xf3, + 0x1c, 0x10, 0x1, 0x1a, 0xb0, 0x0, 0x0, 0x50, + 0x0, 0x0, 0x7f, 0xfd, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+6CD5 "法" */ + 0x2, 0x50, 0x0, 0x0, 0xb, 0x70, 0x0, 0x0, + 0x3, 0xf6, 0x0, 0x0, 0xb, 0x70, 0x0, 0x0, + 0x0, 0x3e, 0x30, 0x0, 0xb, 0x70, 0x0, 0x0, + 0x0, 0x1, 0x9, 0xff, 0xff, 0xff, 0xff, 0x70, + 0x6, 0x0, 0x0, 0x0, 0xb, 0x70, 0x0, 0x0, + 0xa, 0xd3, 0x0, 0x0, 0xb, 0x70, 0x0, 0x0, + 0x0, 0x7a, 0x0, 0x0, 0xb, 0x70, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xf2, + 0x0, 0x13, 0x0, 0x0, 0x9c, 0x0, 0x0, 0x0, + 0x0, 0x7b, 0x0, 0x4, 0xe1, 0x7, 0x0, 0x0, + 0x0, 0xc5, 0x0, 0x2e, 0x40, 0xb, 0x90, 0x0, + 0x2, 0xf0, 0x1, 0xd6, 0x0, 0x1, 0xd6, 0x0, + 0x8, 0xb0, 0xd, 0xfb, 0xcc, 0xde, 0xff, 0x30, + 0xa, 0x50, 0x4, 0x54, 0x32, 0x11, 0x7, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+753B "画" */ + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0x70, 0x6c, 0xcc, 0xcc, 0xc7, 0x6, 0x30, + 0x4, 0xc0, 0x88, 0x17, 0x81, 0x79, 0xb, 0x50, + 0x4, 0xc0, 0x87, 0x7, 0x80, 0x69, 0xb, 0x50, + 0x4, 0xc0, 0x87, 0x7, 0x80, 0x69, 0xb, 0x50, + 0x4, 0xc0, 0x8e, 0xde, 0xed, 0xe9, 0xb, 0x50, + 0x4, 0xc0, 0x87, 0x7, 0x80, 0x69, 0xb, 0x50, + 0x4, 0xc0, 0x87, 0x7, 0x80, 0x69, 0xb, 0x50, + 0x4, 0xc0, 0x7e, 0xde, 0xed, 0xe8, 0xb, 0x50, + 0x4, 0xc0, 0x0, 0x0, 0x0, 0x0, 0xb, 0x50, + 0x4, 0xd3, 0x33, 0x33, 0x33, 0x33, 0x3c, 0x50, + 0x3, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbe, 0x50, + + /* U+76F4 "直" */ + 0x0, 0x0, 0x0, 0x8, 0x80, 0x0, 0x0, 0x0, + 0x9, 0xbb, 0xbb, 0xbe, 0xeb, 0xbb, 0xbb, 0x90, + 0x2, 0x22, 0x22, 0x29, 0x92, 0x22, 0x22, 0x20, + 0x0, 0x0, 0x0, 0x8, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x3f, 0xdd, 0xdd, 0xdd, 0xdd, 0xf3, 0x0, + 0x0, 0x3d, 0x0, 0x0, 0x0, 0x0, 0xd3, 0x0, + 0x0, 0x3f, 0xcc, 0xcc, 0xcc, 0xcc, 0xf3, 0x0, + 0x0, 0x3d, 0x0, 0x0, 0x0, 0x0, 0xd3, 0x0, + 0x0, 0x3f, 0xdd, 0xdd, 0xdd, 0xdd, 0xf3, 0x0, + 0x0, 0x3d, 0x0, 0x0, 0x0, 0x0, 0xd3, 0x0, + 0x0, 0x3f, 0xaa, 0xaa, 0xaa, 0xaa, 0xf3, 0x0, + 0x0, 0x3d, 0x22, 0x22, 0x22, 0x22, 0xd3, 0x0, + 0x0, 0x3d, 0x0, 0x0, 0x0, 0x0, 0xd3, 0x0, + 0x2e, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xe2, + + /* U+7B97 "算" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xb, 0x50, 0x0, 0x7, 0x90, 0x0, 0x0, + 0x0, 0x5f, 0xcc, 0xcc, 0x2e, 0xdc, 0xcc, 0xc0, + 0x3, 0xe2, 0x5a, 0x0, 0xb7, 0xd, 0x10, 0x0, + 0xe, 0x50, 0x9, 0x10, 0x80, 0x5, 0x40, 0x0, + 0x2, 0x5e, 0xbb, 0xbb, 0xbb, 0xbb, 0xe6, 0x0, + 0x0, 0x5b, 0x11, 0x11, 0x11, 0x11, 0xa6, 0x0, + 0x0, 0x5d, 0x99, 0x99, 0x99, 0x99, 0xd6, 0x0, + 0x0, 0x5e, 0xaa, 0xaa, 0xaa, 0xaa, 0xd6, 0x0, + 0x0, 0x5b, 0x0, 0x0, 0x0, 0x0, 0xa6, 0x0, + 0x0, 0x4d, 0xbc, 0xbb, 0xbb, 0xcc, 0xd5, 0x0, + 0x0, 0x0, 0x2e, 0x0, 0x0, 0x78, 0x0, 0x0, + 0x1d, 0xdd, 0xdf, 0xdd, 0xdd, 0xee, 0xdd, 0xd2, + 0x0, 0x0, 0xb7, 0x0, 0x0, 0x78, 0x0, 0x0, + 0x0, 0x8d, 0x70, 0x0, 0x0, 0x78, 0x0, 0x0, + 0x0, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+7C7B "类" */ + 0x0, 0x4, 0x0, 0x5, 0xb0, 0x0, 0x41, 0x0, + 0x0, 0xc, 0xb1, 0x5, 0xb0, 0x7, 0xe3, 0x0, + 0x0, 0x0, 0x9c, 0x5, 0xb0, 0x8c, 0x20, 0x0, + 0x0, 0x11, 0x12, 0x16, 0xb1, 0x21, 0x11, 0x10, + 0x6, 0xdd, 0xdd, 0xef, 0xfd, 0xdd, 0xdd, 0xa0, + 0x0, 0x0, 0x7, 0xc8, 0xda, 0x61, 0x0, 0x0, + 0x0, 0x39, 0xe9, 0x5, 0xb2, 0x7c, 0xc7, 0x20, + 0x8, 0xe8, 0x10, 0x1, 0x40, 0x0, 0x28, 0xb0, + 0x0, 0x0, 0x0, 0x6, 0xb0, 0x0, 0x0, 0x0, + 0x9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, + 0x0, 0x0, 0x0, 0x1e, 0xc6, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xd7, 0x1d, 0x90, 0x0, 0x0, + 0x0, 0x4, 0x9f, 0x60, 0x1, 0xae, 0x83, 0x0, + 0xa, 0xfd, 0x81, 0x0, 0x0, 0x3, 0x9e, 0xf1, + 0x2, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x10, + + /* U+7D20 "素" */ + 0x0, 0x0, 0x0, 0x8, 0x80, 0x0, 0x0, 0x0, + 0x4, 0xaa, 0xaa, 0xad, 0xda, 0xaa, 0xaa, 0x40, + 0x1, 0x22, 0x22, 0x29, 0x92, 0x22, 0x22, 0x10, + 0x0, 0x7c, 0xcc, 0xce, 0xec, 0xcc, 0xc7, 0x0, + 0x0, 0x0, 0x0, 0x8, 0x80, 0x0, 0x0, 0x0, + 0xd, 0xdd, 0xdd, 0xde, 0xed, 0xdd, 0xdd, 0xd0, + 0x0, 0x0, 0x49, 0xb7, 0x0, 0x48, 0x0, 0x0, + 0x0, 0x6f, 0xfb, 0xab, 0xbe, 0xb4, 0x0, 0x0, + 0x0, 0x1, 0x14, 0xbe, 0x81, 0x69, 0x0, 0x0, + 0x0, 0x17, 0xdb, 0x40, 0x0, 0x2d, 0xc1, 0x0, + 0x0, 0xde, 0xdc, 0xcd, 0xeb, 0xba, 0xbd, 0x10, + 0x0, 0x2, 0x83, 0x5, 0xb0, 0x48, 0x22, 0x0, + 0x7, 0xcd, 0x60, 0x6, 0xa0, 0x6, 0xcc, 0x60, + 0x7, 0x30, 0xc, 0xee, 0x50, 0x0, 0x3, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+7EBF "线" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xc, 0x40, 0x0, 0xd3, 0x26, 0x0, 0x0, + 0x0, 0x4d, 0x0, 0x0, 0xc4, 0x1c, 0xa0, 0x0, + 0x0, 0xc5, 0x0, 0x0, 0xc4, 0x0, 0x60, 0x0, + 0x6, 0xb0, 0x45, 0x13, 0xda, 0x9b, 0xdf, 0x60, + 0x1e, 0x20, 0xd4, 0xdc, 0xeb, 0x64, 0x20, 0x0, + 0x4f, 0xef, 0xa0, 0x0, 0x97, 0x0, 0x0, 0x0, + 0x0, 0x2d, 0x10, 0x0, 0x7b, 0x58, 0xac, 0xc0, + 0x0, 0xc4, 0x1, 0xde, 0xee, 0x86, 0x43, 0x0, + 0xa, 0xb4, 0x62, 0x10, 0x1f, 0x0, 0x7c, 0x0, + 0xd, 0xca, 0x82, 0x0, 0xd, 0x49, 0xc1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xf9, 0x0, 0x90, + 0x3, 0x58, 0xa7, 0x2, 0xae, 0xf2, 0x3, 0xc0, + 0x3e, 0xb8, 0x56, 0xce, 0x70, 0x8d, 0x39, 0x80, + 0x0, 0x0, 0x4, 0x60, 0x0, 0x8, 0xed, 0x20, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+7F29 "缩" */ + 0x0, 0x6, 0x30, 0x0, 0x2, 0xb0, 0x0, 0x0, + 0x0, 0x1f, 0x20, 0x0, 0x0, 0xe3, 0x0, 0x0, + 0x0, 0x89, 0x1, 0xfe, 0xee, 0xee, 0xee, 0xe0, + 0x1, 0xe1, 0x34, 0xe1, 0x0, 0x0, 0x0, 0xe0, + 0xa, 0x70, 0xc5, 0x3c, 0x67, 0x77, 0x77, 0x70, + 0xf, 0xef, 0xb0, 0x3c, 0x26, 0x6e, 0x76, 0x60, + 0x0, 0xe, 0x20, 0xb8, 0x0, 0xf, 0x0, 0x0, + 0x0, 0x88, 0x5, 0xf8, 0x1f, 0xdd, 0xde, 0x70, + 0x3, 0xd0, 0x1d, 0xa8, 0x1e, 0x0, 0x8, 0x70, + 0xb, 0xff, 0xc2, 0x78, 0x1e, 0x0, 0x8, 0x70, + 0x2, 0x20, 0x0, 0x78, 0x1f, 0xdd, 0xde, 0x70, + 0x0, 0x0, 0x11, 0x78, 0x1e, 0x0, 0x8, 0x70, + 0xa, 0xdf, 0xe3, 0x78, 0x1e, 0x11, 0x19, 0x70, + 0x5, 0x30, 0x0, 0x78, 0x1f, 0xcc, 0xce, 0x60, + + /* U+8F93 "输" */ + 0x0, 0x16, 0x0, 0x0, 0x2, 0x90, 0x0, 0x0, + 0x0, 0x69, 0x0, 0x0, 0xc, 0xe5, 0x0, 0x0, + 0x8, 0xcb, 0x87, 0x0, 0xb8, 0x1d, 0x50, 0x0, + 0x6, 0xf6, 0x65, 0x2d, 0x80, 0x2, 0xda, 0x10, + 0x2, 0xc2, 0x15, 0xd5, 0xdd, 0xdd, 0x88, 0xe0, + 0x7, 0x79, 0x40, 0x22, 0x22, 0x0, 0x3, 0x30, + 0xc, 0x39, 0x40, 0xcf, 0xff, 0x3, 0x17, 0x60, + 0xf, 0xce, 0xd6, 0xc2, 0xd, 0xa, 0x37, 0x60, + 0x1, 0x1b, 0x50, 0xcb, 0xaf, 0xa, 0x37, 0x60, + 0x0, 0xb, 0x40, 0xc3, 0x2d, 0xa, 0x37, 0x60, + 0x3, 0x4c, 0xb7, 0xc8, 0x7e, 0xa, 0x37, 0x60, + 0x1c, 0xad, 0x72, 0xc6, 0x5d, 0x9, 0x27, 0x60, + 0x0, 0xb, 0x40, 0xc2, 0xd, 0x0, 0x8, 0x60, + 0x0, 0xb, 0x40, 0xc6, 0xec, 0x8, 0xfd, 0x20, + 0x0, 0x1, 0x0, 0x10, 0x0, 0x0, 0x0, 0x0, + + /* U+9009 "选" */ + 0x0, 0x50, 0x0, 0x3, 0x3, 0xe0, 0x0, 0x0, + 0x0, 0xd7, 0x0, 0x2f, 0x3, 0xe0, 0x0, 0x0, + 0x0, 0x2f, 0x40, 0x8c, 0x24, 0xe2, 0x22, 0x10, + 0x0, 0x5, 0x20, 0xed, 0xcd, 0xfc, 0xcc, 0x80, + 0x0, 0x0, 0x7, 0xd0, 0x3, 0xe0, 0x0, 0x0, + 0x9, 0xa9, 0x2, 0x30, 0x3, 0xe0, 0x0, 0x0, + 0x4, 0x6e, 0xe, 0xee, 0xee, 0xfe, 0xee, 0xe4, + 0x0, 0x2e, 0x0, 0x4, 0xb0, 0x1f, 0x0, 0x0, + 0x0, 0x2e, 0x0, 0x6, 0xa0, 0x1f, 0x0, 0x20, + 0x0, 0x2e, 0x0, 0xc, 0x50, 0x1f, 0x0, 0xb4, + 0x0, 0x2e, 0x0, 0xad, 0x0, 0xf, 0x10, 0xe1, + 0x0, 0x5f, 0x29, 0xc1, 0x0, 0x9, 0xee, 0x90, + 0x6, 0xe7, 0xe6, 0x10, 0x0, 0x0, 0x0, 0x0, + 0xc, 0x20, 0x3b, 0xef, 0xff, 0xff, 0xff, 0xf5, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+975E "非" */ + 0x0, 0x0, 0x3e, 0x0, 0x5c, 0x0, 0x0, 0x0, + 0x0, 0x3, 0xe0, 0x5, 0xc0, 0x0, 0x0, 0x6c, + 0xcc, 0xce, 0x0, 0x5f, 0xcc, 0xcc, 0x22, 0x44, + 0x46, 0xe0, 0x5, 0xd4, 0x44, 0x40, 0x0, 0x0, + 0x3e, 0x0, 0x5c, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xe0, 0x5, 0xc0, 0x0, 0x0, 0x5e, 0xee, 0xfe, + 0x0, 0x5f, 0xee, 0xee, 0x0, 0x11, 0x14, 0xe0, + 0x5, 0xc1, 0x11, 0x10, 0x0, 0x0, 0x3e, 0x0, + 0x5c, 0x0, 0x0, 0x0, 0x0, 0x3, 0xe0, 0x5, + 0xc0, 0x0, 0x0, 0xdf, 0xff, 0xfe, 0x0, 0x5f, + 0xff, 0xff, 0x80, 0x0, 0x3, 0xe0, 0x5, 0xc0, + 0x0, 0x0, 0x0, 0x0, 0x3e, 0x0, 0x5c, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xe0, 0x5, 0xc0, 0x0, + 0x0, + + /* U+F001 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x49, 0xdc, + 0x0, 0x0, 0x0, 0x0, 0x16, 0xbf, 0xff, 0xff, + 0x0, 0x0, 0x3, 0x8d, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xc7, 0xff, + 0x0, 0x0, 0xff, 0xff, 0xea, 0x51, 0x0, 0xff, + 0x0, 0x0, 0xff, 0x83, 0x0, 0x0, 0x0, 0xff, + 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x0, 0x0, 0xff, 0x0, 0x0, 0x2b, 0xff, 0xff, + 0x0, 0x0, 0xff, 0x0, 0x0, 0xdf, 0xff, 0xff, + 0x2b, 0xff, 0xff, 0x0, 0x0, 0xdf, 0xff, 0xfd, + 0xdf, 0xff, 0xff, 0x0, 0x0, 0x2b, 0xff, 0xb2, + 0xdf, 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2b, 0xff, 0xb2, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F008 "" */ + 0xd0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xd, + 0xff, 0xff, 0xc8, 0x88, 0x88, 0x8c, 0xff, 0xff, + 0xf0, 0xf, 0x80, 0x0, 0x0, 0x8, 0xf0, 0xf, + 0xf0, 0xf, 0x80, 0x0, 0x0, 0x8, 0xf0, 0xf, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xf0, 0xf, 0xec, 0xcc, 0xcc, 0xce, 0xf0, 0xf, + 0xf0, 0xf, 0xec, 0xcc, 0xcc, 0xce, 0xf0, 0xf, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xf0, 0xf, 0x80, 0x0, 0x0, 0x8, 0xf0, 0xf, + 0xf0, 0xf, 0x80, 0x0, 0x0, 0x8, 0xf0, 0xf, + 0xff, 0xff, 0xc8, 0x88, 0x88, 0x8c, 0xff, 0xff, + 0xd0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xd, + + /* U+F00B "" */ + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + + /* U+F00C "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xb1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, 0xc0, + 0x1b, 0xa0, 0x0, 0x0, 0xb, 0xff, 0xfc, 0x0, + 0xcf, 0xfb, 0x0, 0x0, 0xbf, 0xff, 0xc0, 0x0, + 0xbf, 0xff, 0xb0, 0xb, 0xff, 0xfc, 0x0, 0x0, + 0xc, 0xff, 0xfb, 0xbf, 0xff, 0xc0, 0x0, 0x0, + 0x0, 0xcf, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xff, 0xff, 0xb0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xb0, 0x0, 0x0, 0x0, 0x0, + + /* U+F00D "" */ + 0x3, 0x0, 0x0, 0x0, 0x3, 0x8, 0xfc, 0x10, + 0x0, 0x1c, 0xf8, 0xff, 0xfc, 0x10, 0x1c, 0xff, + 0xf5, 0xff, 0xfc, 0x2c, 0xff, 0xf5, 0x5, 0xff, + 0xff, 0xff, 0xf5, 0x0, 0x5, 0xff, 0xff, 0xf5, + 0x0, 0x0, 0x1d, 0xff, 0xfd, 0x10, 0x0, 0x1c, + 0xff, 0xff, 0xfc, 0x10, 0x1c, 0xff, 0xf9, 0xff, + 0xfc, 0x1c, 0xff, 0xf5, 0x5, 0xff, 0xfc, 0xdf, + 0xf5, 0x0, 0x5, 0xff, 0xd1, 0xa4, 0x0, 0x0, + 0x4, 0xa1, + + /* U+F011 "" */ + 0x0, 0x0, 0x0, 0x4f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0x10, 0x6f, 0xf1, 0x3, 0x10, 0x0, + 0x0, 0x5f, 0xd0, 0x6f, 0xf1, 0x3f, 0xd1, 0x0, + 0x3, 0xff, 0xf1, 0x6f, 0xf1, 0x5f, 0xfd, 0x0, + 0xd, 0xff, 0x40, 0x6f, 0xf1, 0x9, 0xff, 0x70, + 0x4f, 0xf7, 0x0, 0x6f, 0xf1, 0x0, 0xcf, 0xe0, + 0x9f, 0xf0, 0x0, 0x6f, 0xf1, 0x0, 0x5f, 0xf3, + 0xbf, 0xc0, 0x0, 0x6f, 0xf1, 0x0, 0x2f, 0xf5, + 0xbf, 0xc0, 0x0, 0x4f, 0xe0, 0x0, 0x1f, 0xf6, + 0xaf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf4, + 0x6f, 0xf4, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xf0, + 0xf, 0xfe, 0x10, 0x0, 0x0, 0x5, 0xff, 0xa0, + 0x6, 0xff, 0xd3, 0x0, 0x0, 0x7f, 0xff, 0x20, + 0x0, 0x9f, 0xff, 0xda, 0xbe, 0xff, 0xf4, 0x0, + 0x0, 0x6, 0xff, 0xff, 0xff, 0xfd, 0x30, 0x0, + 0x0, 0x0, 0x17, 0xbd, 0xca, 0x50, 0x0, 0x0, + + /* U+F013 "" */ + 0x0, 0x0, 0x0, 0x8b, 0xb8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x30, 0x6, 0xff, 0xff, 0x60, 0x3, 0x0, + 0x4, 0xfd, 0xdf, 0xff, 0xff, 0xfd, 0xef, 0x40, + 0xd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, + 0x4f, 0xff, 0xff, 0xf9, 0x9f, 0xff, 0xff, 0xf4, + 0x8, 0xff, 0xff, 0x20, 0x2, 0xff, 0xff, 0x80, + 0x0, 0xff, 0xf9, 0x0, 0x0, 0x9f, 0xff, 0x0, + 0x0, 0xff, 0xf9, 0x0, 0x0, 0x9f, 0xff, 0x0, + 0x8, 0xff, 0xff, 0x20, 0x2, 0xff, 0xff, 0x80, + 0x4f, 0xff, 0xff, 0xf9, 0x9f, 0xff, 0xff, 0xf4, + 0xd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, + 0x4, 0xfe, 0xdf, 0xff, 0xff, 0xfd, 0xdf, 0x40, + 0x0, 0x30, 0x6, 0xff, 0xff, 0x60, 0x3, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8b, 0xb8, 0x0, 0x0, 0x0, + + /* U+F015 "" */ + 0x0, 0x0, 0x0, 0x3, 0xdd, 0x30, 0x3f, 0xf3, + 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xf5, 0x4f, + 0xf4, 0x0, 0x0, 0x0, 0x9, 0xff, 0x99, 0xff, + 0xbf, 0xf4, 0x0, 0x0, 0x1, 0xbf, 0xf6, 0x22, + 0x6f, 0xff, 0xf4, 0x0, 0x0, 0x2d, 0xfe, 0x35, + 0xff, 0x53, 0xef, 0xf4, 0x0, 0x4, 0xff, 0xc1, + 0x8f, 0xff, 0xf8, 0x2d, 0xfe, 0x40, 0x7f, 0xfa, + 0x1a, 0xff, 0xff, 0xff, 0xa1, 0xaf, 0xf7, 0xcf, + 0x82, 0xdf, 0xff, 0xff, 0xff, 0xfd, 0x28, 0xfc, + 0x14, 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe0, + 0x41, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x0, 0x0, 0xf, 0xff, 0xf9, 0x0, 0x8f, + 0xff, 0xf0, 0x0, 0x0, 0xf, 0xff, 0xf8, 0x0, + 0x8f, 0xff, 0xf0, 0x0, 0x0, 0xf, 0xff, 0xf8, + 0x0, 0x8f, 0xff, 0xf0, 0x0, 0x0, 0xe, 0xff, + 0xf6, 0x0, 0x6f, 0xff, 0xe0, 0x0, + + /* U+F019 "" */ + 0x0, 0x0, 0x0, 0xdf, 0xfd, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xb0, 0x0, + 0x0, 0x0, 0xbf, 0xff, 0xff, 0xfb, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xff, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0xfb, 0x0, 0x0, 0x0, + 0xdf, 0xff, 0xfc, 0x1b, 0xb1, 0xcf, 0xff, 0xfd, + 0xff, 0xff, 0xff, 0xc2, 0x2c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xe0, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, + + /* U+F01C "" */ + 0x0, 0x4, 0xef, 0xff, 0xff, 0xff, 0xfe, 0x40, + 0x0, 0x0, 0x1e, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe1, 0x0, 0x0, 0xaf, 0xb0, 0x0, 0x0, 0x0, + 0xb, 0xfa, 0x0, 0x5, 0xff, 0x10, 0x0, 0x0, + 0x0, 0x1, 0xff, 0x50, 0x1e, 0xf6, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6f, 0xe1, 0xaf, 0xb0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xfa, 0xff, 0xff, + 0xff, 0x80, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf1, 0x0, 0x1f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf8, + + /* U+F021 "" */ + 0x0, 0x0, 0x6, 0xbd, 0xda, 0x50, 0x2, 0xff, + 0x0, 0x5, 0xef, 0xff, 0xff, 0xfe, 0x42, 0xff, + 0x0, 0x7f, 0xff, 0xa7, 0x7b, 0xff, 0xf9, 0xff, + 0x5, 0xff, 0xc1, 0x0, 0x0, 0x2c, 0xff, 0xff, + 0xe, 0xfc, 0x0, 0x0, 0x2, 0x22, 0xdf, 0xff, + 0x5f, 0xf2, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0x8f, 0xb0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, 0xb, 0xf8, + 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x2f, 0xf4, + 0xff, 0xfd, 0x22, 0x20, 0x0, 0x0, 0xcf, 0xe0, + 0xff, 0xff, 0xc2, 0x0, 0x0, 0x2c, 0xff, 0x40, + 0xff, 0x9f, 0xff, 0xb7, 0x6a, 0xff, 0xf7, 0x0, + 0xff, 0x24, 0xdf, 0xff, 0xff, 0xfe, 0x50, 0x0, + 0xff, 0x20, 0x5, 0xac, 0xdb, 0x60, 0x0, 0x0, + + /* U+F026 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8d, + 0x0, 0x0, 0x8, 0xff, 0x0, 0x0, 0x8f, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, + 0x0, 0x0, 0x8f, 0xff, 0x0, 0x0, 0x8, 0xff, + 0x0, 0x0, 0x0, 0x8d, 0x0, 0x0, 0x0, 0x0, + + /* U+F027 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8d, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0x0, 0x0, + 0xcf, 0xff, 0xff, 0xff, 0x1, 0x50, 0xff, 0xff, + 0xff, 0xff, 0x6, 0xf7, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xbe, 0xff, 0xff, 0xff, 0xff, 0x0, 0xae, + 0xff, 0xff, 0xff, 0xff, 0x5, 0xf8, 0xdf, 0xff, + 0xff, 0xff, 0x2, 0x60, 0x0, 0x0, 0x9f, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x9, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9e, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F028 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, + 0xd2, 0x0, 0x0, 0x0, 0x0, 0x8d, 0x0, 0x0, + 0x3, 0xee, 0x10, 0x0, 0x0, 0x8, 0xff, 0x0, + 0xa, 0xb1, 0x2f, 0xb0, 0x0, 0x0, 0x8f, 0xff, + 0x0, 0x5, 0xfc, 0x7, 0xf4, 0xdf, 0xff, 0xff, + 0xff, 0x2, 0x50, 0x5f, 0x60, 0xf9, 0xff, 0xff, + 0xff, 0xff, 0x6, 0xf7, 0xd, 0xc0, 0xbd, 0xff, + 0xff, 0xff, 0xff, 0x0, 0xae, 0x9, 0xf0, 0x9f, + 0xff, 0xff, 0xff, 0xff, 0x0, 0xae, 0x9, 0xf0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0x6, 0xf7, 0xd, + 0xc0, 0xad, 0xdf, 0xff, 0xff, 0xff, 0x2, 0x50, + 0x5f, 0x60, 0xe9, 0x0, 0x0, 0x8f, 0xff, 0x0, + 0x5, 0xfc, 0x6, 0xf4, 0x0, 0x0, 0x8, 0xff, + 0x0, 0xa, 0xb1, 0x2f, 0xb0, 0x0, 0x0, 0x0, + 0x8d, 0x0, 0x0, 0x2, 0xee, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1f, 0xd2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0x10, 0x0, + + /* U+F03E "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x20, 0x2f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0x0, 0xc, 0xff, 0xff, 0xee, 0xff, 0xff, + 0xff, 0x20, 0x2f, 0xff, 0xfe, 0x22, 0xef, 0xff, + 0xff, 0xfc, 0xff, 0xff, 0xe2, 0x0, 0x2e, 0xff, + 0xff, 0xfe, 0x4e, 0xfe, 0x20, 0x0, 0x2, 0xff, + 0xff, 0xe2, 0x2, 0xc2, 0x0, 0x0, 0x0, 0xff, + 0xff, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + + /* U+F043 "" */ + 0x0, 0x0, 0x4e, 0x40, 0x0, 0x0, 0x0, 0xb, + 0xfb, 0x0, 0x0, 0x0, 0x1, 0xff, 0xf1, 0x0, + 0x0, 0x0, 0x9f, 0xff, 0x90, 0x0, 0x0, 0x2f, + 0xff, 0xff, 0x30, 0x0, 0xc, 0xff, 0xff, 0xfc, + 0x0, 0x7, 0xff, 0xff, 0xff, 0xf8, 0x2, 0xff, + 0xff, 0xff, 0xff, 0xf2, 0x9f, 0xff, 0xff, 0xff, + 0xff, 0x9e, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, + 0x2f, 0xff, 0xff, 0xff, 0xfe, 0xf2, 0xbf, 0xff, + 0xff, 0xfe, 0x9f, 0xa1, 0xbf, 0xff, 0xff, 0x92, + 0xff, 0xa2, 0x2f, 0xff, 0xf2, 0x4, 0xff, 0xff, + 0xff, 0xf4, 0x0, 0x2, 0x9e, 0xfe, 0x92, 0x0, + + /* U+F048 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x30, 0x0, + 0x1, 0xcc, 0xff, 0x40, 0x0, 0x2d, 0xff, 0xff, + 0x40, 0x3, 0xef, 0xff, 0xff, 0x40, 0x3f, 0xff, + 0xff, 0xff, 0x44, 0xff, 0xff, 0xff, 0xff, 0x9f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0xff, + 0xff, 0xff, 0xff, 0x45, 0xff, 0xff, 0xff, 0xff, + 0x40, 0x4f, 0xff, 0xff, 0xff, 0x40, 0x3, 0xef, + 0xff, 0xff, 0x40, 0x0, 0x2e, 0xff, 0xff, 0x30, + 0x0, 0x1, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F04B "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0x91, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, + 0x70, 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0xfd, + 0x40, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xfa, + 0x10, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd5, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb2, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xb2, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xd5, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x0, 0x0, 0xff, 0xff, 0xff, 0xfa, 0x10, + 0x0, 0x0, 0xff, 0xff, 0xfd, 0x40, 0x0, 0x0, + 0x0, 0xff, 0xff, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x8e, 0xa1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F04C "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0xff, 0xf8, 0x0, 0x8f, 0xff, 0xf8, 0xff, 0xff, + 0xff, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0xf7, 0x0, 0x7f, 0xff, + 0xf7, + + /* U+F04D "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, + + /* U+F051 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xcc, 0x10, 0x0, + 0x3, 0xff, 0xff, 0xd2, 0x0, 0x4, 0xff, 0xff, + 0xfe, 0x30, 0x4, 0xff, 0xff, 0xff, 0xf4, 0x4, + 0xff, 0xff, 0xff, 0xff, 0x54, 0xff, 0xff, 0xff, + 0xff, 0xf9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf9, 0xff, 0xff, 0xff, 0xff, 0x44, 0xff, 0xff, + 0xff, 0xf3, 0x4, 0xff, 0xff, 0xfe, 0x30, 0x4, + 0xff, 0xff, 0xd2, 0x0, 0x4, 0xff, 0xcc, 0x10, + 0x0, 0x3, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F052 "" */ + 0x0, 0x0, 0x0, 0x2d, 0xd2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xef, 0xfe, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x1d, 0xff, 0xff, 0xd1, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0xff, 0xff, 0xfc, 0x0, 0x0, + 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xb0, 0x0, + 0x0, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, + 0x9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, + + /* U+F053 "" */ + 0x0, 0x0, 0x0, 0x1a, 0x40, 0x0, 0x0, 0x1, + 0xdf, 0xf0, 0x0, 0x0, 0x1d, 0xff, 0xa0, 0x0, + 0x1, 0xdf, 0xfa, 0x0, 0x0, 0x1d, 0xff, 0xa0, + 0x0, 0x1, 0xdf, 0xfa, 0x0, 0x0, 0xc, 0xff, + 0xa0, 0x0, 0x0, 0xd, 0xff, 0x80, 0x0, 0x0, + 0x1, 0xdf, 0xf8, 0x0, 0x0, 0x0, 0x1d, 0xff, + 0x80, 0x0, 0x0, 0x1, 0xdf, 0xf8, 0x0, 0x0, + 0x0, 0x1d, 0xff, 0x80, 0x0, 0x0, 0x1, 0xdf, + 0xf0, 0x0, 0x0, 0x0, 0x1b, 0x50, + + /* U+F054 "" */ + 0x4, 0xa1, 0x0, 0x0, 0x0, 0xf, 0xfd, 0x10, + 0x0, 0x0, 0xa, 0xff, 0xd1, 0x0, 0x0, 0x0, + 0xaf, 0xfd, 0x10, 0x0, 0x0, 0xa, 0xff, 0xd1, + 0x0, 0x0, 0x0, 0xaf, 0xfd, 0x10, 0x0, 0x0, + 0xa, 0xff, 0xc0, 0x0, 0x0, 0x8, 0xff, 0xd0, + 0x0, 0x0, 0x8f, 0xfd, 0x10, 0x0, 0x8, 0xff, + 0xd1, 0x0, 0x0, 0x8f, 0xfd, 0x10, 0x0, 0x8, + 0xff, 0xd1, 0x0, 0x0, 0xf, 0xfd, 0x10, 0x0, + 0x0, 0x5, 0xb1, 0x0, 0x0, 0x0, + + /* U+F067 "" */ + 0x0, 0x0, 0x4, 0xff, 0x40, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0x80, 0x0, 0x0, 0x48, 0x88, 0x8c, 0xff, 0xc8, + 0x88, 0x84, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x48, 0x88, 0x8c, 0xff, 0xc8, 0x88, 0x84, 0x0, + 0x0, 0x8, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0x80, 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0x40, + 0x0, 0x0, + + /* U+F068 "" */ + 0x14, 0x44, 0x44, 0x44, 0x44, 0x44, 0x41, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xb7, + + /* U+F06E "" */ + 0x0, 0x0, 0x5, 0xad, 0xff, 0xda, 0x50, 0x0, + 0x0, 0x0, 0x4, 0xdf, 0xfc, 0x88, 0xcf, 0xfd, + 0x40, 0x0, 0x0, 0x7f, 0xfe, 0x40, 0x0, 0x4, + 0xef, 0xf7, 0x0, 0x7, 0xff, 0xf4, 0x0, 0x9e, + 0x80, 0x4f, 0xff, 0x70, 0x4f, 0xff, 0xc0, 0x0, + 0xaf, 0xf8, 0xc, 0xff, 0xf4, 0xdf, 0xff, 0x80, + 0x9a, 0xff, 0xfe, 0x8, 0xff, 0xfd, 0xdf, 0xff, + 0x80, 0xef, 0xff, 0xfe, 0x8, 0xff, 0xfd, 0x4f, + 0xff, 0xc0, 0x8f, 0xff, 0xf8, 0xc, 0xff, 0xf4, + 0x7, 0xff, 0xf4, 0x8, 0xee, 0x80, 0x4f, 0xff, + 0x70, 0x0, 0x7f, 0xfe, 0x40, 0x0, 0x4, 0xef, + 0xf8, 0x0, 0x0, 0x4, 0xdf, 0xfc, 0x88, 0xcf, + 0xfd, 0x40, 0x0, 0x0, 0x0, 0x5, 0xad, 0xff, + 0xda, 0x50, 0x0, 0x0, + + /* U+F070 "" */ + 0x8c, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0xe4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1b, 0xff, 0x80, 0x49, + 0xdf, 0xfd, 0xa5, 0x0, 0x0, 0x0, 0x0, 0x7f, + 0xff, 0xff, 0xd8, 0x8c, 0xff, 0xd4, 0x0, 0x0, + 0x0, 0x4, 0xef, 0xf8, 0x0, 0x0, 0x4e, 0xff, + 0x70, 0x0, 0x0, 0x0, 0x1c, 0xff, 0x69, 0xe8, + 0x4, 0xff, 0xf7, 0x0, 0x4, 0xe3, 0x0, 0x9f, + 0xfe, 0xff, 0x80, 0xcf, 0xff, 0x40, 0xd, 0xff, + 0x70, 0x5, 0xff, 0xff, 0xe0, 0x8f, 0xff, 0xd0, + 0xd, 0xff, 0xf7, 0x0, 0x2d, 0xff, 0xe0, 0x8f, + 0xff, 0xd0, 0x4, 0xff, 0xfc, 0x0, 0x0, 0xaf, + 0xf8, 0xcf, 0xff, 0x30, 0x0, 0x7f, 0xff, 0x40, + 0x0, 0x6, 0xff, 0xff, 0xf7, 0x0, 0x0, 0x8, + 0xff, 0xf4, 0x0, 0x0, 0x3e, 0xff, 0xa0, 0x0, + 0x0, 0x0, 0x4d, 0xff, 0xc8, 0x82, 0x1, 0xbf, + 0xf7, 0x0, 0x0, 0x0, 0x0, 0x5a, 0xdf, 0xfc, + 0x10, 0x8, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4e, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xc8, + + /* U+F071 "" */ + 0x0, 0x0, 0x0, 0x0, 0x2d, 0xd2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, + 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xd, 0xff, 0xff, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x7f, 0xff, 0xff, 0xf7, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xff, 0xd8, 0x8d, + 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, + 0xa0, 0xa, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xff, 0xb0, 0xb, 0xff, 0xf3, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0xff, 0xc0, 0xc, 0xff, 0xfc, + 0x0, 0x0, 0x0, 0x5, 0xff, 0xff, 0xd0, 0xd, + 0xff, 0xff, 0x50, 0x0, 0x0, 0xe, 0xff, 0xff, + 0xf9, 0x9f, 0xff, 0xff, 0xe0, 0x0, 0x0, 0x8f, + 0xff, 0xff, 0xe2, 0x2e, 0xff, 0xff, 0xf8, 0x0, + 0x2, 0xff, 0xff, 0xff, 0x90, 0x9, 0xff, 0xff, + 0xff, 0x10, 0xa, 0xff, 0xff, 0xff, 0xe3, 0x3e, + 0xff, 0xff, 0xff, 0xa0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + + /* U+F074 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd8, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x80, + 0xff, 0xff, 0x70, 0x0, 0x7, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xf6, 0x0, 0x6f, 0xff, 0xff, 0xfd, + 0x78, 0x8e, 0xff, 0x15, 0xff, 0xe8, 0xff, 0xe2, + 0x0, 0x2, 0xe5, 0x4f, 0xfe, 0x20, 0xfe, 0x20, + 0x0, 0x0, 0x13, 0xff, 0xf3, 0x0, 0x52, 0x0, + 0x0, 0x0, 0x3f, 0xff, 0x31, 0x0, 0x52, 0x0, + 0x0, 0x2, 0xef, 0xf4, 0x5e, 0x20, 0xfe, 0x20, + 0x78, 0x8e, 0xff, 0x51, 0xff, 0xe8, 0xff, 0xe2, + 0xff, 0xff, 0xf6, 0x0, 0x6f, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0x70, 0x0, 0x7, 0xff, 0xff, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd8, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F077 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0xdd, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x1d, 0xff, 0xd1, 0x0, 0x0, 0x0, 0x1, 0xdf, + 0xff, 0xfd, 0x10, 0x0, 0x0, 0x1d, 0xff, 0x99, + 0xff, 0xd1, 0x0, 0x1, 0xdf, 0xf9, 0x0, 0x9f, + 0xfd, 0x10, 0x1d, 0xff, 0x90, 0x0, 0x9, 0xff, + 0xd1, 0xbf, 0xf9, 0x0, 0x0, 0x0, 0x9f, 0xfb, + 0x5f, 0x90, 0x0, 0x0, 0x0, 0x9, 0xf5, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F078 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0x90, 0x0, 0x0, 0x0, 0x9, 0xf5, 0xbf, 0xf9, + 0x0, 0x0, 0x0, 0x9f, 0xfb, 0x1d, 0xff, 0x90, + 0x0, 0x9, 0xff, 0xd1, 0x1, 0xdf, 0xf9, 0x0, + 0x9f, 0xfd, 0x10, 0x0, 0x1d, 0xff, 0x99, 0xff, + 0xd1, 0x0, 0x0, 0x1, 0xdf, 0xff, 0xfd, 0x10, + 0x0, 0x0, 0x0, 0x1d, 0xff, 0xd1, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xdd, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F079 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1d, 0xd1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xdf, 0xfd, 0x10, + 0xef, 0xff, 0xff, 0xff, 0xd0, 0x0, 0x1d, 0xff, + 0xff, 0xd1, 0xaf, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0xcf, 0xcf, 0xfc, 0xfc, 0x0, 0x0, 0x0, 0xf, + 0xf0, 0x0, 0x6b, 0x1f, 0xf1, 0xb6, 0x0, 0x0, + 0x0, 0xf, 0xf0, 0x0, 0x0, 0xf, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0xf, 0xf0, 0x0, 0x0, 0xf, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf0, 0x0, + 0x0, 0xf, 0xf0, 0x0, 0x0, 0x0, 0x6b, 0x1f, + 0xf1, 0xb6, 0x0, 0xf, 0xf0, 0x0, 0x0, 0x0, + 0xcf, 0xcf, 0xfc, 0xfc, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xfa, 0x1d, 0xff, 0xff, 0xd1, 0x0, 0xd, + 0xff, 0xff, 0xff, 0xfe, 0x1, 0xdf, 0xfd, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1d, + 0xd1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F07B "" */ + 0x8f, 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + + /* U+F093 "" */ + 0x0, 0x0, 0x0, 0xb, 0xb0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xff, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0xff, 0xff, 0xfb, 0x0, 0x0, + 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xb0, 0x0, + 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0xdf, 0xff, 0xf0, 0xdf, 0xfd, 0xf, 0xff, 0xfd, + 0xff, 0xff, 0xf9, 0x0, 0x0, 0x9f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xe0, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, + + /* U+F095 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xea, + 0x62, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xff, + 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xff, 0xff, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xef, 0xff, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4, 0xff, 0xf2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0xff, 0x30, 0x0, 0x0, 0x2, + 0x0, 0x0, 0x4f, 0xff, 0x90, 0x0, 0x2, 0x8f, + 0xf3, 0x0, 0x6f, 0xff, 0xd0, 0x0, 0xa, 0xff, + 0xff, 0xe4, 0xbf, 0xff, 0xd1, 0x0, 0x0, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xd1, 0x0, 0x0, 0xa, + 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0x0, 0x0, + 0x6f, 0xff, 0xff, 0xfb, 0x30, 0x0, 0x0, 0x0, + 0x2, 0xff, 0xdb, 0x72, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F0C4 "" */ + 0x8, 0xee, 0x80, 0x0, 0x0, 0x6, 0x61, 0x8, + 0xff, 0xff, 0x80, 0x0, 0x2d, 0xff, 0xd0, 0xef, + 0x33, 0xfe, 0x0, 0x2e, 0xff, 0xf3, 0xe, 0xf3, + 0x3f, 0xe0, 0x2e, 0xff, 0xf3, 0x0, 0x8f, 0xff, + 0xff, 0x6e, 0xff, 0xf3, 0x0, 0x0, 0x8e, 0xff, + 0xff, 0xff, 0xf3, 0x0, 0x0, 0x0, 0x2, 0xef, + 0xff, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x2e, 0xff, + 0xff, 0x30, 0x0, 0x0, 0x8, 0xef, 0xff, 0xff, + 0xff, 0x30, 0x0, 0x8, 0xff, 0xff, 0xf6, 0xef, + 0xff, 0x30, 0x0, 0xef, 0x33, 0xfe, 0x2, 0xef, + 0xff, 0x30, 0xe, 0xf3, 0x3f, 0xe0, 0x2, 0xef, + 0xff, 0x30, 0x8f, 0xff, 0xf8, 0x0, 0x2, 0xdf, + 0xfd, 0x0, 0x8e, 0xe8, 0x0, 0x0, 0x0, 0x66, + 0x10, + + /* U+F0C5 "" */ + 0x0, 0x0, 0xdf, 0xff, 0xff, 0xd, 0x20, 0x0, + 0x0, 0xff, 0xff, 0xff, 0xf, 0xe2, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xf, 0xfd, 0xdf, 0xf0, 0xff, + 0xff, 0xff, 0x20, 0x0, 0xff, 0xf0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xdf, 0xff, + 0xff, 0xff, 0xfd, 0xff, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x0, 0xdf, 0xff, 0xff, 0xff, 0xfd, 0x0, 0x0, + + /* U+F0C7 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xc2, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, 0x20, 0xff, 0x0, + 0x0, 0x0, 0x1, 0xff, 0xe2, 0xff, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xfc, 0xff, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfb, 0x11, 0xbf, 0xff, 0xff, 0xff, + 0xff, 0xf1, 0x0, 0x1f, 0xff, 0xff, 0xff, 0xff, + 0xf1, 0x0, 0x1f, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x11, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, + + /* U+F0C9 "" */ + 0x12, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x12, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x21, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x12, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x21, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x12, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x12, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x21, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x12, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x21, + + /* U+F0E0 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0x9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, + 0xd2, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x2d, + 0xff, 0x62, 0xcf, 0xff, 0xff, 0xfc, 0x26, 0xff, + 0xff, 0xfa, 0x18, 0xff, 0xff, 0x81, 0xaf, 0xff, + 0xff, 0xff, 0xe3, 0x4d, 0xd4, 0x3e, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x81, 0x18, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + + /* U+F0E7 "" */ + 0x0, 0xdf, 0xff, 0xfd, 0x0, 0x0, 0x1, 0xff, + 0xff, 0xfc, 0x0, 0x0, 0x3, 0xff, 0xff, 0xf7, + 0x0, 0x0, 0x6, 0xff, 0xff, 0xf2, 0x0, 0x0, + 0x8, 0xff, 0xff, 0xd0, 0x0, 0x0, 0xa, 0xff, + 0xff, 0xff, 0xff, 0xd0, 0xc, 0xff, 0xff, 0xff, + 0xff, 0xa0, 0xe, 0xff, 0xff, 0xff, 0xff, 0x20, + 0xd, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xe0, 0x0, 0x0, 0x0, 0xe, 0xff, + 0x50, 0x0, 0x0, 0x0, 0x2f, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x5f, 0xf3, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x10, + 0x0, 0x0, 0x0, 0x0, 0xd7, 0x0, 0x0, 0x0, + + /* U+F0EA "" */ + 0x0, 0x4, 0xee, 0x40, 0x0, 0x0, 0x0, 0xdf, + 0xff, 0x99, 0xff, 0xfd, 0x0, 0x0, 0xff, 0xff, + 0x99, 0xff, 0xff, 0x0, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x0, 0xff, 0xff, 0x90, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xd, 0xff, 0xff, + 0xd, 0x20, 0xff, 0xff, 0xf, 0xff, 0xff, 0xf, + 0xe2, 0xff, 0xff, 0xf, 0xff, 0xff, 0xf, 0xfd, + 0xff, 0xff, 0xf, 0xff, 0xff, 0x20, 0x0, 0xff, + 0xff, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xf, 0xff, + 0xff, 0xff, 0xff, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0x0, 0x0, 0xd, 0xff, 0xff, 0xff, 0xfd, + + /* U+F0F3 "" */ + 0x0, 0x0, 0x0, 0xcc, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0xff, 0x30, 0x0, 0x0, 0x0, 0x1, + 0xbf, 0xff, 0xfc, 0x20, 0x0, 0x0, 0x1e, 0xff, + 0xff, 0xff, 0xe1, 0x0, 0x0, 0x9f, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x0, 0xef, 0xff, 0xff, 0xff, + 0xfd, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x1, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x3, 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0x8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x1e, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xe1, 0xcf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfc, 0xcf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xff, 0xe0, 0x0, + 0x0, 0x0, 0x0, 0x4, 0xee, 0x40, 0x0, 0x0, + + /* U+F11C "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x0, 0xf0, 0xf, 0x0, 0xf0, + 0xf, 0x0, 0xff, 0xff, 0x0, 0xf0, 0xf, 0x0, + 0xf0, 0xf, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x8, + 0x80, 0x88, 0x8, 0x80, 0x8f, 0xff, 0xff, 0xf8, + 0x8, 0x80, 0x88, 0x8, 0x80, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x0, 0xf0, 0x0, 0x0, 0x0, 0xf, 0x0, + 0xff, 0xff, 0x0, 0xf0, 0x0, 0x0, 0x0, 0xf, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf8, + + /* U+F124 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xaf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, + 0xcf, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xdf, 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x17, + 0xef, 0xff, 0xff, 0xff, 0x30, 0x0, 0x0, 0x18, + 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0, 0x0, 0x2a, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, 0x8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x60, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, + 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xfa, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xf2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0x80, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+F15B "" */ + 0xdf, 0xff, 0xff, 0xf0, 0xd2, 0x0, 0xff, 0xff, + 0xff, 0xf0, 0xfe, 0x20, 0xff, 0xff, 0xff, 0xf0, + 0xff, 0xe2, 0xff, 0xff, 0xff, 0xf0, 0xff, 0xfd, + 0xff, 0xff, 0xff, 0xf2, 0x0, 0x0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xfd, + + /* U+F1EB "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0x9c, 0xef, 0xfe, + 0xc9, 0x40, 0x0, 0x0, 0x0, 0x7, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x70, 0x0, 0x4, 0xdf, + 0xff, 0xfc, 0xa8, 0x8a, 0xcf, 0xff, 0xfd, 0x40, + 0x6f, 0xff, 0xd5, 0x0, 0x0, 0x0, 0x0, 0x5d, + 0xff, 0xf6, 0xcf, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0xfc, 0x1a, 0x30, 0x0, 0x5a, + 0xdf, 0xfd, 0xa5, 0x0, 0x3, 0xa1, 0x0, 0x0, + 0x4d, 0xff, 0xff, 0xff, 0xff, 0xd4, 0x0, 0x0, + 0x0, 0x5, 0xff, 0xfe, 0xa8, 0x8a, 0xef, 0xff, + 0x50, 0x0, 0x0, 0x1, 0xdf, 0x70, 0x0, 0x0, + 0x7, 0xfd, 0x10, 0x0, 0x0, 0x0, 0x12, 0x0, + 0x0, 0x0, 0x0, 0x21, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4e, 0xe4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xef, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xfe, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4e, 0xe4, 0x0, 0x0, 0x0, 0x0, + + /* U+F240 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0xff, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf, 0xff, + 0xff, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F241 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0xff, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, 0xf, 0xff, + 0xff, 0xf, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x0, 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0x0, 0xf, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F242 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0xff, 0xf, + 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xf, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, + 0xff, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F243 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0xff, 0xf, + 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xf, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xf, 0xff, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xf, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F244 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F287 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xfd, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0xcf, 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xb9, 0x29, 0xfe, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0x10, 0x2, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xdf, 0x80, 0xa, + 0x90, 0x0, 0x0, 0x0, 0x3, 0x70, 0x0, 0xdf, + 0xff, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x8f, + 0xd3, 0xf, 0xff, 0xfd, 0xcc, 0xdf, 0xdc, 0xcc, + 0xcc, 0xcd, 0xff, 0xb0, 0x8f, 0xfe, 0x10, 0x0, + 0xaa, 0x0, 0x0, 0x0, 0x4d, 0x40, 0x0, 0x46, + 0x10, 0x0, 0x1, 0xf2, 0x2, 0x33, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xb1, 0xcf, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x22, + 0x0, 0x0, 0x0, + + /* U+F293 "" */ + 0x0, 0x18, 0xdf, 0xfd, 0x92, 0x0, 0x2, 0xef, + 0xfb, 0xef, 0xff, 0x30, 0xd, 0xff, 0xfa, 0x2e, + 0xff, 0xe0, 0x4f, 0xff, 0xfa, 0x3, 0xff, 0xf5, + 0x9f, 0xfa, 0xfa, 0x35, 0x4f, 0xfa, 0xcf, 0xc0, + 0x8a, 0x3d, 0xb, 0xfd, 0xef, 0xfb, 0x3, 0x12, + 0x8f, 0xfe, 0xff, 0xff, 0xb0, 0x6, 0xff, 0xff, + 0xff, 0xff, 0xd1, 0x8, 0xff, 0xff, 0xef, 0xfd, + 0x11, 0x10, 0x9f, 0xff, 0xdf, 0xd1, 0x59, 0x3b, + 0xb, 0xfd, 0xaf, 0xd7, 0xfa, 0x38, 0x1d, 0xfb, + 0x5f, 0xff, 0xfa, 0x1, 0xdf, 0xf7, 0xd, 0xff, + 0xfa, 0x1d, 0xff, 0xf1, 0x3, 0xef, 0xfc, 0xdf, + 0xff, 0x50, 0x0, 0x18, 0xdf, 0xfe, 0xa3, 0x0, + + /* U+F2ED "" */ + 0x0, 0x0, 0x7f, 0xff, 0xf7, 0x0, 0x0, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0xf, 0xf9, 0x9f, 0x99, 0xf9, 0x9f, + 0xf0, 0xf, 0xf8, 0x8f, 0x88, 0xf8, 0x8f, 0xf0, + 0xf, 0xf8, 0x8f, 0x88, 0xf8, 0x8f, 0xf0, 0xf, + 0xf8, 0x8f, 0x88, 0xf8, 0x8f, 0xf0, 0xf, 0xf8, + 0x8f, 0x88, 0xf8, 0x8f, 0xf0, 0xf, 0xf8, 0x8f, + 0x88, 0xf8, 0x8f, 0xf0, 0xf, 0xf8, 0x8f, 0x88, + 0xf8, 0x8f, 0xf0, 0xf, 0xf9, 0x9f, 0x99, 0xf9, + 0x9f, 0xf0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + + /* U+F304 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xff, + 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x8a, 0x1d, + 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xfa, + 0x1d, 0xff, 0x70, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xfa, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x6f, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0xb, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0xdf, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0xe, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xde, 0xdb, 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F55A "" */ + 0x0, 0x0, 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xe4, 0x0, 0x1, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x0, 0x1d, 0xff, 0xff, + 0xfa, 0xef, 0xfe, 0xaf, 0xff, 0xff, 0x1, 0xdf, + 0xff, 0xff, 0xa0, 0x2e, 0xe2, 0xa, 0xff, 0xff, + 0x1d, 0xff, 0xff, 0xff, 0xe2, 0x2, 0x20, 0x2e, + 0xff, 0xff, 0xcf, 0xff, 0xff, 0xff, 0xfe, 0x20, + 0x2, 0xef, 0xff, 0xff, 0xcf, 0xff, 0xff, 0xff, + 0xfe, 0x20, 0x2, 0xef, 0xff, 0xff, 0x1d, 0xff, + 0xff, 0xff, 0xe2, 0x2, 0x20, 0x2e, 0xff, 0xff, + 0x1, 0xdf, 0xff, 0xff, 0xa0, 0x2e, 0xe2, 0xa, + 0xff, 0xff, 0x0, 0x1d, 0xff, 0xff, 0xfa, 0xef, + 0xfe, 0xaf, 0xff, 0xff, 0x0, 0x1, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x0, 0x0, + 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe4, + + /* U+F7C2 "" */ + 0x0, 0x8, 0xff, 0xff, 0xff, 0xe4, 0x0, 0x8f, + 0xff, 0xff, 0xff, 0xfe, 0x8, 0xf8, 0xf, 0xb, + 0x40, 0xff, 0x8f, 0xf8, 0xf, 0xb, 0x40, 0xff, + 0xff, 0xf8, 0xf, 0xb, 0x40, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x4e, 0xff, 0xff, 0xff, 0xff, 0xe4, + + /* U+F8A2 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xe0, 0x0, 0x0, 0x10, 0x0, 0x0, 0x0, 0x2, + 0xef, 0x10, 0x0, 0xbf, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xf1, 0x0, 0xcf, 0xf1, 0x0, 0x0, 0x0, + 0x7, 0xff, 0x11, 0xcf, 0xff, 0x77, 0x77, 0x77, + 0x77, 0xbf, 0xf1, 0xcf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x17, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe0, 0x7, 0xff, 0xf1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xff, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+FF1A "：" */ + 0x22, 0xe, 0xf1, 0xef, 0x10, 0x0, 0x0, 0x0, + 0x0, 0xef, 0x1e, 0xf2, 0x22, 0x0 +}; + + +/*--------------------- + * GLYPH DESCRIPTION + *--------------------*/ + +static const lv_font_fmt_txt_glyph_dsc_t glyph_dsc[] = { + {.bitmap_index = 0, .adv_w = 0, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0} /* id = 0 reserved */, + {.bitmap_index = 0, .adv_w = 65, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 0, .adv_w = 74, .box_w = 3, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 20, .adv_w = 94, .box_w = 6, .box_h = 5, .ofs_x = 0, .ofs_y = 7}, + {.bitmap_index = 35, .adv_w = 148, .box_w = 10, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 100, .adv_w = 156, .box_w = 10, .box_h = 17, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 185, .adv_w = 239, .box_w = 13, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 270, .adv_w = 190, .box_w = 12, .box_h = 14, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 354, .adv_w = 50, .box_w = 3, .box_h = 5, .ofs_x = 0, .ofs_y = 7}, + {.bitmap_index = 362, .adv_w = 89, .box_w = 5, .box_h = 16, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 402, .adv_w = 89, .box_w = 5, .box_h = 16, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 442, .adv_w = 109, .box_w = 7, .box_h = 7, .ofs_x = 0, .ofs_y = 5}, + {.bitmap_index = 467, .adv_w = 161, .box_w = 10, .box_h = 9, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 512, .adv_w = 76, .box_w = 3, .box_h = 4, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 518, .adv_w = 130, .box_w = 8, .box_h = 3, .ofs_x = 0, .ofs_y = 4}, + {.bitmap_index = 530, .adv_w = 78, .box_w = 3, .box_h = 2, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 533, .adv_w = 72, .box_w = 5, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 566, .adv_w = 147, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 625, .adv_w = 120, .box_w = 5, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 658, .adv_w = 144, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 717, .adv_w = 145, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 776, .adv_w = 147, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 835, .adv_w = 145, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 894, .adv_w = 147, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 953, .adv_w = 145, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1012, .adv_w = 149, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1071, .adv_w = 147, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1130, .adv_w = 76, .box_w = 3, .box_h = 10, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1145, .adv_w = 76, .box_w = 3, .box_h = 14, .ofs_x = 1, .ofs_y = -5}, + {.bitmap_index = 1166, .adv_w = 161, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1226, .adv_w = 157, .box_w = 9, .box_h = 6, .ofs_x = 0, .ofs_y = 2}, + {.bitmap_index = 1253, .adv_w = 159, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1313, .adv_w = 148, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1372, .adv_w = 244, .box_w = 15, .box_h = 14, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 1477, .adv_w = 181, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1555, .adv_w = 179, .box_w = 10, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1620, .adv_w = 196, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1698, .adv_w = 193, .box_w = 11, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1770, .adv_w = 179, .box_w = 10, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1835, .adv_w = 165, .box_w = 9, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1894, .adv_w = 208, .box_w = 13, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1979, .adv_w = 193, .box_w = 10, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2044, .adv_w = 70, .box_w = 2, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2057, .adv_w = 134, .box_w = 8, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 2109, .adv_w = 179, .box_w = 11, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2181, .adv_w = 150, .box_w = 8, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2233, .adv_w = 224, .box_w = 12, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2311, .adv_w = 193, .box_w = 10, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2376, .adv_w = 210, .box_w = 13, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 2461, .adv_w = 179, .box_w = 10, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2526, .adv_w = 210, .box_w = 13, .box_h = 17, .ofs_x = 0, .ofs_y = -5}, + {.bitmap_index = 2637, .adv_w = 193, .box_w = 11, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2709, .adv_w = 179, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 2781, .adv_w = 165, .box_w = 10, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 2846, .adv_w = 196, .box_w = 10, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2911, .adv_w = 183, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 2989, .adv_w = 255, .box_w = 16, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3093, .adv_w = 181, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3171, .adv_w = 179, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3249, .adv_w = 165, .box_w = 10, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3314, .adv_w = 72, .box_w = 4, .box_h = 16, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 3346, .adv_w = 72, .box_w = 5, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3379, .adv_w = 72, .box_w = 4, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3411, .adv_w = 127, .box_w = 8, .box_h = 7, .ofs_x = 0, .ofs_y = 6}, + {.bitmap_index = 3439, .adv_w = 159, .box_w = 11, .box_h = 1, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 3445, .adv_w = 85, .box_w = 4, .box_h = 3, .ofs_x = 0, .ofs_y = 10}, + {.bitmap_index = 3451, .adv_w = 150, .box_w = 9, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3496, .adv_w = 148, .box_w = 8, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3548, .adv_w = 136, .box_w = 9, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3593, .adv_w = 148, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3652, .adv_w = 150, .box_w = 9, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3697, .adv_w = 75, .box_w = 6, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3736, .adv_w = 150, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 3795, .adv_w = 148, .box_w = 8, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3847, .adv_w = 56, .box_w = 2, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3860, .adv_w = 56, .box_w = 4, .box_h = 16, .ofs_x = -1, .ofs_y = -4}, + {.bitmap_index = 3892, .adv_w = 134, .box_w = 8, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3944, .adv_w = 56, .box_w = 2, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3957, .adv_w = 222, .box_w = 13, .box_h = 10, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4022, .adv_w = 150, .box_w = 8, .box_h = 10, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4062, .adv_w = 150, .box_w = 9, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4107, .adv_w = 148, .box_w = 8, .box_h = 13, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 4159, .adv_w = 148, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 4218, .adv_w = 94, .box_w = 5, .box_h = 10, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4243, .adv_w = 139, .box_w = 8, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4283, .adv_w = 74, .box_w = 5, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4318, .adv_w = 148, .box_w = 8, .box_h = 10, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4358, .adv_w = 134, .box_w = 9, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4403, .adv_w = 193, .box_w = 13, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4468, .adv_w = 134, .box_w = 9, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4513, .adv_w = 134, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 4572, .adv_w = 134, .box_w = 9, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4617, .adv_w = 89, .box_w = 6, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 4665, .adv_w = 67, .box_w = 2, .box_h = 16, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 4681, .adv_w = 89, .box_w = 6, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 4729, .adv_w = 157, .box_w = 10, .box_h = 4, .ofs_x = 0, .ofs_y = 4}, + {.bitmap_index = 4749, .adv_w = 256, .box_w = 15, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4862, .adv_w = 256, .box_w = 16, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4974, .adv_w = 256, .box_w = 14, .box_h = 14, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 5072, .adv_w = 256, .box_w = 14, .box_h = 13, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 5163, .adv_w = 256, .box_w = 15, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5276, .adv_w = 256, .box_w = 16, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5388, .adv_w = 256, .box_w = 16, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5500, .adv_w = 256, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5620, .adv_w = 256, .box_w = 15, .box_h = 15, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 5733, .adv_w = 256, .box_w = 15, .box_h = 15, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 5846, .adv_w = 256, .box_w = 16, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5950, .adv_w = 256, .box_w = 15, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6063, .adv_w = 256, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6183, .adv_w = 256, .box_w = 16, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6295, .adv_w = 256, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6415, .adv_w = 256, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6535, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6663, .adv_w = 256, .box_w = 16, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6767, .adv_w = 256, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6887, .adv_w = 256, .box_w = 15, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7000, .adv_w = 256, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7120, .adv_w = 256, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7240, .adv_w = 256, .box_w = 16, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7344, .adv_w = 256, .box_w = 16, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7456, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7584, .adv_w = 256, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7704, .adv_w = 256, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7824, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7952, .adv_w = 256, .box_w = 16, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8064, .adv_w = 256, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 8184, .adv_w = 256, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 8304, .adv_w = 256, .box_w = 15, .box_h = 14, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 8409, .adv_w = 256, .box_w = 16, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 8545, .adv_w = 256, .box_w = 16, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 8641, .adv_w = 256, .box_w = 16, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8753, .adv_w = 256, .box_w = 16, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 8849, .adv_w = 176, .box_w = 11, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 8915, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 9043, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 9171, .adv_w = 288, .box_w = 18, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 9297, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 9425, .adv_w = 288, .box_w = 18, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 9533, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 9661, .adv_w = 128, .box_w = 8, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 9717, .adv_w = 192, .box_w = 12, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 9801, .adv_w = 288, .box_w = 18, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 9945, .adv_w = 256, .box_w = 16, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 10041, .adv_w = 176, .box_w = 11, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 10129, .adv_w = 224, .box_w = 10, .box_h = 16, .ofs_x = 2, .ofs_y = -2}, + {.bitmap_index = 10209, .adv_w = 224, .box_w = 14, .box_h = 18, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 10335, .adv_w = 224, .box_w = 14, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 10440, .adv_w = 224, .box_w = 14, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 10538, .adv_w = 224, .box_w = 10, .box_h = 16, .ofs_x = 2, .ofs_y = -2}, + {.bitmap_index = 10618, .adv_w = 224, .box_w = 16, .box_h = 14, .ofs_x = -1, .ofs_y = -1}, + {.bitmap_index = 10730, .adv_w = 160, .box_w = 10, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 10800, .adv_w = 160, .box_w = 10, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 10870, .adv_w = 224, .box_w = 14, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 10968, .adv_w = 224, .box_w = 14, .box_h = 4, .ofs_x = 0, .ofs_y = 4}, + {.bitmap_index = 10996, .adv_w = 288, .box_w = 18, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 11104, .adv_w = 320, .box_w = 20, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 11264, .adv_w = 288, .box_w = 20, .box_h = 16, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 11424, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 11552, .adv_w = 224, .box_w = 14, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 11622, .adv_w = 224, .box_w = 14, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 11692, .adv_w = 320, .box_w = 20, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 11832, .adv_w = 256, .box_w = 16, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 11928, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 12056, .adv_w = 256, .box_w = 17, .box_h = 17, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 12201, .adv_w = 224, .box_w = 15, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 12306, .adv_w = 224, .box_w = 14, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 12418, .adv_w = 224, .box_w = 14, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 12516, .adv_w = 224, .box_w = 14, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 12614, .adv_w = 256, .box_w = 16, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 12710, .adv_w = 160, .box_w = 12, .box_h = 16, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 12806, .adv_w = 224, .box_w = 14, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 12918, .adv_w = 224, .box_w = 14, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 13030, .adv_w = 288, .box_w = 18, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 13138, .adv_w = 256, .box_w = 18, .box_h = 18, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 13300, .adv_w = 192, .box_w = 12, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 13396, .adv_w = 320, .box_w = 20, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 13546, .adv_w = 320, .box_w = 20, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 13646, .adv_w = 320, .box_w = 20, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 13746, .adv_w = 320, .box_w = 20, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 13846, .adv_w = 320, .box_w = 20, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 13946, .adv_w = 320, .box_w = 20, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 14046, .adv_w = 320, .box_w = 21, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 14193, .adv_w = 224, .box_w = 12, .box_h = 16, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 14289, .adv_w = 224, .box_w = 14, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 14401, .adv_w = 256, .box_w = 17, .box_h = 17, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 14546, .adv_w = 320, .box_w = 20, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 14666, .adv_w = 192, .box_w = 12, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 14762, .adv_w = 258, .box_w = 17, .box_h = 11, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 14856, .adv_w = 192, .box_w = 3, .box_h = 9, .ofs_x = 3, .ofs_y = -1} +}; + +/*--------------------- + * CHARACTER MAPPING + *--------------------*/ + +static const uint16_t unicode_list_1[] = { + 0x0, 0x93, 0x1be, 0x1c1, 0x26c, 0x746, 0x74f, 0x8eb, + 0xb81, 0xbd3, 0xe37, 0xe6a, 0xed3, 0xfeb, 0x12ad, 0x1502, + 0x1534, 0x16c4, 0x1800, 0x19e5, 0x1bf8, 0x1c99, 0x24ff, 0x26b8, + 0x2b5b, 0x2c3f, 0x2ce4, 0x2e83, 0x2eed, 0x3f57, 0x3fcd, 0x4722, + 0x9fc5, 0x9fcc, 0x9fcf, 0x9fd0, 0x9fd1, 0x9fd5, 0x9fd7, 0x9fd9, + 0x9fdd, 0x9fe0, 0x9fe5, 0x9fea, 0x9feb, 0x9fec, 0xa002, 0xa007, + 0xa00c, 0xa00f, 0xa010, 0xa011, 0xa015, 0xa016, 0xa017, 0xa018, + 0xa02b, 0xa02c, 0xa032, 0xa034, 0xa035, 0xa038, 0xa03b, 0xa03c, + 0xa03d, 0xa03f, 0xa057, 0xa059, 0xa088, 0xa089, 0xa08b, 0xa08d, + 0xa0a4, 0xa0ab, 0xa0ae, 0xa0b7, 0xa0e0, 0xa0e8, 0xa11f, 0xa1af, + 0xa204, 0xa205, 0xa206, 0xa207, 0xa208, 0xa24b, 0xa257, 0xa2b1, + 0xa2c8, 0xa51e, 0xa786, 0xa866, 0xaede +}; + +/*Collect the unicode lists and glyph_id offsets*/ +static const lv_font_fmt_txt_cmap_t cmaps[] = +{ + { + .range_start = 32, .range_length = 95, .glyph_id_start = 1, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 20540, .range_length = 44767, .glyph_id_start = 96, + .unicode_list = unicode_list_1, .glyph_id_ofs_list = NULL, .list_length = 93, .type = LV_FONT_FMT_TXT_CMAP_SPARSE_TINY + } +}; + + + +/*-------------------- + * ALL CUSTOM DATA + *--------------------*/ + +#if LV_VERSION_CHECK(8, 0, 0) +/*Store all the custom data of the font*/ +static lv_font_fmt_txt_glyph_cache_t cache; +static const lv_font_fmt_txt_dsc_t font_dsc = { +#else +static lv_font_fmt_txt_dsc_t font_dsc = { +#endif + .glyph_bitmap = glyph_bitmap, + .glyph_dsc = glyph_dsc, + .cmaps = cmaps, + .kern_dsc = NULL, + .kern_scale = 0, + .cmap_num = 2, + .bpp = 4, + .kern_classes = 0, + .bitmap_format = 0, +#if LV_VERSION_CHECK(8, 0, 0) + .cache = &cache +#endif +}; + + +/*----------------- + * PUBLIC FONT + *----------------*/ + +/*Initialize a public general font descriptor*/ +#if LV_VERSION_CHECK(8, 0, 0) +const lv_font_t lv_font_MI_LanTing_Regular_16 = { +#else +lv_font_t lv_font_MI_LanTing_Regular_16 = { +#endif + .get_glyph_dsc = lv_font_get_glyph_dsc_fmt_txt, /*Function pointer to get glyph's data*/ + .get_glyph_bitmap = lv_font_get_bitmap_fmt_txt, /*Function pointer to get glyph's bitmap*/ + .line_height = 16, /*The maximum line height required by the font default: (f.src.ascent - f.src.descent)*/ + .base_line = 3, /*Baseline measured from the bottom of the line*/ +#if !(LVGL_VERSION_MAJOR == 6 && LVGL_VERSION_MINOR == 0) + .subpx = LV_FONT_SUBPX_NONE, +#endif +#if LV_VERSION_CHECK(7, 4, 0) || LVGL_VERSION_MAJOR >= 8 + .underline_position = -2, + .underline_thickness = 1, +#endif + .dsc = &font_dsc /*The custom font data. Will be accessed by `get_glyph_bitmap/dsc` */ +}; + + + +#endif /*#if LV_FONT_MI_LANTING_REGULAR_16*/ + diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_18.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_18.c new file mode 100644 index 0000000000000000000000000000000000000000..ad5b70d8f70ff4b43c2ca61fa59fdb816a2886d1 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_18.c @@ -0,0 +1,2979 @@ +/* + * Copyright 2024 NXP + * NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in + * accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, + * activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to + * comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license + * terms, then you may not retain, install, activate or otherwise use the software. + */ +/******************************************************************************* + * Size: 18 px + * Bpp: 4 + * Opts: --user-data-dir=C:\Users\hp\AppData\Roaming\gui-guider --app-path=C:\NXP\GUI-Guider-1.7.2-GA\resources\app.asar --no-sandbox --no-zygote --lang=zh-CN --device-scale-factor=1.5 --num-raster-threads=4 --enable-main-frame-before-activation --renderer-client-id=5 --time-ticks-at-unix-epoch=-1732015070561205 --launch-time-ticks=65380923608 --mojo-platform-channel-handle=3108 --field-trial-handle=1864,i,17219279099561217522,18026807573185265005,131072 --disable-features=SpareRendererForSitePerProcess,WinRetrieveSuggestionsOnlyOnDemand /prefetch:1 + ******************************************************************************/ + +#ifdef LV_LVGL_H_INCLUDE_SIMPLE +#include "lvgl.h" +#else +#include "lvgl.h" +#endif + +#ifndef LV_FONT_MI_LANTING_REGULAR_18 +#define LV_FONT_MI_LANTING_REGULAR_18 1 +#endif + +#if LV_FONT_MI_LANTING_REGULAR_18 + +/*----------------- + * BITMAPS + *----------------*/ + +/*Store the image of the glyphs*/ +static LV_ATTRIBUTE_LARGE_CONST const uint8_t glyph_bitmap[] = { + /* U+0020 " " */ + + /* U+0021 "!" */ + 0x4f, 0x93, 0xf8, 0x3f, 0x72, 0xf7, 0x2f, 0x61, + 0xf6, 0x1f, 0x50, 0xf5, 0xf, 0x40, 0xf3, 0x7, + 0x10, 0x0, 0x0, 0x2, 0xf7, 0x2f, 0x70, + + /* U+0022 "\"" */ + 0xf, 0xa0, 0xfc, 0xf, 0x90, 0xeb, 0xe, 0x80, + 0xda, 0xd, 0x70, 0xc9, 0xc, 0x60, 0xa8, 0x0, + 0x0, 0x0, + + /* U+0023 "#" */ + 0x0, 0x0, 0xe4, 0x4, 0xe0, 0x0, 0x0, 0xf, + 0x10, 0x7b, 0x0, 0x0, 0x3, 0xf0, 0x9, 0x90, + 0x0, 0x0, 0x6c, 0x0, 0xc6, 0x0, 0x0, 0x8, + 0xa0, 0xe, 0x40, 0x0, 0xcf, 0xff, 0xff, 0xff, + 0xf3, 0x2, 0x2e, 0x62, 0x6e, 0x22, 0x0, 0x1, + 0xf1, 0x6, 0xb0, 0x0, 0x0, 0x3f, 0x0, 0x99, + 0x0, 0x0, 0x6, 0xc0, 0xb, 0x60, 0x0, 0xaf, + 0xff, 0xff, 0xff, 0xf5, 0x2, 0x2d, 0x72, 0x4f, + 0x32, 0x0, 0x0, 0xf2, 0x5, 0xd0, 0x0, 0x0, + 0x3f, 0x0, 0x99, 0x0, 0x0, 0x6, 0xc0, 0xc, + 0x60, 0x0, 0x0, + + /* U+0024 "$" */ + 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x0, 0x14, + 0xf4, 0x0, 0x0, 0x0, 0x7f, 0xff, 0xfe, 0x40, + 0x0, 0x4f, 0x71, 0xe2, 0xcf, 0x10, 0xa, 0xb0, + 0xe, 0x1, 0xf8, 0x0, 0xd8, 0x0, 0xe0, 0x8, + 0x70, 0xb, 0xd0, 0xe, 0x0, 0x0, 0x0, 0x3f, + 0xd6, 0xe0, 0x0, 0x0, 0x0, 0x2b, 0xff, 0xc6, + 0x0, 0x0, 0x0, 0x1, 0xfb, 0xfc, 0x0, 0x0, + 0x0, 0xe, 0x3, 0xe9, 0x0, 0x40, 0x0, 0xe0, + 0x5, 0xf0, 0x2f, 0x30, 0xe, 0x0, 0x3f, 0x10, + 0xda, 0x0, 0xe0, 0x8, 0xe0, 0x3, 0xf9, 0x1e, + 0x16, 0xf5, 0x0, 0x3, 0xbe, 0xff, 0xd5, 0x0, + 0x0, 0x0, 0xe, 0x10, 0x0, 0x0, 0x0, 0x0, + 0xe0, 0x0, 0x0, + + /* U+0025 "%" */ + 0x8, 0xee, 0x80, 0x0, 0x0, 0xb9, 0x0, 0x6, + 0xe4, 0x4e, 0x60, 0x0, 0x3f, 0x10, 0x0, 0xb6, + 0x0, 0x7b, 0x0, 0xb, 0x90, 0x0, 0xd, 0x40, + 0x5, 0xc0, 0x3, 0xf1, 0x0, 0x0, 0xb6, 0x0, + 0x6b, 0x0, 0xb9, 0x0, 0x0, 0x5, 0xd1, 0x1d, + 0x60, 0x3f, 0x20, 0x0, 0x0, 0x7, 0xee, 0x90, + 0xb, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xf2, 0x8, 0xdd, 0x50, 0x0, 0x0, 0x0, 0xb9, + 0x6, 0xe4, 0x5f, 0x20, 0x0, 0x0, 0x3f, 0x20, + 0xc6, 0x0, 0x98, 0x0, 0x0, 0xb, 0x90, 0xe, + 0x30, 0x6, 0xa0, 0x0, 0x3, 0xf2, 0x0, 0xe3, + 0x0, 0x6b, 0x0, 0x0, 0xb9, 0x0, 0xb, 0x60, + 0x9, 0x90, 0x0, 0x3f, 0x20, 0x0, 0x5e, 0x55, + 0xf3, 0x0, 0xb, 0x90, 0x0, 0x0, 0x7e, 0xd6, + 0x0, + + /* U+0026 "&" */ + 0x0, 0x1, 0xbf, 0xd7, 0x0, 0x0, 0x0, 0x0, + 0xd, 0xa3, 0x5f, 0x60, 0x0, 0x0, 0x0, 0x4f, + 0x0, 0x9, 0xc0, 0x0, 0x0, 0x0, 0x5e, 0x0, + 0x8, 0xd0, 0x0, 0x0, 0x0, 0x1f, 0x20, 0xd, + 0x90, 0x0, 0x0, 0x0, 0x9, 0xb1, 0xbd, 0x10, + 0x0, 0x0, 0x0, 0x1, 0xff, 0xa1, 0x0, 0x0, + 0x0, 0x0, 0x3e, 0xcf, 0x60, 0x0, 0xaa, 0x0, + 0x3, 0xf8, 0x4, 0xf5, 0x0, 0xc9, 0x0, 0xc, + 0xb0, 0x0, 0x5f, 0x50, 0xf5, 0x0, 0x1f, 0x40, + 0x0, 0x6, 0xfa, 0xf0, 0x0, 0x1f, 0x40, 0x0, + 0x0, 0x7f, 0xb0, 0x0, 0xd, 0xa0, 0x0, 0x0, + 0xbf, 0xf9, 0x0, 0x5, 0xfa, 0x54, 0x7e, 0xe2, + 0x6f, 0xb0, 0x0, 0x5c, 0xff, 0xc7, 0x0, 0x5, + 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+0027 "'" */ + 0x1f, 0xa0, 0xf8, 0xf, 0x70, 0xe6, 0xc, 0x50, + 0x0, + + /* U+0028 "(" */ + 0x0, 0xc, 0x60, 0x6, 0xc0, 0x0, 0xf3, 0x0, + 0x7c, 0x0, 0xe, 0x60, 0x2, 0xf1, 0x0, 0x7d, + 0x0, 0x9, 0xc0, 0x0, 0xba, 0x0, 0xb, 0xa0, + 0x0, 0x9b, 0x0, 0x6, 0xd0, 0x0, 0x2f, 0x0, + 0x0, 0xe4, 0x0, 0x7, 0xb0, 0x0, 0x1f, 0x20, + 0x0, 0x7b, 0x0, 0x0, 0xc5, + + /* U+0029 ")" */ + 0x1e, 0x30, 0x0, 0x5, 0xd0, 0x0, 0x0, 0xc6, + 0x0, 0x0, 0x5d, 0x0, 0x0, 0xe, 0x40, 0x0, + 0xa, 0x90, 0x0, 0x7, 0xd0, 0x0, 0x5, 0xf0, + 0x0, 0x4, 0xf1, 0x0, 0x3, 0xf1, 0x0, 0x4, + 0xf0, 0x0, 0x6, 0xd0, 0x0, 0xa, 0x80, 0x0, + 0xe, 0x40, 0x0, 0x4d, 0x0, 0x0, 0xb6, 0x0, + 0x4, 0xd0, 0x0, 0xe, 0x30, 0x0, + + /* U+002A "*" */ + 0x0, 0xf, 0x80, 0x0, 0x0, 0xc, 0x50, 0x10, + 0x4f, 0x8b, 0x6b, 0xd0, 0x15, 0x8f, 0xc6, 0x40, + 0x0, 0xa9, 0xe3, 0x0, 0x7, 0xf1, 0x7f, 0x20, + 0x1, 0x50, 0x6, 0x0, + + /* U+002B "+" */ + 0x0, 0x0, 0xa4, 0x0, 0x0, 0x0, 0x0, 0xe5, + 0x0, 0x0, 0x0, 0x0, 0xe5, 0x0, 0x0, 0x0, + 0x0, 0xe5, 0x0, 0x0, 0x1, 0x11, 0xe6, 0x11, + 0x10, 0xef, 0xff, 0xff, 0xff, 0xf5, 0x34, 0x44, + 0xe8, 0x44, 0x41, 0x0, 0x0, 0xe5, 0x0, 0x0, + 0x0, 0x0, 0xe5, 0x0, 0x0, 0x0, 0x0, 0xe5, + 0x0, 0x0, + + /* U+002D "-" */ + 0x11, 0x11, 0x11, 0x10, 0xff, 0xff, 0xff, 0xf1, + 0x44, 0x44, 0x44, 0x40, + + /* U+002E "." */ + 0x2, 0x23, 0xfd, 0x3f, 0xd0, + + /* U+002F "/" */ + 0x0, 0x2, 0xf0, 0x0, 0x6, 0xc0, 0x0, 0xb, + 0x80, 0x0, 0xf, 0x30, 0x0, 0x3f, 0x0, 0x0, + 0x7b, 0x0, 0x0, 0xb7, 0x0, 0x0, 0xf3, 0x0, + 0x4, 0xe0, 0x0, 0x8, 0xa0, 0x0, 0xc, 0x60, + 0x0, 0x1f, 0x20, 0x0, 0x5e, 0x0, 0x0, 0x99, + 0x0, 0x0, 0xd5, 0x0, 0x0, + + /* U+0030 "0" */ + 0x0, 0x8, 0xef, 0xb3, 0x0, 0x0, 0x9f, 0x85, + 0xbf, 0x20, 0x3, 0xf4, 0x0, 0xc, 0xc0, 0xa, + 0xc0, 0x0, 0x4, 0xf2, 0xe, 0x70, 0x0, 0x0, + 0xe6, 0xf, 0x40, 0x0, 0x0, 0xc8, 0x1f, 0x30, + 0x0, 0x0, 0xaa, 0x2f, 0x20, 0x0, 0x0, 0x9b, + 0x1f, 0x30, 0x0, 0x0, 0xaa, 0xf, 0x40, 0x0, + 0x0, 0xc8, 0xe, 0x70, 0x0, 0x0, 0xe6, 0xa, + 0xc0, 0x0, 0x3, 0xf2, 0x4, 0xf4, 0x0, 0xb, + 0xc0, 0x0, 0xaf, 0x75, 0xbf, 0x30, 0x0, 0x8, + 0xef, 0xc3, 0x0, + + /* U+0031 "1" */ + 0x0, 0x4e, 0xa1, 0xaf, 0xfa, 0xad, 0x4a, 0xa4, + 0x0, 0xaa, 0x0, 0xa, 0xa0, 0x0, 0xaa, 0x0, + 0xa, 0xa0, 0x0, 0xaa, 0x0, 0xa, 0xa0, 0x0, + 0xaa, 0x0, 0xa, 0xa0, 0x0, 0xaa, 0x0, 0xa, + 0xa0, 0x0, 0xaa, 0x0, 0xa, 0xa0, + + /* U+0032 "2" */ + 0x0, 0x2b, 0xff, 0xb2, 0x0, 0x2, 0xfd, 0x77, + 0xcf, 0x10, 0xb, 0xc0, 0x0, 0xc, 0x90, 0xf, + 0x50, 0x0, 0x6, 0xe0, 0x6, 0x10, 0x0, 0x6, + 0xf0, 0x0, 0x0, 0x0, 0xa, 0xc0, 0x0, 0x0, + 0x0, 0x3f, 0x50, 0x0, 0x0, 0x0, 0xdb, 0x0, + 0x0, 0x0, 0xb, 0xe1, 0x0, 0x0, 0x0, 0x8f, + 0x30, 0x0, 0x0, 0x5, 0xf6, 0x0, 0x0, 0x0, + 0x2f, 0x90, 0x0, 0x0, 0x1, 0xec, 0x0, 0x0, + 0x0, 0xc, 0xf6, 0x44, 0x44, 0x40, 0x1f, 0xff, + 0xff, 0xff, 0xf3, + + /* U+0033 "3" */ + 0x0, 0x19, 0xef, 0xc3, 0x0, 0x0, 0xdd, 0x65, + 0xaf, 0x50, 0x8, 0xd0, 0x0, 0x9, 0xe0, 0x6, + 0x40, 0x0, 0x3, 0xf1, 0x0, 0x0, 0x0, 0x4, + 0xf0, 0x0, 0x0, 0x0, 0x8, 0xb0, 0x0, 0x0, + 0x1, 0x6b, 0x10, 0x0, 0x4, 0xff, 0xfd, 0x30, + 0x0, 0x1, 0x34, 0x9f, 0xe0, 0x0, 0x0, 0x0, + 0x7, 0xf4, 0x0, 0x0, 0x0, 0x0, 0xf6, 0x2, + 0x0, 0x0, 0x0, 0xf5, 0x1f, 0x70, 0x0, 0x5, + 0xf1, 0x6, 0xfa, 0x55, 0x8f, 0x70, 0x0, 0x4b, + 0xef, 0xc5, 0x0, + + /* U+0034 "4" */ + 0x0, 0x0, 0x0, 0x6e, 0x0, 0x0, 0x0, 0x0, + 0x1e, 0xe0, 0x0, 0x0, 0x0, 0x9, 0xfe, 0x0, + 0x0, 0x0, 0x3, 0xfa, 0xe0, 0x0, 0x0, 0x0, + 0xca, 0x6e, 0x0, 0x0, 0x0, 0x6f, 0x16, 0xe0, + 0x0, 0x0, 0x1e, 0x70, 0x6e, 0x0, 0x0, 0x9, + 0xd0, 0x6, 0xe0, 0x0, 0x3, 0xf4, 0x0, 0x6e, + 0x0, 0x0, 0xcb, 0x0, 0x6, 0xe0, 0x0, 0x6f, + 0x20, 0x0, 0x6e, 0x0, 0xc, 0xff, 0xff, 0xff, + 0xff, 0xf2, 0x23, 0x33, 0x33, 0x8f, 0x33, 0x0, + 0x0, 0x0, 0x6, 0xe0, 0x0, 0x0, 0x0, 0x0, + 0x6e, 0x0, 0x0, + + /* U+0035 "5" */ + 0x0, 0xff, 0xff, 0xff, 0xc0, 0x1, 0xf6, 0x44, + 0x44, 0x30, 0x3, 0xf1, 0x0, 0x0, 0x0, 0x4, + 0xf0, 0x0, 0x0, 0x0, 0x6, 0xe0, 0x0, 0x0, + 0x0, 0x7, 0xd0, 0x0, 0x0, 0x0, 0x8, 0xca, + 0xef, 0xc4, 0x0, 0xa, 0xf9, 0x45, 0xaf, 0x50, + 0x7, 0x60, 0x0, 0xa, 0xd0, 0x0, 0x0, 0x0, + 0x3, 0xf2, 0x0, 0x0, 0x0, 0x1, 0xf3, 0x0, + 0x0, 0x0, 0x3, 0xf2, 0x8, 0x40, 0x0, 0xa, + 0xd0, 0x8, 0xf8, 0x56, 0xbf, 0x30, 0x0, 0x6c, + 0xff, 0xb3, 0x0, + + /* U+0036 "6" */ + 0x0, 0x7, 0xdf, 0xd6, 0x0, 0x0, 0x9f, 0x85, + 0x9f, 0x70, 0x3, 0xf4, 0x0, 0x6, 0xf1, 0x8, + 0xc0, 0x0, 0x0, 0x81, 0xc, 0x80, 0x0, 0x0, + 0x0, 0xf, 0x50, 0x0, 0x0, 0x0, 0xf, 0x48, + 0xef, 0xd5, 0x0, 0x1f, 0xdd, 0x64, 0x9f, 0x60, + 0x2f, 0xd0, 0x0, 0x7, 0xe1, 0x1f, 0x60, 0x0, + 0x0, 0xf5, 0xf, 0x40, 0x0, 0x0, 0xe7, 0xd, + 0x60, 0x0, 0x0, 0xf5, 0x8, 0xc0, 0x0, 0x7, + 0xf1, 0x0, 0xec, 0x65, 0x9f, 0x70, 0x0, 0x1a, + 0xef, 0xc4, 0x0, + + /* U+0037 "7" */ + 0xff, 0xff, 0xff, 0xff, 0x24, 0x44, 0x44, 0x49, + 0xf0, 0x0, 0x0, 0x0, 0xca, 0x0, 0x0, 0x0, + 0x2f, 0x30, 0x0, 0x0, 0x8, 0xd0, 0x0, 0x0, + 0x0, 0xe7, 0x0, 0x0, 0x0, 0x4f, 0x10, 0x0, + 0x0, 0xa, 0xb0, 0x0, 0x0, 0x1, 0xf5, 0x0, + 0x0, 0x0, 0x7e, 0x0, 0x0, 0x0, 0xd, 0x90, + 0x0, 0x0, 0x3, 0xf3, 0x0, 0x0, 0x0, 0x9d, + 0x0, 0x0, 0x0, 0xf, 0x70, 0x0, 0x0, 0x5, + 0xf1, 0x0, 0x0, 0x0, + + /* U+0038 "8" */ + 0x0, 0x8, 0xef, 0xc3, 0x0, 0x0, 0xbe, 0x75, + 0xbf, 0x30, 0x5, 0xf2, 0x0, 0xa, 0xd0, 0x9, + 0xc0, 0x0, 0x4, 0xf0, 0x9, 0xc0, 0x0, 0x4, + 0xf0, 0x5, 0xf1, 0x0, 0x9, 0xd0, 0x0, 0xdb, + 0x21, 0x7f, 0x50, 0x0, 0x3f, 0xff, 0xfa, 0x0, + 0x3, 0xfb, 0x54, 0x7e, 0xa0, 0xd, 0x90, 0x0, + 0x2, 0xf5, 0x2f, 0x20, 0x0, 0x0, 0xb9, 0x3f, + 0x20, 0x0, 0x0, 0xba, 0xf, 0x90, 0x0, 0x2, + 0xf6, 0x6, 0xfb, 0x65, 0x8e, 0xc0, 0x0, 0x3b, + 0xff, 0xd7, 0x0, + + /* U+0039 "9" */ + 0x0, 0x9, 0xef, 0xc3, 0x0, 0x0, 0xde, 0x65, + 0xbf, 0x30, 0x7, 0xe1, 0x0, 0xc, 0xc0, 0xe, + 0x80, 0x0, 0x4, 0xf1, 0x1f, 0x40, 0x0, 0x1, + 0xf5, 0x1f, 0x40, 0x0, 0x0, 0xf6, 0xf, 0x60, + 0x0, 0x3, 0xf7, 0xb, 0xc0, 0x0, 0x9, 0xf6, + 0x3, 0xf8, 0x11, 0x8f, 0xf5, 0x0, 0x4e, 0xff, + 0xe5, 0xf4, 0x0, 0x0, 0x22, 0x1, 0xf2, 0x0, + 0x0, 0x0, 0x5, 0xf0, 0xc, 0x40, 0x0, 0xd, + 0xa0, 0x7, 0xf8, 0x55, 0xce, 0x10, 0x0, 0x5c, + 0xfe, 0xb2, 0x0, + + /* U+003A ":" */ + 0x4f, 0xc4, 0xfc, 0x2, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2, 0x14, 0xfc, 0x4f, + 0xc0, + + /* U+003B ";" */ + 0x4f, 0xc4, 0xfc, 0x2, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2, 0x14, 0xfc, 0x4f, + 0xc0, 0x3b, 0x7, 0x72, 0xd1, 0x2, 0x0, + + /* U+003C "<" */ + 0x0, 0x0, 0x0, 0x0, 0x43, 0x0, 0x0, 0x0, + 0x1a, 0xf4, 0x0, 0x0, 0x7, 0xfd, 0x40, 0x0, + 0x3, 0xdf, 0x70, 0x0, 0x1, 0x9f, 0x91, 0x0, + 0x0, 0x6e, 0xc3, 0x0, 0x0, 0x0, 0xea, 0x0, + 0x0, 0x0, 0x0, 0x7f, 0xb2, 0x0, 0x0, 0x0, + 0x2, 0xbf, 0x80, 0x0, 0x0, 0x0, 0x5, 0xee, + 0x50, 0x0, 0x0, 0x0, 0x9, 0xfc, 0x20, 0x0, + 0x0, 0x0, 0x3c, 0xf3, 0x0, 0x0, 0x0, 0x0, + 0x74, + + /* U+003D "=" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xff, 0xff, + 0xff, 0xf1, 0x33, 0x33, 0x33, 0x33, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0x11, 0x11, 0x11, + 0x10, 0xef, 0xff, 0xff, 0xff, 0xf1, 0x33, 0x33, + 0x33, 0x33, 0x30, + + /* U+003E ">" */ + 0x70, 0x0, 0x0, 0x0, 0x0, 0xed, 0x40, 0x0, + 0x0, 0x0, 0x1a, 0xfa, 0x10, 0x0, 0x0, 0x0, + 0x3c, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x6e, 0xd3, + 0x0, 0x0, 0x0, 0x0, 0x9f, 0x91, 0x0, 0x0, + 0x0, 0x4, 0xf4, 0x0, 0x0, 0x0, 0x8f, 0xb1, + 0x0, 0x0, 0x5e, 0xe5, 0x0, 0x0, 0x2b, 0xf9, + 0x0, 0x0, 0x8, 0xfc, 0x30, 0x0, 0x0, 0xdf, + 0x60, 0x0, 0x0, 0x0, 0x91, 0x0, 0x0, 0x0, + 0x0, + + /* U+003F "?" */ + 0x0, 0x18, 0xdf, 0xd7, 0x0, 0x1, 0xde, 0x64, + 0x7f, 0xb0, 0xa, 0xe1, 0x0, 0x5, 0xf4, 0xf, + 0x70, 0x0, 0x0, 0xf7, 0x1, 0x10, 0x0, 0x0, + 0xf8, 0x0, 0x0, 0x0, 0x6, 0xf3, 0x0, 0x0, + 0x0, 0x4f, 0xa0, 0x0, 0x0, 0x5, 0xfa, 0x0, + 0x0, 0x0, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x7e, + 0x0, 0x0, 0x0, 0x0, 0x9b, 0x0, 0x0, 0x0, + 0x0, 0x22, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xab, 0x0, 0x0, 0x0, 0x0, + 0xde, 0x0, 0x0, + + /* U+0040 "@" */ + 0x0, 0x0, 0x17, 0xcf, 0xfd, 0x92, 0x0, 0x0, + 0x0, 0x7, 0xfc, 0x73, 0x35, 0xaf, 0x70, 0x0, + 0x0, 0x9f, 0x50, 0x0, 0x0, 0x4, 0xe7, 0x0, + 0x6, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x5f, 0x10, + 0xe, 0x70, 0x1, 0xae, 0xe6, 0xf0, 0xc, 0x80, + 0x6e, 0x0, 0x1e, 0xa3, 0x4e, 0xe0, 0x7, 0xc0, + 0xba, 0x0, 0xab, 0x0, 0x9, 0xc0, 0x3, 0xf0, + 0xd7, 0x0, 0xf4, 0x0, 0x8, 0xa0, 0x2, 0xf1, + 0xf5, 0x4, 0xf1, 0x0, 0xa, 0x80, 0x3, 0xf0, + 0xd5, 0x5, 0xf0, 0x0, 0xe, 0x60, 0x5, 0xc0, + 0xa7, 0x3, 0xf0, 0x0, 0x5f, 0x50, 0xb, 0x60, + 0x6c, 0x0, 0xd6, 0x4, 0xcb, 0x80, 0x7d, 0x0, + 0xe, 0x40, 0x3d, 0xfc, 0x24, 0xff, 0xb1, 0x0, + 0x5, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, + 0x0, 0x6f, 0x83, 0x0, 0x0, 0x26, 0xba, 0x0, + 0x0, 0x2, 0x9e, 0xff, 0xff, 0xc8, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x1, 0x10, 0x0, 0x0, 0x0, + + /* U+0041 "A" */ + 0x0, 0x0, 0x9, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xfe, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x5e, + 0x5f, 0x10, 0x0, 0x0, 0x0, 0xb, 0x90, 0xe6, + 0x0, 0x0, 0x0, 0x1, 0xf4, 0x9, 0xc0, 0x0, + 0x0, 0x0, 0x7e, 0x0, 0x3f, 0x20, 0x0, 0x0, + 0xd, 0x90, 0x0, 0xd8, 0x0, 0x0, 0x3, 0xf3, + 0x0, 0x8, 0xe0, 0x0, 0x0, 0x9e, 0x11, 0x11, + 0x3f, 0x40, 0x0, 0xe, 0xff, 0xff, 0xff, 0xfa, + 0x0, 0x4, 0xf5, 0x44, 0x44, 0x48, 0xf1, 0x0, + 0xac, 0x0, 0x0, 0x0, 0x1f, 0x60, 0x1f, 0x60, + 0x0, 0x0, 0x0, 0xbc, 0x6, 0xf1, 0x0, 0x0, + 0x0, 0x6, 0xf2, 0xcb, 0x0, 0x0, 0x0, 0x0, + 0xf, 0x80, + + /* U+0042 "B" */ + 0x9f, 0xff, 0xff, 0xd8, 0x10, 0x9, 0xe6, 0x66, + 0x68, 0xee, 0x10, 0x9d, 0x0, 0x0, 0x1, 0xe9, + 0x9, 0xd0, 0x0, 0x0, 0xa, 0xe0, 0x9d, 0x0, + 0x0, 0x0, 0xad, 0x9, 0xd0, 0x0, 0x0, 0x1e, + 0x90, 0x9d, 0x22, 0x22, 0x5c, 0xd1, 0x9, 0xff, + 0xff, 0xff, 0xc2, 0x0, 0x9d, 0x55, 0x55, 0x6b, + 0xf6, 0x9, 0xd0, 0x0, 0x0, 0x7, 0xf2, 0x9d, + 0x0, 0x0, 0x0, 0xf, 0x79, 0xd0, 0x0, 0x0, + 0x0, 0xf8, 0x9d, 0x0, 0x0, 0x0, 0x6f, 0x39, + 0xd4, 0x44, 0x45, 0x9f, 0x90, 0x9f, 0xff, 0xff, + 0xfd, 0x70, 0x0, + + /* U+0043 "C" */ + 0x0, 0x5, 0xbe, 0xfd, 0x81, 0x0, 0x0, 0x9f, + 0xb5, 0x48, 0xfd, 0x10, 0x7, 0xf6, 0x0, 0x0, + 0x3f, 0xd0, 0x1f, 0x90, 0x0, 0x0, 0x7, 0xf6, + 0x7f, 0x20, 0x0, 0x0, 0x0, 0x61, 0xbd, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xea, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xea, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcc, 0x0, + 0x0, 0x0, 0x0, 0x20, 0x7f, 0x10, 0x0, 0x0, + 0x0, 0xfc, 0x1f, 0x80, 0x0, 0x0, 0x6, 0xf7, + 0x8, 0xf5, 0x0, 0x0, 0x2f, 0xe1, 0x0, 0x9f, + 0xb6, 0x69, 0xfe, 0x30, 0x0, 0x4, 0xae, 0xfd, + 0x81, 0x0, + + /* U+0044 "D" */ + 0x8f, 0xff, 0xff, 0xea, 0x30, 0x0, 0x8f, 0x55, + 0x55, 0x7c, 0xf7, 0x0, 0x8f, 0x0, 0x0, 0x0, + 0x7f, 0x50, 0x8f, 0x0, 0x0, 0x0, 0xa, 0xe0, + 0x8f, 0x0, 0x0, 0x0, 0x3, 0xf4, 0x8f, 0x0, + 0x0, 0x0, 0x0, 0xf8, 0x8f, 0x0, 0x0, 0x0, + 0x0, 0xda, 0x8f, 0x0, 0x0, 0x0, 0x0, 0xcb, + 0x8f, 0x0, 0x0, 0x0, 0x0, 0xca, 0x8f, 0x0, + 0x0, 0x0, 0x0, 0xf8, 0x8f, 0x0, 0x0, 0x0, + 0x3, 0xf4, 0x8f, 0x0, 0x0, 0x0, 0xa, 0xe0, + 0x8f, 0x0, 0x0, 0x0, 0x6f, 0x60, 0x8f, 0x44, + 0x45, 0x7c, 0xf8, 0x0, 0x8f, 0xff, 0xff, 0xea, + 0x30, 0x0, + + /* U+0045 "E" */ + 0x7f, 0xff, 0xff, 0xff, 0xff, 0x47, 0xf5, 0x55, + 0x55, 0x55, 0x51, 0x7f, 0x0, 0x0, 0x0, 0x0, + 0x7, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0x0, + 0x0, 0x0, 0x0, 0x7, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0x7f, 0x11, 0x11, 0x11, 0x10, 0x7, 0xff, + 0xff, 0xff, 0xff, 0xc0, 0x7f, 0x44, 0x44, 0x44, + 0x43, 0x7, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x7f, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xf5, 0x55, 0x55, 0x55, 0x53, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0xa0, + + /* U+0046 "F" */ + 0x7f, 0xff, 0xff, 0xff, 0xfb, 0x7f, 0x55, 0x55, + 0x55, 0x53, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x7f, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0, + 0x0, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x7f, 0x11, + 0x11, 0x11, 0x0, 0x7f, 0xff, 0xff, 0xff, 0xb0, + 0x7f, 0x44, 0x44, 0x44, 0x20, 0x7f, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x7f, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0, + 0x0, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x7f, 0x0, + 0x0, 0x0, 0x0, + + /* U+0047 "G" */ + 0x0, 0x4, 0xbe, 0xfd, 0xb4, 0x0, 0x0, 0x9, + 0xfb, 0x64, 0x6b, 0xfb, 0x0, 0x6, 0xf7, 0x0, + 0x0, 0x6, 0xfa, 0x0, 0xfa, 0x0, 0x0, 0x0, + 0xa, 0xf3, 0x6f, 0x20, 0x0, 0x0, 0x0, 0x13, + 0xa, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdb, + 0x0, 0x0, 0x1, 0x11, 0x11, 0xe, 0xa0, 0x0, + 0x4, 0xff, 0xff, 0xf8, 0xdb, 0x0, 0x0, 0x14, + 0x44, 0x4e, 0x8a, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0xe8, 0x5f, 0x40, 0x0, 0x0, 0x0, 0xe, 0x80, + 0xec, 0x0, 0x0, 0x0, 0x0, 0xe8, 0x4, 0xf9, + 0x0, 0x0, 0x0, 0x9f, 0x60, 0x5, 0xfd, 0x74, + 0x58, 0xdf, 0x80, 0x0, 0x1, 0x8c, 0xfe, 0xd9, + 0x20, 0x0, + + /* U+0048 "H" */ + 0x7f, 0x0, 0x0, 0x0, 0x5, 0xf2, 0x7f, 0x0, + 0x0, 0x0, 0x5, 0xf2, 0x7f, 0x0, 0x0, 0x0, + 0x5, 0xf2, 0x7f, 0x0, 0x0, 0x0, 0x5, 0xf2, + 0x7f, 0x0, 0x0, 0x0, 0x5, 0xf2, 0x7f, 0x0, + 0x0, 0x0, 0x5, 0xf2, 0x7f, 0x11, 0x11, 0x11, + 0x15, 0xf2, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf2, + 0x7f, 0x44, 0x44, 0x44, 0x47, 0xf2, 0x7f, 0x0, + 0x0, 0x0, 0x5, 0xf2, 0x7f, 0x0, 0x0, 0x0, + 0x5, 0xf2, 0x7f, 0x0, 0x0, 0x0, 0x5, 0xf2, + 0x7f, 0x0, 0x0, 0x0, 0x5, 0xf2, 0x7f, 0x0, + 0x0, 0x0, 0x5, 0xf2, 0x7f, 0x0, 0x0, 0x0, + 0x5, 0xf2, + + /* U+0049 "I" */ + 0x3f, 0x43, 0xf4, 0x3f, 0x43, 0xf4, 0x3f, 0x43, + 0xf4, 0x3f, 0x43, 0xf4, 0x3f, 0x43, 0xf4, 0x3f, + 0x43, 0xf4, 0x3f, 0x43, 0xf4, 0x3f, 0x40, + + /* U+004A "J" */ + 0x0, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0, 0x7, + 0xf0, 0x0, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0, + 0x7, 0xf0, 0x0, 0x0, 0x0, 0x7f, 0x0, 0x0, + 0x0, 0x7, 0xf0, 0x0, 0x0, 0x0, 0x7f, 0x0, + 0x0, 0x0, 0x7, 0xf0, 0x0, 0x0, 0x0, 0x7f, + 0x0, 0x0, 0x0, 0x7, 0xf0, 0x27, 0x0, 0x0, + 0x7f, 0x5, 0xf1, 0x0, 0x9, 0xf0, 0x2f, 0x70, + 0x0, 0xdb, 0x0, 0xbf, 0x97, 0xcf, 0x40, 0x1, + 0x9e, 0xfd, 0x50, 0x0, + + /* U+004B "K" */ + 0x9d, 0x0, 0x0, 0x0, 0x4f, 0xc0, 0x9d, 0x0, + 0x0, 0x3, 0xfc, 0x0, 0x9d, 0x0, 0x0, 0x2e, + 0xd1, 0x0, 0x9d, 0x0, 0x1, 0xee, 0x20, 0x0, + 0x9d, 0x0, 0xd, 0xe2, 0x0, 0x0, 0x9d, 0x0, + 0xbf, 0x30, 0x0, 0x0, 0x9d, 0xa, 0xfc, 0x0, + 0x0, 0x0, 0x9d, 0x8f, 0x7f, 0x70, 0x0, 0x0, + 0x9f, 0xf6, 0x7, 0xf2, 0x0, 0x0, 0x9f, 0x70, + 0x0, 0xdc, 0x0, 0x0, 0x9d, 0x0, 0x0, 0x3f, + 0x70, 0x0, 0x9d, 0x0, 0x0, 0x9, 0xf2, 0x0, + 0x9d, 0x0, 0x0, 0x1, 0xed, 0x0, 0x9d, 0x0, + 0x0, 0x0, 0x6f, 0x80, 0x9d, 0x0, 0x0, 0x0, + 0xc, 0xf3, + + /* U+004C "L" */ + 0x9d, 0x0, 0x0, 0x0, 0x9, 0xd0, 0x0, 0x0, + 0x0, 0x9d, 0x0, 0x0, 0x0, 0x9, 0xd0, 0x0, + 0x0, 0x0, 0x9d, 0x0, 0x0, 0x0, 0x9, 0xd0, + 0x0, 0x0, 0x0, 0x9d, 0x0, 0x0, 0x0, 0x9, + 0xd0, 0x0, 0x0, 0x0, 0x9d, 0x0, 0x0, 0x0, + 0x9, 0xd0, 0x0, 0x0, 0x0, 0x9d, 0x0, 0x0, + 0x0, 0x9, 0xd0, 0x0, 0x0, 0x0, 0x9d, 0x0, + 0x0, 0x0, 0x9, 0xe5, 0x55, 0x55, 0x54, 0x9f, + 0xff, 0xff, 0xff, 0xe0, + + /* U+004D "M" */ + 0x9f, 0x90, 0x0, 0x0, 0x0, 0xa, 0xf7, 0x9f, + 0xe0, 0x0, 0x0, 0x0, 0xf, 0xf7, 0x9e, 0xf4, + 0x0, 0x0, 0x0, 0x5e, 0xe7, 0x9d, 0xaa, 0x0, + 0x0, 0x0, 0xb9, 0xe7, 0x9d, 0x4f, 0x0, 0x0, + 0x1, 0xf3, 0xe7, 0x9d, 0xe, 0x50, 0x0, 0x7, + 0xd0, 0xe7, 0x9d, 0x9, 0xb0, 0x0, 0xc, 0x70, + 0xe7, 0x9d, 0x3, 0xf1, 0x0, 0x2f, 0x20, 0xe7, + 0x9d, 0x0, 0xd7, 0x0, 0x8c, 0x0, 0xe7, 0x9d, + 0x0, 0x7c, 0x0, 0xd6, 0x0, 0xe7, 0x9d, 0x0, + 0x1f, 0x23, 0xf1, 0x0, 0xe7, 0x9d, 0x0, 0xb, + 0x89, 0xb0, 0x0, 0xe7, 0x9d, 0x0, 0x6, 0xee, + 0x50, 0x0, 0xe7, 0x9d, 0x0, 0x0, 0xff, 0x0, + 0x0, 0xe7, 0x9d, 0x0, 0x0, 0xa9, 0x0, 0x0, + 0xe7, + + /* U+004E "N" */ + 0x9f, 0x70, 0x0, 0x0, 0x5, 0xf2, 0x9f, 0xf1, + 0x0, 0x0, 0x5, 0xf2, 0x9e, 0xc9, 0x0, 0x0, + 0x5, 0xf2, 0x9e, 0x3f, 0x30, 0x0, 0x5, 0xf2, + 0x9e, 0x9, 0xc0, 0x0, 0x5, 0xf2, 0x9e, 0x1, + 0xf5, 0x0, 0x5, 0xf2, 0x9e, 0x0, 0x7e, 0x0, + 0x5, 0xf2, 0x9e, 0x0, 0xd, 0x80, 0x5, 0xf2, + 0x9e, 0x0, 0x4, 0xf2, 0x5, 0xf2, 0x9e, 0x0, + 0x0, 0xbb, 0x5, 0xf2, 0x9e, 0x0, 0x0, 0x2f, + 0x45, 0xf2, 0x9e, 0x0, 0x0, 0x8, 0xd5, 0xf2, + 0x9e, 0x0, 0x0, 0x0, 0xeb, 0xf2, 0x9e, 0x0, + 0x0, 0x0, 0x6f, 0xf2, 0x9e, 0x0, 0x0, 0x0, + 0xc, 0xf2, + + /* U+004F "O" */ + 0x0, 0x0, 0x4a, 0xef, 0xeb, 0x40, 0x0, 0x0, + 0x9, 0xff, 0xa8, 0xbf, 0xf9, 0x0, 0x0, 0x8f, + 0xb1, 0x0, 0x1, 0xcf, 0x70, 0x2, 0xfc, 0x0, + 0x0, 0x0, 0xd, 0xf1, 0x8, 0xf3, 0x0, 0x0, + 0x0, 0x5, 0xf7, 0xc, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0xfb, 0xf, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0xce, 0xf, 0x80, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0xf, 0x90, 0x0, 0x0, 0x0, 0x0, 0xbe, 0xd, + 0xc0, 0x0, 0x0, 0x0, 0x0, 0xeb, 0x9, 0xf1, + 0x0, 0x0, 0x0, 0x2, 0xf8, 0x3, 0xf9, 0x0, + 0x0, 0x0, 0x9, 0xf2, 0x0, 0xaf, 0x70, 0x0, + 0x0, 0x6f, 0x90, 0x0, 0xc, 0xfc, 0x75, 0x7c, + 0xfa, 0x0, 0x0, 0x0, 0x6c, 0xef, 0xeb, 0x50, + 0x0, + + /* U+0050 "P" */ + 0x8f, 0xff, 0xff, 0xfd, 0x70, 0x8, 0xf5, 0x55, + 0x56, 0xaf, 0xa0, 0x8f, 0x0, 0x0, 0x0, 0x5f, + 0x48, 0xf0, 0x0, 0x0, 0x0, 0xe9, 0x8f, 0x0, + 0x0, 0x0, 0xb, 0xc8, 0xf0, 0x0, 0x0, 0x0, + 0xdb, 0x8f, 0x0, 0x0, 0x0, 0x3f, 0x78, 0xf1, + 0x11, 0x12, 0x6e, 0xe0, 0x8f, 0xff, 0xff, 0xff, + 0xc2, 0x8, 0xf4, 0x44, 0x43, 0x10, 0x0, 0x8f, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+0051 "Q" */ + 0x0, 0x0, 0x5b, 0xef, 0xea, 0x30, 0x0, 0x0, + 0xb, 0xfb, 0x64, 0x7e, 0xf7, 0x0, 0x0, 0xaf, + 0x50, 0x0, 0x0, 0xbf, 0x40, 0x3, 0xf8, 0x0, + 0x0, 0x0, 0xe, 0xd0, 0xa, 0xf1, 0x0, 0x0, + 0x0, 0x7, 0xf4, 0xe, 0xb0, 0x0, 0x0, 0x0, + 0x2, 0xf8, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0, + 0xeb, 0x2f, 0x60, 0x0, 0x0, 0x0, 0x0, 0xdd, + 0x1f, 0x70, 0x0, 0x0, 0x0, 0x0, 0xdc, 0xf, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0xf9, 0xb, 0xe0, + 0x0, 0x0, 0x0, 0x4, 0xf5, 0x5, 0xf6, 0x0, + 0x0, 0x0, 0xb, 0xe0, 0x0, 0xcf, 0x50, 0x0, + 0x0, 0x8f, 0x60, 0x0, 0x1d, 0xfb, 0x65, 0x7c, + 0xf9, 0x0, 0x0, 0x0, 0x7c, 0xff, 0xfc, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xeb, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x77, 0x10, + + /* U+0052 "R" */ + 0x7f, 0xff, 0xff, 0xff, 0xb4, 0x0, 0x7, 0xf4, + 0x44, 0x44, 0x6b, 0xf6, 0x0, 0x7f, 0x0, 0x0, + 0x0, 0xa, 0xf0, 0x7, 0xf0, 0x0, 0x0, 0x0, + 0x4f, 0x40, 0x7f, 0x0, 0x0, 0x0, 0x4, 0xf4, + 0x7, 0xf0, 0x0, 0x0, 0x0, 0x9f, 0x10, 0x7f, + 0x11, 0x11, 0x13, 0x9f, 0xa0, 0x7, 0xff, 0xff, + 0xff, 0xff, 0xc1, 0x0, 0x7f, 0x44, 0x46, 0xfa, + 0x20, 0x0, 0x7, 0xf0, 0x0, 0x8, 0xf3, 0x0, + 0x0, 0x7f, 0x0, 0x0, 0xc, 0xe1, 0x0, 0x7, + 0xf0, 0x0, 0x0, 0x2f, 0xb0, 0x0, 0x7f, 0x0, + 0x0, 0x0, 0x6f, 0x70, 0x7, 0xf0, 0x0, 0x0, + 0x0, 0xaf, 0x30, 0x7f, 0x0, 0x0, 0x0, 0x1, + 0xee, 0x10, + + /* U+0053 "S" */ + 0x0, 0x7, 0xdf, 0xfd, 0x81, 0x0, 0x0, 0xbf, + 0x96, 0x58, 0xfe, 0x20, 0x5, 0xf5, 0x0, 0x0, + 0x3f, 0xc0, 0x9, 0xf0, 0x0, 0x0, 0x9, 0xf1, + 0x9, 0xf1, 0x0, 0x0, 0x1, 0x10, 0x3, 0xfd, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x5e, 0xfd, 0x95, + 0x0, 0x0, 0x0, 0x0, 0x6b, 0xff, 0xf7, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xaf, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xf5, 0x9, 0x60, 0x0, 0x0, + 0x0, 0xf9, 0xe, 0xc0, 0x0, 0x0, 0x1, 0xf8, + 0x7, 0xf6, 0x0, 0x0, 0x7, 0xf3, 0x0, 0xaf, + 0xb6, 0x46, 0xaf, 0x90, 0x0, 0x5, 0xbe, 0xff, + 0xc5, 0x0, + + /* U+0054 "T" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x25, 0x55, + 0x5e, 0xb5, 0x55, 0x51, 0x0, 0x0, 0xe, 0x90, + 0x0, 0x0, 0x0, 0x0, 0xe, 0x90, 0x0, 0x0, + 0x0, 0x0, 0xe, 0x90, 0x0, 0x0, 0x0, 0x0, + 0xe, 0x90, 0x0, 0x0, 0x0, 0x0, 0xe, 0x90, + 0x0, 0x0, 0x0, 0x0, 0xe, 0x90, 0x0, 0x0, + 0x0, 0x0, 0xe, 0x90, 0x0, 0x0, 0x0, 0x0, + 0xe, 0x90, 0x0, 0x0, 0x0, 0x0, 0xe, 0x90, + 0x0, 0x0, 0x0, 0x0, 0xe, 0x90, 0x0, 0x0, + 0x0, 0x0, 0xe, 0x90, 0x0, 0x0, 0x0, 0x0, + 0xe, 0x90, 0x0, 0x0, 0x0, 0x0, 0xe, 0x90, + 0x0, 0x0, + + /* U+0055 "U" */ + 0x7f, 0x0, 0x0, 0x0, 0x3, 0xf3, 0x7f, 0x0, + 0x0, 0x0, 0x3, 0xf3, 0x7f, 0x0, 0x0, 0x0, + 0x3, 0xf3, 0x7f, 0x0, 0x0, 0x0, 0x3, 0xf3, + 0x7f, 0x0, 0x0, 0x0, 0x3, 0xf3, 0x7f, 0x0, + 0x0, 0x0, 0x3, 0xf3, 0x7f, 0x0, 0x0, 0x0, + 0x3, 0xf3, 0x7f, 0x0, 0x0, 0x0, 0x3, 0xf3, + 0x7f, 0x0, 0x0, 0x0, 0x3, 0xf3, 0x6f, 0x0, + 0x0, 0x0, 0x4, 0xf2, 0x5f, 0x20, 0x0, 0x0, + 0x6, 0xf0, 0x1f, 0x70, 0x0, 0x0, 0xb, 0xd0, + 0xb, 0xe1, 0x0, 0x0, 0x5f, 0x60, 0x2, 0xee, + 0x85, 0x6a, 0xfb, 0x0, 0x0, 0x19, 0xdf, 0xfc, + 0x60, 0x0, + + /* U+0056 "V" */ + 0x8f, 0x10, 0x0, 0x0, 0x0, 0xf, 0x92, 0xf6, + 0x0, 0x0, 0x0, 0x5, 0xf3, 0xc, 0xb0, 0x0, + 0x0, 0x0, 0xad, 0x0, 0x6f, 0x10, 0x0, 0x0, + 0x1f, 0x70, 0x1, 0xf6, 0x0, 0x0, 0x6, 0xf2, + 0x0, 0xb, 0xc0, 0x0, 0x0, 0xbc, 0x0, 0x0, + 0x5f, 0x20, 0x0, 0x1f, 0x60, 0x0, 0x0, 0xe7, + 0x0, 0x7, 0xf0, 0x0, 0x0, 0x9, 0xd0, 0x0, + 0xca, 0x0, 0x0, 0x0, 0x3f, 0x20, 0x2f, 0x40, + 0x0, 0x0, 0x0, 0xd8, 0x8, 0xe0, 0x0, 0x0, + 0x0, 0x8, 0xd0, 0xd8, 0x0, 0x0, 0x0, 0x0, + 0x2f, 0x6f, 0x20, 0x0, 0x0, 0x0, 0x0, 0xcf, + 0xc0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xf6, 0x0, + 0x0, 0x0, + + /* U+0057 "W" */ + 0x9e, 0x0, 0x0, 0x0, 0xdf, 0x0, 0x0, 0x0, + 0xda, 0x5f, 0x20, 0x0, 0x1, 0xff, 0x30, 0x0, + 0x1, 0xf6, 0x1f, 0x60, 0x0, 0x6, 0xfe, 0x70, + 0x0, 0x5, 0xf1, 0xd, 0x90, 0x0, 0xa, 0xca, + 0xb0, 0x0, 0x9, 0xd0, 0x9, 0xd0, 0x0, 0xe, + 0x75, 0xf0, 0x0, 0xd, 0x90, 0x5, 0xf1, 0x0, + 0x3f, 0x21, 0xf3, 0x0, 0xf, 0x50, 0x1, 0xf4, + 0x0, 0x7e, 0x0, 0xd7, 0x0, 0x4f, 0x10, 0x0, + 0xd8, 0x0, 0xb9, 0x0, 0x8b, 0x0, 0x8d, 0x0, + 0x0, 0x9b, 0x0, 0xf4, 0x0, 0x4f, 0x0, 0xc8, + 0x0, 0x0, 0x5f, 0x4, 0xf0, 0x0, 0xf, 0x30, + 0xf4, 0x0, 0x0, 0x1f, 0x38, 0xb0, 0x0, 0xb, + 0x73, 0xf0, 0x0, 0x0, 0xd, 0x6c, 0x70, 0x0, + 0x7, 0xb7, 0xc0, 0x0, 0x0, 0x9, 0xbf, 0x20, + 0x0, 0x3, 0xfb, 0x80, 0x0, 0x0, 0x5, 0xfd, + 0x0, 0x0, 0x0, 0xef, 0x40, 0x0, 0x0, 0x1, + 0xf9, 0x0, 0x0, 0x0, 0xaf, 0x0, 0x0, + + /* U+0058 "X" */ + 0xd, 0xc0, 0x0, 0x0, 0x0, 0xeb, 0x0, 0x3f, + 0x70, 0x0, 0x0, 0x9f, 0x20, 0x0, 0x8f, 0x10, + 0x0, 0x3f, 0x60, 0x0, 0x0, 0xdb, 0x0, 0xc, + 0xc0, 0x0, 0x0, 0x3, 0xf5, 0x7, 0xf2, 0x0, + 0x0, 0x0, 0x9, 0xe3, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0xd, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xaf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x4f, 0x9f, + 0x20, 0x0, 0x0, 0x0, 0x1e, 0x80, 0xcc, 0x0, + 0x0, 0x0, 0xb, 0xd0, 0x2, 0xf7, 0x0, 0x0, + 0x6, 0xf3, 0x0, 0x8, 0xf2, 0x0, 0x2, 0xf9, + 0x0, 0x0, 0xd, 0xc0, 0x0, 0xce, 0x0, 0x0, + 0x0, 0x4f, 0x80, 0x8f, 0x40, 0x0, 0x0, 0x0, + 0xaf, 0x30, + + /* U+0059 "Y" */ + 0x9f, 0x10, 0x0, 0x0, 0x0, 0x9f, 0x20, 0xea, + 0x0, 0x0, 0x0, 0x3f, 0x80, 0x5, 0xf4, 0x0, + 0x0, 0xc, 0xd0, 0x0, 0xb, 0xd0, 0x0, 0x6, + 0xf4, 0x0, 0x0, 0x2f, 0x70, 0x1, 0xe9, 0x0, + 0x0, 0x0, 0x7f, 0x10, 0x9e, 0x10, 0x0, 0x0, + 0x0, 0xda, 0x3f, 0x50, 0x0, 0x0, 0x0, 0x4, + 0xfe, 0xb0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8e, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8e, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8e, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xe0, 0x0, + 0x0, 0x0, + + /* U+005A "Z" */ + 0xd, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x4, 0x55, + 0x55, 0x55, 0x8f, 0x70, 0x0, 0x0, 0x0, 0x0, + 0xdc, 0x0, 0x0, 0x0, 0x0, 0x8, 0xf2, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0x70, 0x0, 0x0, 0x0, + 0x0, 0xdc, 0x0, 0x0, 0x0, 0x0, 0x8, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0x70, 0x0, 0x0, + 0x0, 0x0, 0xdc, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xf2, 0x0, 0x0, 0x0, 0x0, 0x3f, 0x60, 0x0, + 0x0, 0x0, 0x0, 0xdc, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xa4, + 0x44, 0x44, 0x44, 0x40, 0x9f, 0xff, 0xff, 0xff, + 0xff, 0xf2, + + /* U+005B "[" */ + 0xae, 0xed, 0xb8, 0x11, 0xb8, 0x0, 0xb8, 0x0, + 0xb8, 0x0, 0xb8, 0x0, 0xb8, 0x0, 0xb8, 0x0, + 0xb8, 0x0, 0xb8, 0x0, 0xb8, 0x0, 0xb8, 0x0, + 0xb8, 0x0, 0xb8, 0x0, 0xb8, 0x0, 0xb8, 0x0, + 0xb8, 0x0, 0xbf, 0xee, 0x11, 0x11, + + /* U+005C "\\" */ + 0xd5, 0x0, 0x0, 0x99, 0x0, 0x0, 0x5d, 0x0, + 0x0, 0x1f, 0x20, 0x0, 0xc, 0x60, 0x0, 0x8, + 0xa0, 0x0, 0x4, 0xe0, 0x0, 0x0, 0xf2, 0x0, + 0x0, 0xb7, 0x0, 0x0, 0x7b, 0x0, 0x0, 0x3f, + 0x0, 0x0, 0xf, 0x30, 0x0, 0xb, 0x70, 0x0, + 0x6, 0xb0, 0x0, 0x2, 0xf0, + + /* U+005D "]" */ + 0xae, 0xed, 0x11, 0x6e, 0x0, 0x5e, 0x0, 0x5e, + 0x0, 0x5e, 0x0, 0x5e, 0x0, 0x5e, 0x0, 0x5e, + 0x0, 0x5e, 0x0, 0x5e, 0x0, 0x5e, 0x0, 0x5e, + 0x0, 0x5e, 0x0, 0x5e, 0x0, 0x5e, 0x0, 0x5e, + 0x0, 0x5e, 0xae, 0xfe, 0x11, 0x11, + + /* U+005E "^" */ + 0x0, 0x4, 0xf3, 0x0, 0x0, 0x0, 0xbe, 0xa0, + 0x0, 0x0, 0x2f, 0x4f, 0x10, 0x0, 0x8, 0xc0, + 0xb8, 0x0, 0x0, 0xe6, 0x5, 0xe0, 0x0, 0x6f, + 0x0, 0xe, 0x50, 0xd, 0x90, 0x0, 0x8c, 0x3, + 0xf3, 0x0, 0x2, 0xf3, + + /* U+005F "_" */ + 0xef, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x20, + + /* U+0060 "`" */ + 0xb, 0xf1, 0x0, 0x1e, 0x80, 0x0, 0x3e, 0x0, + + /* U+0061 "a" */ + 0x0, 0x3b, 0xef, 0xe9, 0x0, 0x3, 0xfa, 0x43, + 0x5e, 0xa0, 0xb, 0xc0, 0x0, 0x6, 0xf1, 0x3, + 0x30, 0x0, 0x3, 0xf3, 0x0, 0x0, 0x2, 0x5b, + 0xf4, 0x0, 0x7d, 0xff, 0xe9, 0xf4, 0x9, 0xf8, + 0x41, 0x2, 0xf4, 0x1f, 0x60, 0x0, 0x5, 0xf4, + 0x2f, 0x40, 0x0, 0xb, 0xf4, 0xd, 0xc4, 0x24, + 0xbc, 0xf5, 0x2, 0xae, 0xfd, 0x70, 0xc9, + + /* U+0062 "b" */ + 0xba, 0x0, 0x0, 0x0, 0xb, 0xa0, 0x0, 0x0, + 0x0, 0xba, 0x0, 0x0, 0x0, 0xb, 0xa0, 0x0, + 0x0, 0x0, 0xba, 0x2c, 0xfd, 0x60, 0xb, 0xce, + 0x74, 0x7f, 0x70, 0xbf, 0x40, 0x0, 0x5f, 0x1b, + 0xd0, 0x0, 0x0, 0xe7, 0xba, 0x0, 0x0, 0xb, + 0xab, 0xa0, 0x0, 0x0, 0x9c, 0xba, 0x0, 0x0, + 0xa, 0xbb, 0xc0, 0x0, 0x0, 0xd8, 0xbf, 0x20, + 0x0, 0x2f, 0x3b, 0xdc, 0x20, 0x2d, 0xb0, 0xba, + 0x4c, 0xfe, 0x90, 0x0, + + /* U+0063 "c" */ + 0x0, 0x1a, 0xef, 0xc4, 0x0, 0x1, 0xdc, 0x54, + 0x9f, 0x50, 0x8, 0xd0, 0x0, 0xa, 0xe0, 0xe, + 0x70, 0x0, 0x2, 0x30, 0x2f, 0x40, 0x0, 0x0, + 0x0, 0x3f, 0x30, 0x0, 0x0, 0x0, 0x2f, 0x40, + 0x0, 0x0, 0x0, 0xf, 0x70, 0x0, 0x3, 0xd2, + 0xa, 0xd0, 0x0, 0x9, 0xe0, 0x2, 0xec, 0x65, + 0x9f, 0x50, 0x0, 0x2b, 0xff, 0xc5, 0x0, + + /* U+0064 "d" */ + 0x0, 0x0, 0x0, 0x3, 0xf3, 0x0, 0x0, 0x0, + 0x3, 0xf3, 0x0, 0x0, 0x0, 0x3, 0xf3, 0x0, + 0x0, 0x0, 0x3, 0xf3, 0x0, 0x3b, 0xfe, 0x73, + 0xf3, 0x2, 0xfb, 0x44, 0xbb, 0xf3, 0xa, 0xc0, + 0x0, 0xc, 0xf3, 0xf, 0x50, 0x0, 0x6, 0xf3, + 0x3f, 0x20, 0x0, 0x3, 0xf3, 0x4f, 0x10, 0x0, + 0x3, 0xf3, 0x2f, 0x20, 0x0, 0x4, 0xf3, 0xf, + 0x50, 0x0, 0x6, 0xf3, 0x9, 0xb0, 0x0, 0xc, + 0xf3, 0x1, 0xea, 0x45, 0xbb, 0xf3, 0x0, 0x2b, + 0xfd, 0x73, 0xf3, + + /* U+0065 "e" */ + 0x0, 0x6, 0xdf, 0xd6, 0x0, 0x0, 0xae, 0x74, + 0x7f, 0x70, 0x5, 0xf2, 0x0, 0x5, 0xf1, 0xc, + 0x90, 0x0, 0x0, 0xe7, 0xf, 0x60, 0x0, 0x0, + 0xcb, 0x3f, 0xff, 0xff, 0xff, 0xfd, 0x3f, 0x73, + 0x33, 0x33, 0x32, 0xf, 0x70, 0x0, 0x0, 0x30, + 0xa, 0xe0, 0x0, 0x3, 0xf9, 0x2, 0xed, 0x65, + 0x7e, 0xe1, 0x0, 0x2a, 0xef, 0xe9, 0x10, + + /* U+0066 "f" */ + 0x0, 0x9f, 0xf9, 0x4, 0xf7, 0x33, 0x6, 0xf0, + 0x0, 0x7, 0xf0, 0x0, 0xff, 0xff, 0xf0, 0x38, + 0xf3, 0x30, 0x7, 0xf0, 0x0, 0x7, 0xf0, 0x0, + 0x7, 0xf0, 0x0, 0x7, 0xf0, 0x0, 0x7, 0xf0, + 0x0, 0x7, 0xf0, 0x0, 0x7, 0xf0, 0x0, 0x7, + 0xf0, 0x0, 0x7, 0xf0, 0x0, + + /* U+0067 "g" */ + 0x0, 0x19, 0xee, 0x81, 0xf5, 0x1, 0xda, 0x44, + 0xab, 0xf5, 0x9, 0xb0, 0x0, 0xa, 0xf5, 0xf, + 0x40, 0x0, 0x3, 0xf5, 0x3f, 0x10, 0x0, 0x1, + 0xf5, 0x5f, 0x0, 0x0, 0x0, 0xf5, 0x4f, 0x10, + 0x0, 0x1, 0xf5, 0x1f, 0x40, 0x0, 0x3, 0xf5, + 0xd, 0xa0, 0x0, 0xa, 0xf5, 0x4, 0xf8, 0x23, + 0x9b, 0xf5, 0x0, 0x5d, 0xfe, 0x92, 0xf4, 0x0, + 0x0, 0x0, 0x6, 0xf1, 0x9, 0x84, 0x34, 0x8f, + 0x90, 0x1, 0x9e, 0xff, 0xc7, 0x0, + + /* U+0068 "h" */ + 0xba, 0x0, 0x0, 0x0, 0xb, 0xa0, 0x0, 0x0, + 0x0, 0xba, 0x0, 0x0, 0x0, 0xb, 0xa0, 0x0, + 0x0, 0x0, 0xba, 0x2b, 0xff, 0xa1, 0xb, 0xcd, + 0x84, 0x7f, 0xb0, 0xbf, 0x40, 0x0, 0x7f, 0x1b, + 0xd0, 0x0, 0x3, 0xf3, 0xba, 0x0, 0x0, 0x2f, + 0x4b, 0xa0, 0x0, 0x2, 0xf4, 0xba, 0x0, 0x0, + 0x2f, 0x4b, 0xa0, 0x0, 0x2, 0xf4, 0xba, 0x0, + 0x0, 0x2f, 0x4b, 0xa0, 0x0, 0x2, 0xf4, 0xba, + 0x0, 0x0, 0x2f, 0x40, + + /* U+0069 "i" */ + 0xbb, 0xa9, 0x0, 0x0, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + + /* U+006A "j" */ + 0x0, 0xb, 0xb0, 0x0, 0x9a, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xb, 0xb0, 0x0, 0xbb, 0x0, + 0xb, 0xb0, 0x0, 0xbb, 0x0, 0xb, 0xb0, 0x0, + 0xbb, 0x0, 0xb, 0xb0, 0x0, 0xbb, 0x0, 0xb, + 0xb0, 0x0, 0xbb, 0x0, 0xb, 0xb0, 0x0, 0xbb, + 0x2, 0x3e, 0x90, 0xcf, 0xd2, + + /* U+006B "k" */ + 0xba, 0x0, 0x0, 0x0, 0xb, 0xa0, 0x0, 0x0, + 0x0, 0xba, 0x0, 0x0, 0x0, 0xb, 0xa0, 0x0, + 0x0, 0x0, 0xba, 0x0, 0x6, 0xf9, 0xb, 0xa0, + 0x4, 0xfa, 0x0, 0xba, 0x2, 0xfb, 0x0, 0xb, + 0xa1, 0xec, 0x0, 0x0, 0xbb, 0xdf, 0x70, 0x0, + 0xb, 0xfd, 0x8f, 0x10, 0x0, 0xbe, 0x20, 0xda, + 0x0, 0xb, 0xa0, 0x4, 0xf4, 0x0, 0xba, 0x0, + 0xb, 0xd0, 0xb, 0xa0, 0x0, 0x2f, 0x80, 0xba, + 0x0, 0x0, 0x9f, 0x20, + + /* U+006C "l" */ + 0xca, 0xca, 0xca, 0xca, 0xca, 0xca, 0xca, 0xca, + 0xca, 0xca, 0xca, 0xca, 0xca, 0xca, 0xca, + + /* U+006D "m" */ + 0xba, 0x3c, 0xfd, 0x40, 0x4d, 0xfc, 0x30, 0xbb, + 0xc5, 0x3a, 0xf4, 0xd5, 0x3a, 0xf1, 0xbf, 0x20, + 0x0, 0xff, 0x10, 0x0, 0xf7, 0xbc, 0x0, 0x0, + 0xdb, 0x0, 0x0, 0xd8, 0xba, 0x0, 0x0, 0xc9, + 0x0, 0x0, 0xc9, 0xba, 0x0, 0x0, 0xc9, 0x0, + 0x0, 0xc9, 0xba, 0x0, 0x0, 0xc9, 0x0, 0x0, + 0xc9, 0xba, 0x0, 0x0, 0xc9, 0x0, 0x0, 0xc9, + 0xba, 0x0, 0x0, 0xc9, 0x0, 0x0, 0xc9, 0xba, + 0x0, 0x0, 0xc9, 0x0, 0x0, 0xc9, 0xba, 0x0, + 0x0, 0xc9, 0x0, 0x0, 0xc9, + + /* U+006E "n" */ + 0xba, 0x2b, 0xff, 0xa1, 0xb, 0xbe, 0x84, 0x6f, + 0xb0, 0xbf, 0x40, 0x0, 0x6f, 0x1b, 0xd0, 0x0, + 0x2, 0xf4, 0xba, 0x0, 0x0, 0x1f, 0x4b, 0xa0, + 0x0, 0x1, 0xf4, 0xba, 0x0, 0x0, 0x1f, 0x4b, + 0xa0, 0x0, 0x1, 0xf4, 0xba, 0x0, 0x0, 0x1f, + 0x4b, 0xa0, 0x0, 0x1, 0xf4, 0xba, 0x0, 0x0, + 0x1f, 0x40, + + /* U+006F "o" */ + 0x0, 0x19, 0xef, 0xd7, 0x0, 0x1, 0xeb, 0x43, + 0x9f, 0x90, 0x9, 0xc0, 0x0, 0x8, 0xf3, 0xf, + 0x60, 0x0, 0x1, 0xf8, 0x3f, 0x20, 0x0, 0x0, + 0xcc, 0x5f, 0x10, 0x0, 0x0, 0xad, 0x3f, 0x20, + 0x0, 0x0, 0xbc, 0xf, 0x50, 0x0, 0x0, 0xe9, + 0xb, 0xc0, 0x0, 0x4, 0xf3, 0x2, 0xfb, 0x43, + 0x6f, 0xa0, 0x0, 0x2b, 0xff, 0xd7, 0x0, + + /* U+0070 "p" */ + 0xca, 0x3c, 0xfd, 0x60, 0xc, 0xdd, 0x41, 0x4e, + 0x70, 0xcf, 0x20, 0x0, 0x4f, 0x1c, 0xc0, 0x0, + 0x0, 0xd6, 0xca, 0x0, 0x0, 0xb, 0xac, 0xa0, + 0x0, 0x0, 0xab, 0xcb, 0x0, 0x0, 0xb, 0xac, + 0xd0, 0x0, 0x0, 0xe7, 0xcf, 0x30, 0x0, 0x4f, + 0x2c, 0xcd, 0x63, 0x6e, 0x90, 0xca, 0x3b, 0xfe, + 0x70, 0xc, 0xa0, 0x0, 0x0, 0x0, 0xca, 0x0, + 0x0, 0x0, 0xc, 0xa0, 0x0, 0x0, 0x0, + + /* U+0071 "q" */ + 0x0, 0x3c, 0xfe, 0x73, 0xf2, 0x2, 0xfa, 0x45, + 0xbb, 0xf2, 0xb, 0xb0, 0x0, 0xc, 0xf2, 0xf, + 0x40, 0x0, 0x6, 0xf2, 0x3f, 0x10, 0x0, 0x4, + 0xf2, 0x4f, 0x0, 0x0, 0x3, 0xf2, 0x2f, 0x10, + 0x0, 0x4, 0xf2, 0xf, 0x40, 0x0, 0x6, 0xf2, + 0x9, 0xb0, 0x0, 0xd, 0xf2, 0x2, 0xea, 0x55, + 0xcb, 0xf2, 0x0, 0x2b, 0xfd, 0x73, 0xf2, 0x0, + 0x0, 0x0, 0x3, 0xf2, 0x0, 0x0, 0x0, 0x3, + 0xf2, 0x0, 0x0, 0x0, 0x3, 0xf2, + + /* U+0072 "r" */ + 0xca, 0x5e, 0xf6, 0xcc, 0xc4, 0x61, 0xcf, 0x20, + 0x0, 0xcc, 0x0, 0x0, 0xca, 0x0, 0x0, 0xca, + 0x0, 0x0, 0xca, 0x0, 0x0, 0xca, 0x0, 0x0, + 0xca, 0x0, 0x0, 0xca, 0x0, 0x0, 0xca, 0x0, + 0x0, + + /* U+0073 "s" */ + 0x0, 0x7d, 0xfe, 0xa1, 0x0, 0x7f, 0x74, 0x6e, + 0xd0, 0xd, 0x90, 0x0, 0x4e, 0x30, 0xcb, 0x0, + 0x0, 0x0, 0x4, 0xfc, 0x62, 0x0, 0x0, 0x3, + 0xae, 0xfd, 0x50, 0x0, 0x0, 0x3, 0xaf, 0x51, + 0x71, 0x0, 0x0, 0xcb, 0x1f, 0x70, 0x0, 0xc, + 0xa0, 0x8f, 0x84, 0x49, 0xf3, 0x0, 0x6d, 0xfe, + 0xb4, 0x0, + + /* U+0074 "t" */ + 0x0, 0x50, 0x0, 0x6, 0xf0, 0x0, 0x7, 0xf0, + 0x0, 0x7, 0xf0, 0x0, 0xcf, 0xff, 0xd0, 0x28, + 0xf3, 0x20, 0x7, 0xf0, 0x0, 0x7, 0xf0, 0x0, + 0x7, 0xf0, 0x0, 0x7, 0xf0, 0x0, 0x7, 0xf0, + 0x0, 0x7, 0xf0, 0x0, 0x6, 0xf0, 0x0, 0x4, + 0xf4, 0x10, 0x0, 0xaf, 0xd0, + + /* U+0075 "u" */ + 0xd9, 0x0, 0x0, 0x2f, 0x3d, 0x90, 0x0, 0x2, + 0xf3, 0xd9, 0x0, 0x0, 0x2f, 0x3d, 0x90, 0x0, + 0x2, 0xf3, 0xd9, 0x0, 0x0, 0x2f, 0x3d, 0x90, + 0x0, 0x2, 0xf3, 0xd9, 0x0, 0x0, 0x2f, 0x3c, + 0xa0, 0x0, 0x5, 0xf3, 0xae, 0x0, 0x0, 0xcf, + 0x34, 0xfa, 0x35, 0xca, 0xf3, 0x6, 0xdf, 0xd7, + 0x2f, 0x30, + + /* U+0076 "v" */ + 0x9f, 0x0, 0x0, 0x6, 0xf1, 0x3f, 0x40, 0x0, + 0xb, 0xb0, 0xe, 0x90, 0x0, 0x1f, 0x60, 0x9, + 0xd0, 0x0, 0x6f, 0x10, 0x3, 0xf2, 0x0, 0xba, + 0x0, 0x0, 0xe7, 0x0, 0xf5, 0x0, 0x0, 0x8c, + 0x5, 0xf0, 0x0, 0x0, 0x3f, 0x1b, 0x90, 0x0, + 0x0, 0xe, 0x7f, 0x40, 0x0, 0x0, 0x8, 0xfe, + 0x0, 0x0, 0x0, 0x3, 0xf8, 0x0, 0x0, + + /* U+0077 "w" */ + 0xc9, 0x0, 0x0, 0xfa, 0x0, 0x0, 0xe7, 0x8d, + 0x0, 0x3, 0xfe, 0x0, 0x3, 0xf3, 0x3f, 0x20, + 0x7, 0x9f, 0x10, 0x7, 0xe0, 0xe, 0x60, 0xa, + 0x6b, 0x50, 0xb, 0x90, 0xa, 0xa0, 0xe, 0x28, + 0x80, 0xf, 0x40, 0x5, 0xe0, 0x2e, 0x5, 0xc0, + 0x4f, 0x0, 0x1, 0xf2, 0x6b, 0x1, 0xf0, 0x8b, + 0x0, 0x0, 0xc6, 0x97, 0x0, 0xe3, 0xc6, 0x0, + 0x0, 0x8a, 0xd4, 0x0, 0xa8, 0xf1, 0x0, 0x0, + 0x3f, 0xf0, 0x0, 0x7f, 0xc0, 0x0, 0x0, 0xf, + 0xc0, 0x0, 0x4f, 0x80, 0x0, + + /* U+0078 "x" */ + 0x2f, 0x80, 0x0, 0xd, 0xc0, 0x6, 0xf2, 0x0, + 0x7f, 0x20, 0x0, 0xcb, 0x1, 0xf7, 0x0, 0x0, + 0x2f, 0x4a, 0xc0, 0x0, 0x0, 0x7, 0xef, 0x20, + 0x0, 0x0, 0x1, 0xfb, 0x0, 0x0, 0x0, 0xa, + 0xbe, 0x40, 0x0, 0x0, 0x5f, 0x26, 0xe1, 0x0, + 0x1, 0xe7, 0x0, 0xda, 0x0, 0xb, 0xd0, 0x0, + 0x4f, 0x40, 0x6f, 0x30, 0x0, 0xa, 0xe1, + + /* U+0079 "y" */ + 0x7f, 0x0, 0x0, 0x5, 0xf2, 0x2f, 0x60, 0x0, + 0xb, 0xc0, 0xb, 0xb0, 0x0, 0x1f, 0x60, 0x5, + 0xf1, 0x0, 0x6f, 0x0, 0x0, 0xf6, 0x0, 0xb9, + 0x0, 0x0, 0x9c, 0x1, 0xf3, 0x0, 0x0, 0x3f, + 0x17, 0xd0, 0x0, 0x0, 0xd, 0x6c, 0x70, 0x0, + 0x0, 0x7, 0xdf, 0x10, 0x0, 0x0, 0x1, 0xfb, + 0x0, 0x0, 0x0, 0x1, 0xf5, 0x0, 0x0, 0x0, + 0x7, 0xe0, 0x0, 0x0, 0x2, 0x5f, 0x80, 0x0, + 0x0, 0x2e, 0xfa, 0x0, 0x0, 0x0, + + /* U+007A "z" */ + 0x2f, 0xff, 0xff, 0xff, 0xd0, 0x4, 0x44, 0x44, + 0x8f, 0x40, 0x0, 0x0, 0x1, 0xe9, 0x0, 0x0, + 0x0, 0xc, 0xd0, 0x0, 0x0, 0x0, 0x7f, 0x20, + 0x0, 0x0, 0x3, 0xf7, 0x0, 0x0, 0x0, 0xd, + 0xb0, 0x0, 0x0, 0x0, 0xae, 0x10, 0x0, 0x0, + 0x5, 0xf4, 0x0, 0x0, 0x0, 0x2f, 0xb3, 0x33, + 0x33, 0x30, 0x9f, 0xff, 0xff, 0xff, 0xf1, + + /* U+007B "{" */ + 0x0, 0x5, 0xcd, 0x0, 0x2f, 0x50, 0x0, 0x6c, + 0x0, 0x0, 0x7b, 0x0, 0x0, 0x7b, 0x0, 0x0, + 0x7b, 0x0, 0x0, 0x7b, 0x0, 0x0, 0x8a, 0x0, + 0x3, 0xe4, 0x0, 0x7f, 0x80, 0x0, 0x3, 0xd5, + 0x0, 0x0, 0x8a, 0x0, 0x0, 0x7b, 0x0, 0x0, + 0x7b, 0x0, 0x0, 0x7b, 0x0, 0x0, 0x6b, 0x0, + 0x0, 0x4f, 0x40, 0x0, 0x7, 0xdd, + + /* U+007C "|" */ + 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, + 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, + 0x3f, 0x3f, + + /* U+007D "}" */ + 0x7e, 0x80, 0x0, 0x2, 0xd8, 0x0, 0x0, 0x6c, + 0x0, 0x0, 0x5d, 0x0, 0x0, 0x5d, 0x0, 0x0, + 0x5d, 0x0, 0x0, 0x5d, 0x0, 0x0, 0x4e, 0x0, + 0x0, 0xd, 0x60, 0x0, 0x3, 0xfd, 0x0, 0x1e, + 0x60, 0x0, 0x5d, 0x0, 0x0, 0x5d, 0x0, 0x0, + 0x5d, 0x0, 0x0, 0x5d, 0x0, 0x0, 0x6c, 0x0, + 0x2, 0xc9, 0x0, 0x7e, 0xa1, 0x0, + + /* U+007E "~" */ + 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0xaf, 0xff, + 0xb6, 0x23, 0x74, 0x3c, 0x65, 0x7c, 0xff, 0xfe, + 0x30, 0x0, 0x0, 0x1, 0x33, 0x0, + + /* U+4E09 "三" */ + 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, + 0x4, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x0, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, + + /* U+4E34 "临" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3e, 0x0, 0x1, 0xf4, 0x0, 0x0, + 0x0, 0x19, 0x3, 0xe0, 0x0, 0x9b, 0x0, 0x0, + 0x0, 0x2, 0xe0, 0x3e, 0x0, 0x2f, 0xff, 0xff, + 0xff, 0xf1, 0x2e, 0x3, 0xe0, 0xd, 0x82, 0x52, + 0x22, 0x22, 0x2, 0xe0, 0x3e, 0xb, 0xc0, 0xc, + 0xa0, 0x0, 0x0, 0x2e, 0x3, 0xe1, 0xb1, 0x0, + 0x1c, 0xa0, 0x0, 0x2, 0xe0, 0x3e, 0x0, 0x0, + 0x0, 0x1, 0x0, 0x0, 0x2e, 0x3, 0xe0, 0x3f, + 0xff, 0xff, 0xff, 0xf2, 0x2, 0xe0, 0x3e, 0x3, + 0xe1, 0x14, 0xd1, 0x1e, 0x20, 0x2e, 0x3, 0xe0, + 0x3e, 0x0, 0x3d, 0x0, 0xe2, 0x2, 0xe0, 0x3e, + 0x3, 0xe0, 0x3, 0xd0, 0xe, 0x20, 0x2e, 0x3, + 0xe0, 0x3e, 0x0, 0x3d, 0x0, 0xe2, 0x2, 0xe0, + 0x3e, 0x3, 0xe0, 0x3, 0xd0, 0xe, 0x20, 0x2c, + 0x3, 0xe0, 0x3f, 0xff, 0xff, 0xff, 0xf2, 0x0, + 0x0, 0x3e, 0x2, 0xd2, 0x22, 0x22, 0x2d, 0x20, + + /* U+51FA "出" */ + 0x0, 0x0, 0x0, 0xe5, 0x0, 0x0, 0x0, 0x49, + 0x0, 0x0, 0xe5, 0x0, 0x0, 0xa3, 0x6c, 0x0, + 0x0, 0xe5, 0x0, 0x0, 0xe4, 0x6c, 0x0, 0x0, + 0xe5, 0x0, 0x0, 0xe4, 0x6c, 0x0, 0x0, 0xe5, + 0x0, 0x0, 0xe4, 0x6d, 0x33, 0x33, 0xe7, 0x33, + 0x33, 0xf4, 0x6f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf4, 0x0, 0x0, 0x0, 0xe5, 0x0, 0x0, 0x0, + 0x41, 0x0, 0x0, 0xe5, 0x0, 0x0, 0x23, 0xe5, + 0x0, 0x0, 0xe5, 0x0, 0x0, 0x7c, 0xe5, 0x0, + 0x0, 0xe5, 0x0, 0x0, 0x7c, 0xe5, 0x0, 0x0, + 0xe5, 0x0, 0x0, 0x7c, 0xe5, 0x0, 0x0, 0xe5, + 0x0, 0x0, 0x7c, 0xe8, 0x55, 0x55, 0xe8, 0x55, + 0x55, 0x9c, 0xce, 0xee, 0xee, 0xee, 0xee, 0xee, + 0xec, + + /* U+52A8 "动" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x30, 0x0, + 0x0, 0x3d, 0xdd, 0xdd, 0xd0, 0x0, 0xf3, 0x0, + 0x0, 0x0, 0x22, 0x22, 0x22, 0x0, 0xf, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0xff, 0xff, + 0xff, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1f, + 0x21, 0x1c, 0x60, 0x44, 0x44, 0x44, 0x43, 0x1, + 0xf1, 0x0, 0xc6, 0xd, 0xdd, 0xfd, 0xdd, 0x90, + 0x2f, 0x0, 0xc, 0x60, 0x0, 0x8b, 0x0, 0x0, + 0x3, 0xf0, 0x0, 0xd5, 0x0, 0xe, 0x40, 0x20, + 0x0, 0x6c, 0x0, 0xd, 0x50, 0x5, 0xd0, 0x4e, + 0x0, 0x9, 0x90, 0x0, 0xe5, 0x0, 0xc5, 0x0, + 0xd7, 0x0, 0xd5, 0x0, 0xf, 0x40, 0x4d, 0x0, + 0x18, 0xe0, 0x4f, 0x0, 0x0, 0xf4, 0xd, 0xff, + 0xfe, 0xdf, 0x6d, 0x80, 0x0, 0x1f, 0x30, 0x32, + 0x10, 0x0, 0x29, 0xe1, 0x24, 0x4a, 0xf0, 0x0, + 0x0, 0x0, 0x4, 0xf4, 0x5, 0xff, 0xe5, 0x0, + 0x0, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, + + /* U+53CC "双" */ + 0x2, 0x22, 0x22, 0x21, 0x12, 0x22, 0x22, 0x22, + 0x0, 0xe, 0xff, 0xff, 0xfb, 0xaf, 0xff, 0xff, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x8a, 0x2f, 0x0, + 0x0, 0x5f, 0x0, 0x1, 0x30, 0x0, 0xb7, 0xf, + 0x20, 0x0, 0x8c, 0x0, 0x7, 0xd0, 0x0, 0xe5, + 0xe, 0x40, 0x0, 0xb8, 0x0, 0x0, 0xd9, 0x1, + 0xf1, 0xa, 0x80, 0x0, 0xf4, 0x0, 0x0, 0x3f, + 0x36, 0xd0, 0x6, 0xc0, 0x4, 0xf0, 0x0, 0x0, + 0x8, 0xdb, 0x80, 0x1, 0xf2, 0xa, 0x90, 0x0, + 0x0, 0x0, 0xdf, 0x20, 0x0, 0xb9, 0x2f, 0x20, + 0x0, 0x0, 0x0, 0xaf, 0x20, 0x0, 0x3f, 0xca, + 0x0, 0x0, 0x0, 0x4, 0xfc, 0xc0, 0x0, 0xc, + 0xf1, 0x0, 0x0, 0x0, 0x1e, 0x81, 0xf7, 0x0, + 0x6f, 0xeb, 0x0, 0x0, 0x0, 0xcd, 0x0, 0x6d, + 0x8, 0xf6, 0x2e, 0xb1, 0x0, 0xa, 0xe2, 0x0, + 0x3, 0xcf, 0x50, 0x2, 0xee, 0x40, 0xa, 0x30, + 0x0, 0x3f, 0xc2, 0x0, 0x0, 0x1b, 0xc0, 0x0, + 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+578B "型" */ + 0x4f, 0xff, 0xff, 0xff, 0xf1, 0x79, 0x2, 0xf0, + 0x0, 0x89, 0x0, 0xb6, 0x0, 0x79, 0x2, 0xf0, + 0x0, 0x89, 0x0, 0xb6, 0x0, 0x79, 0x2, 0xf0, + 0x0, 0x89, 0x0, 0xb6, 0x0, 0x79, 0x2, 0xf0, + 0xef, 0xff, 0xff, 0xff, 0xf9, 0x79, 0x2, 0xf0, + 0x11, 0xc7, 0x11, 0xb7, 0x10, 0x23, 0x2, 0xf0, + 0x1, 0xf3, 0x0, 0xb6, 0x0, 0x0, 0x2, 0xf0, + 0x9, 0xc0, 0x0, 0xb6, 0x0, 0x2, 0x28, 0xf0, + 0x3e, 0x20, 0x0, 0x84, 0x0, 0xe, 0xfe, 0x60, + 0x1, 0x0, 0x0, 0x7, 0x80, 0x0, 0x0, 0x0, + 0x7, 0xee, 0xee, 0xef, 0xfe, 0xee, 0xee, 0x80, + 0x1, 0x22, 0x22, 0x2a, 0xb2, 0x22, 0x22, 0x10, + 0x0, 0x0, 0x0, 0x9, 0xa0, 0x0, 0x0, 0x0, + 0x12, 0x22, 0x22, 0x2a, 0xa2, 0x22, 0x22, 0x21, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + + /* U+5927 "大" */ + 0x0, 0x0, 0x0, 0x7, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8d, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9c, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x2, 0x44, 0x44, 0x44, 0xce, 0x44, + 0x44, 0x44, 0x30, 0x0, 0x0, 0x0, 0xe, 0xf1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xfc, + 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8b, + 0x6d, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, + 0x50, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, + 0xd0, 0x6, 0xf2, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xf2, 0x0, 0xb, 0xe2, 0x0, 0x0, 0x0, 0x1b, + 0xf4, 0x0, 0x0, 0xc, 0xf6, 0x0, 0x0, 0x6e, + 0xe3, 0x0, 0x0, 0x0, 0x8, 0xfc, 0x50, 0x8f, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x3, 0xcb, 0x0, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+5BBD "宽" */ + 0x0, 0x0, 0x0, 0x5, 0x50, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0xc0, 0x0, 0x0, 0x0, + 0x4f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0x5e, 0x11, 0x14, 0x11, 0x11, 0x32, 0x11, 0xc7, + 0x26, 0x0, 0x3f, 0x0, 0x0, 0xc6, 0x0, 0x53, + 0x9e, 0xee, 0xef, 0xee, 0xee, 0xfe, 0xee, 0xec, + 0x12, 0x22, 0x5f, 0x22, 0x22, 0xd7, 0x22, 0x22, + 0x0, 0x0, 0x3, 0x0, 0x0, 0x31, 0x0, 0x0, + 0x0, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xfb, 0x0, + 0x0, 0xd6, 0x0, 0x0, 0x0, 0x0, 0x7c, 0x0, + 0x0, 0xd6, 0x0, 0xd, 0x60, 0x0, 0x7c, 0x0, + 0x0, 0xd6, 0x0, 0xf, 0xb4, 0x0, 0x7c, 0x0, + 0x0, 0xd6, 0x0, 0x6e, 0xd6, 0x0, 0x6b, 0x17, + 0x0, 0x10, 0x6, 0xf5, 0xd6, 0x0, 0x0, 0x4d, + 0x0, 0x27, 0xdf, 0x60, 0xca, 0x11, 0x12, 0xaa, + 0x7e, 0xfd, 0x71, 0x0, 0x4d, 0xff, 0xff, 0xc2, + 0x25, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+5C0F "小" */ + 0x0, 0x0, 0x0, 0x7, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7d, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xd0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x53, 0x0, 0x7d, 0x0, 0x33, + 0x0, 0x0, 0x0, 0xe, 0x70, 0x7, 0xd0, 0x8, + 0xd0, 0x0, 0x0, 0x4, 0xf1, 0x0, 0x7d, 0x0, + 0x1f, 0x60, 0x0, 0x0, 0xbb, 0x0, 0x7, 0xd0, + 0x0, 0x9d, 0x0, 0x0, 0x2f, 0x40, 0x0, 0x7d, + 0x0, 0x1, 0xf6, 0x0, 0x9, 0xd0, 0x0, 0x7, + 0xd0, 0x0, 0x9, 0xe0, 0x1, 0xf5, 0x0, 0x0, + 0x7d, 0x0, 0x0, 0x2f, 0x60, 0xad, 0x0, 0x0, + 0x7, 0xd0, 0x0, 0x0, 0xae, 0x5, 0x50, 0x0, + 0x0, 0x7d, 0x0, 0x0, 0x2, 0x20, 0x0, 0x0, + 0x0, 0x7, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5, 0x55, 0xdc, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0xfd, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+5EA6 "度" */ + 0x0, 0x0, 0x0, 0x0, 0x66, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xc0, 0x0, 0x0, + 0x0, 0x4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x10, 0x4e, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x20, 0x4, 0xe0, 0x1, 0xf0, 0x0, 0x2, + 0xf0, 0x0, 0x0, 0x4e, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xd0, 0x4, 0xe0, 0x12, 0xf1, 0x11, + 0x13, 0xf1, 0x11, 0x0, 0x4e, 0x0, 0x1f, 0x0, + 0x0, 0x2f, 0x0, 0x0, 0x4, 0xe0, 0x1, 0xee, + 0xee, 0xee, 0xe0, 0x0, 0x0, 0x4e, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xd0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x20, 0x0, 0x6b, 0x0, + 0x7d, 0x20, 0x0, 0x1c, 0xb0, 0x0, 0x9, 0x90, + 0x0, 0x9d, 0x30, 0x3d, 0xa0, 0x0, 0x0, 0xd5, + 0x0, 0x0, 0x6f, 0xbe, 0x50, 0x0, 0x0, 0x4f, + 0x10, 0x2, 0x7c, 0xfb, 0xfb, 0x74, 0x0, 0xb, + 0x91, 0xcf, 0xfb, 0x60, 0x1, 0x6b, 0xff, 0xd0, + 0x11, 0x6, 0x40, 0x0, 0x0, 0x0, 0x0, 0x23, + 0x0, + + /* U+5F0F "式" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf3, 0x18, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf3, 0x9, + 0xe3, 0x0, 0x1, 0x11, 0x11, 0x11, 0x11, 0xf4, + 0x11, 0x83, 0x10, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xd5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xb7, 0x0, 0x0, 0x0, 0x1, 0x33, + 0x33, 0x33, 0x30, 0xa8, 0x0, 0x0, 0x0, 0x6, + 0xff, 0xff, 0xff, 0xf1, 0x8a, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4e, 0x0, 0x0, 0x6d, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4e, 0x0, 0x0, 0x3f, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4e, 0x0, 0x0, 0xf, + 0x30, 0x0, 0x10, 0x0, 0x0, 0x4e, 0x0, 0x23, + 0xa, 0x90, 0x2, 0xf0, 0x5, 0x68, 0xbf, 0xef, + 0xea, 0x3, 0xf1, 0x5, 0xc0, 0xa, 0xa8, 0x64, + 0x20, 0x0, 0x0, 0xaa, 0x1b, 0x70, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xeb, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+6027 "性" */ + 0x0, 0xe, 0x40, 0x0, 0x0, 0xe, 0x40, 0x0, + 0x0, 0x0, 0xe4, 0x0, 0x1f, 0x10, 0xf4, 0x0, + 0x0, 0x0, 0xe, 0x91, 0x6, 0xd0, 0xf, 0x40, + 0x0, 0x0, 0x83, 0xeb, 0xd1, 0xbf, 0xff, 0xff, + 0xff, 0xf6, 0xc, 0x2e, 0x49, 0x4f, 0x43, 0x3f, + 0x63, 0x33, 0x10, 0xf0, 0xe4, 0x9, 0xb0, 0x0, + 0xf4, 0x0, 0x0, 0x2d, 0xe, 0x40, 0x84, 0x0, + 0xf, 0x40, 0x0, 0x0, 0x30, 0xe4, 0x0, 0x0, + 0x0, 0xf4, 0x0, 0x0, 0x0, 0xe, 0x40, 0x1f, + 0xff, 0xff, 0xff, 0xff, 0x20, 0x0, 0xe4, 0x0, + 0x22, 0x22, 0xf6, 0x22, 0x20, 0x0, 0xe, 0x40, + 0x0, 0x0, 0xf, 0x40, 0x0, 0x0, 0x0, 0xe4, + 0x0, 0x0, 0x0, 0xf4, 0x0, 0x0, 0x0, 0xe, + 0x40, 0x0, 0x0, 0xf, 0x40, 0x0, 0x0, 0x0, + 0xe4, 0x3, 0x33, 0x33, 0xf6, 0x33, 0x32, 0x0, + 0xe, 0x42, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe0, + + /* U+653E "放" */ + 0x0, 0x0, 0x11, 0x0, 0x0, 0x3, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xc8, 0x0, 0x0, 0x2f, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x7d, 0x0, 0x0, 0x8c, + 0x0, 0x0, 0x0, 0x4, 0x44, 0x6e, 0x54, 0x30, + 0xe8, 0x33, 0x33, 0x30, 0xb, 0xdf, 0xdd, 0xdd, + 0x96, 0xff, 0xff, 0xff, 0xf0, 0x0, 0xf, 0x10, + 0x0, 0xe, 0xb0, 0x0, 0x89, 0x0, 0x0, 0x1f, + 0x10, 0x0, 0x9e, 0xd0, 0x0, 0xa7, 0x0, 0x0, + 0x1f, 0xdd, 0xda, 0xb3, 0xf0, 0x0, 0xd4, 0x0, + 0x0, 0x2f, 0x44, 0x8c, 0x0, 0xc4, 0x1, 0xf0, + 0x0, 0x0, 0x3e, 0x0, 0x5c, 0x0, 0x79, 0x7, + 0xb0, 0x0, 0x0, 0x5c, 0x0, 0x6b, 0x0, 0x1f, + 0x1d, 0x40, 0x0, 0x0, 0x7a, 0x0, 0x7b, 0x0, + 0x9, 0xdc, 0x0, 0x0, 0x0, 0xb7, 0x0, 0x7a, + 0x0, 0x8, 0xf9, 0x0, 0x0, 0x1, 0xf2, 0x0, + 0x89, 0x0, 0x8f, 0x8f, 0x90, 0x0, 0x8, 0xc0, + 0x33, 0xd7, 0x1b, 0xf5, 0x4, 0xfc, 0x20, 0xf, + 0x41, 0xff, 0xb3, 0xfd, 0x30, 0x0, 0x2d, 0xd0, + 0x3, 0x0, 0x0, 0x0, 0x50, 0x0, 0x0, 0x0, + 0x20, + + /* U+6700 "最" */ + 0x0, 0xb, 0xed, 0xdd, 0xdd, 0xdd, 0xde, 0xc0, + 0x0, 0x0, 0xb, 0x70, 0x0, 0x0, 0x0, 0x6, + 0xc0, 0x0, 0x0, 0xb, 0xec, 0xcc, 0xcc, 0xcc, + 0xcd, 0xc0, 0x0, 0x0, 0xb, 0x70, 0x0, 0x0, + 0x0, 0x6, 0xc0, 0x0, 0x0, 0xb, 0xed, 0xdd, + 0xdd, 0xdd, 0xde, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf1, 0x0, + 0x6c, 0x0, 0x8, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6e, 0xaa, 0xad, 0x96, 0xed, 0xdd, 0xdd, + 0x0, 0x0, 0x6c, 0x22, 0x29, 0x90, 0xa6, 0x0, + 0x6b, 0x0, 0x0, 0x6c, 0x0, 0x8, 0x90, 0x4d, + 0x0, 0xd4, 0x0, 0x0, 0x6f, 0xdd, 0xde, 0x90, + 0xb, 0x78, 0xb0, 0x0, 0x0, 0x6c, 0x0, 0x9, + 0xa4, 0x1, 0xfe, 0x10, 0x0, 0x8, 0xcf, 0xcc, + 0xbd, 0xd8, 0x5d, 0x99, 0xd7, 0x20, 0x2, 0x20, + 0x0, 0x8, 0x99, 0x92, 0x0, 0x29, 0xa0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+683C "格" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0x50, 0x0, 0x7, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0xc, 0x50, 0x0, 0x1f, 0xc8, + 0x88, 0x88, 0x0, 0x1, 0x1d, 0x61, 0x0, 0xbd, + 0x77, 0x77, 0xbf, 0x10, 0xe, 0xff, 0xff, 0x4a, + 0xef, 0x30, 0x1, 0xe6, 0x0, 0x0, 0x1f, 0x50, + 0x7e, 0x26, 0xd1, 0x1d, 0x90, 0x0, 0x0, 0x6f, + 0x90, 0x2, 0x0, 0x8e, 0xe8, 0x0, 0x0, 0x0, + 0xbe, 0xdd, 0x20, 0x4, 0xbe, 0xfa, 0x30, 0x0, + 0x3, 0xcc, 0x59, 0xb9, 0xed, 0x60, 0x19, 0xfe, + 0x90, 0xb, 0x6c, 0x50, 0x99, 0x30, 0x0, 0x0, + 0x5, 0x80, 0x3e, 0xc, 0x50, 0x3, 0xff, 0xff, + 0xff, 0xfe, 0x0, 0x6, 0xc, 0x50, 0x4, 0xe2, + 0x22, 0x22, 0x5e, 0x0, 0x0, 0xc, 0x50, 0x4, + 0xe0, 0x0, 0x0, 0x4e, 0x0, 0x0, 0xc, 0x50, + 0x4, 0xe0, 0x0, 0x0, 0x4e, 0x0, 0x0, 0xc, + 0x50, 0x4, 0xf4, 0x44, 0x44, 0x7e, 0x0, 0x0, + 0xc, 0x50, 0x4, 0xfd, 0xdd, 0xdd, 0xde, 0x0, + + /* U+6B21 "次" */ + 0x0, 0x0, 0x0, 0x0, 0x44, 0x0, 0x0, 0x0, + 0x0, 0x24, 0x0, 0x0, 0xc, 0x80, 0x0, 0x0, + 0x0, 0x5, 0xf2, 0x0, 0x2, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xc0, 0x0, 0x8f, 0xdd, 0xdd, + 0xdd, 0xd3, 0x0, 0xe, 0x90, 0x1f, 0x74, 0x44, + 0x44, 0x6f, 0x20, 0x0, 0x47, 0x8, 0xd0, 0xa, + 0x30, 0x8, 0xb0, 0x0, 0x0, 0x2, 0xf4, 0x0, + 0xf4, 0x0, 0xe4, 0x0, 0x0, 0x3, 0x5, 0x0, + 0x1f, 0x60, 0x29, 0x0, 0x0, 0x6, 0xf0, 0x0, + 0x4, 0xfa, 0x0, 0x0, 0x0, 0x0, 0xd8, 0x0, + 0x0, 0x9b, 0xf0, 0x0, 0x0, 0x0, 0x5f, 0x10, + 0x0, 0xe, 0x4c, 0x70, 0x0, 0x0, 0xd, 0x90, + 0x0, 0x9, 0xc0, 0x5e, 0x10, 0x0, 0x5, 0xf1, + 0x0, 0x6, 0xf3, 0x0, 0xbc, 0x0, 0x0, 0xe9, + 0x0, 0x7, 0xf7, 0x0, 0x1, 0xec, 0x10, 0x6, + 0x10, 0x1b, 0xf6, 0x0, 0x0, 0x2, 0xde, 0x40, + 0x0, 0xa, 0xe4, 0x0, 0x0, 0x0, 0x1, 0xb7, + 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+6CD5 "法" */ + 0x1, 0x70, 0x0, 0x0, 0x0, 0x8b, 0x0, 0x0, + 0x0, 0x1, 0xcd, 0x20, 0x0, 0x0, 0x8b, 0x0, + 0x0, 0x0, 0x0, 0xa, 0xc0, 0x33, 0x33, 0xac, + 0x33, 0x33, 0x0, 0x0, 0x0, 0x0, 0xde, 0xee, + 0xff, 0xee, 0xee, 0x30, 0x5, 0x20, 0x0, 0x0, + 0x0, 0x8b, 0x0, 0x0, 0x0, 0x8, 0xf7, 0x0, + 0x0, 0x0, 0x8b, 0x0, 0x0, 0x0, 0x0, 0x4e, + 0x20, 0x0, 0x0, 0x8b, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x1, 0x22, 0x28, 0xf4, 0x22, 0x22, + 0x20, 0x0, 0xf, 0x30, 0x0, 0x1e, 0x70, 0x0, + 0x0, 0x0, 0x0, 0x5f, 0x0, 0x0, 0xac, 0x0, + 0x9b, 0x0, 0x0, 0x0, 0xaa, 0x0, 0x7, 0xe1, + 0x0, 0x1e, 0x70, 0x0, 0x0, 0xf5, 0x0, 0x5f, + 0x30, 0x0, 0x4, 0xf3, 0x0, 0x5, 0xf0, 0x3, + 0xfe, 0xcd, 0xde, 0xff, 0xfe, 0x10, 0x9, 0xb0, + 0x0, 0x76, 0x54, 0x32, 0x11, 0x1c, 0x70, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+753B "画" */ + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1e, 0x10, 0xef, 0xff, 0xff, 0xff, 0x0, 0xe2, + 0x1f, 0x10, 0xf2, 0x8, 0x90, 0x1f, 0x0, 0xf2, + 0x1f, 0x10, 0xf2, 0x8, 0x80, 0x1f, 0x0, 0xf2, + 0x1f, 0x10, 0xf2, 0x8, 0x80, 0x1f, 0x0, 0xf2, + 0x1f, 0x10, 0xff, 0xff, 0xff, 0xff, 0x0, 0xf2, + 0x1f, 0x10, 0xf2, 0x8, 0x80, 0x1f, 0x0, 0xf2, + 0x1f, 0x10, 0xf2, 0x8, 0x80, 0x1f, 0x0, 0xf2, + 0x1f, 0x10, 0xf3, 0x18, 0x91, 0x2f, 0x0, 0xf2, + 0x1f, 0x10, 0xdd, 0xdd, 0xdd, 0xdd, 0x0, 0xf2, + 0x1f, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf2, + 0x1f, 0x54, 0x44, 0x44, 0x44, 0x44, 0x44, 0xf2, + 0x1d, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xf2, + + /* U+7B97 "算" */ + 0x0, 0x0, 0x50, 0x0, 0x0, 0x5, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xc0, 0x0, 0x0, 0x7c, 0x0, + 0x0, 0x0, 0x0, 0x2f, 0xee, 0xee, 0xe3, 0xee, + 0xee, 0xee, 0xc0, 0x2, 0xe6, 0xc, 0x60, 0xb, + 0x90, 0x99, 0x0, 0x0, 0xd, 0x90, 0x2, 0x90, + 0x8, 0x0, 0x19, 0x0, 0x0, 0x3, 0xf, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xf1, 0x0, 0x0, 0xf, + 0x20, 0x0, 0x0, 0x0, 0x1, 0xf1, 0x0, 0x0, + 0xf, 0xcb, 0xbb, 0xbb, 0xbb, 0xbc, 0xf1, 0x0, + 0x0, 0xf, 0x31, 0x11, 0x11, 0x11, 0x12, 0xf1, + 0x0, 0x0, 0xf, 0xba, 0xaa, 0xaa, 0xaa, 0xaa, + 0xf1, 0x0, 0x0, 0xf, 0x31, 0x11, 0x11, 0x11, + 0x13, 0xf1, 0x0, 0x0, 0xb, 0xbf, 0xfb, 0xbb, + 0xbc, 0xfb, 0xb0, 0x0, 0x0, 0x0, 0x9, 0x90, + 0x0, 0x2, 0xf0, 0x0, 0x0, 0xe, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, + 0x5f, 0x30, 0x0, 0x2, 0xf0, 0x0, 0x0, 0x0, + 0x5d, 0xc3, 0x0, 0x0, 0x2, 0xf0, 0x0, 0x0, + 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+7C7B "类" */ + 0x0, 0x23, 0x0, 0x5, 0xe0, 0x0, 0x5, 0x0, + 0x0, 0x5, 0xf8, 0x0, 0x5e, 0x0, 0x3d, 0xc1, + 0x0, 0x0, 0x2, 0xd9, 0x5, 0xe0, 0x3f, 0x70, + 0x0, 0x1, 0x44, 0x44, 0x44, 0x8e, 0x44, 0x54, + 0x44, 0x30, 0x3c, 0xcc, 0xcc, 0xef, 0xfc, 0xcc, + 0xcc, 0xc8, 0x0, 0x0, 0x0, 0x6e, 0x8e, 0x83, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xcc, 0x25, 0xe8, + 0xed, 0x71, 0x0, 0x0, 0x5c, 0xe6, 0x0, 0x5d, + 0x0, 0x5b, 0xfb, 0x40, 0x3c, 0x60, 0x0, 0x2, + 0x70, 0x0, 0x1, 0x8a, 0x1, 0x44, 0x44, 0x44, + 0x9d, 0x44, 0x44, 0x44, 0x30, 0x4c, 0xcc, 0xcc, + 0xcf, 0xfc, 0xcc, 0xcc, 0xca, 0x0, 0x0, 0x0, + 0x2, 0xfb, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xe8, 0xc, 0xc2, 0x0, 0x0, 0x0, 0x0, + 0x3a, 0xf8, 0x0, 0x9, 0xfa, 0x40, 0x0, 0x6b, + 0xef, 0xa2, 0x0, 0x0, 0x3, 0xaf, 0xfc, 0x14, + 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x60, + + /* U+7EBF "线" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xd4, 0x0, 0x5, 0xd0, 0x46, 0x0, + 0x0, 0x0, 0x7c, 0x0, 0x0, 0x4e, 0x2, 0xda, + 0x10, 0x0, 0x1e, 0x30, 0x0, 0x4, 0xe0, 0x0, + 0x70, 0x10, 0xb, 0x80, 0x47, 0x24, 0x8f, 0x9b, + 0xce, 0xfa, 0x7, 0xd1, 0x2e, 0x6a, 0xba, 0xf6, + 0x43, 0x10, 0x0, 0xcf, 0xff, 0xb0, 0x0, 0xf, + 0x20, 0x0, 0x0, 0x0, 0x3, 0xe1, 0x0, 0x0, + 0xe5, 0x46, 0x8b, 0xd2, 0x0, 0xd5, 0x0, 0x9b, + 0xef, 0xec, 0x97, 0x53, 0x0, 0xb9, 0x0, 0x5, + 0x42, 0x99, 0x0, 0x2b, 0x10, 0x7f, 0xef, 0xf6, + 0x0, 0x5, 0xd0, 0x3e, 0x70, 0x2, 0x53, 0x10, + 0x0, 0x0, 0x1f, 0x9e, 0x50, 0x10, 0x0, 0x0, + 0x1, 0x0, 0x3, 0xee, 0x20, 0xd, 0x34, 0x8a, + 0xdf, 0xb0, 0x4b, 0xf9, 0xf2, 0x1, 0xf0, 0x8a, + 0x74, 0x24, 0xdf, 0x91, 0x9, 0xe5, 0x9c, 0x0, + 0x0, 0x0, 0x27, 0x10, 0x0, 0x8, 0xee, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+7F29 "缩" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, 0x0, + 0x0, 0x4, 0xe0, 0x0, 0x0, 0xd, 0x70, 0x0, + 0x0, 0x0, 0xb9, 0x0, 0x22, 0x22, 0x9c, 0x22, + 0x22, 0x0, 0x4f, 0x10, 0x4f, 0xee, 0xee, 0xee, + 0xee, 0xe0, 0xd, 0x60, 0x55, 0xd0, 0x0, 0x0, + 0x0, 0x3e, 0x7, 0xc0, 0x3f, 0x34, 0xc7, 0x66, + 0x66, 0x66, 0x70, 0xcf, 0xff, 0x70, 0x3e, 0x27, + 0x7a, 0xe7, 0x77, 0x1, 0x17, 0xc0, 0xc, 0x80, + 0x0, 0x99, 0x0, 0x0, 0x1, 0xe2, 0x7, 0xf8, + 0xc, 0xef, 0xfe, 0xe5, 0x0, 0xb7, 0x2, 0xfc, + 0x80, 0xd3, 0x0, 0xc, 0x50, 0x7f, 0xbd, 0x86, + 0x98, 0xd, 0x30, 0x0, 0xc5, 0x3, 0x74, 0x31, + 0x9, 0x80, 0xdd, 0xcc, 0xcf, 0x50, 0x0, 0x0, + 0x0, 0x98, 0xd, 0x52, 0x22, 0xc5, 0x0, 0x3, + 0x58, 0x9, 0x80, 0xd3, 0x0, 0xc, 0x50, 0xaf, + 0xff, 0xc0, 0x98, 0xd, 0x41, 0x11, 0xc5, 0x4, + 0x41, 0x0, 0x9, 0x80, 0xde, 0xee, 0xef, 0x50, + + /* U+8F93 "输" */ + 0x0, 0x1, 0x0, 0x0, 0x0, 0x3, 0x10, 0x0, + 0x0, 0x0, 0xe2, 0x0, 0x0, 0x4, 0xf5, 0x0, + 0x0, 0x0, 0x3e, 0x0, 0x0, 0x2, 0xe8, 0xe2, + 0x0, 0x0, 0xce, 0xfd, 0xd7, 0x3, 0xe7, 0x6, + 0xe4, 0x0, 0x3, 0xc7, 0x33, 0x26, 0xf8, 0x22, + 0x27, 0xf9, 0x10, 0xf, 0x24, 0xb, 0xb3, 0xdd, + 0xdd, 0xd4, 0xbc, 0x4, 0xc2, 0xc0, 0x2, 0x22, + 0x20, 0x0, 0x8, 0x10, 0x97, 0x2c, 0x0, 0xff, + 0xff, 0x40, 0x20, 0xe1, 0xd, 0xa9, 0xe8, 0x1f, + 0x22, 0xb4, 0x4b, 0xe, 0x10, 0x67, 0xae, 0x71, + 0xf4, 0x4c, 0x44, 0xb0, 0xe1, 0x0, 0x4, 0xc0, + 0xf, 0xaa, 0xe4, 0x4b, 0xe, 0x10, 0x0, 0x4c, + 0x0, 0xf0, 0xa, 0x44, 0xb0, 0xe1, 0x7, 0x9c, + 0xff, 0x5f, 0xcc, 0xe4, 0x4b, 0xe, 0x10, 0x97, + 0x8c, 0x0, 0xf1, 0x1b, 0x42, 0x70, 0xe1, 0x0, + 0x4, 0xc0, 0xf, 0x0, 0xb4, 0x0, 0x1f, 0x0, + 0x0, 0x4c, 0x0, 0xf5, 0xfe, 0x12, 0xff, 0xa0, + 0x0, 0x0, 0x20, 0x2, 0x1, 0x0, 0x0, 0x0, + 0x0, + + /* U+8FD1 "近" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc8, 0x0, 0x0, 0x1, 0x12, 0x46, + 0x89, 0x0, 0x0, 0x3f, 0x50, 0x5, 0xff, 0xfe, + 0xdc, 0xa9, 0x10, 0x0, 0x7, 0xe0, 0x5, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x10, 0x5, + 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5, 0xe0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0x40, 0x5, 0xff, 0xff, 0xff, 0xff, 0xe0, 0x3, + 0x3e, 0x40, 0x6, 0xd1, 0x11, 0x5e, 0x11, 0x0, + 0x0, 0xe, 0x40, 0x7, 0xc0, 0x0, 0x5e, 0x0, + 0x0, 0x0, 0xe, 0x40, 0xa, 0xa0, 0x0, 0x5e, + 0x0, 0x0, 0x0, 0xe, 0x40, 0xf, 0x60, 0x0, + 0x5e, 0x0, 0x0, 0x0, 0xe, 0x40, 0x8e, 0x0, + 0x0, 0x5e, 0x0, 0x0, 0x0, 0xf, 0x62, 0xf6, + 0x0, 0x0, 0x5e, 0x0, 0x0, 0x0, 0xbd, 0xf4, + 0x40, 0x0, 0x0, 0x28, 0x0, 0x0, 0x8, 0xe1, + 0x6f, 0xa5, 0x33, 0x33, 0x33, 0x33, 0x40, 0xe, + 0x40, 0x2, 0x9c, 0xee, 0xef, 0xff, 0xff, 0xe0, + 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+975E "非" */ + 0x0, 0x0, 0x0, 0xe5, 0x0, 0xe5, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xe, 0x50, 0xe, 0x50, 0x0, + 0x0, 0xc, 0xff, 0xff, 0xf5, 0x0, 0xef, 0xff, + 0xff, 0x40, 0x22, 0x22, 0x2e, 0x50, 0xe, 0x72, + 0x22, 0x20, 0x0, 0x0, 0x0, 0xe5, 0x0, 0xe5, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0x50, 0xe, + 0x50, 0x0, 0x0, 0x3, 0x55, 0x55, 0xf5, 0x0, + 0xe8, 0x55, 0x55, 0x0, 0x7c, 0xcc, 0xcf, 0x50, + 0xe, 0xdc, 0xcc, 0xc0, 0x0, 0x0, 0x0, 0xe5, + 0x0, 0xe5, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, + 0x50, 0xe, 0x50, 0x0, 0x0, 0x2, 0x22, 0x22, + 0xe5, 0x0, 0xe7, 0x22, 0x22, 0x12, 0xff, 0xff, + 0xff, 0x50, 0xe, 0xff, 0xff, 0xfa, 0x0, 0x0, + 0x0, 0xe5, 0x0, 0xe5, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xe, 0x50, 0xe, 0x50, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xe5, 0x0, 0xe5, 0x0, 0x0, 0x0, + + /* U+F001 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x27, + 0xba, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, + 0xdf, 0xff, 0xf2, 0x0, 0x0, 0x0, 0x1, 0x6a, + 0xff, 0xff, 0xff, 0xff, 0x20, 0x0, 0x0, 0x7c, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, 0x0, 0x0, + 0x4f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x20, + 0x0, 0x5, 0xff, 0xff, 0xff, 0xff, 0xb7, 0x3f, + 0xf2, 0x0, 0x0, 0x5f, 0xff, 0xfe, 0x95, 0x0, + 0x1, 0xff, 0x20, 0x0, 0x5, 0xff, 0x73, 0x0, + 0x0, 0x0, 0x1f, 0xf2, 0x0, 0x0, 0x5f, 0xe0, + 0x0, 0x0, 0x0, 0x1, 0xff, 0x20, 0x0, 0x5, + 0xfe, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xf2, 0x0, + 0x0, 0x5f, 0xe0, 0x0, 0x0, 0x0, 0x1, 0xff, + 0x20, 0x0, 0x5, 0xfe, 0x0, 0x0, 0x0, 0x69, + 0x8f, 0xf2, 0x0, 0x0, 0x5f, 0xe0, 0x0, 0x2, + 0xef, 0xff, 0xff, 0x20, 0x3, 0x58, 0xfe, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xf2, 0x2d, 0xff, 0xff, + 0xe0, 0x0, 0x4, 0xff, 0xff, 0xfd, 0xb, 0xff, + 0xff, 0xfe, 0x0, 0x0, 0x4, 0xbd, 0xc8, 0x10, + 0xaf, 0xff, 0xff, 0xb0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0xff, 0xb1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F008 "" */ + 0x51, 0x6, 0x88, 0x88, 0x88, 0x88, 0x88, 0x30, + 0x15, 0xf7, 0x6e, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xb6, 0x8f, 0xfd, 0xcf, 0xf3, 0x33, 0x33, 0x33, + 0x6f, 0xec, 0xdf, 0xf2, 0xc, 0xe0, 0x0, 0x0, + 0x0, 0x3f, 0x70, 0x2f, 0xf2, 0xc, 0xe0, 0x0, + 0x0, 0x0, 0x3f, 0x80, 0x2f, 0xff, 0xff, 0xe0, + 0x0, 0x0, 0x0, 0x3f, 0xff, 0xff, 0xf4, 0x2d, + 0xf9, 0x99, 0x99, 0x99, 0xbf, 0x92, 0x4f, 0xf2, + 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x2f, + 0xfb, 0xaf, 0xf1, 0x11, 0x11, 0x11, 0x5f, 0xda, + 0xbf, 0xf9, 0x8e, 0xe0, 0x0, 0x0, 0x0, 0x3f, + 0xc8, 0x9f, 0xf2, 0xc, 0xe0, 0x0, 0x0, 0x0, + 0x3f, 0x70, 0x2f, 0xf6, 0x4d, 0xe0, 0x0, 0x0, + 0x0, 0x3f, 0xa4, 0x6f, 0xfe, 0xef, 0xfb, 0xbb, + 0xbb, 0xbb, 0xcf, 0xfe, 0xef, 0xc2, 0xc, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x80, 0x2c, + + /* U+F00B "" */ + 0x58, 0x88, 0x70, 0x28, 0x88, 0x88, 0x88, 0x88, + 0x85, 0xff, 0xff, 0xf3, 0x9f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf3, 0xaf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xaf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xd1, 0x6f, + 0xff, 0xff, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, + 0xe1, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfc, 0xff, + 0xff, 0xf3, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf3, 0xaf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf3, 0x9f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x58, 0x88, 0x60, 0x27, 0x88, 0x88, + 0x88, 0x88, 0x85, 0x47, 0x77, 0x50, 0x17, 0x77, + 0x77, 0x77, 0x77, 0x74, 0xff, 0xff, 0xf3, 0x9f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, + 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf3, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, + 0xff, 0xf1, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F00C "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8f, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0x90, 0x9, 0xd2, 0x0, + 0x0, 0x0, 0x8f, 0xff, 0xf9, 0x0, 0x9f, 0xfe, + 0x20, 0x0, 0x8, 0xff, 0xff, 0x90, 0x0, 0xdf, + 0xff, 0xe2, 0x0, 0x8f, 0xff, 0xf9, 0x0, 0x0, + 0x2e, 0xff, 0xfe, 0x28, 0xff, 0xff, 0x90, 0x0, + 0x0, 0x2, 0xef, 0xff, 0xff, 0xff, 0xf9, 0x0, + 0x0, 0x0, 0x0, 0x2e, 0xff, 0xff, 0xff, 0x90, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, 0xff, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2e, 0xff, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xd8, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F00D "" */ + 0x2d, 0xb0, 0x0, 0x0, 0x6, 0xe6, 0xd, 0xff, + 0xc0, 0x0, 0x6, 0xff, 0xf3, 0xcf, 0xff, 0xc0, + 0x6, 0xff, 0xff, 0x31, 0xdf, 0xff, 0xc7, 0xff, + 0xff, 0x50, 0x1, 0xdf, 0xff, 0xff, 0xff, 0x50, + 0x0, 0x1, 0xdf, 0xff, 0xff, 0x50, 0x0, 0x0, + 0x7, 0xff, 0xff, 0xd0, 0x0, 0x0, 0x6, 0xff, + 0xff, 0xff, 0xc0, 0x0, 0x6, 0xff, 0xff, 0xdf, + 0xff, 0xc0, 0x6, 0xff, 0xff, 0x51, 0xdf, 0xff, + 0xc0, 0xff, 0xff, 0x50, 0x1, 0xdf, 0xff, 0x58, + 0xff, 0x50, 0x0, 0x1, 0xdf, 0xd0, 0x5, 0x30, + 0x0, 0x0, 0x1, 0x61, 0x0, + + /* U+F011 "" */ + 0x0, 0x0, 0x0, 0x0, 0xcd, 0x50, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xe3, 0x3, 0xff, + 0xa0, 0xb, 0xc1, 0x0, 0x0, 0x8, 0xff, 0xb0, + 0x3f, 0xfa, 0x4, 0xff, 0xd1, 0x0, 0x4, 0xff, + 0xf6, 0x3, 0xff, 0xa0, 0x1e, 0xff, 0xa0, 0x0, + 0xdf, 0xf7, 0x0, 0x3f, 0xfa, 0x0, 0x2e, 0xff, + 0x40, 0x3f, 0xfc, 0x0, 0x3, 0xff, 0xa0, 0x0, + 0x6f, 0xfa, 0x8, 0xff, 0x60, 0x0, 0x3f, 0xfa, + 0x0, 0x0, 0xef, 0xf0, 0xaf, 0xf2, 0x0, 0x3, + 0xff, 0xa0, 0x0, 0xb, 0xff, 0x1b, 0xff, 0x10, + 0x0, 0x1f, 0xf8, 0x0, 0x0, 0xbf, 0xf1, 0x9f, + 0xf3, 0x0, 0x0, 0x24, 0x0, 0x0, 0xd, 0xff, + 0x6, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xff, 0xd0, 0x1f, 0xff, 0x20, 0x0, 0x0, 0x0, + 0x0, 0xbf, 0xf8, 0x0, 0x9f, 0xfd, 0x20, 0x0, + 0x0, 0x0, 0x9f, 0xfe, 0x10, 0x0, 0xcf, 0xfe, + 0x71, 0x0, 0x4, 0xcf, 0xff, 0x50, 0x0, 0x1, + 0xdf, 0xff, 0xfe, 0xdf, 0xff, 0xff, 0x60, 0x0, + 0x0, 0x0, 0x9f, 0xff, 0xff, 0xff, 0xfd, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x28, 0xce, 0xfd, 0xa5, + 0x0, 0x0, 0x0, + + /* U+F013 "" */ + 0x0, 0x0, 0x0, 0x4, 0x66, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, 0xf3, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x78, 0x17, 0xff, 0xff, + 0xff, 0x71, 0x87, 0x0, 0x4, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x40, 0xd, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x3f, 0xff, + 0xff, 0xfe, 0x88, 0xef, 0xff, 0xff, 0xf3, 0x8, + 0xff, 0xff, 0xd0, 0x0, 0xd, 0xff, 0xff, 0x80, + 0x0, 0xaf, 0xff, 0x50, 0x0, 0x5, 0xff, 0xfa, + 0x0, 0x0, 0xbf, 0xff, 0x30, 0x0, 0x3, 0xff, + 0xfb, 0x0, 0x1, 0xcf, 0xff, 0x80, 0x0, 0x8, + 0xff, 0xfc, 0x10, 0x3e, 0xff, 0xff, 0xf6, 0x0, + 0x6f, 0xff, 0xff, 0xe3, 0x1f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf1, 0x9, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0xdf, + 0x8e, 0xff, 0xff, 0xff, 0xe8, 0xfd, 0x0, 0x0, + 0x11, 0x1, 0x9f, 0xff, 0xf9, 0x10, 0x11, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xff, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2c, 0xee, 0xd2, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+F015 "" */ + 0x0, 0x0, 0x0, 0x0, 0x8, 0x92, 0x0, 0x6b, + 0xb1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2d, 0xff, + 0xe4, 0xa, 0xff, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x4e, 0xff, 0xff, 0xf6, 0xaf, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0xfe, 0x31, 0xcf, 0xff, 0xff, + 0x20, 0x0, 0x0, 0x0, 0x9f, 0xfd, 0x25, 0x70, + 0xaf, 0xff, 0xf2, 0x0, 0x0, 0x1, 0xbf, 0xfa, + 0x8, 0xff, 0xb0, 0x7f, 0xff, 0x40, 0x0, 0x2, + 0xdf, 0xf8, 0xa, 0xff, 0xff, 0xd2, 0x5f, 0xff, + 0x50, 0x4, 0xff, 0xf5, 0x1d, 0xff, 0xff, 0xff, + 0xe4, 0x2e, 0xff, 0x70, 0xdf, 0xe3, 0x3e, 0xff, + 0xff, 0xff, 0xff, 0xf6, 0x1c, 0xff, 0x13, 0xb1, + 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x9, + 0x60, 0x0, 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xe0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0xfd, + 0x88, 0xbf, 0xff, 0xfe, 0x0, 0x0, 0x0, 0xa, + 0xff, 0xff, 0x70, 0x3, 0xff, 0xff, 0xe0, 0x0, + 0x0, 0x0, 0xaf, 0xff, 0xf7, 0x0, 0x3f, 0xff, + 0xfe, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, 0x70, + 0x3, 0xff, 0xff, 0xe0, 0x0, 0x0, 0x0, 0x8f, + 0xff, 0xf5, 0x0, 0x2f, 0xff, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+F019 "" */ + 0x0, 0x0, 0x0, 0x9, 0xaa, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, 0xf3, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, + 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, + 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xee, 0xef, 0xff, 0xfe, 0xee, 0xc0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, + 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, + 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xf8, 0x0, 0x0, 0x0, 0x24, 0x44, 0x44, 0x7, + 0xff, 0x70, 0x44, 0x44, 0x42, 0xff, 0xff, 0xff, + 0xc1, 0x66, 0x1d, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x66, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x66, 0xc4, + 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+F01C "" */ + 0x0, 0x0, 0x4, 0x44, 0x44, 0x44, 0x44, 0x41, + 0x0, 0x0, 0x0, 0x0, 0x1e, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0xb, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, + 0x6, 0xff, 0x50, 0x0, 0x0, 0x0, 0x1, 0xff, + 0xa0, 0x0, 0x1, 0xff, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x5, 0xff, 0x50, 0x0, 0xbf, 0xd0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xfe, 0x10, 0x6f, + 0xf3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1e, + 0xfa, 0xe, 0xff, 0xcc, 0xcc, 0x20, 0x0, 0x0, + 0xbc, 0xcc, 0xef, 0xf2, 0xff, 0xff, 0xff, 0xfa, + 0x0, 0x0, 0x6f, 0xff, 0xff, 0xff, 0x4f, 0xff, + 0xff, 0xff, 0xf8, 0x88, 0x8e, 0xff, 0xff, 0xff, + 0xf4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x4f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x37, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xa0, + + /* U+F021 "" */ + 0x0, 0x0, 0x0, 0x15, 0x66, 0x40, 0x0, 0x5, + 0xcb, 0x0, 0x0, 0x3b, 0xff, 0xff, 0xff, 0x92, + 0x7, 0xff, 0x0, 0x7, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x66, 0xff, 0x0, 0x8f, 0xff, 0xa4, 0x12, + 0x5b, 0xff, 0xfd, 0xff, 0x4, 0xff, 0xe4, 0x0, + 0x0, 0x0, 0x4e, 0xff, 0xff, 0xd, 0xff, 0x30, + 0x0, 0x0, 0x45, 0x46, 0xff, 0xff, 0x4f, 0xf7, + 0x0, 0x0, 0x0, 0xdf, 0xff, 0xff, 0xff, 0x8f, + 0xf1, 0x0, 0x0, 0x0, 0xdf, 0xff, 0xff, 0xff, + 0x2, 0x10, 0x0, 0x0, 0x0, 0x12, 0x22, 0x22, + 0x21, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x67, 0x77, 0x77, 0x75, 0x0, 0x0, + 0x0, 0x6, 0x73, 0xff, 0xff, 0xff, 0xfe, 0x0, + 0x0, 0x0, 0x3f, 0xf6, 0xff, 0xff, 0xee, 0xfd, + 0x0, 0x0, 0x0, 0xcf, 0xf1, 0xff, 0xff, 0x70, + 0x0, 0x0, 0x0, 0x9, 0xff, 0xa0, 0xff, 0xff, + 0xfb, 0x20, 0x0, 0x2, 0xbf, 0xfe, 0x10, 0xff, + 0x8d, 0xff, 0xfc, 0xa9, 0xcf, 0xff, 0xe2, 0x0, + 0xff, 0x61, 0x9f, 0xff, 0xff, 0xff, 0xfb, 0x10, + 0x0, 0xff, 0x70, 0x1, 0x7c, 0xee, 0xd9, 0x30, + 0x0, 0x0, 0x56, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+F026 "" */ + 0x0, 0x0, 0x0, 0x2, 0x40, 0x0, 0x0, 0x2, + 0xef, 0x0, 0x0, 0x2, 0xef, 0xf0, 0x0, 0x3, + 0xef, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0xbb, 0xdf, + 0xff, 0xf0, 0x0, 0x0, 0xbf, 0xff, 0x0, 0x0, + 0x0, 0xbf, 0xf0, 0x0, 0x0, 0x0, 0xbe, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F027 "" */ + 0x0, 0x0, 0x0, 0x2, 0x40, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2e, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xef, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x3e, + 0xff, 0xf0, 0x0, 0x0, 0xdf, 0xff, 0xff, 0xff, + 0xf0, 0x7, 0x10, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x3f, 0xd0, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8, + 0xf5, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x4, 0xf7, + 0xff, 0xff, 0xff, 0xff, 0xf0, 0xd, 0xf3, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0x3f, 0x70, 0x8b, 0xbb, + 0xdf, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0xb, + 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F028 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x7, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0x40, 0x0, 0x0, 0x2d, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xef, 0x0, 0x0, 0x40, 0x1c, + 0xf4, 0x0, 0x0, 0x0, 0x2, 0xef, 0xf0, 0x0, + 0x5f, 0xb0, 0x1e, 0xe1, 0x0, 0x0, 0x3, 0xef, + 0xff, 0x0, 0x0, 0xaf, 0xa0, 0x6f, 0x70, 0xdf, + 0xff, 0xff, 0xff, 0xf0, 0x7, 0x10, 0xbf, 0x30, + 0xfd, 0xf, 0xff, 0xff, 0xff, 0xff, 0x3, 0xfd, + 0x3, 0xf9, 0xa, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x7, 0xf5, 0xe, 0xc0, 0x8f, 0x2f, 0xff, + 0xff, 0xff, 0xff, 0x0, 0x4f, 0x70, 0xdd, 0x7, + 0xf3, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x1d, 0xf3, + 0xf, 0xb0, 0x9f, 0x2f, 0xff, 0xff, 0xff, 0xff, + 0x3, 0xf7, 0x7, 0xf6, 0xc, 0xf0, 0x7b, 0xbb, + 0xdf, 0xff, 0xf0, 0x0, 0x3, 0xfe, 0x12, 0xfa, + 0x0, 0x0, 0x0, 0xbf, 0xff, 0x0, 0x3, 0xff, + 0x40, 0xaf, 0x30, 0x0, 0x0, 0x0, 0xbf, 0xf0, + 0x0, 0x3c, 0x30, 0x6f, 0xa0, 0x0, 0x0, 0x0, + 0x0, 0xbe, 0x0, 0x0, 0x0, 0x6f, 0xe1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, + 0xd2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3, 0x90, 0x0, 0x0, + + /* U+F03E "" */ + 0x3a, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xa3, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0xff, 0xd5, 0x6e, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x20, 0x4, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x2, 0xff, + 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff, 0x50, 0x7, + 0xff, 0xff, 0xf5, 0x8, 0xff, 0xff, 0xff, 0xfb, + 0xbf, 0xff, 0xff, 0x50, 0x0, 0x8f, 0xff, 0xff, + 0xff, 0xcb, 0xff, 0xf5, 0x0, 0x0, 0x9, 0xff, + 0xff, 0xfc, 0x0, 0xaf, 0x50, 0x0, 0x0, 0x4, + 0xff, 0xff, 0xc0, 0x0, 0x3, 0x0, 0x0, 0x0, + 0x4, 0xff, 0xff, 0x40, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4, 0xff, 0xff, 0x74, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x47, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x6f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, + + /* U+F043 "" */ + 0x0, 0x0, 0x6, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x1, 0xff, 0x40, 0x0, 0x0, 0x0, 0x0, 0x6f, + 0xfa, 0x0, 0x0, 0x0, 0x0, 0xd, 0xff, 0xf2, + 0x0, 0x0, 0x0, 0x5, 0xff, 0xff, 0x90, 0x0, + 0x0, 0x0, 0xef, 0xff, 0xff, 0x30, 0x0, 0x0, + 0x9f, 0xff, 0xff, 0xfd, 0x0, 0x0, 0x5f, 0xff, + 0xff, 0xff, 0xf9, 0x0, 0xe, 0xff, 0xff, 0xff, + 0xff, 0xf3, 0x7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xa0, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf, + 0xfb, 0xff, 0xff, 0xff, 0xff, 0xf2, 0xff, 0x4a, + 0xff, 0xff, 0xff, 0xff, 0x2c, 0xf8, 0x4f, 0xff, + 0xff, 0xff, 0xf0, 0x7f, 0xf2, 0x5c, 0xff, 0xff, + 0xfb, 0x0, 0xef, 0xe5, 0x8, 0xff, 0xff, 0x30, + 0x2, 0xef, 0xff, 0xff, 0xff, 0x50, 0x0, 0x1, + 0xaf, 0xff, 0xfb, 0x30, 0x0, 0x0, 0x0, 0x3, + 0x31, 0x0, 0x0, 0x0, + + /* U+F048 "" */ + 0x6b, 0x90, 0x0, 0x0, 0x3, 0xa2, 0x9f, 0xe0, + 0x0, 0x0, 0x4f, 0xf9, 0x9f, 0xe0, 0x0, 0x5, + 0xff, 0xfa, 0x9f, 0xe0, 0x0, 0x6f, 0xff, 0xfa, + 0x9f, 0xe0, 0x7, 0xff, 0xff, 0xfa, 0x9f, 0xe0, + 0x8f, 0xff, 0xff, 0xfa, 0x9f, 0xe9, 0xff, 0xff, + 0xff, 0xfa, 0x9f, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0x9f, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x9f, 0xfe, + 0xff, 0xff, 0xff, 0xfa, 0x9f, 0xe1, 0xdf, 0xff, + 0xff, 0xfa, 0x9f, 0xe0, 0x1c, 0xff, 0xff, 0xfa, + 0x9f, 0xe0, 0x0, 0xbf, 0xff, 0xfa, 0x9f, 0xe0, + 0x0, 0xa, 0xff, 0xfa, 0x9f, 0xe0, 0x0, 0x0, + 0x9f, 0xfa, 0x9f, 0xe0, 0x0, 0x0, 0x8, 0xf6, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F04B "" */ + 0x3a, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xef, 0xfe, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xfb, 0x20, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xe6, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xc3, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x91, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x60, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe2, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, 0x20, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0x70, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xa1, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xd3, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xaf, 0xe6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F04C "" */ + 0x3a, 0xbb, 0xb9, 0x10, 0x3, 0xab, 0xbb, 0x91, + 0xef, 0xff, 0xff, 0xa0, 0xe, 0xff, 0xff, 0xfa, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xb0, 0xf, 0xff, 0xff, 0xfb, + 0x7f, 0xff, 0xfe, 0x40, 0x7, 0xff, 0xff, 0xe4, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F04D "" */ + 0x3a, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x91, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe4, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F051 "" */ + 0x4a, 0x20, 0x0, 0x0, 0xa, 0xb4, 0xbf, 0xe3, + 0x0, 0x0, 0xf, 0xf8, 0xcf, 0xff, 0x40, 0x0, + 0xf, 0xf8, 0xcf, 0xff, 0xf5, 0x0, 0xf, 0xf8, + 0xcf, 0xff, 0xff, 0x60, 0xf, 0xf8, 0xcf, 0xff, + 0xff, 0xf7, 0xf, 0xf8, 0xcf, 0xff, 0xff, 0xff, + 0x9f, 0xf8, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xcf, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xcf, 0xff, + 0xff, 0xff, 0xdf, 0xf8, 0xcf, 0xff, 0xff, 0xfc, + 0x1f, 0xf8, 0xcf, 0xff, 0xff, 0xb0, 0xf, 0xf8, + 0xcf, 0xff, 0xfa, 0x0, 0xf, 0xf8, 0xcf, 0xff, + 0x80, 0x0, 0xf, 0xf8, 0xbf, 0xf7, 0x0, 0x0, + 0xf, 0xf8, 0x7f, 0x60, 0x0, 0x0, 0xf, 0xf7, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F052 "" */ + 0x0, 0x0, 0x0, 0x2, 0xca, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2e, 0xff, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xef, 0xff, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1d, 0xff, 0xff, + 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, + 0xff, 0xff, 0xf9, 0x0, 0x0, 0x0, 0xb, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x70, 0x0, 0x0, 0xaf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x0, 0x8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xb0, 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x60, 0x0, 0x34, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x42, 0x0, 0x3, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x10, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xb0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb0, 0xc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F053 "" */ + 0x0, 0x0, 0x0, 0x0, 0x41, 0x0, 0x0, 0x0, + 0x0, 0x9f, 0xd0, 0x0, 0x0, 0x0, 0x9f, 0xff, + 0x20, 0x0, 0x0, 0x9f, 0xff, 0x50, 0x0, 0x0, + 0x9f, 0xff, 0x50, 0x0, 0x0, 0x9f, 0xff, 0x50, + 0x0, 0x0, 0x9f, 0xff, 0x50, 0x0, 0x0, 0x9f, + 0xff, 0x50, 0x0, 0x0, 0xe, 0xff, 0xd1, 0x0, + 0x0, 0x0, 0x3e, 0xff, 0xc1, 0x0, 0x0, 0x0, + 0x3e, 0xff, 0xc1, 0x0, 0x0, 0x0, 0x3e, 0xff, + 0xc1, 0x0, 0x0, 0x0, 0x3e, 0xff, 0xc1, 0x0, + 0x0, 0x0, 0x3e, 0xff, 0xc0, 0x0, 0x0, 0x0, + 0x3e, 0xff, 0x20, 0x0, 0x0, 0x0, 0x3c, 0x60, + + /* U+F054 "" */ + 0x0, 0x50, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xc1, + 0x0, 0x0, 0x0, 0xe, 0xff, 0xc1, 0x0, 0x0, + 0x0, 0x2e, 0xff, 0xc1, 0x0, 0x0, 0x0, 0x2e, + 0xff, 0xc1, 0x0, 0x0, 0x0, 0x2e, 0xff, 0xc1, + 0x0, 0x0, 0x0, 0x2e, 0xff, 0xc1, 0x0, 0x0, + 0x0, 0x2e, 0xff, 0xc0, 0x0, 0x0, 0x0, 0xaf, + 0xff, 0x20, 0x0, 0x0, 0x9f, 0xff, 0x50, 0x0, + 0x0, 0x9f, 0xff, 0x50, 0x0, 0x0, 0x9f, 0xff, + 0x50, 0x0, 0x0, 0x9f, 0xff, 0x50, 0x0, 0x0, + 0x9f, 0xff, 0x60, 0x0, 0x0, 0xe, 0xff, 0x60, + 0x0, 0x0, 0x0, 0x3d, 0x50, 0x0, 0x0, 0x0, + + /* U+F067 "" */ + 0x0, 0x0, 0x0, 0x39, 0x91, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0xf9, 0x0, 0x0, 0x0, + 0x36, 0x77, 0x77, 0xef, 0xfc, 0x77, 0x77, 0x61, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0xae, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe6, + 0x0, 0x0, 0x0, 0xdf, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9f, 0xf5, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0x10, 0x0, 0x0, 0x0, + + /* U+F068 "" */ + 0x36, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x61, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, + + /* U+F06E "" */ + 0x0, 0x0, 0x0, 0x3, 0x68, 0x87, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8e, 0xff, 0xff, + 0xff, 0xf9, 0x20, 0x0, 0x0, 0x0, 0x4, 0xef, + 0xfd, 0x63, 0x25, 0xbf, 0xff, 0x70, 0x0, 0x0, + 0x7, 0xff, 0xfa, 0x0, 0x0, 0x0, 0x7f, 0xff, + 0xa0, 0x0, 0x6, 0xff, 0xfd, 0x0, 0x8, 0xfc, + 0x20, 0x9f, 0xff, 0xa0, 0x2, 0xff, 0xff, 0x50, + 0x0, 0x8f, 0xfe, 0x12, 0xff, 0xff, 0x60, 0xcf, + 0xff, 0xf2, 0x16, 0x7f, 0xff, 0xf5, 0xe, 0xff, + 0xfe, 0x1e, 0xff, 0xff, 0x12, 0xff, 0xff, 0xff, + 0x70, 0xdf, 0xff, 0xf2, 0x6f, 0xff, 0xf3, 0xe, + 0xff, 0xff, 0xf3, 0xf, 0xff, 0xfb, 0x0, 0xbf, + 0xff, 0x90, 0x4f, 0xff, 0xf8, 0x5, 0xff, 0xfe, + 0x10, 0x1, 0xdf, 0xff, 0x40, 0x28, 0x84, 0x1, + 0xef, 0xff, 0x30, 0x0, 0x1, 0xbf, 0xff, 0x60, + 0x0, 0x4, 0xef, 0xfd, 0x30, 0x0, 0x0, 0x0, + 0x6e, 0xff, 0xfb, 0xbe, 0xff, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xad, 0xff, 0xeb, 0x71, + 0x0, 0x0, 0x0, + + /* U+F070 "" */ + 0x4a, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xe, 0xfe, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0xff, 0x60, 0x0, 0x15, 0x78, 0x74, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2d, 0xff, 0xa6, 0xdf, 0xff, + 0xff, 0xff, 0xa2, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xff, 0xff, 0xe8, 0x32, 0x5b, 0xff, 0xf8, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xff, 0xf6, 0x0, 0x10, + 0x6, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xef, 0xf8, 0x7f, 0xd3, 0x9, 0xff, 0xfb, 0x0, + 0x0, 0x1e, 0x70, 0x1, 0xbf, 0xfe, 0xff, 0xf2, + 0x1f, 0xff, 0xf7, 0x0, 0x9, 0xff, 0xa0, 0x0, + 0x8f, 0xff, 0xff, 0x70, 0xdf, 0xff, 0xf1, 0x0, + 0xcf, 0xff, 0xd1, 0x0, 0x5f, 0xff, 0xf9, 0xc, + 0xff, 0xff, 0x30, 0x5, 0xff, 0xff, 0x60, 0x0, + 0x2d, 0xff, 0xb0, 0xef, 0xff, 0xb0, 0x0, 0xa, + 0xff, 0xfc, 0x0, 0x0, 0xa, 0xff, 0xef, 0xff, + 0xe1, 0x0, 0x0, 0xc, 0xff, 0xf6, 0x0, 0x0, + 0x6, 0xff, 0xff, 0xf3, 0x0, 0x0, 0x0, 0xa, + 0xff, 0xf8, 0x10, 0x0, 0x3, 0xef, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xef, 0xff, 0xcb, 0x80, + 0x1, 0xbf, 0xfb, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x5a, 0xdf, 0xfe, 0x70, 0x0, 0x8f, 0xfe, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5f, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2d, 0xe1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0x0, + + /* U+F071 "" */ + 0x0, 0x0, 0x0, 0x0, 0x1, 0xcd, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0xff, 0xff, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xff, 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xe, 0xff, 0xff, 0xff, 0xf3, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xfb, 0x33, + 0x8f, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xff, 0xf9, 0x0, 0x6f, 0xff, 0x60, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xff, 0xfa, 0x0, 0x6f, 0xff, + 0xe0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xfb, + 0x0, 0x7f, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0xff, 0xfc, 0x0, 0x8f, 0xff, 0xff, 0x10, + 0x0, 0x0, 0x6, 0xff, 0xff, 0xfd, 0x0, 0x9f, + 0xff, 0xff, 0xa0, 0x0, 0x0, 0xe, 0xff, 0xff, + 0xff, 0xcb, 0xff, 0xff, 0xff, 0xf3, 0x0, 0x0, + 0x8f, 0xff, 0xff, 0xfc, 0x0, 0x8f, 0xff, 0xff, + 0xfc, 0x0, 0x2, 0xff, 0xff, 0xff, 0xf9, 0x0, + 0x4f, 0xff, 0xff, 0xff, 0x60, 0xa, 0xff, 0xff, + 0xff, 0xfe, 0x42, 0xcf, 0xff, 0xff, 0xff, 0xe0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf3, 0x9, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0, 0x23, + 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, + 0x0, + + /* U+F074 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xf9, 0x0, 0x12, 0x22, 0x10, 0x0, 0x0, 0x1, + 0x29, 0xff, 0x90, 0xff, 0xff, 0xe2, 0x0, 0x0, + 0x6f, 0xff, 0xff, 0xf8, 0xff, 0xff, 0xfe, 0x20, + 0x5, 0xff, 0xff, 0xff, 0xfd, 0x9a, 0xad, 0xff, + 0xd0, 0x5f, 0xff, 0xbd, 0xff, 0xe2, 0x0, 0x0, + 0xcf, 0x44, 0xff, 0xf9, 0x8, 0xfe, 0x20, 0x0, + 0x0, 0x4, 0x4f, 0xff, 0x90, 0x4, 0xd2, 0x0, + 0x0, 0x0, 0x3, 0xff, 0xfa, 0x0, 0x0, 0x10, + 0x0, 0x0, 0x0, 0x3f, 0xff, 0xa1, 0x91, 0x6, + 0xf6, 0x0, 0x0, 0x2, 0xef, 0xfb, 0xc, 0xfc, + 0x8, 0xff, 0x60, 0xef, 0xff, 0xff, 0xb0, 0x1d, + 0xff, 0xff, 0xff, 0xf6, 0xff, 0xff, 0xfc, 0x0, + 0x2, 0xef, 0xff, 0xff, 0xfe, 0xdd, 0xdd, 0xb0, + 0x0, 0x0, 0x2d, 0xde, 0xff, 0xf5, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xf5, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F077 "" */ + 0x0, 0x0, 0x0, 0x4, 0x20, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5f, 0xe2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xff, 0xfe, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0xff, 0xff, 0xe3, 0x0, 0x0, + 0x0, 0x6, 0xff, 0xfa, 0xcf, 0xfe, 0x30, 0x0, + 0x0, 0x6f, 0xff, 0x90, 0xc, 0xff, 0xe3, 0x0, + 0x6, 0xff, 0xf9, 0x0, 0x0, 0xcf, 0xfe, 0x30, + 0x5f, 0xff, 0x90, 0x0, 0x0, 0xc, 0xff, 0xe2, + 0xaf, 0xf9, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xf6, + 0x1b, 0x80, 0x0, 0x0, 0x0, 0x0, 0xb, 0x90, + + /* U+F078 "" */ + 0x3, 0x20, 0x0, 0x0, 0x0, 0x0, 0x3, 0x20, + 0x6f, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xf2, + 0xaf, 0xfe, 0x20, 0x0, 0x0, 0x5, 0xff, 0xf6, + 0x1c, 0xff, 0xe3, 0x0, 0x0, 0x5f, 0xff, 0x90, + 0x1, 0xcf, 0xfe, 0x30, 0x5, 0xff, 0xf9, 0x0, + 0x0, 0x1c, 0xff, 0xe3, 0x5f, 0xff, 0x90, 0x0, + 0x0, 0x1, 0xcf, 0xff, 0xff, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x1c, 0xff, 0xff, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xcf, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1b, 0x90, 0x0, 0x0, 0x0, + + /* U+F079 "" */ + 0x0, 0x0, 0x26, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, 0xa0, + 0x0, 0x44, 0x44, 0x44, 0x44, 0x42, 0x0, 0x0, + 0x0, 0x3e, 0xff, 0xfa, 0x4, 0xff, 0xff, 0xff, + 0xff, 0xfd, 0x0, 0x0, 0x3, 0xef, 0xff, 0xff, + 0xa0, 0xaf, 0xff, 0xff, 0xff, 0xfe, 0x0, 0x0, + 0xe, 0xfd, 0xef, 0xcf, 0xf8, 0x0, 0x0, 0x0, + 0x5, 0xfe, 0x0, 0x0, 0xb, 0xe2, 0xdf, 0x67, + 0xf5, 0x0, 0x0, 0x0, 0x5, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0x60, 0x0, 0x0, 0x0, 0x0, + 0x5, 0xfe, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0x60, 0x0, 0x0, 0x0, 0x4, + 0x15, 0xfe, 0x3, 0x20, 0x0, 0x0, 0xdf, 0x60, + 0x0, 0x0, 0x0, 0x6f, 0xd6, 0xfe, 0x4f, 0xf1, + 0x0, 0x0, 0xdf, 0x94, 0x44, 0x44, 0x41, 0x3f, + 0xff, 0xff, 0xff, 0xc0, 0x0, 0x0, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0x24, 0xff, 0xff, 0xfc, 0x10, + 0x0, 0x0, 0x9f, 0xff, 0xff, 0xff, 0xfe, 0x30, + 0x4f, 0xff, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x10, 0x0, 0x0, + + /* U+F07B "" */ + 0x17, 0x88, 0x88, 0x84, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0xff, 0xff, 0xff, 0x50, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x44, + 0x44, 0x44, 0x30, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfa, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, + + /* U+F093 "" */ + 0x0, 0x0, 0x0, 0x0, 0x47, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0x90, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, + 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, + 0xff, 0xff, 0xf9, 0x0, 0x0, 0x0, 0x4, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0x0, 0xc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf1, 0x0, 0x0, + 0x0, 0x11, 0x2f, 0xff, 0xf7, 0x11, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xff, 0xf6, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1f, 0xff, 0xf6, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xff, 0xf6, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xff, + 0xf6, 0x0, 0x0, 0x0, 0x24, 0x44, 0x42, 0x1f, + 0xff, 0xf6, 0x24, 0x44, 0x42, 0xff, 0xff, 0xfc, + 0x8, 0xbb, 0xa2, 0xcf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xa5, 0x55, 0x5a, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x66, 0xc4, + 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+F095 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xb8, + 0x41, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1f, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xff, 0xff, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xdf, 0xff, 0xff, 0xc0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3, 0xff, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xdf, 0xff, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0x90, + 0x0, 0x0, 0x4, 0xa5, 0x0, 0x0, 0xaf, 0xff, + 0xd0, 0x0, 0x0, 0x7d, 0xff, 0xf4, 0x2, 0xcf, + 0xff, 0xe2, 0x0, 0x0, 0xdf, 0xff, 0xff, 0xe9, + 0xff, 0xff, 0xf3, 0x0, 0x0, 0xd, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, 0x9f, + 0xff, 0xff, 0xff, 0xff, 0xa1, 0x0, 0x0, 0x0, + 0x6, 0xff, 0xff, 0xff, 0xfc, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xff, 0xfd, 0x83, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x23, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F0C4 "" */ + 0x0, 0x35, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1c, 0xff, 0xfa, 0x0, 0x0, 0x1, 0x9c, 0xa1, + 0xaf, 0xfe, 0xff, 0x60, 0x0, 0x2e, 0xff, 0xf9, + 0xef, 0x60, 0xaf, 0xb0, 0x3, 0xef, 0xff, 0xb0, + 0xef, 0x92, 0xcf, 0x90, 0x3e, 0xff, 0xfa, 0x0, + 0x7f, 0xff, 0xff, 0xe6, 0xff, 0xff, 0xa0, 0x0, + 0x8, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, 0x0, + 0x0, 0x1, 0xcf, 0xff, 0xff, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0xff, 0xff, 0x10, 0x0, 0x0, + 0x0, 0x36, 0xef, 0xff, 0xff, 0xd1, 0x0, 0x0, + 0x1c, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x10, 0x0, + 0xaf, 0xfe, 0xff, 0xc2, 0xdf, 0xff, 0xd1, 0x0, + 0xef, 0x60, 0xaf, 0xa0, 0x1c, 0xff, 0xfd, 0x20, + 0xef, 0x92, 0xcf, 0xa0, 0x0, 0xcf, 0xff, 0xe2, + 0x7f, 0xff, 0xff, 0x40, 0x0, 0xb, 0xff, 0xf9, + 0x8, 0xff, 0xe5, 0x0, 0x0, 0x0, 0x58, 0x50, + 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F0C5 "" */ + 0x0, 0x0, 0x6f, 0xff, 0xff, 0xf1, 0x68, 0x0, + 0x0, 0x0, 0xaf, 0xff, 0xff, 0xf1, 0x7f, 0x80, + 0x0, 0x0, 0xaf, 0xff, 0xff, 0xf1, 0x7f, 0xf8, + 0x36, 0x62, 0xaf, 0xff, 0xff, 0xf1, 0x36, 0x66, + 0xff, 0xf6, 0xaf, 0xff, 0xff, 0xf6, 0x22, 0x22, + 0xff, 0xf6, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xf6, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xf6, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xf6, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xf6, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xf6, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xf6, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xf6, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xf6, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xf7, 0x6f, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0xff, 0xfe, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf1, 0x0, 0x0, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, + 0x14, 0x44, 0x44, 0x44, 0x44, 0x20, 0x0, 0x0, + + /* U+F0C7 "" */ + 0x5, 0x66, 0x66, 0x66, 0x66, 0x64, 0x0, 0x0, + 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, + 0xff, 0xed, 0xdd, 0xdd, 0xdd, 0xef, 0xf9, 0x0, + 0xff, 0x40, 0x0, 0x0, 0x0, 0xf, 0xff, 0x90, + 0xff, 0x40, 0x0, 0x0, 0x0, 0xe, 0xff, 0xf6, + 0xff, 0x40, 0x0, 0x0, 0x0, 0xe, 0xff, 0xf9, + 0xff, 0x40, 0x0, 0x0, 0x0, 0xf, 0xff, 0xf9, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, + 0xff, 0xff, 0xff, 0xc5, 0x7f, 0xff, 0xff, 0xf9, + 0xff, 0xff, 0xfe, 0x0, 0x5, 0xff, 0xff, 0xf9, + 0xff, 0xff, 0xfa, 0x0, 0x1, 0xff, 0xff, 0xf9, + 0xff, 0xff, 0xfd, 0x0, 0x4, 0xff, 0xff, 0xf9, + 0xff, 0xff, 0xff, 0x93, 0x4d, 0xff, 0xff, 0xf9, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe3, + 0x1, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0x0, + + /* U+F0C9 "" */ + 0x79, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x95, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x68, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x84, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x67, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x74, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F0E0 "" */ + 0x3, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x30, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xcf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfc, 0xa, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xa0, 0xa1, 0x6f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf6, 0x3d, 0xfe, 0x42, + 0xdf, 0xff, 0xff, 0xff, 0xfd, 0x26, 0xff, 0xff, + 0xf9, 0x19, 0xff, 0xff, 0xff, 0x91, 0xbf, 0xff, + 0xff, 0xff, 0xd3, 0x5f, 0xff, 0xe5, 0x4e, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x71, 0x99, 0x17, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x77, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, + + /* U+F0E7 "" */ + 0x0, 0xaf, 0xff, 0xff, 0xa0, 0x0, 0x0, 0xf, + 0xff, 0xff, 0xfb, 0x0, 0x0, 0x1, 0xff, 0xff, + 0xff, 0x60, 0x0, 0x0, 0x3f, 0xff, 0xff, 0xf1, + 0x0, 0x0, 0x5, 0xff, 0xff, 0xfb, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xa5, 0x55, 0x40, 0xa, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0xcf, 0xff, + 0xff, 0xff, 0xff, 0xc0, 0xe, 0xff, 0xff, 0xff, + 0xff, 0xf3, 0x0, 0xef, 0xff, 0xff, 0xff, 0xfa, + 0x0, 0x1, 0x22, 0x23, 0xff, 0xff, 0x10, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0x70, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, 0xcf, + 0xf5, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xff, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x7, 0xe1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F0EA "" */ + 0x0, 0x0, 0x8d, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x8b, 0xbc, 0xfa, 0xfd, 0xbb, 0x90, 0x0, 0x0, + 0xff, 0xff, 0xd0, 0xcf, 0xff, 0xf1, 0x0, 0x0, + 0xff, 0xff, 0xf8, 0xff, 0xff, 0xf1, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf1, 0x0, 0x0, + 0xff, 0xff, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0x95, 0xff, 0xff, 0xf1, 0x79, 0x0, + 0xff, 0xff, 0x88, 0xff, 0xff, 0xf1, 0x7f, 0xb0, + 0xff, 0xff, 0x88, 0xff, 0xff, 0xf1, 0x7f, 0xfa, + 0xff, 0xff, 0x88, 0xff, 0xff, 0xf2, 0x2, 0x21, + 0xff, 0xff, 0x88, 0xff, 0xff, 0xff, 0xdd, 0xdc, + 0xff, 0xff, 0x88, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0x88, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0x88, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x7a, 0xaa, 0x58, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x0, 0x0, 0x6, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F0F3 "" */ + 0x0, 0x0, 0x0, 0x8, 0x60, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6, 0xcf, 0xfa, 0x40, 0x0, 0x0, + 0x0, 0x1, 0xcf, 0xff, 0xff, 0xf9, 0x0, 0x0, + 0x0, 0xc, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, + 0x0, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xf1, 0x0, + 0x0, 0x9f, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x0, + 0x0, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x0, + 0x0, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, + 0x0, 0xef, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, + 0x2, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x0, + 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, + 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd1, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0xf7, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0x10, 0x0, 0x0, 0x0, + + /* U+F11C "" */ + 0x4, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x41, 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xe0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, + 0xf4, 0x4, 0xd0, 0x2f, 0x0, 0xf3, 0x3, 0xf0, + 0xf, 0xf4, 0xff, 0x40, 0x5d, 0x2, 0xf0, 0xf, + 0x40, 0x4f, 0x0, 0xff, 0x4f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0xff, + 0xff, 0x22, 0xb7, 0x29, 0xa2, 0x4f, 0x42, 0xcf, + 0xff, 0x4f, 0xff, 0xf0, 0xa, 0x60, 0x79, 0x2, + 0xf2, 0xb, 0xff, 0xf4, 0xff, 0xff, 0xdd, 0xfe, + 0xdf, 0xfd, 0xef, 0xed, 0xff, 0xff, 0x4f, 0xf8, + 0x48, 0xe4, 0x44, 0x44, 0x44, 0x47, 0xf4, 0x5f, + 0xf4, 0xff, 0x40, 0x4d, 0x0, 0x0, 0x0, 0x0, + 0x3e, 0x0, 0xff, 0x4f, 0xf7, 0x48, 0xe4, 0x44, + 0x44, 0x44, 0x47, 0xf4, 0x4f, 0xf4, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x37, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xa0, + + /* U+F124 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0x8b, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xaf, 0xff, 0xd0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xbf, 0xff, 0xff, 0xd0, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xcf, 0xff, 0xff, + 0xff, 0x70, 0x0, 0x0, 0x0, 0x6, 0xdf, 0xff, + 0xff, 0xff, 0xfe, 0x0, 0x0, 0x0, 0x17, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x29, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf1, 0x0, + 0x7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x90, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x20, 0x0, 0xb, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x56, + 0x66, 0x66, 0x7f, 0xff, 0xff, 0xf3, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2f, 0xff, 0xff, 0xc0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xff, + 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2f, 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xff, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2f, 0xff, 0xe0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xff, + 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x30, 0x0, 0x0, 0x0, 0x0, + + /* U+F15B "" */ + 0x58, 0x88, 0x88, 0x87, 0x6, 0x0, 0x0, 0xff, + 0xff, 0xff, 0xfe, 0xf, 0x90, 0x0, 0xff, 0xff, + 0xff, 0xfe, 0xf, 0xf9, 0x0, 0xff, 0xff, 0xff, + 0xfe, 0xf, 0xff, 0x90, 0xff, 0xff, 0xff, 0xfe, + 0xf, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0x32, + 0x22, 0x21, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x14, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x30, + + /* U+F1EB "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x36, + 0x89, 0xa9, 0x74, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x29, 0xef, 0xff, 0xff, 0xff, 0xff, 0xc6, + 0x0, 0x0, 0x0, 0x1, 0xaf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x60, 0x0, 0x6, 0xff, + 0xff, 0xfc, 0x75, 0x43, 0x46, 0x9e, 0xff, 0xff, + 0xb1, 0x8, 0xff, 0xfe, 0x71, 0x0, 0x0, 0x0, + 0x0, 0x3, 0xcf, 0xff, 0xe2, 0xcf, 0xfa, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4e, 0xff, + 0x40, 0xb6, 0x0, 0x0, 0x59, 0xde, 0xfe, 0xc7, + 0x20, 0x0, 0x1b, 0x50, 0x0, 0x0, 0x5, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0xa1, 0x0, 0x0, 0x0, + 0x0, 0x9, 0xff, 0xff, 0xfe, 0xde, 0xff, 0xff, + 0xe3, 0x0, 0x0, 0x0, 0x0, 0xdf, 0xfc, 0x40, + 0x0, 0x2, 0x8f, 0xff, 0x50, 0x0, 0x0, 0x0, + 0x1, 0xb6, 0x0, 0x0, 0x0, 0x0, 0x1b, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x35, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0xfe, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0xff, 0xf6, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xdf, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0xb0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F240 "" */ + 0x4, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x10, 0xa, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x10, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0xf, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0xf3, 0xff, 0x4a, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf, + 0xff, 0x5f, 0xf4, 0xaf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0x3f, 0xf5, 0xff, 0x4a, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0xef, + 0x5f, 0xf4, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x8f, 0xf5, 0xff, 0x45, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0xf, 0xff, 0x5f, + 0xf7, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x45, 0xff, 0xc1, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x6, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfb, 0x0, + + /* U+F241 "" */ + 0x4, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x10, 0xa, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x10, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0xf, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0xf3, 0xff, 0x4d, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x60, 0x0, 0xf, + 0xff, 0x5f, 0xf4, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0xf6, 0x0, 0x0, 0x3f, 0xf5, 0xff, 0x4d, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x60, 0x0, 0x0, 0xef, + 0x5f, 0xf4, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xf6, + 0x0, 0x0, 0x8f, 0xf5, 0xff, 0x46, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x30, 0x0, 0xf, 0xff, 0x5f, + 0xf7, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x45, 0xff, 0xc1, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x6, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfb, 0x0, + + /* U+F242 "" */ + 0x4, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x10, 0xa, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x10, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0xf, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0xf3, 0xff, 0x4c, + 0xff, 0xff, 0xff, 0xf1, 0x0, 0x0, 0x0, 0xf, + 0xff, 0x5f, 0xf4, 0xcf, 0xff, 0xff, 0xff, 0x10, + 0x0, 0x0, 0x0, 0x3f, 0xf5, 0xff, 0x4c, 0xff, + 0xff, 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, 0xef, + 0x5f, 0xf4, 0xcf, 0xff, 0xff, 0xff, 0x10, 0x0, + 0x0, 0x0, 0x8f, 0xf5, 0xff, 0x46, 0x88, 0x88, + 0x88, 0x80, 0x0, 0x0, 0x0, 0xf, 0xff, 0x5f, + 0xf7, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x45, 0xff, 0xc1, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x6, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfb, 0x0, + + /* U+F243 "" */ + 0x4, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x10, 0xa, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x10, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0xf, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0xf3, 0xff, 0x49, + 0xff, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xff, 0x5f, 0xf4, 0x9f, 0xff, 0xe0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0xf5, 0xff, 0x49, 0xff, + 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, + 0x5f, 0xf4, 0x9f, 0xff, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xf5, 0xff, 0x44, 0x88, 0x87, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0x5f, + 0xf7, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x45, 0xff, 0xc1, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x6, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfb, 0x0, + + /* U+F244 "" */ + 0x4, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x10, 0xa, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x10, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0xf, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0xf3, 0xff, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xff, 0x5f, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0xf5, 0xff, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, + 0x5f, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xf5, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0x5f, + 0xf7, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x45, 0xff, 0xc1, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x6, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfb, 0x0, + + /* U+F287 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x78, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x26, 0x9f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xef, 0xff, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0x80, + 0x2e, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20, + 0x0, 0x6, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3, 0xef, 0xe3, 0x0, 0xd7, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xa1, 0x0, 0xcf, 0xff, 0xd4, + 0x9f, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7f, 0xf7, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0xaf, 0xff, 0xa0, 0x0, + 0xb, 0xb0, 0x0, 0x0, 0x0, 0x3f, 0xb2, 0x0, + 0x9c, 0x90, 0x0, 0x0, 0x3f, 0x30, 0x0, 0x0, + 0x1, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbb, 0x2, 0xbb, 0xb5, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0xf9, 0x9f, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xbd, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, 0x80, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F293 "" */ + 0x0, 0x1, 0x7b, 0xdd, 0xb8, 0x20, 0x0, 0x0, + 0x5f, 0xff, 0xdf, 0xff, 0xf6, 0x0, 0x4, 0xff, + 0xff, 0x68, 0xff, 0xff, 0x40, 0xe, 0xff, 0xff, + 0x60, 0x9f, 0xff, 0xd0, 0x4f, 0xff, 0xff, 0x60, + 0x9, 0xff, 0xf3, 0x8f, 0xf6, 0xbf, 0x61, 0xc0, + 0x9f, 0xf7, 0xbf, 0xf6, 0xb, 0x60, 0xe2, 0x5f, + 0xf9, 0xdf, 0xff, 0x50, 0x20, 0x33, 0xff, 0xfb, + 0xef, 0xff, 0xf5, 0x0, 0x2e, 0xff, 0xfc, 0xef, + 0xff, 0xfc, 0x0, 0x7f, 0xff, 0xfc, 0xdf, 0xff, + 0xd1, 0x0, 0x9, 0xff, 0xfc, 0xcf, 0xfc, 0x14, + 0x50, 0x90, 0xaf, 0xfb, 0xaf, 0xf2, 0x4f, 0x60, + 0xf3, 0x2f, 0xf9, 0x6f, 0xfd, 0xff, 0x70, 0x52, + 0xef, 0xf6, 0x1f, 0xff, 0xff, 0x70, 0x2e, 0xff, + 0xf1, 0x9, 0xff, 0xff, 0x72, 0xef, 0xff, 0x90, + 0x0, 0xbf, 0xff, 0xae, 0xff, 0xfd, 0x10, 0x0, + 0x5, 0xcf, 0xff, 0xfd, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x11, 0x0, 0x0, 0x0, + + /* U+F2ED "" */ + 0x0, 0x0, 0x5, 0x88, 0x88, 0x30, 0x0, 0x0, + 0x56, 0x66, 0x7f, 0xff, 0xff, 0xe6, 0x66, 0x63, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0xcd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, + 0x3, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x20, + 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa0, + 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa0, + 0xe, 0xff, 0x1f, 0xf6, 0xaf, 0xc4, 0xff, 0xa0, + 0xe, 0xff, 0xf, 0xf5, 0x9f, 0xb3, 0xff, 0xa0, + 0xe, 0xff, 0xf, 0xf5, 0x9f, 0xb3, 0xff, 0xa0, + 0xe, 0xff, 0xf, 0xf5, 0x9f, 0xb3, 0xff, 0xa0, + 0xe, 0xff, 0xf, 0xf5, 0x9f, 0xb3, 0xff, 0xa0, + 0xe, 0xff, 0xf, 0xf5, 0x9f, 0xb3, 0xff, 0xa0, + 0xe, 0xff, 0xf, 0xf5, 0x9f, 0xb3, 0xff, 0xa0, + 0xe, 0xff, 0xf, 0xf5, 0x9f, 0xb3, 0xff, 0xa0, + 0xe, 0xff, 0x1f, 0xf6, 0xaf, 0xc4, 0xff, 0xa0, + 0xd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, + 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, + 0x0, 0x24, 0x44, 0x44, 0x44, 0x44, 0x31, 0x0, + + /* U+F304 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8a, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xbf, 0xff, 0xff, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x34, 0xff, 0xff, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0x44, 0xff, 0xff, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, 0x44, 0xff, + 0xf4, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, 0xff, + 0x44, 0xf4, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, + 0xff, 0xff, 0x41, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0xff, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xff, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, + 0x0, 0xbf, 0xff, 0xff, 0xff, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, + 0xf4, 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, + 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, + 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xe, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xd4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0x31, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F55A "" */ + 0x0, 0x0, 0x0, 0x57, 0x88, 0x88, 0x88, 0x88, + 0x88, 0x88, 0x72, 0x0, 0x0, 0x0, 0xaf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, 0x0, + 0x0, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x70, 0x0, 0xbf, 0xff, 0xff, 0xf8, + 0xaf, 0xff, 0xa8, 0xff, 0xff, 0xf8, 0x0, 0xbf, + 0xff, 0xff, 0xfa, 0x0, 0xaf, 0xa0, 0xa, 0xff, + 0xff, 0x80, 0xbf, 0xff, 0xff, 0xff, 0xf3, 0x0, + 0x60, 0x3, 0xff, 0xff, 0xf8, 0xaf, 0xff, 0xff, + 0xff, 0xff, 0xf3, 0x0, 0x3, 0xff, 0xff, 0xff, + 0x8e, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, + 0x9f, 0xff, 0xff, 0xf8, 0x4f, 0xff, 0xff, 0xff, + 0xff, 0xa0, 0x0, 0x0, 0xaf, 0xff, 0xff, 0x80, + 0x4f, 0xff, 0xff, 0xff, 0xb0, 0x3, 0xe3, 0x0, + 0xbf, 0xff, 0xf8, 0x0, 0x4f, 0xff, 0xff, 0xfe, + 0x23, 0xff, 0xf3, 0x2e, 0xff, 0xff, 0x80, 0x0, + 0x4f, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xfe, 0xff, + 0xff, 0xf7, 0x0, 0x0, 0x4f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x0, 0x0, + 0x3d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x90, + + /* U+F7C2 "" */ + 0x0, 0x1, 0xcf, 0xff, 0xff, 0xfe, 0x60, 0x0, + 0x1c, 0xff, 0xff, 0xff, 0xff, 0xf2, 0x0, 0xcf, + 0x47, 0xf4, 0xd8, 0x4f, 0xf5, 0xc, 0xff, 0x3, + 0xe0, 0xc5, 0xe, 0xf5, 0xcf, 0xff, 0x3, 0xe0, + 0xc5, 0xe, 0xf5, 0xff, 0xff, 0x24, 0xe2, 0xc6, + 0x2e, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x5f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xa0, 0x1, 0x34, + 0x44, 0x44, 0x44, 0x42, 0x0, + + /* U+F8A2 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xff, 0x10, 0x0, 0x3e, 0x90, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0xf1, 0x0, 0x4f, + 0xfb, 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0x10, + 0x5f, 0xff, 0xb0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0xf1, 0x6f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x1d, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0x3e, 0xff, 0xfe, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xca, 0x0, 0x2e, 0xff, + 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1d, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1b, 0x60, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0 +}; + + +/*--------------------- + * GLYPH DESCRIPTION + *--------------------*/ + +static const lv_font_fmt_txt_glyph_dsc_t glyph_dsc[] = { + {.bitmap_index = 0, .adv_w = 0, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0} /* id = 0 reserved */, + {.bitmap_index = 0, .adv_w = 73, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 0, .adv_w = 83, .box_w = 3, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 23, .adv_w = 106, .box_w = 6, .box_h = 6, .ofs_x = 0, .ofs_y = 8}, + {.bitmap_index = 41, .adv_w = 167, .box_w = 11, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 124, .adv_w = 175, .box_w = 11, .box_h = 18, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 223, .adv_w = 269, .box_w = 15, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 336, .adv_w = 214, .box_w = 14, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 448, .adv_w = 57, .box_w = 3, .box_h = 6, .ofs_x = 0, .ofs_y = 8}, + {.bitmap_index = 457, .adv_w = 100, .box_w = 5, .box_h = 18, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 502, .adv_w = 100, .box_w = 6, .box_h = 18, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 556, .adv_w = 122, .box_w = 8, .box_h = 7, .ofs_x = 0, .ofs_y = 7}, + {.bitmap_index = 584, .adv_w = 181, .box_w = 10, .box_h = 10, .ofs_x = 1, .ofs_y = 2}, + {.bitmap_index = 634, .adv_w = 146, .box_w = 8, .box_h = 3, .ofs_x = 1, .ofs_y = 5}, + {.bitmap_index = 646, .adv_w = 87, .box_w = 3, .box_h = 3, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 651, .adv_w = 81, .box_w = 6, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 696, .adv_w = 165, .box_w = 10, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 771, .adv_w = 135, .box_w = 5, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 809, .adv_w = 162, .box_w = 10, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 884, .adv_w = 163, .box_w = 10, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 959, .adv_w = 165, .box_w = 11, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1042, .adv_w = 163, .box_w = 10, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1117, .adv_w = 165, .box_w = 10, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1192, .adv_w = 163, .box_w = 9, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1260, .adv_w = 167, .box_w = 10, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1335, .adv_w = 165, .box_w = 10, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1410, .adv_w = 85, .box_w = 3, .box_h = 11, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1427, .adv_w = 85, .box_w = 3, .box_h = 15, .ofs_x = 1, .ofs_y = -5}, + {.bitmap_index = 1450, .adv_w = 181, .box_w = 10, .box_h = 13, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1515, .adv_w = 177, .box_w = 10, .box_h = 7, .ofs_x = 1, .ofs_y = 3}, + {.bitmap_index = 1550, .adv_w = 179, .box_w = 10, .box_h = 13, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1615, .adv_w = 167, .box_w = 10, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1690, .adv_w = 275, .box_w = 16, .box_h = 17, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 1826, .adv_w = 203, .box_w = 13, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1924, .adv_w = 201, .box_w = 11, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2007, .adv_w = 220, .box_w = 12, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2097, .adv_w = 217, .box_w = 12, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2187, .adv_w = 201, .box_w = 11, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2270, .adv_w = 185, .box_w = 10, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2345, .adv_w = 234, .box_w = 13, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2443, .adv_w = 217, .box_w = 12, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2533, .adv_w = 79, .box_w = 3, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2556, .adv_w = 151, .box_w = 9, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 2624, .adv_w = 201, .box_w = 12, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2714, .adv_w = 169, .box_w = 9, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2782, .adv_w = 252, .box_w = 14, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2887, .adv_w = 217, .box_w = 12, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2977, .adv_w = 236, .box_w = 14, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3082, .adv_w = 201, .box_w = 11, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3165, .adv_w = 236, .box_w = 14, .box_h = 19, .ofs_x = 0, .ofs_y = -5}, + {.bitmap_index = 3298, .adv_w = 217, .box_w = 13, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3396, .adv_w = 201, .box_w = 12, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3486, .adv_w = 185, .box_w = 12, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3576, .adv_w = 220, .box_w = 12, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3666, .adv_w = 205, .box_w = 13, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3764, .adv_w = 287, .box_w = 18, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3899, .adv_w = 203, .box_w = 13, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3997, .adv_w = 201, .box_w = 13, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4095, .adv_w = 185, .box_w = 12, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4185, .adv_w = 81, .box_w = 4, .box_h = 19, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 4223, .adv_w = 81, .box_w = 6, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4268, .adv_w = 81, .box_w = 4, .box_h = 19, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 4306, .adv_w = 142, .box_w = 9, .box_h = 8, .ofs_x = 0, .ofs_y = 6}, + {.bitmap_index = 4342, .adv_w = 179, .box_w = 12, .box_h = 2, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 4354, .adv_w = 95, .box_w = 5, .box_h = 3, .ofs_x = 0, .ofs_y = 11}, + {.bitmap_index = 4362, .adv_w = 169, .box_w = 10, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4417, .adv_w = 167, .box_w = 9, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4485, .adv_w = 152, .box_w = 10, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4540, .adv_w = 167, .box_w = 10, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4615, .adv_w = 169, .box_w = 10, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4670, .adv_w = 85, .box_w = 6, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4715, .adv_w = 169, .box_w = 10, .box_h = 14, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 4785, .adv_w = 167, .box_w = 9, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4853, .adv_w = 63, .box_w = 2, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4868, .adv_w = 63, .box_w = 5, .box_h = 18, .ofs_x = -2, .ofs_y = -4}, + {.bitmap_index = 4913, .adv_w = 151, .box_w = 9, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4981, .adv_w = 63, .box_w = 2, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4996, .adv_w = 250, .box_w = 14, .box_h = 11, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 5073, .adv_w = 169, .box_w = 9, .box_h = 11, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 5123, .adv_w = 169, .box_w = 10, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5178, .adv_w = 167, .box_w = 9, .box_h = 14, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 5241, .adv_w = 167, .box_w = 10, .box_h = 14, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 5311, .adv_w = 105, .box_w = 6, .box_h = 11, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 5344, .adv_w = 157, .box_w = 9, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5394, .adv_w = 83, .box_w = 6, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5439, .adv_w = 167, .box_w = 9, .box_h = 11, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 5489, .adv_w = 151, .box_w = 10, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5544, .adv_w = 217, .box_w = 14, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5621, .adv_w = 151, .box_w = 10, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5676, .adv_w = 151, .box_w = 10, .box_h = 14, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 5746, .adv_w = 151, .box_w = 10, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5801, .adv_w = 100, .box_w = 6, .box_h = 18, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 5855, .adv_w = 75, .box_w = 2, .box_h = 18, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 5873, .adv_w = 100, .box_w = 6, .box_h = 18, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 5927, .adv_w = 177, .box_w = 11, .box_h = 4, .ofs_x = 0, .ofs_y = 4}, + {.bitmap_index = 5949, .adv_w = 288, .box_w = 16, .box_h = 14, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 6061, .adv_w = 288, .box_w = 17, .box_h = 16, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 6197, .adv_w = 288, .box_w = 14, .box_h = 15, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 6302, .adv_w = 288, .box_w = 17, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6438, .adv_w = 288, .box_w = 18, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6582, .adv_w = 288, .box_w = 16, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 6702, .adv_w = 288, .box_w = 17, .box_h = 16, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 6838, .adv_w = 288, .box_w = 16, .box_h = 17, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 6974, .adv_w = 288, .box_w = 17, .box_h = 16, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 7110, .adv_w = 288, .box_w = 17, .box_h = 17, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 7255, .adv_w = 288, .box_w = 18, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7399, .adv_w = 288, .box_w = 17, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7527, .adv_w = 288, .box_w = 18, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7680, .adv_w = 288, .box_w = 18, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7824, .adv_w = 288, .box_w = 18, .box_h = 16, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7968, .adv_w = 288, .box_w = 17, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 8113, .adv_w = 288, .box_w = 18, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 8257, .adv_w = 288, .box_w = 16, .box_h = 15, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 8377, .adv_w = 288, .box_w = 18, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 8530, .adv_w = 288, .box_w = 17, .box_h = 16, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 8666, .adv_w = 288, .box_w = 17, .box_h = 17, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 8811, .adv_w = 288, .box_w = 17, .box_h = 16, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 8947, .adv_w = 288, .box_w = 17, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 9092, .adv_w = 288, .box_w = 18, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 9245, .adv_w = 288, .box_w = 17, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 9373, .adv_w = 288, .box_w = 19, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 9554, .adv_w = 288, .box_w = 18, .box_h = 14, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 9680, .adv_w = 288, .box_w = 18, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 9833, .adv_w = 288, .box_w = 18, .box_h = 14, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 9959, .adv_w = 198, .box_w = 13, .box_h = 13, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 10044, .adv_w = 288, .box_w = 19, .box_h = 18, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 10215, .adv_w = 288, .box_w = 18, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 10386, .adv_w = 324, .box_w = 21, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 10565, .adv_w = 288, .box_w = 18, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 10736, .adv_w = 324, .box_w = 21, .box_h = 14, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 10883, .adv_w = 288, .box_w = 18, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 11054, .adv_w = 144, .box_w = 9, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 11122, .adv_w = 216, .box_w = 14, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 11227, .adv_w = 324, .box_w = 21, .box_h = 18, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 11416, .adv_w = 288, .box_w = 18, .box_h = 14, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 11542, .adv_w = 198, .box_w = 13, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 11666, .adv_w = 252, .box_w = 12, .box_h = 17, .ofs_x = 2, .ofs_y = -2}, + {.bitmap_index = 11768, .adv_w = 252, .box_w = 16, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 11920, .adv_w = 252, .box_w = 16, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 12056, .adv_w = 252, .box_w = 16, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 12192, .adv_w = 252, .box_w = 12, .box_h = 17, .ofs_x = 2, .ofs_y = -2}, + {.bitmap_index = 12294, .adv_w = 252, .box_w = 18, .box_h = 17, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 12447, .adv_w = 180, .box_w = 11, .box_h = 16, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 12535, .adv_w = 180, .box_w = 11, .box_h = 16, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 12623, .adv_w = 252, .box_w = 16, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 12759, .adv_w = 252, .box_w = 16, .box_h = 4, .ofs_x = 0, .ofs_y = 5}, + {.bitmap_index = 12791, .adv_w = 324, .box_w = 21, .box_h = 14, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 12938, .adv_w = 360, .box_w = 23, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 13157, .adv_w = 324, .box_w = 22, .box_h = 19, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 13366, .adv_w = 288, .box_w = 18, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 13519, .adv_w = 252, .box_w = 16, .box_h = 10, .ofs_x = 0, .ofs_y = 2}, + {.bitmap_index = 13599, .adv_w = 252, .box_w = 16, .box_h = 10, .ofs_x = 0, .ofs_y = 2}, + {.bitmap_index = 13679, .adv_w = 360, .box_w = 24, .box_h = 15, .ofs_x = -1, .ofs_y = -1}, + {.bitmap_index = 13859, .adv_w = 288, .box_w = 18, .box_h = 14, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 13985, .adv_w = 288, .box_w = 18, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 14156, .adv_w = 288, .box_w = 19, .box_h = 19, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 14337, .adv_w = 252, .box_w = 16, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 14473, .adv_w = 252, .box_w = 16, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 14625, .adv_w = 252, .box_w = 16, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 14761, .adv_w = 252, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 14881, .adv_w = 288, .box_w = 18, .box_h = 14, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 15007, .adv_w = 180, .box_w = 13, .box_h = 19, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 15131, .adv_w = 252, .box_w = 16, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 15283, .adv_w = 252, .box_w = 16, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 15435, .adv_w = 324, .box_w = 21, .box_h = 14, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 15582, .adv_w = 288, .box_w = 20, .box_h = 20, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 15782, .adv_w = 216, .box_w = 14, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 15915, .adv_w = 360, .box_w = 23, .box_h = 18, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 16122, .adv_w = 360, .box_w = 23, .box_h = 12, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 16260, .adv_w = 360, .box_w = 23, .box_h = 12, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 16398, .adv_w = 360, .box_w = 23, .box_h = 12, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 16536, .adv_w = 360, .box_w = 23, .box_h = 12, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 16674, .adv_w = 360, .box_w = 23, .box_h = 12, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 16812, .adv_w = 360, .box_w = 23, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 16985, .adv_w = 252, .box_w = 14, .box_h = 19, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 17118, .adv_w = 252, .box_w = 16, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 17270, .adv_w = 288, .box_w = 19, .box_h = 19, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 17451, .adv_w = 360, .box_w = 23, .box_h = 14, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 17612, .adv_w = 216, .box_w = 14, .box_h = 19, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 17745, .adv_w = 290, .box_w = 19, .box_h = 12, .ofs_x = 0, .ofs_y = 1} +}; + +/*--------------------- + * CHARACTER MAPPING + *--------------------*/ + +static const uint16_t unicode_list_2[] = { + 0x0, 0x2b, 0x3f1, 0x49f, 0x5c3, 0x982, 0xb1e, 0xdb4, + 0xe06, 0x109d, 0x1106, 0x121e, 0x1735, 0x18f7, 0x1a33, 0x1d18, + 0x1ecc, 0x2732, 0x2d8e, 0x2e72, 0x30b6, 0x3120, 0x418a, 0x41c8, + 0x4955, 0xa1f8, 0xa1ff, 0xa202, 0xa203, 0xa204, 0xa208, 0xa20a, + 0xa20c, 0xa210, 0xa213, 0xa218, 0xa21d, 0xa21e, 0xa21f, 0xa235, + 0xa23a, 0xa23f, 0xa242, 0xa243, 0xa244, 0xa248, 0xa249, 0xa24a, + 0xa24b, 0xa25e, 0xa25f, 0xa265, 0xa267, 0xa268, 0xa26b, 0xa26e, + 0xa26f, 0xa270, 0xa272, 0xa28a, 0xa28c, 0xa2bb, 0xa2bc, 0xa2be, + 0xa2c0, 0xa2d7, 0xa2de, 0xa2e1, 0xa2ea, 0xa313, 0xa31b, 0xa352, + 0xa3e2, 0xa437, 0xa438, 0xa439, 0xa43a, 0xa43b, 0xa47e, 0xa48a, + 0xa4e4, 0xa4fb, 0xa751, 0xa9b9, 0xaa99 +}; + +/*Collect the unicode lists and glyph_id offsets*/ +static const lv_font_fmt_txt_cmap_t cmaps[] = +{ + { + .range_start = 32, .range_length = 12, .glyph_id_start = 1, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 45, .range_length = 82, .glyph_id_start = 13, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 19977, .range_length = 43674, .glyph_id_start = 95, + .unicode_list = unicode_list_2, .glyph_id_ofs_list = NULL, .list_length = 85, .type = LV_FONT_FMT_TXT_CMAP_SPARSE_TINY + } +}; + + + +/*-------------------- + * ALL CUSTOM DATA + *--------------------*/ + +#if LV_VERSION_CHECK(8, 0, 0) +/*Store all the custom data of the font*/ +static lv_font_fmt_txt_glyph_cache_t cache; +static const lv_font_fmt_txt_dsc_t font_dsc = { +#else +static lv_font_fmt_txt_dsc_t font_dsc = { +#endif + .glyph_bitmap = glyph_bitmap, + .glyph_dsc = glyph_dsc, + .cmaps = cmaps, + .kern_dsc = NULL, + .kern_scale = 0, + .cmap_num = 3, + .bpp = 4, + .kern_classes = 0, + .bitmap_format = 0, +#if LV_VERSION_CHECK(8, 0, 0) + .cache = &cache +#endif +}; + + +/*----------------- + * PUBLIC FONT + *----------------*/ + +/*Initialize a public general font descriptor*/ +#if LV_VERSION_CHECK(8, 0, 0) +const lv_font_t lv_font_MI_LanTing_Regular_18 = { +#else +lv_font_t lv_font_MI_LanTing_Regular_18 = { +#endif + .get_glyph_dsc = lv_font_get_glyph_dsc_fmt_txt, /*Function pointer to get glyph's data*/ + .get_glyph_bitmap = lv_font_get_bitmap_fmt_txt, /*Function pointer to get glyph's bitmap*/ + .line_height = 18, /*The maximum line height required by the font default: (f.src.ascent - f.src.descent)*/ + .base_line = 3, /*Baseline measured from the bottom of the line*/ +#if !(LVGL_VERSION_MAJOR == 6 && LVGL_VERSION_MINOR == 0) + .subpx = LV_FONT_SUBPX_NONE, +#endif +#if LV_VERSION_CHECK(7, 4, 0) || LVGL_VERSION_MAJOR >= 8 + .underline_position = -2, + .underline_thickness = 1, +#endif + .dsc = &font_dsc /*The custom font data. Will be accessed by `get_glyph_bitmap/dsc` */ +}; + + + +#endif /*#if LV_FONT_MI_LANTING_REGULAR_18*/ + diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_24.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_24.c new file mode 100644 index 0000000000000000000000000000000000000000..eb24d9506cb4f7a08e814d4be12beecb694b3841 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_24.c @@ -0,0 +1,3687 @@ +/* + * Copyright 2024 NXP + * NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in + * accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, + * activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to + * comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license + * terms, then you may not retain, install, activate or otherwise use the software. + */ +/******************************************************************************* + * Size: 24 px + * Bpp: 4 + * Opts: --user-data-dir=C:\Users\hp\AppData\Roaming\gui-guider --app-path=C:\NXP\GUI-Guider-1.7.2-GA\resources\app.asar --no-sandbox --no-zygote --lang=zh-CN --device-scale-factor=1.5 --num-raster-threads=4 --enable-main-frame-before-activation --renderer-client-id=5 --time-ticks-at-unix-epoch=-1732015070561205 --launch-time-ticks=65380923608 --mojo-platform-channel-handle=3108 --field-trial-handle=1864,i,17219279099561217522,18026807573185265005,131072 --disable-features=SpareRendererForSitePerProcess,WinRetrieveSuggestionsOnlyOnDemand /prefetch:1 + ******************************************************************************/ + +#ifdef LV_LVGL_H_INCLUDE_SIMPLE +#include "lvgl.h" +#else +#include "lvgl.h" +#endif + +#ifndef LV_FONT_MI_LANTING_REGULAR_24 +#define LV_FONT_MI_LANTING_REGULAR_24 1 +#endif + +#if LV_FONT_MI_LANTING_REGULAR_24 + +/*----------------- + * BITMAPS + *----------------*/ + +/*Store the image of the glyphs*/ +static LV_ATTRIBUTE_LARGE_CONST const uint8_t glyph_bitmap[] = { + /* U+0020 " " */ + + /* U+0021 "!" */ + 0xbf, 0xca, 0xfb, 0x9f, 0xa9, 0xfa, 0x8f, 0x98, + 0xf9, 0x7f, 0x87, 0xf7, 0x6f, 0x76, 0xf6, 0x5f, + 0x64, 0xf5, 0x4f, 0x42, 0xa2, 0x0, 0x0, 0x0, + 0x48, 0x59, 0xfa, 0x9f, 0xa0, + + /* U+0022 "\"" */ + 0xbf, 0x90, 0x9f, 0xba, 0xf8, 0x8, 0xfa, 0x9f, + 0x70, 0x7f, 0x98, 0xf5, 0x6, 0xf7, 0x7f, 0x40, + 0x5f, 0x65, 0xf3, 0x4, 0xf5, 0x28, 0x10, 0x18, + 0x20, + + /* U+0023 "#" */ + 0x0, 0x0, 0x8, 0xf0, 0x0, 0xbd, 0x0, 0x0, + 0x0, 0xc, 0xc0, 0x0, 0xea, 0x0, 0x0, 0x0, + 0xf, 0x90, 0x2, 0xf6, 0x0, 0x0, 0x0, 0x3f, + 0x60, 0x5, 0xf3, 0x0, 0x0, 0x22, 0x7f, 0x42, + 0x29, 0xf2, 0x21, 0x6, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfa, 0x2, 0x55, 0xec, 0x55, 0x5f, 0xb5, + 0x52, 0x0, 0x0, 0xf8, 0x0, 0x2f, 0x60, 0x0, + 0x0, 0x2, 0xf5, 0x0, 0x5f, 0x30, 0x0, 0x0, + 0x5, 0xf3, 0x0, 0x7f, 0x0, 0x0, 0x0, 0x8, + 0xf0, 0x0, 0xad, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x68, 0x8f, 0xc8, 0x89, + 0xfb, 0x88, 0x30, 0x0, 0x1f, 0x60, 0x4, 0xf4, + 0x0, 0x0, 0x0, 0x5f, 0x30, 0x7, 0xf1, 0x0, + 0x0, 0x0, 0x8f, 0x0, 0xb, 0xe0, 0x0, 0x0, + 0x0, 0xbd, 0x0, 0xe, 0xa0, 0x0, 0x0, 0x0, + 0xea, 0x0, 0x1f, 0x70, 0x0, 0x0, + + /* U+0024 "$" */ + 0x0, 0x0, 0x0, 0x27, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4, 0x9f, 0x62, 0x0, 0x0, 0x0, 0x7, 0xff, + 0xff, 0xff, 0xa1, 0x0, 0x0, 0x8f, 0xe7, 0x7f, + 0x6d, 0xfc, 0x0, 0x1, 0xfe, 0x10, 0x4f, 0x0, + 0xcf, 0x70, 0x5, 0xf7, 0x0, 0x4f, 0x0, 0x3f, + 0xd0, 0x7, 0xf6, 0x0, 0x4f, 0x0, 0xb, 0x80, + 0x5, 0xfb, 0x0, 0x4f, 0x0, 0x0, 0x0, 0x0, + 0xef, 0xa1, 0x4f, 0x0, 0x0, 0x0, 0x0, 0x2e, + 0xff, 0xdf, 0x20, 0x0, 0x0, 0x0, 0x0, 0x7d, + 0xff, 0xfd, 0x60, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0xbf, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x4f, 0x1, + 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x4f, 0x0, 0xa, + 0xf2, 0x7, 0xa0, 0x0, 0x4f, 0x0, 0x4, 0xf7, + 0xe, 0xf0, 0x0, 0x4f, 0x0, 0x5, 0xf7, 0x9, + 0xf8, 0x0, 0x4f, 0x0, 0x9, 0xf4, 0x1, 0xff, + 0x50, 0x4f, 0x0, 0x4f, 0xd0, 0x0, 0x5f, 0xfc, + 0xaf, 0x9c, 0xff, 0x30, 0x0, 0x2, 0xae, 0xff, + 0xff, 0xa2, 0x0, 0x0, 0x0, 0x0, 0x4f, 0x20, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x27, 0x0, 0x0, 0x0, + + /* U+0025 "%" */ + 0x0, 0x9e, 0xfd, 0x60, 0x0, 0x0, 0x0, 0xdd, + 0x0, 0x0, 0xb, 0xfb, 0x8d, 0xf5, 0x0, 0x0, + 0x6, 0xf5, 0x0, 0x0, 0x3f, 0x80, 0x0, 0xed, + 0x0, 0x0, 0xe, 0xd0, 0x0, 0x0, 0x6f, 0x20, + 0x0, 0x8f, 0x0, 0x0, 0x6f, 0x40, 0x0, 0x0, + 0x7f, 0x0, 0x0, 0x6f, 0x10, 0x0, 0xec, 0x0, + 0x0, 0x0, 0x5f, 0x10, 0x0, 0x7f, 0x0, 0x7, + 0xf4, 0x0, 0x0, 0x0, 0x1f, 0x60, 0x0, 0xcc, + 0x0, 0x1f, 0xb0, 0x0, 0x0, 0x0, 0x7, 0xf6, + 0x28, 0xf4, 0x0, 0x8f, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x5b, 0xdb, 0x40, 0x1, 0xfa, 0x0, 0x0, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xf2, + 0x1, 0xbf, 0xfe, 0x50, 0x0, 0x0, 0x0, 0x0, + 0x2f, 0xa0, 0xc, 0xf7, 0x5c, 0xf3, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x20, 0x3f, 0x60, 0x0, 0xf9, + 0x0, 0x0, 0x0, 0x2, 0xf9, 0x0, 0x7f, 0x0, + 0x0, 0xad, 0x0, 0x0, 0x0, 0xb, 0xf1, 0x0, + 0x9e, 0x0, 0x0, 0x8f, 0x0, 0x0, 0x0, 0x3f, + 0x80, 0x0, 0x9f, 0x0, 0x0, 0x9f, 0x0, 0x0, + 0x0, 0xbe, 0x10, 0x0, 0x6f, 0x20, 0x0, 0xbd, + 0x0, 0x0, 0x4, 0xf7, 0x0, 0x0, 0x2f, 0xa0, + 0x2, 0xf9, 0x0, 0x0, 0xc, 0xe0, 0x0, 0x0, + 0x8, 0xfc, 0xae, 0xf2, 0x0, 0x0, 0x5f, 0x60, + 0x0, 0x0, 0x0, 0x6d, 0xfc, 0x30, + + /* U+0026 "&" */ + 0x0, 0x0, 0x7d, 0xfe, 0xa1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x9f, 0xb8, 0xaf, 0xe0, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0xa0, 0x0, 0x6f, 0x80, 0x0, + 0x0, 0x0, 0x7, 0xf4, 0x0, 0x0, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x7f, 0x20, 0x0, 0xf, 0xc0, + 0x0, 0x0, 0x0, 0x3, 0xf7, 0x0, 0x5, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0xc, 0xe1, 0x3, 0xee, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xb9, 0xfe, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x1, 0xcf, 0xf9, + 0x10, 0x0, 0x1, 0x0, 0x0, 0x5, 0xef, 0xbf, + 0x90, 0x0, 0x3, 0xfa, 0x0, 0x6, 0xfd, 0x20, + 0x8f, 0x80, 0x0, 0x5f, 0x80, 0x2, 0xfd, 0x10, + 0x0, 0x9f, 0x90, 0x8, 0xf4, 0x0, 0x9f, 0x40, + 0x0, 0x0, 0x9f, 0xa0, 0xdf, 0x0, 0xd, 0xf0, + 0x0, 0x0, 0x0, 0x9f, 0xcf, 0x90, 0x0, 0xdf, + 0x0, 0x0, 0x0, 0x0, 0x9f, 0xf4, 0x0, 0xa, + 0xf5, 0x0, 0x0, 0x0, 0xa, 0xff, 0xe3, 0x0, + 0x3f, 0xe3, 0x0, 0x0, 0x3c, 0xfb, 0x7f, 0xf6, + 0x0, 0x7f, 0xfd, 0xbb, 0xef, 0xf8, 0x0, 0x5f, + 0xf7, 0x0, 0x4b, 0xef, 0xec, 0x82, 0x0, 0x0, + 0x4c, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+0027 "'" */ + 0xcf, 0x8b, 0xf7, 0xaf, 0x69, 0xf4, 0x8f, 0x37, + 0xf2, 0x38, 0x0, + + /* U+0028 "(" */ + 0x0, 0x0, 0x4f, 0x30, 0x0, 0x1e, 0x80, 0x0, + 0x9, 0xe0, 0x0, 0x2, 0xf6, 0x0, 0x0, 0xae, + 0x0, 0x0, 0x1f, 0x90, 0x0, 0x7, 0xf3, 0x0, + 0x0, 0xbf, 0x0, 0x0, 0xf, 0xc0, 0x0, 0x2, + 0xfa, 0x0, 0x0, 0x4f, 0x80, 0x0, 0x4, 0xf8, + 0x0, 0x0, 0x3f, 0x80, 0x0, 0x1, 0xf9, 0x0, + 0x0, 0xe, 0xb0, 0x0, 0x0, 0xae, 0x0, 0x0, + 0x6, 0xf2, 0x0, 0x0, 0x1f, 0x70, 0x0, 0x0, + 0xae, 0x0, 0x0, 0x2, 0xf6, 0x0, 0x0, 0xa, + 0xd0, 0x0, 0x0, 0x1e, 0x90, 0x0, 0x0, 0x5f, + 0x30, + + /* U+0029 ")" */ + 0xa, 0xd0, 0x0, 0x0, 0x1e, 0x80, 0x0, 0x0, + 0x6f, 0x30, 0x0, 0x0, 0xdb, 0x0, 0x0, 0x5, + 0xf3, 0x0, 0x0, 0xf, 0xa0, 0x0, 0x0, 0xbf, + 0x0, 0x0, 0x7, 0xf4, 0x0, 0x0, 0x3f, 0x80, + 0x0, 0x1, 0xfb, 0x0, 0x0, 0xf, 0xd0, 0x0, + 0x0, 0xfd, 0x0, 0x0, 0xf, 0xc0, 0x0, 0x0, + 0xfa, 0x0, 0x0, 0x2f, 0x70, 0x0, 0x5, 0xf3, + 0x0, 0x0, 0x9e, 0x0, 0x0, 0xe, 0x90, 0x0, + 0x5, 0xf2, 0x0, 0x0, 0xcb, 0x0, 0x0, 0x5f, + 0x30, 0x0, 0xe, 0x80, 0x0, 0xa, 0xd0, 0x0, + 0x0, + + /* U+002A "*" */ + 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0xce, + 0x0, 0x0, 0x8, 0x20, 0xab, 0x1, 0x70, 0x2f, + 0xfb, 0xbb, 0xaf, 0xf3, 0x14, 0x69, 0xff, 0x97, + 0x41, 0x0, 0x7, 0xdc, 0x80, 0x0, 0x0, 0x7f, + 0x54, 0xf8, 0x0, 0x2, 0xfd, 0x0, 0xcf, 0x30, + 0x0, 0x23, 0x0, 0x34, 0x0, + + /* U+002B "+" */ + 0x0, 0x0, 0x2, 0xb5, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3f, 0x70, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0x70, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0x70, 0x0, 0x0, 0x9f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xd6, 0xbb, 0xbb, + 0xcf, 0xdb, 0xbb, 0xb9, 0x0, 0x0, 0x3, 0xf7, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0x70, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xf7, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xf7, 0x0, 0x0, 0x0, + + /* U+002D "-" */ + 0x7d, 0xdd, 0xdd, 0xdd, 0xda, 0x9f, 0xff, 0xff, + 0xff, 0xfc, + + /* U+002E "." */ + 0x8d, 0xd1, 0xaf, 0xf1, 0xaf, 0xf1, + + /* U+002F "/" */ + 0x0, 0x0, 0xd, 0xb0, 0x0, 0x1, 0xf7, 0x0, + 0x0, 0x6f, 0x20, 0x0, 0xa, 0xe0, 0x0, 0x0, + 0xea, 0x0, 0x0, 0x3f, 0x50, 0x0, 0x8, 0xf1, + 0x0, 0x0, 0xcc, 0x0, 0x0, 0x1f, 0x80, 0x0, + 0x5, 0xf4, 0x0, 0x0, 0x9f, 0x0, 0x0, 0xe, + 0xb0, 0x0, 0x2, 0xf6, 0x0, 0x0, 0x6f, 0x20, + 0x0, 0xb, 0xe0, 0x0, 0x0, 0xf9, 0x0, 0x0, + 0x4f, 0x50, 0x0, 0x8, 0xf1, 0x0, 0x0, 0xdc, + 0x0, 0x0, 0x0, + + /* U+0030 "0" */ + 0x0, 0x4, 0xce, 0xec, 0x40, 0x0, 0x0, 0x7f, + 0xfc, 0xcf, 0xf7, 0x0, 0x4, 0xfe, 0x20, 0x2, + 0xdf, 0x40, 0xc, 0xf3, 0x0, 0x0, 0x2f, 0xd0, + 0x2f, 0xb0, 0x0, 0x0, 0xa, 0xf3, 0x7f, 0x50, + 0x0, 0x0, 0x4, 0xf8, 0xaf, 0x20, 0x0, 0x0, + 0x1, 0xfb, 0xcf, 0x0, 0x0, 0x0, 0x0, 0xed, + 0xdf, 0x0, 0x0, 0x0, 0x0, 0xde, 0xee, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0xdf, 0x0, 0x0, 0x0, + 0x0, 0xde, 0xcf, 0x0, 0x0, 0x0, 0x0, 0xed, + 0xaf, 0x10, 0x0, 0x0, 0x1, 0xfb, 0x7f, 0x50, + 0x0, 0x0, 0x4, 0xf8, 0x3f, 0xa0, 0x0, 0x0, + 0xa, 0xf3, 0xd, 0xf2, 0x0, 0x0, 0x2f, 0xd0, + 0x4, 0xfd, 0x20, 0x2, 0xdf, 0x40, 0x0, 0x8f, + 0xfc, 0xbf, 0xf8, 0x0, 0x0, 0x4, 0xce, 0xec, + 0x50, 0x0, + + /* U+0031 "1" */ + 0x0, 0x1, 0x9f, 0x80, 0x6, 0xef, 0xf8, 0x1c, + 0xfe, 0x8f, 0x83, 0xf9, 0x13, 0xf8, 0x13, 0x0, + 0x3f, 0x80, 0x0, 0x3, 0xf8, 0x0, 0x0, 0x3f, + 0x80, 0x0, 0x3, 0xf8, 0x0, 0x0, 0x3f, 0x80, + 0x0, 0x3, 0xf8, 0x0, 0x0, 0x3f, 0x80, 0x0, + 0x3, 0xf8, 0x0, 0x0, 0x3f, 0x80, 0x0, 0x3, + 0xf8, 0x0, 0x0, 0x3f, 0x80, 0x0, 0x3, 0xf8, + 0x0, 0x0, 0x3f, 0x80, 0x0, 0x3, 0xf8, 0x0, + 0x0, 0x3f, 0x80, + + /* U+0032 "2" */ + 0x0, 0x19, 0xdf, 0xeb, 0x40, 0x0, 0x3, 0xff, + 0xfd, 0xef, 0xf7, 0x0, 0xe, 0xf6, 0x0, 0x4, + 0xef, 0x30, 0x7f, 0x80, 0x0, 0x0, 0x3f, 0xa0, + 0xbf, 0x20, 0x0, 0x0, 0xe, 0xe0, 0x68, 0x0, + 0x0, 0x0, 0xd, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0x80, + 0x0, 0x0, 0x0, 0x2, 0xfe, 0x10, 0x0, 0x0, + 0x0, 0xd, 0xf5, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0x80, 0x0, 0x0, 0x0, 0x9, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0xc0, 0x0, 0x0, 0x0, 0x5, + 0xfe, 0x10, 0x0, 0x0, 0x0, 0x3f, 0xf3, 0x0, + 0x0, 0x0, 0x1, 0xef, 0x50, 0x0, 0x0, 0x0, + 0xd, 0xf7, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xfa, + 0xaa, 0xaa, 0xaa, 0xa2, 0xcf, 0xff, 0xff, 0xff, + 0xff, 0xf4, + + /* U+0033 "3" */ + 0x0, 0x7, 0xdf, 0xfc, 0x60, 0x0, 0x1, 0xdf, + 0xeb, 0xce, 0xfb, 0x0, 0xc, 0xf6, 0x0, 0x0, + 0x9f, 0x90, 0x4f, 0x90, 0x0, 0x0, 0xd, 0xf0, + 0x12, 0x0, 0x0, 0x0, 0x9, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x2f, 0xd0, 0x0, 0x0, 0x0, 0x15, 0xdf, 0x40, + 0x0, 0x0, 0xff, 0xff, 0xe4, 0x0, 0x0, 0x0, + 0xaa, 0xbf, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xbf, 0xb0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xf3, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x3, 0xf9, 0x4, 0x0, 0x0, 0x0, + 0x4, 0xf8, 0xcf, 0x20, 0x0, 0x0, 0xa, 0xf4, + 0x4f, 0xe4, 0x0, 0x0, 0x7f, 0xc0, 0x7, 0xff, + 0xdb, 0xbe, 0xfd, 0x10, 0x0, 0x29, 0xdf, 0xfc, + 0x70, 0x0, + + /* U+0034 "4" */ + 0x0, 0x0, 0x0, 0x0, 0x2f, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x1e, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0x8f, 0x90, 0x0, 0x0, 0x0, 0x4, 0xfb, 0x3f, + 0x90, 0x0, 0x0, 0x0, 0xd, 0xf1, 0x3f, 0x90, + 0x0, 0x0, 0x0, 0x8f, 0x70, 0x3f, 0x90, 0x0, + 0x0, 0x2, 0xfd, 0x0, 0x3f, 0x90, 0x0, 0x0, + 0xc, 0xf3, 0x0, 0x3f, 0x90, 0x0, 0x0, 0x6f, + 0x90, 0x0, 0x3f, 0x90, 0x0, 0x1, 0xee, 0x10, + 0x0, 0x3f, 0x90, 0x0, 0xa, 0xf5, 0x0, 0x0, + 0x3f, 0x90, 0x0, 0x4f, 0xb0, 0x0, 0x0, 0x3f, + 0x90, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0x7b, 0xbb, 0xbb, 0xbb, 0xbf, 0xdb, 0xb5, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0x90, 0x0, + + /* U+0035 "5" */ + 0x5, 0xff, 0xff, 0xff, 0xff, 0xa0, 0x7, 0xfc, + 0xbb, 0xbb, 0xbb, 0x70, 0x8, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0xb, 0xf0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xa6, 0xcf, 0xeb, 0x40, 0x0, + 0x2f, 0xff, 0xdb, 0xcf, 0xf9, 0x0, 0x3f, 0xe4, + 0x0, 0x1, 0xcf, 0x60, 0x29, 0x30, 0x0, 0x0, + 0x2f, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xf5, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xf5, 0x0, 0x0, 0x0, 0x0, + 0x9, 0xf2, 0x19, 0x0, 0x0, 0x0, 0x1f, 0xd0, + 0x7f, 0xb1, 0x0, 0x2, 0xcf, 0x50, 0x9, 0xff, + 0xcb, 0xcf, 0xf8, 0x0, 0x0, 0x4a, 0xef, 0xea, + 0x30, 0x0, + + /* U+0036 "6" */ + 0x0, 0x4, 0xbe, 0xfd, 0x81, 0x0, 0x0, 0x7f, + 0xfc, 0xbe, 0xfe, 0x20, 0x4, 0xfd, 0x20, 0x0, + 0x7f, 0xd0, 0xc, 0xf2, 0x0, 0x0, 0x8, 0xf5, + 0x1f, 0xa0, 0x0, 0x0, 0x0, 0x40, 0x5f, 0x50, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0x20, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x4, 0xbe, 0xfc, 0x60, 0x0, + 0xce, 0x8f, 0xfb, 0xbf, 0xfb, 0x0, 0xcf, 0xf9, + 0x0, 0x1, 0xbf, 0x90, 0xdf, 0xb0, 0x0, 0x0, + 0xd, 0xf2, 0xdf, 0x30, 0x0, 0x0, 0x5, 0xf6, + 0xcf, 0x0, 0x0, 0x0, 0x2, 0xf9, 0xbf, 0x0, + 0x0, 0x0, 0x2, 0xf9, 0x8f, 0x20, 0x0, 0x0, + 0x5, 0xf7, 0x3f, 0x90, 0x0, 0x0, 0xb, 0xf3, + 0xb, 0xf7, 0x0, 0x0, 0x9f, 0xb0, 0x1, 0xdf, + 0xeb, 0xbf, 0xfc, 0x10, 0x0, 0x8, 0xdf, 0xfc, + 0x60, 0x0, + + /* U+0037 "7" */ + 0x9f, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x6b, 0xbb, + 0xbb, 0xbb, 0xbe, 0xf2, 0x0, 0x0, 0x0, 0x0, + 0x1f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0x60, + 0x0, 0x0, 0x0, 0x0, 0xdf, 0x0, 0x0, 0x0, + 0x0, 0x4, 0xf9, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xf2, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0x7f, 0x60, 0x0, 0x0, 0x0, + 0x0, 0xef, 0x0, 0x0, 0x0, 0x0, 0x4, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0x1f, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x8f, 0x50, 0x0, 0x0, 0x0, 0x0, 0xee, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0xb, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x2f, + 0xc0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0x50, 0x0, + 0x0, 0x0, + + /* U+0038 "8" */ + 0x0, 0x6, 0xcf, 0xfc, 0x60, 0x0, 0x0, 0xbf, + 0xfb, 0xbf, 0xfb, 0x0, 0x8, 0xfb, 0x10, 0x1, + 0xbf, 0x80, 0xf, 0xe0, 0x0, 0x0, 0xe, 0xe0, + 0x2f, 0xa0, 0x0, 0x0, 0xa, 0xf1, 0x1f, 0xb0, + 0x0, 0x0, 0xa, 0xf1, 0xd, 0xe0, 0x0, 0x0, + 0x1f, 0xd0, 0x6, 0xfa, 0x0, 0x1, 0xbf, 0x60, + 0x0, 0x8f, 0xeb, 0xbe, 0xf8, 0x0, 0x0, 0x8f, + 0xff, 0xff, 0xf7, 0x0, 0xb, 0xfb, 0x30, 0x4, + 0xcf, 0xa0, 0x6f, 0x90, 0x0, 0x0, 0x9, 0xf5, + 0xcf, 0x0, 0x0, 0x0, 0x1, 0xfc, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0xde, 0xed, 0x0, 0x0, 0x0, + 0x0, 0xed, 0xbf, 0x40, 0x0, 0x0, 0x4, 0xfa, + 0x3f, 0xe5, 0x0, 0x0, 0x5e, 0xf2, 0x6, 0xff, + 0xeb, 0xbe, 0xff, 0x50, 0x0, 0x29, 0xdf, 0xfd, + 0x92, 0x0, + + /* U+0039 "9" */ + 0x0, 0x7, 0xcf, 0xfc, 0x50, 0x0, 0x1, 0xcf, + 0xeb, 0xcf, 0xf9, 0x0, 0xb, 0xf8, 0x0, 0x1, + 0xcf, 0x60, 0x4f, 0xb0, 0x0, 0x0, 0x1f, 0xe0, + 0x9f, 0x30, 0x0, 0x0, 0x8, 0xf3, 0xcf, 0x0, + 0x0, 0x0, 0x5, 0xf6, 0xcf, 0x0, 0x0, 0x0, + 0x5, 0xf8, 0xaf, 0x20, 0x0, 0x0, 0x8, 0xf9, + 0x5f, 0x90, 0x0, 0x0, 0x1f, 0xf9, 0xd, 0xf5, + 0x0, 0x2, 0xcf, 0xf9, 0x3, 0xef, 0xdb, 0xcf, + 0xf8, 0xf8, 0x0, 0x19, 0xdf, 0xea, 0x34, 0xf6, + 0x0, 0x0, 0x0, 0x0, 0x6, 0xf5, 0x0, 0x0, + 0x0, 0x0, 0x9, 0xf3, 0x1, 0x0, 0x0, 0x0, + 0xe, 0xf0, 0x9f, 0x10, 0x0, 0x0, 0x6f, 0xa0, + 0x4f, 0xd2, 0x0, 0x4, 0xff, 0x20, 0x6, 0xff, + 0xdb, 0xdf, 0xf6, 0x0, 0x0, 0x3a, 0xdf, 0xeb, + 0x30, 0x0, + + /* U+003A ":" */ + 0xbf, 0xf0, 0xbf, 0xf0, 0x9d, 0xd0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9d, 0xd0, + 0xbf, 0xf0, 0xbf, 0xf0, + + /* U+003B ";" */ + 0xbf, 0xf0, 0xbf, 0xf0, 0x9d, 0xd0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8c, 0xc0, + 0xaf, 0xf1, 0xaf, 0xf0, 0x4, 0xf0, 0x6, 0xc0, + 0xd, 0x60, 0x9c, 0x0, 0x20, 0x0, + + /* U+003C "<" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x4, 0xdc, 0x0, 0x0, 0x0, + 0x0, 0x1a, 0xff, 0x80, 0x0, 0x0, 0x0, 0x7f, + 0xfb, 0x20, 0x0, 0x0, 0x4, 0xdf, 0xd4, 0x0, + 0x0, 0x0, 0x2b, 0xfe, 0x70, 0x0, 0x0, 0x0, + 0x8f, 0xf9, 0x10, 0x0, 0x0, 0x3, 0xdf, 0xb2, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0x60, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xff, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x2, 0xbf, 0xe6, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5e, 0xfc, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xa1, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xbf, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5e, + 0xfe, 0x50, 0x0, 0x0, 0x0, 0x0, 0x8, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x80, + + /* U+003D "=" */ + 0x6b, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x49, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6b, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x49, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf6, + + /* U+003E ">" */ + 0x41, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xe6, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xfc, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x1a, 0xff, 0x91, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xcf, 0xe6, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5e, 0xfc, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xff, 0x91, 0x0, 0x0, 0x0, + 0x0, 0x1, 0x9f, 0xe5, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x7f, + 0xf7, 0x0, 0x0, 0x0, 0x4, 0xdf, 0xc3, 0x0, + 0x0, 0x0, 0x2b, 0xff, 0x60, 0x0, 0x0, 0x0, + 0x8f, 0xfa, 0x10, 0x0, 0x0, 0x6, 0xef, 0xd4, + 0x0, 0x0, 0x0, 0x3c, 0xff, 0x70, 0x0, 0x0, + 0x0, 0x9, 0xfa, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x64, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+003F "?" */ + 0x0, 0x6, 0xbe, 0xfd, 0x92, 0x0, 0x0, 0x1d, + 0xff, 0xba, 0xdf, 0xf5, 0x0, 0xd, 0xfa, 0x10, + 0x0, 0x6f, 0xf1, 0x6, 0xfc, 0x0, 0x0, 0x0, + 0xaf, 0x70, 0xcf, 0x40, 0x0, 0x0, 0x5, 0xfb, + 0x0, 0x50, 0x0, 0x0, 0x0, 0x5f, 0xb0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x4, 0xff, 0x10, 0x0, 0x0, 0x0, 0x4, + 0xff, 0x40, 0x0, 0x0, 0x0, 0x6, 0xfe, 0x40, + 0x0, 0x0, 0x0, 0x4, 0xfd, 0x20, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x1f, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x25, 0x40, 0x0, 0x0, 0x0, 0x0, + 0x7, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, + 0xd0, 0x0, 0x0, 0x0, + + /* U+0040 "@" */ + 0x0, 0x0, 0x0, 0x4, 0x9c, 0xff, 0xdb, 0x71, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5d, 0xff, 0xb8, + 0x8a, 0xdf, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0xd5, 0x0, 0x0, 0x0, 0x3b, 0xfb, 0x0, 0x0, + 0x0, 0xaf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xf9, 0x0, 0x0, 0x7f, 0x60, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xf3, 0x0, 0x1f, 0xa0, 0x0, + 0x4, 0xbf, 0xe7, 0x7f, 0x10, 0x2f, 0xa0, 0x9, + 0xf2, 0x0, 0x9, 0xfc, 0x79, 0xfd, 0xe0, 0x0, + 0xbf, 0x0, 0xeb, 0x0, 0x8, 0xf7, 0x0, 0x5, + 0xfc, 0x0, 0x6, 0xf3, 0x3f, 0x60, 0x1, 0xfb, + 0x0, 0x0, 0xf, 0xa0, 0x0, 0x4f, 0x56, 0xf3, + 0x0, 0x7f, 0x50, 0x0, 0x0, 0xf8, 0x0, 0x2, + 0xf6, 0x8f, 0x10, 0xb, 0xf1, 0x0, 0x0, 0x2f, + 0x60, 0x0, 0x3f, 0x58, 0xf1, 0x0, 0xdf, 0x0, + 0x0, 0x6, 0xf4, 0x0, 0x6, 0xf1, 0x7f, 0x30, + 0xb, 0xe0, 0x0, 0x0, 0xcf, 0x20, 0x0, 0xad, + 0x4, 0xf5, 0x0, 0x8f, 0x10, 0x0, 0x6d, 0xf2, + 0x0, 0x3f, 0x50, 0x1f, 0x90, 0x1, 0xfb, 0x32, + 0x8e, 0x4f, 0x81, 0x5e, 0xa0, 0x0, 0xbe, 0x0, + 0x4, 0xef, 0xfc, 0x20, 0xaf, 0xff, 0x80, 0x0, + 0x4, 0xf7, 0x0, 0x0, 0x32, 0x0, 0x0, 0x23, + 0x0, 0x0, 0x0, 0xa, 0xf4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0xc, 0xf7, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4d, 0xd0, 0x0, + 0x0, 0xa, 0xfe, 0x85, 0x32, 0x23, 0x69, 0xef, + 0x80, 0x0, 0x0, 0x0, 0x3, 0xae, 0xff, 0xff, + 0xff, 0xb6, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0x34, 0x32, 0x0, 0x0, 0x0, 0x0, + + /* U+0041 "A" */ + 0x0, 0x0, 0x0, 0xc, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0xff, 0xf1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x9f, 0x7f, 0x70, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xd0, 0xed, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xf7, 0x8, 0xf3, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0x10, 0x2f, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xb0, 0x0, + 0xcf, 0x10, 0x0, 0x0, 0x0, 0x8, 0xf5, 0x0, + 0x6, 0xf6, 0x0, 0x0, 0x0, 0x0, 0xef, 0x0, + 0x0, 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x4f, 0xa0, + 0x0, 0x0, 0xaf, 0x30, 0x0, 0x0, 0xa, 0xf4, + 0x0, 0x0, 0x4, 0xf9, 0x0, 0x0, 0x1, 0xff, + 0xbb, 0xbb, 0xbb, 0xcf, 0xf0, 0x0, 0x0, 0x7f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x60, 0x0, 0xd, + 0xf2, 0x0, 0x0, 0x0, 0x2, 0xfc, 0x0, 0x3, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf3, 0x0, + 0x9f, 0x60, 0x0, 0x0, 0x0, 0x0, 0x6f, 0x90, + 0xf, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xff, + 0x5, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xf5, 0xcf, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xc0, + + /* U+0042 "B" */ + 0x1f, 0xff, 0xff, 0xff, 0xeb, 0x60, 0x0, 0x1, + 0xff, 0xcc, 0xcc, 0xce, 0xff, 0xe2, 0x0, 0x1f, + 0xc0, 0x0, 0x0, 0x1, 0x9f, 0xe0, 0x1, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0x60, 0x1f, 0xc0, + 0x0, 0x0, 0x0, 0x7, 0xf9, 0x1, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x8f, 0x70, 0x1f, 0xc0, 0x0, + 0x0, 0x0, 0x1e, 0xf2, 0x1, 0xfc, 0x0, 0x0, + 0x0, 0x3c, 0xf7, 0x0, 0x1f, 0xfe, 0xee, 0xee, + 0xff, 0xb4, 0x0, 0x1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x91, 0x0, 0x1f, 0xc0, 0x0, 0x0, 0x3, + 0x8f, 0xe2, 0x1, 0xfc, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xb0, 0x1f, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0x21, 0xfc, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xf6, 0x1f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0x51, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xf1, + 0x1f, 0xc0, 0x0, 0x0, 0x0, 0x2c, 0xf8, 0x1, + 0xfe, 0xaa, 0xaa, 0xaa, 0xcf, 0xfa, 0x0, 0x1f, + 0xff, 0xff, 0xff, 0xfe, 0xb5, 0x0, 0x0, + + /* U+0043 "C" */ + 0x0, 0x0, 0x6, 0xbe, 0xff, 0xc7, 0x10, 0x0, + 0x0, 0x0, 0x3d, 0xff, 0xca, 0xbf, 0xfe, 0x40, + 0x0, 0x0, 0x3e, 0xfa, 0x20, 0x0, 0x1a, 0xff, + 0x40, 0x0, 0xd, 0xf8, 0x0, 0x0, 0x0, 0xa, + 0xff, 0x10, 0x7, 0xfc, 0x0, 0x0, 0x0, 0x0, + 0xd, 0xf9, 0x0, 0xdf, 0x40, 0x0, 0x0, 0x0, + 0x0, 0x49, 0x40, 0x2f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0x80, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xf6, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0x70, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xd0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x94, 0x0, 0xef, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xf1, 0x7, + 0xfb, 0x0, 0x0, 0x0, 0x0, 0xc, 0xfb, 0x0, + 0xd, 0xf7, 0x0, 0x0, 0x0, 0x7, 0xff, 0x20, + 0x0, 0x3e, 0xfa, 0x20, 0x0, 0x19, 0xff, 0x60, + 0x0, 0x0, 0x2c, 0xff, 0xdb, 0xcf, 0xff, 0x60, + 0x0, 0x0, 0x0, 0x4, 0x9d, 0xfe, 0xc7, 0x10, + 0x0, 0x0, + + /* U+0044 "D" */ + 0xf, 0xff, 0xff, 0xff, 0xec, 0x81, 0x0, 0x0, + 0xf, 0xfb, 0xbb, 0xbc, 0xdf, 0xff, 0x70, 0x0, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x6e, 0xf9, 0x0, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x1, 0xdf, 0x50, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xd0, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0xb, 0xf4, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xf9, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xfc, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xfe, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xfe, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xfc, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xf9, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xf5, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xe0, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x1, 0xdf, 0x60, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0x5e, 0xfa, 0x0, + 0xf, 0xfb, 0xbb, 0xbb, 0xcf, 0xff, 0x80, 0x0, + 0xf, 0xff, 0xff, 0xff, 0xec, 0x82, 0x0, 0x0, + + /* U+0045 "E" */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xff, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb0, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x30, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb5, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf8, + + /* U+0046 "F" */ + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0x4e, 0xfc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xc3, 0xef, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xe, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xef, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xe, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xef, 0xbb, 0xbb, 0xbb, + 0xbb, 0xa0, 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xef, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xe, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xef, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+0047 "G" */ + 0x0, 0x0, 0x5, 0xad, 0xff, 0xeb, 0x60, 0x0, + 0x0, 0x0, 0x2, 0xcf, 0xfd, 0xaa, 0xcf, 0xfe, + 0x40, 0x0, 0x0, 0x2e, 0xfc, 0x30, 0x0, 0x2, + 0xbf, 0xf5, 0x0, 0x0, 0xcf, 0xa0, 0x0, 0x0, + 0x0, 0x9, 0xff, 0x20, 0x5, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0xa0, 0xc, 0xf5, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x48, 0x40, 0x1f, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x9f, 0x70, 0x0, 0x0, 0xa, 0xff, 0xff, + 0xff, 0xf0, 0x7f, 0x90, 0x0, 0x0, 0x7, 0xbb, + 0xbb, 0xbf, 0xf0, 0x5f, 0xc0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xd, 0xf0, 0x1f, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xd, 0xf0, 0xc, 0xf6, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xd, 0xf0, 0x4, 0xfe, + 0x10, 0x0, 0x0, 0x0, 0x0, 0xd, 0xf0, 0x0, + 0xaf, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xf0, + 0x0, 0xb, 0xfd, 0x50, 0x0, 0x0, 0x2a, 0xff, + 0x50, 0x0, 0x0, 0x8f, 0xfe, 0xba, 0xbe, 0xff, + 0xd4, 0x0, 0x0, 0x0, 0x1, 0x6b, 0xef, 0xed, + 0x94, 0x0, 0x0, + + /* U+0048 "H" */ + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x2f, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf2, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x2f, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0xc, 0xf2, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0x2f, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xf2, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0x2f, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xf2, 0xff, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xef, 0x2f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf2, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0x2f, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xf2, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0x2f, 0xf0, 0x0, 0x0, 0x0, 0x0, 0xc, + 0xf2, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, + 0x2f, 0xf0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf2, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x2f, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf2, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x20, + + /* U+0049 "I" */ + 0xaf, 0x5a, 0xf5, 0xaf, 0x5a, 0xf5, 0xaf, 0x5a, + 0xf5, 0xaf, 0x5a, 0xf5, 0xaf, 0x5a, 0xf5, 0xaf, + 0x5a, 0xf5, 0xaf, 0x5a, 0xf5, 0xaf, 0x5a, 0xf5, + 0xaf, 0x5a, 0xf5, 0xaf, 0x50, + + /* U+004A "J" */ + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xb0, 0x0, 0x0, + 0x0, 0x4, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x4f, + 0xb0, 0x0, 0x0, 0x0, 0x4, 0xfb, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xb0, 0x0, 0x0, 0x0, 0x4, + 0xfb, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xb0, 0x0, + 0x0, 0x0, 0x4, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xb0, 0x0, 0x0, 0x0, 0x4, 0xfb, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xb0, 0x0, 0x0, 0x0, + 0x4, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xa1, + 0x98, 0x0, 0x0, 0x4, 0xfa, 0x2f, 0xc0, 0x0, + 0x0, 0x6f, 0x90, 0xef, 0x20, 0x0, 0xa, 0xf6, + 0x9, 0xfc, 0x10, 0x6, 0xff, 0x10, 0x1e, 0xff, + 0xef, 0xff, 0x60, 0x0, 0x19, 0xef, 0xeb, 0x40, + 0x0, + + /* U+004B "K" */ + 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x1, 0xdf, 0xc0, + 0x2f, 0xc0, 0x0, 0x0, 0x0, 0xc, 0xfc, 0x10, + 0x2f, 0xc0, 0x0, 0x0, 0x0, 0xcf, 0xd1, 0x0, + 0x2f, 0xc0, 0x0, 0x0, 0xb, 0xfd, 0x10, 0x0, + 0x2f, 0xc0, 0x0, 0x0, 0xaf, 0xd1, 0x0, 0x0, + 0x2f, 0xc0, 0x0, 0x9, 0xfd, 0x10, 0x0, 0x0, + 0x2f, 0xc0, 0x0, 0x9f, 0xe2, 0x0, 0x0, 0x0, + 0x2f, 0xc0, 0x8, 0xfe, 0x20, 0x0, 0x0, 0x0, + 0x2f, 0xc0, 0x7f, 0xff, 0x30, 0x0, 0x0, 0x0, + 0x2f, 0xc6, 0xfe, 0x5f, 0xd0, 0x0, 0x0, 0x0, + 0x2f, 0xff, 0xf3, 0x7, 0xfa, 0x0, 0x0, 0x0, + 0x2f, 0xff, 0x30, 0x0, 0xcf, 0x50, 0x0, 0x0, + 0x2f, 0xf3, 0x0, 0x0, 0x2f, 0xf2, 0x0, 0x0, + 0x2f, 0xc0, 0x0, 0x0, 0x8, 0xfc, 0x0, 0x0, + 0x2f, 0xc0, 0x0, 0x0, 0x0, 0xdf, 0x80, 0x0, + 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x3f, 0xf3, 0x0, + 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x9, 0xfe, 0x0, + 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0xa0, + 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf6, + + /* U+004C "L" */ + 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, + 0xc0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2f, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xfc, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xc0, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2f, 0xc0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xff, + 0xbb, 0xbb, 0xbb, 0xbb, 0xb1, 0x2f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x20, + + /* U+004D "M" */ + 0x1f, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0x41, 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xdf, 0xf4, 0x1f, 0xff, 0x70, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0x41, 0xfc, 0xed, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xfa, 0xf4, 0x1f, 0xc8, + 0xf3, 0x0, 0x0, 0x0, 0x0, 0xfc, 0x8f, 0x41, + 0xfc, 0x2f, 0x90, 0x0, 0x0, 0x0, 0x5f, 0x68, + 0xf4, 0x1f, 0xc0, 0xcf, 0x0, 0x0, 0x0, 0xb, + 0xf0, 0x8f, 0x41, 0xfc, 0x6, 0xf5, 0x0, 0x0, + 0x1, 0xf9, 0x8, 0xf4, 0x1f, 0xc0, 0xf, 0xb0, + 0x0, 0x0, 0x7f, 0x30, 0x8f, 0x41, 0xfc, 0x0, + 0x9f, 0x20, 0x0, 0xd, 0xd0, 0x8, 0xf4, 0x1f, + 0xc0, 0x3, 0xf7, 0x0, 0x3, 0xf7, 0x0, 0x8f, + 0x41, 0xfc, 0x0, 0xd, 0xd0, 0x0, 0x9f, 0x10, + 0x8, 0xf4, 0x1f, 0xc0, 0x0, 0x7f, 0x40, 0xf, + 0xb0, 0x0, 0x8f, 0x41, 0xfc, 0x0, 0x1, 0xfa, + 0x5, 0xf5, 0x0, 0x8, 0xf4, 0x1f, 0xc0, 0x0, + 0xb, 0xf0, 0xbe, 0x0, 0x0, 0x8f, 0x41, 0xfc, + 0x0, 0x0, 0x5f, 0x8f, 0x90, 0x0, 0x8, 0xf4, + 0x1f, 0xc0, 0x0, 0x0, 0xef, 0xf3, 0x0, 0x0, + 0x8f, 0x41, 0xfc, 0x0, 0x0, 0x8, 0xfd, 0x0, + 0x0, 0x8, 0xf4, 0x1f, 0xc0, 0x0, 0x0, 0x2f, + 0x70, 0x0, 0x0, 0x8f, 0x40, + + /* U+004E "N" */ + 0x1f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf2, + 0x1f, 0xff, 0x20, 0x0, 0x0, 0x0, 0xc, 0xf2, + 0x1f, 0xef, 0xb0, 0x0, 0x0, 0x0, 0xc, 0xf2, + 0x1f, 0xd8, 0xf5, 0x0, 0x0, 0x0, 0xc, 0xf2, + 0x1f, 0xd0, 0xde, 0x10, 0x0, 0x0, 0xc, 0xf2, + 0x1f, 0xd0, 0x4f, 0x90, 0x0, 0x0, 0xc, 0xf2, + 0x1f, 0xd0, 0xa, 0xf3, 0x0, 0x0, 0xc, 0xf2, + 0x1f, 0xd0, 0x1, 0xfc, 0x0, 0x0, 0xc, 0xf2, + 0x1f, 0xd0, 0x0, 0x7f, 0x60, 0x0, 0xc, 0xf2, + 0x1f, 0xd0, 0x0, 0xd, 0xf1, 0x0, 0xc, 0xf2, + 0x1f, 0xd0, 0x0, 0x3, 0xfa, 0x0, 0xc, 0xf2, + 0x1f, 0xd0, 0x0, 0x0, 0x9f, 0x40, 0xc, 0xf2, + 0x1f, 0xd0, 0x0, 0x0, 0x1e, 0xd0, 0xc, 0xf2, + 0x1f, 0xd0, 0x0, 0x0, 0x6, 0xf7, 0xc, 0xf2, + 0x1f, 0xd0, 0x0, 0x0, 0x0, 0xcf, 0x2c, 0xf2, + 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x2f, 0xbc, 0xf2, + 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xf2, + 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xf2, + 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xf2, + + /* U+004F "O" */ + 0x0, 0x0, 0x5, 0xad, 0xff, 0xea, 0x50, 0x0, + 0x0, 0x0, 0x2, 0xcf, 0xfe, 0xbc, 0xff, 0xfd, + 0x20, 0x0, 0x0, 0x3e, 0xfd, 0x40, 0x0, 0x5, + 0xef, 0xe2, 0x0, 0x1, 0xef, 0xa0, 0x0, 0x0, + 0x0, 0x1c, 0xfd, 0x0, 0x8, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xff, 0x60, 0xf, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0xd0, 0x4f, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xf2, 0x8f, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xf6, + 0xaf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xf8, 0xbf, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xfa, 0xaf, 0x60, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x9, 0xf8, 0x8f, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xf6, 0x4f, 0xd0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xf, 0xf3, 0xf, 0xf3, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xe0, 0x9, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x80, 0x2, + 0xff, 0x90, 0x0, 0x0, 0x0, 0x8, 0xfe, 0x10, + 0x0, 0x5f, 0xfc, 0x40, 0x0, 0x3, 0xbf, 0xf4, + 0x0, 0x0, 0x5, 0xef, 0xfe, 0xcc, 0xef, 0xfe, + 0x30, 0x0, 0x0, 0x0, 0x7, 0xbe, 0xff, 0xda, + 0x60, 0x0, 0x0, + + /* U+0050 "P" */ + 0xff, 0xff, 0xff, 0xff, 0xfc, 0x70, 0x0, 0xff, + 0xbb, 0xbb, 0xbc, 0xdf, 0xfd, 0x20, 0xff, 0x0, + 0x0, 0x0, 0x1, 0xaf, 0xd0, 0xff, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xf5, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xfa, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x4, 0xfc, 0xff, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xfa, 0xff, 0x0, 0x0, 0x0, 0x0, 0xd, 0xf5, + 0xff, 0x0, 0x0, 0x0, 0x2, 0xbf, 0xd0, 0xff, + 0xcc, 0xcc, 0xcc, 0xdf, 0xfe, 0x20, 0xff, 0xff, + 0xff, 0xff, 0xfc, 0x81, 0x0, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+0051 "Q" */ + 0x0, 0x0, 0x6, 0xbe, 0xff, 0xd9, 0x40, 0x0, + 0x0, 0x0, 0x4, 0xef, 0xfc, 0x9b, 0xef, 0xfb, + 0x0, 0x0, 0x0, 0x5f, 0xfa, 0x10, 0x0, 0x5, + 0xef, 0xc0, 0x0, 0x2, 0xff, 0x70, 0x0, 0x0, + 0x0, 0x1d, 0xf9, 0x0, 0xa, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0x3, 0xff, 0x20, 0x1f, 0xf2, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0x90, 0x6f, 0xb0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xe0, 0xaf, + 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf2, + 0xcf, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, + 0xf5, 0xef, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xb, 0xf6, 0xdf, 0x40, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xf6, 0xbf, 0x60, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xe, 0xf4, 0x8f, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xf0, 0x3f, 0xf1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0xb0, 0xd, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0x50, 0x4, + 0xff, 0x60, 0x0, 0x0, 0x0, 0xa, 0xfc, 0x0, + 0x0, 0x8f, 0xfa, 0x20, 0x0, 0x3, 0xcf, 0xe2, + 0x0, 0x0, 0x7, 0xff, 0xfe, 0xbc, 0xef, 0xfd, + 0x20, 0x0, 0x0, 0x0, 0x17, 0xce, 0xff, 0xfd, + 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xfc, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xaf, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xfc, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0xef, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3b, 0x82, 0x0, + + /* U+0052 "R" */ + 0xff, 0xff, 0xff, 0xff, 0xfe, 0xb5, 0x0, 0x0, + 0xff, 0xbb, 0xbb, 0xbb, 0xbd, 0xff, 0xb0, 0x0, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x2c, 0xf9, 0x0, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0x10, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x50, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0x70, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x50, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0x10, + 0xff, 0x0, 0x0, 0x0, 0x2, 0x7f, 0xfa, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x0, + 0xff, 0xcc, 0xcc, 0xcf, 0xfc, 0x95, 0x0, 0x0, + 0xff, 0x0, 0x0, 0x9, 0xfa, 0x0, 0x0, 0x0, + 0xff, 0x0, 0x0, 0x0, 0xcf, 0x70, 0x0, 0x0, + 0xff, 0x0, 0x0, 0x0, 0x2e, 0xf4, 0x0, 0x0, + 0xff, 0x0, 0x0, 0x0, 0x4, 0xff, 0x20, 0x0, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xd1, 0x0, + 0xff, 0x0, 0x0, 0x0, 0x0, 0xb, 0xfb, 0x0, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x1, 0xef, 0x90, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xf6, + + /* U+0053 "S" */ + 0x0, 0x4, 0xad, 0xff, 0xeb, 0x60, 0x0, 0x0, + 0x9, 0xff, 0xeb, 0xbd, 0xff, 0xd2, 0x0, 0x7, + 0xfd, 0x30, 0x0, 0x3, 0xcf, 0xe1, 0x0, 0xef, + 0x30, 0x0, 0x0, 0x1, 0xef, 0x90, 0x1f, 0xe0, + 0x0, 0x0, 0x0, 0x6, 0xfe, 0x2, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x15, 0x0, 0xe, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xfe, 0x72, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2b, 0xff, 0xfe, + 0xa6, 0x10, 0x0, 0x0, 0x0, 0x2, 0x8c, 0xff, + 0xff, 0x91, 0x0, 0x0, 0x0, 0x0, 0x0, 0x49, + 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xaf, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0x59, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x9, + 0xf8, 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0x62, 0xff, 0x30, 0x0, 0x0, 0x0, 0x1f, 0xf2, + 0x7, 0xff, 0x60, 0x0, 0x0, 0x3d, 0xf9, 0x0, + 0x7, 0xff, 0xfc, 0xab, 0xdf, 0xfa, 0x0, 0x0, + 0x1, 0x7c, 0xef, 0xfd, 0xa4, 0x0, 0x0, + + /* U+0054 "T" */ + 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + 0xbb, 0xbb, 0xbc, 0xfe, 0xbb, 0xbb, 0xbb, 0x0, + 0x0, 0x0, 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, + 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xc0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2f, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2f, 0xc0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xfc, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xc0, 0x0, 0x0, 0x0, + + /* U+0055 "U" */ + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x4f, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xf4, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x4f, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xf4, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0x4f, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0xa, 0xf4, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0x4f, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xf4, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x4f, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xf4, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xaf, 0x4f, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0xb, 0xf4, 0xef, 0x10, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0x3b, 0xf3, 0x0, 0x0, 0x0, 0x0, 0xe, + 0xf0, 0x7f, 0x90, 0x0, 0x0, 0x0, 0x4, 0xfc, + 0x1, 0xff, 0x20, 0x0, 0x0, 0x0, 0xdf, 0x60, + 0x8, 0xfe, 0x50, 0x0, 0x3, 0xcf, 0xc0, 0x0, + 0x9, 0xff, 0xec, 0xce, 0xff, 0xc1, 0x0, 0x0, + 0x3, 0xad, 0xff, 0xea, 0x50, 0x0, 0x0, + + /* U+0056 "V" */ + 0x6f, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, + 0xd0, 0xf, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0x70, 0xa, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0x10, 0x3, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0x5, 0xfa, 0x0, 0x0, 0xdf, 0x20, 0x0, + 0x0, 0x0, 0xb, 0xf4, 0x0, 0x0, 0x7f, 0x80, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x1f, + 0xe0, 0x0, 0x0, 0x0, 0x7f, 0x80, 0x0, 0x0, + 0xb, 0xf3, 0x0, 0x0, 0x0, 0xdf, 0x20, 0x0, + 0x0, 0x5, 0xf9, 0x0, 0x0, 0x3, 0xfb, 0x0, + 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, 0x9, 0xf5, + 0x0, 0x0, 0x0, 0x0, 0x9f, 0x50, 0x0, 0xe, + 0xe0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xb0, 0x0, + 0x5f, 0x90, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf1, + 0x0, 0xbf, 0x20, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xf6, 0x1, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0xfc, 0x7, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x2d, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xbf, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xff, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xfd, 0x0, + 0x0, 0x0, 0x0, + + /* U+0057 "W" */ + 0x7f, 0x80, 0x0, 0x0, 0x0, 0x1f, 0xf4, 0x0, + 0x0, 0x0, 0x7, 0xf9, 0x3f, 0xc0, 0x0, 0x0, + 0x0, 0x6f, 0xf8, 0x0, 0x0, 0x0, 0xb, 0xf4, + 0xf, 0xf0, 0x0, 0x0, 0x0, 0xaf, 0xfc, 0x0, + 0x0, 0x0, 0xf, 0xf0, 0xb, 0xf4, 0x0, 0x0, + 0x0, 0xed, 0xaf, 0x10, 0x0, 0x0, 0x3f, 0xb0, + 0x7, 0xf7, 0x0, 0x0, 0x3, 0xf8, 0x6f, 0x50, + 0x0, 0x0, 0x7f, 0x70, 0x2, 0xfb, 0x0, 0x0, + 0x7, 0xf3, 0x1f, 0x90, 0x0, 0x0, 0xbf, 0x30, + 0x0, 0xef, 0x0, 0x0, 0xc, 0xe0, 0xd, 0xd0, + 0x0, 0x0, 0xfe, 0x0, 0x0, 0xaf, 0x30, 0x0, + 0x1f, 0xa0, 0x8, 0xf1, 0x0, 0x3, 0xfa, 0x0, + 0x0, 0x6f, 0x70, 0x0, 0x5f, 0x50, 0x4, 0xf6, + 0x0, 0x7, 0xf6, 0x0, 0x0, 0x2f, 0xa0, 0x0, + 0x9f, 0x10, 0x0, 0xfa, 0x0, 0xb, 0xf1, 0x0, + 0x0, 0xd, 0xe0, 0x0, 0xec, 0x0, 0x0, 0xbe, + 0x0, 0xf, 0xd0, 0x0, 0x0, 0x9, 0xf2, 0x2, + 0xf7, 0x0, 0x0, 0x7f, 0x20, 0x3f, 0x80, 0x0, + 0x0, 0x5, 0xf6, 0x7, 0xf2, 0x0, 0x0, 0x2f, + 0x70, 0x7f, 0x40, 0x0, 0x0, 0x1, 0xfa, 0xb, + 0xd0, 0x0, 0x0, 0xe, 0xb0, 0xbf, 0x0, 0x0, + 0x0, 0x0, 0xce, 0xf, 0x90, 0x0, 0x0, 0x9, + 0xf0, 0xeb, 0x0, 0x0, 0x0, 0x0, 0x8f, 0x6f, + 0x40, 0x0, 0x0, 0x5, 0xf6, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xef, 0x0, 0x0, 0x0, 0x1, + 0xfe, 0xf2, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0xe0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0x8f, 0xa0, 0x0, 0x0, + + /* U+0058 "X" */ + 0x9, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x8, 0xfc, + 0x0, 0xd, 0xf5, 0x0, 0x0, 0x0, 0x2, 0xff, + 0x10, 0x0, 0x3f, 0xe1, 0x0, 0x0, 0x0, 0xcf, + 0x50, 0x0, 0x0, 0x8f, 0xa0, 0x0, 0x0, 0x7f, + 0xa0, 0x0, 0x0, 0x0, 0xcf, 0x50, 0x0, 0x2f, + 0xe1, 0x0, 0x0, 0x0, 0x2, 0xfe, 0x10, 0xc, + 0xf4, 0x0, 0x0, 0x0, 0x0, 0x6, 0xfa, 0x7, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, 0xf8, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1e, + 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8f, 0xbf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xc0, 0xbf, 0x50, 0x0, 0x0, 0x0, 0x0, + 0x1e, 0xf2, 0x1, 0xfe, 0x10, 0x0, 0x0, 0x0, + 0xb, 0xf6, 0x0, 0x6, 0xfc, 0x0, 0x0, 0x0, + 0x7, 0xfb, 0x0, 0x0, 0xb, 0xf7, 0x0, 0x0, + 0x3, 0xfe, 0x10, 0x0, 0x0, 0x2f, 0xf3, 0x0, + 0x1, 0xef, 0x50, 0x0, 0x0, 0x0, 0x6f, 0xd0, + 0x0, 0xbf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0xcf, + 0xa0, 0x7f, 0xe1, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xff, 0x50, + + /* U+0059 "Y" */ + 0x8f, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xef, + 0x40, 0xdf, 0x50, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0xa0, 0x3, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x4f, + 0xe1, 0x0, 0x9, 0xf9, 0x0, 0x0, 0x0, 0xe, + 0xf4, 0x0, 0x0, 0xe, 0xf3, 0x0, 0x0, 0x9, + 0xfa, 0x0, 0x0, 0x0, 0x4f, 0xd0, 0x0, 0x3, + 0xfe, 0x10, 0x0, 0x0, 0x0, 0xaf, 0x70, 0x0, + 0xdf, 0x40, 0x0, 0x0, 0x0, 0x1, 0xef, 0x20, + 0x7f, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xfb, + 0x2f, 0xe1, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, + 0xfe, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1f, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xaf, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xf3, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xa, 0xf3, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xf3, 0x0, 0x0, + 0x0, 0x0, + + /* U+005A "Z" */ + 0x7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, + 0x5b, 0xbb, 0xbb, 0xbb, 0xbb, 0xcf, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xfd, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xff, 0x20, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0x60, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x7f, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xe1, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, + 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0xfd, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xef, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0x70, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6f, 0xb0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xff, 0xba, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, + + /* U+005B "[" */ + 0x1, 0x11, 0x10, 0x4f, 0xff, 0xf8, 0x4f, 0x84, + 0x42, 0x4f, 0x50, 0x0, 0x4f, 0x50, 0x0, 0x4f, + 0x50, 0x0, 0x4f, 0x50, 0x0, 0x4f, 0x50, 0x0, + 0x4f, 0x50, 0x0, 0x4f, 0x50, 0x0, 0x4f, 0x50, + 0x0, 0x4f, 0x50, 0x0, 0x4f, 0x50, 0x0, 0x4f, + 0x50, 0x0, 0x4f, 0x50, 0x0, 0x4f, 0x50, 0x0, + 0x4f, 0x50, 0x0, 0x4f, 0x50, 0x0, 0x4f, 0x50, + 0x0, 0x4f, 0x50, 0x0, 0x4f, 0x50, 0x0, 0x4f, + 0x50, 0x0, 0x4f, 0x61, 0x10, 0x4f, 0xff, 0xf9, + 0x14, 0x44, 0x42, + + /* U+005C "\\" */ + 0xdc, 0x0, 0x0, 0x8, 0xf0, 0x0, 0x0, 0x4f, + 0x40, 0x0, 0x0, 0xf9, 0x0, 0x0, 0xb, 0xd0, + 0x0, 0x0, 0x6f, 0x20, 0x0, 0x2, 0xf6, 0x0, + 0x0, 0xe, 0xa0, 0x0, 0x0, 0x9f, 0x0, 0x0, + 0x5, 0xf3, 0x0, 0x0, 0x1f, 0x80, 0x0, 0x0, + 0xcc, 0x0, 0x0, 0x8, 0xf1, 0x0, 0x0, 0x3f, + 0x50, 0x0, 0x0, 0xe9, 0x0, 0x0, 0xa, 0xe0, + 0x0, 0x0, 0x6f, 0x20, 0x0, 0x1, 0xf6, 0x0, + 0x0, 0xd, 0xb0, + + /* U+005D "]" */ + 0x1, 0x11, 0x10, 0x9f, 0xff, 0xf3, 0x24, 0x48, + 0xf3, 0x0, 0x6, 0xf3, 0x0, 0x6, 0xf3, 0x0, + 0x6, 0xf3, 0x0, 0x6, 0xf3, 0x0, 0x6, 0xf3, + 0x0, 0x6, 0xf3, 0x0, 0x6, 0xf3, 0x0, 0x6, + 0xf3, 0x0, 0x6, 0xf3, 0x0, 0x6, 0xf3, 0x0, + 0x6, 0xf3, 0x0, 0x6, 0xf3, 0x0, 0x6, 0xf3, + 0x0, 0x6, 0xf3, 0x0, 0x6, 0xf3, 0x0, 0x6, + 0xf3, 0x0, 0x6, 0xf3, 0x0, 0x6, 0xf3, 0x0, + 0x6, 0xf3, 0x1, 0x17, 0xf3, 0xaf, 0xff, 0xf3, + 0x24, 0x44, 0x40, + + /* U+005E "^" */ + 0x0, 0x0, 0xe, 0xe0, 0x0, 0x0, 0x0, 0x0, + 0x6f, 0xf6, 0x0, 0x0, 0x0, 0x0, 0xdd, 0xbd, + 0x0, 0x0, 0x0, 0x5, 0xf6, 0x4f, 0x40, 0x0, + 0x0, 0xc, 0xf0, 0xd, 0xb0, 0x0, 0x0, 0x3f, + 0x90, 0x7, 0xf3, 0x0, 0x0, 0xbf, 0x20, 0x1, + 0xfa, 0x0, 0x2, 0xfb, 0x0, 0x0, 0xaf, 0x20, + 0x9, 0xf4, 0x0, 0x0, 0x4f, 0x90, 0x1f, 0xd0, + 0x0, 0x0, 0xd, 0xf1, + + /* U+005F "_" */ + 0x12, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x20, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x40, + + /* U+0060 "`" */ + 0x7f, 0xf1, 0x0, 0xaf, 0x70, 0x0, 0xde, 0x0, + 0x2, 0xf6, + + /* U+0061 "a" */ + 0x0, 0x2, 0x9d, 0xff, 0xea, 0x30, 0x0, 0x0, + 0x5f, 0xfc, 0x98, 0xaf, 0xf4, 0x0, 0x1, 0xff, + 0x40, 0x0, 0x3, 0xfe, 0x0, 0x7, 0xf7, 0x0, + 0x0, 0x0, 0xbf, 0x30, 0x0, 0x21, 0x0, 0x0, + 0x0, 0x8f, 0x50, 0x0, 0x0, 0x0, 0x0, 0x25, + 0xdf, 0x50, 0x0, 0x2, 0x8b, 0xdf, 0xff, 0xef, + 0x50, 0x0, 0x9f, 0xfe, 0xb9, 0x62, 0x8f, 0x50, + 0x7, 0xfc, 0x30, 0x0, 0x0, 0x8f, 0x50, 0xd, + 0xf2, 0x0, 0x0, 0x0, 0xcf, 0x50, 0xf, 0xf0, + 0x0, 0x0, 0x4, 0xff, 0x50, 0xa, 0xf7, 0x0, + 0x0, 0x5e, 0xef, 0x60, 0x2, 0xff, 0xeb, 0xce, + 0xfc, 0x4f, 0x70, 0x0, 0x2a, 0xdf, 0xeb, 0x60, + 0xe, 0xc0, + + /* U+0062 "b" */ + 0x5f, 0x80, 0x0, 0x0, 0x0, 0x0, 0x5, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, 0x80, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5f, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x5, 0xf8, 0x7, 0xdf, 0xd8, 0x10, 0x0, 0x5f, + 0x8b, 0xfc, 0xad, 0xfd, 0x10, 0x5, 0xfe, 0xd2, + 0x0, 0x6, 0xfb, 0x0, 0x5f, 0xf3, 0x0, 0x0, + 0x9, 0xf3, 0x5, 0xfc, 0x0, 0x0, 0x0, 0x3f, + 0x90, 0x5f, 0x90, 0x0, 0x0, 0x0, 0xfd, 0x5, + 0xf8, 0x0, 0x0, 0x0, 0xd, 0xf0, 0x5f, 0x80, + 0x0, 0x0, 0x0, 0xdf, 0x5, 0xf9, 0x0, 0x0, + 0x0, 0xe, 0xe0, 0x5f, 0xb0, 0x0, 0x0, 0x1, + 0xfb, 0x5, 0xfe, 0x0, 0x0, 0x0, 0x6f, 0x70, + 0x5f, 0xf8, 0x0, 0x0, 0x1e, 0xe1, 0x5, 0xf9, + 0xda, 0x54, 0x7e, 0xf5, 0x0, 0x5f, 0x80, 0x8d, + 0xff, 0xb3, 0x0, 0x0, + + /* U+0063 "c" */ + 0x0, 0x0, 0x7d, 0xfe, 0xc6, 0x0, 0x0, 0x1, + 0xcf, 0xd9, 0xae, 0xfb, 0x0, 0x0, 0xaf, 0x60, + 0x0, 0xa, 0xf9, 0x0, 0x3f, 0xa0, 0x0, 0x0, + 0xf, 0xf0, 0x9, 0xf4, 0x0, 0x0, 0x0, 0x31, + 0x0, 0xdf, 0x10, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xd, 0xf1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0x50, 0x0, 0x0, 0xa, + 0xe3, 0x4, 0xfb, 0x0, 0x0, 0x0, 0xef, 0x10, + 0xc, 0xf8, 0x0, 0x1, 0xaf, 0xa0, 0x0, 0x2e, + 0xfe, 0xbc, 0xff, 0xd1, 0x0, 0x0, 0x18, 0xdf, + 0xfd, 0x70, 0x0, + + /* U+0064 "d" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xf4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x9f, 0x40, 0x0, 0x0, 0x0, 0x0, + 0x9, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0x40, 0x0, 0x29, 0xef, 0xd7, 0x9, 0xf4, 0x0, + 0x3f, 0xfc, 0x9b, 0xfa, 0x9f, 0x40, 0xd, 0xf5, + 0x0, 0x2, 0xdf, 0xf4, 0x6, 0xf8, 0x0, 0x0, + 0x3, 0xff, 0x40, 0xbf, 0x10, 0x0, 0x0, 0xd, + 0xf4, 0xe, 0xe0, 0x0, 0x0, 0x0, 0xaf, 0x40, + 0xfc, 0x0, 0x0, 0x0, 0x9, 0xf4, 0xf, 0xc0, + 0x0, 0x0, 0x0, 0x9f, 0x40, 0xee, 0x0, 0x0, + 0x0, 0xa, 0xf4, 0xb, 0xf1, 0x0, 0x0, 0x0, + 0xdf, 0x40, 0x5f, 0x70, 0x0, 0x0, 0x2f, 0xf4, + 0x0, 0xdf, 0x40, 0x0, 0x1c, 0xef, 0x40, 0x2, + 0xef, 0xc9, 0xbf, 0xb9, 0xf4, 0x0, 0x1, 0x9e, + 0xfc, 0x70, 0x9f, 0x40, + + /* U+0065 "e" */ + 0x0, 0x0, 0x3a, 0xef, 0xd8, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xc9, 0xcf, 0xd1, 0x0, 0x0, 0x6f, + 0xb1, 0x0, 0x4, 0xfc, 0x0, 0x1, 0xfd, 0x0, + 0x0, 0x0, 0x8f, 0x50, 0x7, 0xf6, 0x0, 0x0, + 0x0, 0x2f, 0xb0, 0xb, 0xf2, 0x0, 0x0, 0x0, + 0xf, 0xf0, 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf1, 0xf, 0xf8, 0x88, 0x88, 0x88, 0x88, 0x81, + 0xd, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xf4, 0x0, 0x0, 0x0, 0x5, 0x10, 0x4, 0xfb, + 0x0, 0x0, 0x0, 0x6f, 0xd0, 0x0, 0xcf, 0x80, + 0x0, 0x5, 0xff, 0x50, 0x0, 0x1d, 0xfe, 0xbb, + 0xdf, 0xf7, 0x0, 0x0, 0x0, 0x7c, 0xff, 0xda, + 0x30, 0x0, + + /* U+0066 "f" */ + 0x0, 0x9, 0xef, 0xe7, 0x0, 0x8f, 0xd9, 0x96, + 0x0, 0xcf, 0x20, 0x0, 0x0, 0xef, 0x0, 0x0, + 0x0, 0xef, 0x0, 0x0, 0xff, 0xff, 0xff, 0xb0, + 0x89, 0xff, 0x99, 0x60, 0x0, 0xef, 0x0, 0x0, + 0x0, 0xef, 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, + 0x0, 0xef, 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, + 0x0, 0xef, 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, + 0x0, 0xef, 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, + 0x0, 0xef, 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, + 0x0, 0xef, 0x0, 0x0, + + /* U+0067 "g" */ + 0x0, 0x0, 0x6c, 0xfe, 0x80, 0x6f, 0x70, 0x1, + 0xcf, 0xc9, 0xbf, 0xd7, 0xf7, 0x0, 0xcf, 0x40, + 0x0, 0x1b, 0xff, 0x70, 0x5f, 0x60, 0x0, 0x0, + 0x1e, 0xf7, 0xc, 0xf0, 0x0, 0x0, 0x0, 0x9f, + 0x70, 0xfc, 0x0, 0x0, 0x0, 0x6, 0xf7, 0x1f, + 0xb0, 0x0, 0x0, 0x0, 0x6f, 0x71, 0xfb, 0x0, + 0x0, 0x0, 0x6, 0xf7, 0xf, 0xd0, 0x0, 0x0, + 0x0, 0x8f, 0x70, 0xbf, 0x20, 0x0, 0x0, 0xc, + 0xf7, 0x5, 0xfb, 0x0, 0x0, 0x4, 0xff, 0x70, + 0xb, 0xfb, 0x42, 0x38, 0xfa, 0xf7, 0x0, 0xa, + 0xff, 0xff, 0xd4, 0x6f, 0x70, 0x0, 0x1, 0x44, + 0x20, 0x6, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0x40, 0x0, 0x0, 0x0, 0x0, 0xe, 0xf1, + 0x3, 0xc2, 0x0, 0x0, 0xa, 0xfb, 0x0, 0x3e, + 0xfc, 0x98, 0xaf, 0xfd, 0x10, 0x0, 0x7, 0xcf, + 0xfe, 0xc7, 0x10, 0x0, + + /* U+0068 "h" */ + 0x5f, 0x90, 0x0, 0x0, 0x0, 0x0, 0x5f, 0x90, + 0x0, 0x0, 0x0, 0x0, 0x5f, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x5f, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x5f, 0x90, 0x0, 0x0, 0x0, 0x0, 0x5f, 0x90, + 0x6c, 0xff, 0xc5, 0x0, 0x5f, 0x9a, 0xfd, 0xac, + 0xff, 0x60, 0x5f, 0xed, 0x30, 0x0, 0x7f, 0xe0, + 0x5f, 0xf3, 0x0, 0x0, 0xd, 0xf3, 0x5f, 0xc0, + 0x0, 0x0, 0x9, 0xf5, 0x5f, 0x90, 0x0, 0x0, + 0x8, 0xf5, 0x5f, 0x90, 0x0, 0x0, 0x8, 0xf5, + 0x5f, 0x90, 0x0, 0x0, 0x8, 0xf5, 0x5f, 0x90, + 0x0, 0x0, 0x8, 0xf5, 0x5f, 0x90, 0x0, 0x0, + 0x8, 0xf5, 0x5f, 0x90, 0x0, 0x0, 0x8, 0xf5, + 0x5f, 0x90, 0x0, 0x0, 0x8, 0xf5, 0x5f, 0x90, + 0x0, 0x0, 0x8, 0xf5, 0x5f, 0x90, 0x0, 0x0, + 0x8, 0xf5, + + /* U+0069 "i" */ + 0x4f, 0x94, 0xf9, 0x17, 0x40, 0x0, 0x0, 0x4, + 0xf9, 0x4f, 0x94, 0xf9, 0x4f, 0x94, 0xf9, 0x4f, + 0x94, 0xf9, 0x4f, 0x94, 0xf9, 0x4f, 0x94, 0xf9, + 0x4f, 0x94, 0xf9, 0x4f, 0x90, + + /* U+006A "j" */ + 0x0, 0x3, 0xf9, 0x0, 0x3, 0xf9, 0x0, 0x1, + 0x74, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xf9, 0x0, 0x3, 0xf9, 0x0, 0x3, 0xf9, + 0x0, 0x3, 0xf9, 0x0, 0x3, 0xf9, 0x0, 0x3, + 0xf9, 0x0, 0x4, 0xf9, 0x0, 0x4, 0xf9, 0x0, + 0x4, 0xfa, 0x0, 0x4, 0xfa, 0x0, 0x4, 0xfa, + 0x0, 0x4, 0xfa, 0x0, 0x4, 0xfa, 0x0, 0x4, + 0xfa, 0x0, 0x4, 0xfa, 0x0, 0x4, 0xfa, 0x0, + 0x6, 0xf8, 0x18, 0x8e, 0xf5, 0x3c, 0xfe, 0x80, + + /* U+006B "k" */ + 0x5f, 0x90, 0x0, 0x0, 0x0, 0x0, 0x5f, 0x90, + 0x0, 0x0, 0x0, 0x0, 0x5f, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x5f, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x5f, 0x90, 0x0, 0x0, 0x0, 0x0, 0x5f, 0x90, + 0x0, 0x2, 0xef, 0x90, 0x5f, 0x90, 0x0, 0x1d, + 0xf9, 0x0, 0x5f, 0x90, 0x0, 0xcf, 0xa0, 0x0, + 0x5f, 0x90, 0xc, 0xfa, 0x0, 0x0, 0x5f, 0x90, + 0xbf, 0xa0, 0x0, 0x0, 0x5f, 0x99, 0xff, 0x20, + 0x0, 0x0, 0x5f, 0xef, 0xcf, 0xb0, 0x0, 0x0, + 0x5f, 0xfc, 0xa, 0xf6, 0x0, 0x0, 0x5f, 0xc0, + 0x1, 0xfe, 0x10, 0x0, 0x5f, 0x90, 0x0, 0x6f, + 0xa0, 0x0, 0x5f, 0x90, 0x0, 0xd, 0xf5, 0x0, + 0x5f, 0x90, 0x0, 0x3, 0xfe, 0x10, 0x5f, 0x90, + 0x0, 0x0, 0xaf, 0x90, 0x5f, 0x90, 0x0, 0x0, + 0x1f, 0xf4, + + /* U+006C "l" */ + 0x5f, 0x85, 0xf8, 0x5f, 0x85, 0xf8, 0x5f, 0x85, + 0xf8, 0x5f, 0x85, 0xf8, 0x5f, 0x85, 0xf8, 0x5f, + 0x85, 0xf8, 0x5f, 0x85, 0xf8, 0x5f, 0x85, 0xf8, + 0x5f, 0x85, 0xf8, 0x5f, 0x80, + + /* U+006D "m" */ + 0x5f, 0x80, 0x8e, 0xfd, 0x60, 0x1, 0x9e, 0xfd, + 0x70, 0x5, 0xf8, 0xbd, 0x99, 0xef, 0x80, 0xdd, + 0x99, 0xef, 0x90, 0x5f, 0xea, 0x0, 0x1, 0xef, + 0x9a, 0x0, 0x1, 0xff, 0x15, 0xfe, 0x0, 0x0, + 0x9, 0xfe, 0x0, 0x0, 0x9, 0xf5, 0x5f, 0xa0, + 0x0, 0x0, 0x6f, 0xa0, 0x0, 0x0, 0x7f, 0x75, + 0xf8, 0x0, 0x0, 0x5, 0xf7, 0x0, 0x0, 0x6, + 0xf7, 0x5f, 0x80, 0x0, 0x0, 0x5f, 0x70, 0x0, + 0x0, 0x6f, 0x75, 0xf8, 0x0, 0x0, 0x5, 0xf7, + 0x0, 0x0, 0x6, 0xf7, 0x5f, 0x80, 0x0, 0x0, + 0x5f, 0x70, 0x0, 0x0, 0x6f, 0x75, 0xf8, 0x0, + 0x0, 0x5, 0xf7, 0x0, 0x0, 0x6, 0xf7, 0x5f, + 0x80, 0x0, 0x0, 0x5f, 0x70, 0x0, 0x0, 0x6f, + 0x75, 0xf8, 0x0, 0x0, 0x5, 0xf7, 0x0, 0x0, + 0x6, 0xf7, 0x5f, 0x80, 0x0, 0x0, 0x5f, 0x70, + 0x0, 0x0, 0x6f, 0x75, 0xf8, 0x0, 0x0, 0x5, + 0xf7, 0x0, 0x0, 0x6, 0xf7, + + /* U+006E "n" */ + 0x5f, 0x80, 0x6c, 0xff, 0xc5, 0x0, 0x5f, 0x8a, + 0xfc, 0x9c, 0xff, 0x60, 0x5f, 0xed, 0x30, 0x0, + 0x5f, 0xe0, 0x5f, 0xf2, 0x0, 0x0, 0xc, 0xf3, + 0x5f, 0xb0, 0x0, 0x0, 0x9, 0xf5, 0x5f, 0x80, + 0x0, 0x0, 0x7, 0xf5, 0x5f, 0x80, 0x0, 0x0, + 0x7, 0xf6, 0x5f, 0x80, 0x0, 0x0, 0x7, 0xf6, + 0x5f, 0x80, 0x0, 0x0, 0x7, 0xf6, 0x5f, 0x80, + 0x0, 0x0, 0x7, 0xf6, 0x5f, 0x80, 0x0, 0x0, + 0x7, 0xf6, 0x5f, 0x80, 0x0, 0x0, 0x7, 0xf6, + 0x5f, 0x80, 0x0, 0x0, 0x7, 0xf6, 0x5f, 0x80, + 0x0, 0x0, 0x7, 0xf6, + + /* U+006F "o" */ + 0x0, 0x0, 0x7c, 0xff, 0xd9, 0x10, 0x0, 0x0, + 0x1d, 0xfc, 0x89, 0xef, 0xe3, 0x0, 0x0, 0xcf, + 0x50, 0x0, 0x9, 0xfe, 0x0, 0x5, 0xf9, 0x0, + 0x0, 0x0, 0xcf, 0x60, 0xa, 0xf2, 0x0, 0x0, + 0x0, 0x5f, 0xc0, 0xe, 0xf0, 0x0, 0x0, 0x0, + 0x1f, 0xf0, 0xf, 0xd0, 0x0, 0x0, 0x0, 0xe, + 0xf1, 0x1f, 0xd0, 0x0, 0x0, 0x0, 0xe, 0xf1, + 0xf, 0xe0, 0x0, 0x0, 0x0, 0xf, 0xf0, 0xb, + 0xf2, 0x0, 0x0, 0x0, 0x2f, 0xc0, 0x6, 0xf8, + 0x0, 0x0, 0x0, 0x9f, 0x70, 0x0, 0xdf, 0x50, + 0x0, 0x5, 0xfe, 0x10, 0x0, 0x2e, 0xfc, 0x98, + 0xcf, 0xe3, 0x0, 0x0, 0x1, 0x8d, 0xff, 0xd8, + 0x10, 0x0, + + /* U+0070 "p" */ + 0x5f, 0x80, 0x7d, 0xfd, 0x80, 0x0, 0x5, 0xf8, + 0xbf, 0xca, 0xdf, 0xd1, 0x0, 0x5f, 0xfc, 0x20, + 0x0, 0x6f, 0xb0, 0x5, 0xff, 0x20, 0x0, 0x0, + 0x9f, 0x30, 0x5f, 0xb0, 0x0, 0x0, 0x3, 0xf9, + 0x5, 0xf8, 0x0, 0x0, 0x0, 0xf, 0xd0, 0x5f, + 0x80, 0x0, 0x0, 0x0, 0xdf, 0x5, 0xf8, 0x0, + 0x0, 0x0, 0xd, 0xf0, 0x5f, 0x80, 0x0, 0x0, + 0x0, 0xfd, 0x5, 0xfb, 0x0, 0x0, 0x0, 0x2f, + 0xa0, 0x5f, 0xf1, 0x0, 0x0, 0x8, 0xf5, 0x5, + 0xfe, 0xb0, 0x0, 0x4, 0xfd, 0x0, 0x5f, 0x8b, + 0xea, 0x9b, 0xfe, 0x20, 0x5, 0xf8, 0x7, 0xdf, + 0xe9, 0x10, 0x0, 0x5f, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x5, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5f, 0x80, 0x0, 0x0, 0x0, 0x0, 0x5, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, 0x80, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+0071 "q" */ + 0x0, 0x2, 0xae, 0xfd, 0x60, 0xaf, 0x30, 0x3, + 0xff, 0xc9, 0xbf, 0xaa, 0xf3, 0x0, 0xef, 0x40, + 0x0, 0x2d, 0xff, 0x30, 0x6f, 0x70, 0x0, 0x0, + 0x3f, 0xf3, 0xb, 0xf1, 0x0, 0x0, 0x0, 0xdf, + 0x30, 0xfd, 0x0, 0x0, 0x0, 0xa, 0xf3, 0x1f, + 0xb0, 0x0, 0x0, 0x0, 0xaf, 0x31, 0xfb, 0x0, + 0x0, 0x0, 0xa, 0xf3, 0xf, 0xd0, 0x0, 0x0, + 0x0, 0xbf, 0x30, 0xbf, 0x10, 0x0, 0x0, 0xd, + 0xf3, 0x5, 0xf7, 0x0, 0x0, 0x3, 0xff, 0x30, + 0xd, 0xf4, 0x0, 0x2, 0xde, 0xf3, 0x0, 0x2e, + 0xfc, 0xab, 0xfa, 0xaf, 0x30, 0x0, 0x19, 0xef, + 0xc6, 0xa, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xaf, 0x30, 0x0, 0x0, 0x0, 0x0, 0xa, 0xf3, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x30, 0x0, + 0x0, 0x0, 0x0, 0xa, 0xf3, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x30, + + /* U+0072 "r" */ + 0x5f, 0x81, 0xaf, 0xe8, 0x5f, 0x8c, 0xfe, 0xf6, + 0x5f, 0xcd, 0x20, 0x20, 0x5f, 0xf2, 0x0, 0x0, + 0x5f, 0xb0, 0x0, 0x0, 0x5f, 0x90, 0x0, 0x0, + 0x5f, 0x80, 0x0, 0x0, 0x5f, 0x80, 0x0, 0x0, + 0x5f, 0x80, 0x0, 0x0, 0x5f, 0x80, 0x0, 0x0, + 0x5f, 0x80, 0x0, 0x0, 0x5f, 0x80, 0x0, 0x0, + 0x5f, 0x80, 0x0, 0x0, 0x5f, 0x80, 0x0, 0x0, + + /* U+0073 "s" */ + 0x0, 0x7, 0xdf, 0xfd, 0x92, 0x0, 0x0, 0xaf, + 0xea, 0x9d, 0xff, 0x30, 0x4, 0xfc, 0x0, 0x0, + 0x8f, 0xd0, 0x8, 0xf5, 0x0, 0x0, 0xc, 0x80, + 0x7, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x1, 0xef, + 0xa4, 0x0, 0x0, 0x0, 0x0, 0x2b, 0xff, 0xfc, + 0x82, 0x0, 0x0, 0x0, 0x27, 0xbe, 0xff, 0x70, + 0x0, 0x0, 0x0, 0x0, 0x5e, 0xf4, 0x3, 0x60, + 0x0, 0x0, 0x5, 0xfa, 0xe, 0xf1, 0x0, 0x0, + 0x4, 0xfa, 0x7, 0xfc, 0x10, 0x0, 0xb, 0xf5, + 0x0, 0xbf, 0xfa, 0x9a, 0xef, 0xa0, 0x0, 0x6, + 0xcf, 0xfe, 0xc6, 0x0, + + /* U+0074 "t" */ + 0x0, 0x6, 0x0, 0x0, 0xd, 0xf0, 0x0, 0x0, + 0xef, 0x0, 0x0, 0xe, 0xf0, 0x0, 0x0, 0xef, + 0x0, 0xa, 0xff, 0xff, 0xf6, 0x69, 0xff, 0x99, + 0x30, 0xe, 0xf0, 0x0, 0x0, 0xef, 0x0, 0x0, + 0xe, 0xf0, 0x0, 0x0, 0xef, 0x0, 0x0, 0xe, + 0xf0, 0x0, 0x0, 0xef, 0x0, 0x0, 0xe, 0xf0, + 0x0, 0x0, 0xef, 0x0, 0x0, 0xe, 0xf0, 0x0, + 0x0, 0xdf, 0x10, 0x0, 0x9, 0xfb, 0x53, 0x0, + 0x1a, 0xfe, 0x70, + + /* U+0075 "u" */ + 0x6f, 0x60, 0x0, 0x0, 0x9, 0xf4, 0x6f, 0x60, + 0x0, 0x0, 0x9, 0xf4, 0x6f, 0x60, 0x0, 0x0, + 0x9, 0xf4, 0x6f, 0x60, 0x0, 0x0, 0x9, 0xf4, + 0x6f, 0x60, 0x0, 0x0, 0x9, 0xf4, 0x6f, 0x60, + 0x0, 0x0, 0x9, 0xf4, 0x6f, 0x60, 0x0, 0x0, + 0x9, 0xf4, 0x6f, 0x60, 0x0, 0x0, 0x9, 0xf4, + 0x6f, 0x60, 0x0, 0x0, 0x9, 0xf4, 0x6f, 0x80, + 0x0, 0x0, 0xc, 0xf4, 0x4f, 0xb0, 0x0, 0x0, + 0x3f, 0xf4, 0xf, 0xf4, 0x0, 0x3, 0xde, 0xf4, + 0x7, 0xff, 0xb9, 0xcf, 0xa9, 0xf4, 0x0, 0x5c, + 0xff, 0xc6, 0x9, 0xf4, + + /* U+0076 "v" */ + 0x7f, 0x90, 0x0, 0x0, 0x0, 0xdf, 0x31, 0xfe, + 0x0, 0x0, 0x0, 0x2f, 0xd0, 0xc, 0xf3, 0x0, + 0x0, 0x8, 0xf7, 0x0, 0x6f, 0x80, 0x0, 0x0, + 0xdf, 0x10, 0x1, 0xfd, 0x0, 0x0, 0x3f, 0xb0, + 0x0, 0xb, 0xf2, 0x0, 0x8, 0xf5, 0x0, 0x0, + 0x5f, 0x70, 0x0, 0xde, 0x0, 0x0, 0x0, 0xfc, + 0x0, 0x3f, 0x90, 0x0, 0x0, 0xa, 0xf1, 0x9, + 0xf3, 0x0, 0x0, 0x0, 0x4f, 0x60, 0xed, 0x0, + 0x0, 0x0, 0x0, 0xec, 0x4f, 0x70, 0x0, 0x0, + 0x0, 0x9, 0xfa, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, + 0x50, 0x0, 0x0, + + /* U+0077 "w" */ + 0xcf, 0x10, 0x0, 0x0, 0xff, 0x30, 0x0, 0x0, + 0xef, 0x7, 0xf6, 0x0, 0x0, 0x3f, 0xf6, 0x0, + 0x0, 0x2f, 0xb0, 0x2f, 0xa0, 0x0, 0x7, 0xfc, + 0xa0, 0x0, 0x7, 0xf6, 0x0, 0xde, 0x0, 0x0, + 0xab, 0x8e, 0x0, 0x0, 0xbf, 0x10, 0x9, 0xf3, + 0x0, 0xe, 0x84, 0xf2, 0x0, 0xf, 0xc0, 0x0, + 0x4f, 0x70, 0x2, 0xf4, 0x1f, 0x50, 0x4, 0xf7, + 0x0, 0x0, 0xfb, 0x0, 0x6f, 0x0, 0xd9, 0x0, + 0x8f, 0x20, 0x0, 0xa, 0xf0, 0xa, 0xc0, 0xa, + 0xd0, 0xd, 0xd0, 0x0, 0x0, 0x6f, 0x40, 0xe8, + 0x0, 0x6f, 0x11, 0xf8, 0x0, 0x0, 0x1, 0xf8, + 0x2f, 0x50, 0x3, 0xf4, 0x6f, 0x30, 0x0, 0x0, + 0xc, 0xd5, 0xf1, 0x0, 0xf, 0x8a, 0xe0, 0x0, + 0x0, 0x0, 0x7f, 0xbd, 0x0, 0x0, 0xcc, 0xe9, + 0x0, 0x0, 0x0, 0x3, 0xff, 0x90, 0x0, 0x8, + 0xff, 0x40, 0x0, 0x0, 0x0, 0xe, 0xf6, 0x0, + 0x0, 0x5f, 0xf0, 0x0, 0x0, + + /* U+0078 "x" */ + 0xd, 0xf4, 0x0, 0x0, 0x6, 0xfc, 0x0, 0x3f, + 0xd0, 0x0, 0x1, 0xef, 0x20, 0x0, 0x7f, 0x80, + 0x0, 0xaf, 0x60, 0x0, 0x0, 0xcf, 0x20, 0x3f, + 0xb0, 0x0, 0x0, 0x2, 0xfc, 0xd, 0xe1, 0x0, + 0x0, 0x0, 0x6, 0xfc, 0xf5, 0x0, 0x0, 0x0, + 0x0, 0xb, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xef, 0xd0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0x5f, + 0x80, 0x0, 0x0, 0x0, 0x6f, 0x70, 0x9f, 0x40, + 0x0, 0x0, 0x3f, 0xc0, 0x1, 0xee, 0x10, 0x0, + 0xd, 0xf3, 0x0, 0x6, 0xfa, 0x0, 0x9, 0xf8, + 0x0, 0x0, 0xc, 0xf6, 0x5, 0xfd, 0x0, 0x0, + 0x0, 0x2f, 0xf2, + + /* U+0079 "y" */ + 0x6f, 0xa0, 0x0, 0x0, 0x0, 0xbf, 0x40, 0xff, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0xa, 0xf5, 0x0, + 0x0, 0x6, 0xf8, 0x0, 0x4f, 0xa0, 0x0, 0x0, + 0xcf, 0x20, 0x0, 0xef, 0x0, 0x0, 0x1f, 0xc0, + 0x0, 0x8, 0xf5, 0x0, 0x7, 0xf6, 0x0, 0x0, + 0x2f, 0xa0, 0x0, 0xcf, 0x10, 0x0, 0x0, 0xcf, + 0x0, 0x1f, 0xa0, 0x0, 0x0, 0x6, 0xf5, 0x7, + 0xf4, 0x0, 0x0, 0x0, 0x1f, 0xa0, 0xce, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0x3f, 0x80, 0x0, 0x0, + 0x0, 0x4, 0xfd, 0xf2, 0x0, 0x0, 0x0, 0x0, + 0xe, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0x60, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf1, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0x40, 0x0, 0x0, 0x0, 0x78, + 0xcf, 0xb0, 0x0, 0x0, 0x0, 0xb, 0xfe, 0xa1, + 0x0, 0x0, 0x0, 0x0, + + /* U+007A "z" */ + 0xe, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0, 0x8a, + 0xaa, 0xaa, 0xaa, 0xff, 0x60, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x4f, + 0xd0, 0x0, 0x0, 0x0, 0x0, 0x1e, 0xf2, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x9, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x5, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0x2, 0xff, 0x20, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0x50, 0x0, 0x0, + 0x0, 0x0, 0x9f, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x5f, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xfb, + 0x99, 0x99, 0x99, 0x99, 0x17, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf2, + + /* U+007B "{" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3b, 0xfd, + 0x0, 0x2, 0xfe, 0x63, 0x0, 0x8, 0xf2, 0x0, + 0x0, 0x9, 0xf0, 0x0, 0x0, 0x9, 0xf0, 0x0, + 0x0, 0x9, 0xf0, 0x0, 0x0, 0x9, 0xf0, 0x0, + 0x0, 0x9, 0xf0, 0x0, 0x0, 0x9, 0xf0, 0x0, + 0x0, 0xc, 0xc0, 0x0, 0x2, 0x8f, 0x40, 0x0, + 0x4f, 0xf4, 0x0, 0x0, 0x15, 0xbf, 0x30, 0x0, + 0x0, 0xd, 0xb0, 0x0, 0x0, 0xa, 0xe0, 0x0, + 0x0, 0x9, 0xf0, 0x0, 0x0, 0x9, 0xf0, 0x0, + 0x0, 0x9, 0xf0, 0x0, 0x0, 0x9, 0xf0, 0x0, + 0x0, 0x9, 0xf0, 0x0, 0x0, 0x8, 0xf1, 0x0, + 0x0, 0x4, 0xfc, 0x31, 0x0, 0x0, 0x7e, 0xfd, + 0x0, 0x0, 0x0, 0x22, + + /* U+007C "|" */ + 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, + 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, + 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, + + /* U+007D "}" */ + 0x0, 0x0, 0x0, 0x0, 0x5f, 0xd7, 0x0, 0x0, + 0x15, 0xaf, 0x90, 0x0, 0x0, 0xa, 0xf0, 0x0, + 0x0, 0x7, 0xf1, 0x0, 0x0, 0x7, 0xf1, 0x0, + 0x0, 0x7, 0xf1, 0x0, 0x0, 0x7, 0xf1, 0x0, + 0x0, 0x7, 0xf1, 0x0, 0x0, 0x7, 0xf1, 0x0, + 0x0, 0x4, 0xf4, 0x0, 0x0, 0x0, 0xcd, 0x41, + 0x0, 0x0, 0xb, 0xfc, 0x0, 0x0, 0xaf, 0x73, + 0x0, 0x4, 0xf6, 0x0, 0x0, 0x6, 0xf2, 0x0, + 0x0, 0x7, 0xf1, 0x0, 0x0, 0x7, 0xf1, 0x0, + 0x0, 0x7, 0xf1, 0x0, 0x0, 0x7, 0xf1, 0x0, + 0x0, 0x7, 0xf1, 0x0, 0x0, 0xa, 0xf0, 0x0, + 0x2, 0x7f, 0xc0, 0x0, 0x5f, 0xfb, 0x20, 0x0, + 0x12, 0x0, 0x0, 0x0, + + /* U+007E "~" */ + 0x4a, 0xdf, 0xeb, 0x72, 0x0, 0x2, 0x7f, 0xfe, + 0xde, 0xff, 0xfe, 0xde, 0xfc, 0x92, 0x0, 0x2, + 0x7b, 0xef, 0xeb, 0x40, + + /* U+F001 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x7b, 0xe8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x49, 0xdf, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x16, 0xbf, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x3, 0x8c, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x3a, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0x0, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xaf, 0xff, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xd8, 0x30, 0xf, 0xff, 0x0, 0x0, 0x0, 0xff, + 0xff, 0xff, 0xfb, 0x62, 0x0, 0x0, 0xf, 0xff, + 0x0, 0x0, 0x0, 0xff, 0xfe, 0x94, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xff, 0x0, 0x0, 0x0, 0xff, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0x0, 0x0, 0x0, 0xff, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xff, 0x0, 0x0, 0x0, 0xff, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0x0, 0x0, 0x0, 0xff, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xff, 0x0, 0x0, 0x0, 0xff, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0x0, 0x0, 0x0, 0xff, 0xf0, 0x0, 0x0, 0x0, + 0x3a, 0xdf, 0xef, 0xff, 0x0, 0x0, 0x0, 0xff, + 0xf0, 0x0, 0x0, 0x6, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0x0, 0xff, 0xf0, 0x0, 0x0, 0xe, + 0xff, 0xff, 0xff, 0xff, 0x3, 0xad, 0xfe, 0xff, + 0xf0, 0x0, 0x0, 0xe, 0xff, 0xff, 0xff, 0xfe, + 0x6f, 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x6, + 0xff, 0xff, 0xff, 0xf6, 0xef, 0xff, 0xff, 0xff, + 0xf0, 0x0, 0x0, 0x0, 0x3a, 0xef, 0xea, 0x30, + 0xef, 0xff, 0xff, 0xff, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xff, 0xff, + 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xae, 0xfe, 0xa3, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F008 "" */ + 0xb7, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf4, 0x0, 0x7b, 0xfd, 0x88, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, 0x88, 0xdf, + 0xff, 0xff, 0xff, 0xb4, 0x44, 0x44, 0x44, 0x44, + 0x5f, 0xff, 0xff, 0xff, 0xf9, 0x0, 0xcf, 0x80, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xf5, 0x0, 0x9f, + 0xf8, 0x0, 0xbf, 0x80, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf4, 0x0, 0x8f, 0xf9, 0x0, 0xcf, 0x80, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xf5, 0x0, 0x9f, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xff, 0xfd, 0x88, 0xef, 0xa2, + 0x22, 0x22, 0x22, 0x22, 0x3f, 0xfb, 0x88, 0xdf, + 0xf8, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf4, 0x0, 0x8f, 0xf8, 0x0, 0xbf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, 0x8f, + 0xfd, 0x88, 0xef, 0xa2, 0x22, 0x22, 0x22, 0x22, + 0x3f, 0xfb, 0x88, 0xdf, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xf9, 0x0, 0xcf, 0x80, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf5, 0x0, 0x9f, 0xf8, 0x0, 0xbf, 0x80, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xf4, 0x0, 0x8f, + 0xf9, 0x0, 0xcf, 0x80, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf5, 0x0, 0x9f, 0xff, 0xff, 0xff, 0xb4, + 0x44, 0x44, 0x44, 0x44, 0x5f, 0xff, 0xff, 0xff, + 0xfd, 0x88, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfb, 0x88, 0xdf, 0xb7, 0x0, 0xbf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, 0x7b, + + /* U+F00B "" */ + 0x14, 0x44, 0x44, 0x10, 0x3, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x41, 0xef, 0xff, 0xff, 0xe0, + 0x6f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x7b, 0xbb, 0xbb, 0x60, 0x2a, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xb7, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xff, 0xff, 0xb0, 0x4f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xf0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xff, 0xb0, + 0x4f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x14, 0x44, 0x44, 0x10, + 0x3, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x41, + 0xef, 0xff, 0xff, 0xe0, 0x6f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xf0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x7b, 0xbb, 0xbb, 0x60, + 0x2a, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb7, + + /* U+F00C "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xbd, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0xe2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, 0xfd, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0xff, 0xff, 0xd1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, 0xfd, 0x10, + 0x2, 0xdb, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, + 0xff, 0xff, 0xd1, 0x0, 0x2e, 0xff, 0xc0, 0x0, + 0x0, 0x0, 0xc, 0xff, 0xff, 0xfd, 0x10, 0x0, + 0xdf, 0xff, 0xfc, 0x0, 0x0, 0x0, 0xcf, 0xff, + 0xff, 0xd1, 0x0, 0x0, 0xdf, 0xff, 0xff, 0xc0, + 0x0, 0xc, 0xff, 0xff, 0xfd, 0x10, 0x0, 0x0, + 0x1d, 0xff, 0xff, 0xfc, 0x0, 0xcf, 0xff, 0xff, + 0xd1, 0x0, 0x0, 0x0, 0x1, 0xdf, 0xff, 0xff, + 0xcc, 0xff, 0xff, 0xfd, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x1d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xdf, 0xff, + 0xff, 0xff, 0xfd, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1d, 0xff, 0xff, 0xff, 0xd1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xdf, + 0xff, 0xfd, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1d, 0xff, 0xd1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xcc, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F00D "" */ + 0x1, 0x41, 0x0, 0x0, 0x0, 0x0, 0x3, 0x30, + 0x1, 0xdf, 0xd2, 0x0, 0x0, 0x0, 0x7, 0xff, + 0x70, 0xcf, 0xff, 0xe2, 0x0, 0x0, 0x8, 0xff, + 0xff, 0x4e, 0xff, 0xff, 0xe2, 0x0, 0x8, 0xff, + 0xff, 0xf6, 0x4f, 0xff, 0xff, 0xe2, 0x8, 0xff, + 0xff, 0xfb, 0x0, 0x4f, 0xff, 0xff, 0xe9, 0xff, + 0xff, 0xfb, 0x0, 0x0, 0x4f, 0xff, 0xff, 0xff, + 0xff, 0xfb, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xff, + 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, + 0xff, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xff, 0xff, 0xe2, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xe2, 0x0, 0x8, 0xff, + 0xff, 0xfb, 0x5f, 0xff, 0xff, 0xe2, 0x7, 0xff, + 0xff, 0xfb, 0x0, 0x4f, 0xff, 0xff, 0xe1, 0xff, + 0xff, 0xfb, 0x0, 0x0, 0x4f, 0xff, 0xff, 0x7a, + 0xff, 0xfb, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xf3, + 0xb, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf4, + 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F011 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xf8, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xef, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0x60, 0x0, 0xef, 0xfd, 0x0, + 0x7, 0x70, 0x0, 0x0, 0x0, 0x1, 0xcf, 0xf3, + 0x0, 0xef, 0xfd, 0x0, 0x5f, 0xfb, 0x0, 0x0, + 0x0, 0xc, 0xff, 0xfb, 0x0, 0xef, 0xfd, 0x0, + 0xcf, 0xff, 0xb0, 0x0, 0x0, 0x9f, 0xff, 0xf6, + 0x0, 0xef, 0xfd, 0x0, 0x7f, 0xff, 0xf7, 0x0, + 0x3, 0xff, 0xff, 0x60, 0x0, 0xef, 0xfd, 0x0, + 0x8, 0xff, 0xff, 0x20, 0xa, 0xff, 0xf9, 0x0, + 0x0, 0xef, 0xfd, 0x0, 0x0, 0xbf, 0xff, 0x90, + 0x1f, 0xff, 0xe0, 0x0, 0x0, 0xef, 0xfd, 0x0, + 0x0, 0x1f, 0xff, 0xf0, 0x5f, 0xff, 0x90, 0x0, + 0x0, 0xef, 0xfd, 0x0, 0x0, 0xa, 0xff, 0xf3, + 0x8f, 0xff, 0x40, 0x0, 0x0, 0xef, 0xfd, 0x0, + 0x0, 0x6, 0xff, 0xf6, 0x9f, 0xff, 0x20, 0x0, + 0x0, 0xef, 0xfd, 0x0, 0x0, 0x4, 0xff, 0xf8, + 0x9f, 0xff, 0x20, 0x0, 0x0, 0xef, 0xfc, 0x0, + 0x0, 0x4, 0xff, 0xf7, 0x8f, 0xff, 0x40, 0x0, + 0x0, 0x37, 0x72, 0x0, 0x0, 0x6, 0xff, 0xf6, + 0x5f, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xff, 0xf4, 0x1f, 0xff, 0xe0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xff, 0xf0, + 0xb, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xaf, 0xff, 0xa0, 0x3, 0xff, 0xff, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xff, 0xff, 0x20, + 0x0, 0xaf, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x1, + 0x9f, 0xff, 0xf8, 0x0, 0x0, 0xd, 0xff, 0xff, + 0xe8, 0x42, 0x24, 0x9e, 0xff, 0xff, 0xb0, 0x0, + 0x0, 0x1, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfb, 0x10, 0x0, 0x0, 0x0, 0xa, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3b, 0xff, 0xff, 0xff, 0xff, + 0xb3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x15, 0x89, 0x97, 0x51, 0x0, 0x0, 0x0, 0x0, + + /* U+F013 "" */ + 0x0, 0x0, 0x0, 0x0, 0x4, 0x89, 0x98, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xc3, 0x2c, 0xff, 0xff, 0xff, 0xff, + 0xc2, 0x3c, 0xc0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, + 0x3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x30, 0xa, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0x94, 0x49, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0x6, 0xef, 0xff, 0xff, + 0xf4, 0x0, 0x0, 0x4f, 0xff, 0xff, 0xfe, 0x60, + 0x0, 0x1e, 0xff, 0xff, 0x90, 0x0, 0x0, 0x9, + 0xff, 0xff, 0xe1, 0x0, 0x0, 0xf, 0xff, 0xff, + 0x40, 0x0, 0x0, 0x4, 0xff, 0xff, 0xf0, 0x0, + 0x0, 0xf, 0xff, 0xff, 0x40, 0x0, 0x0, 0x4, + 0xff, 0xff, 0xf0, 0x0, 0x0, 0x1e, 0xff, 0xff, + 0x90, 0x0, 0x0, 0x9, 0xff, 0xff, 0xe1, 0x0, + 0x6, 0xef, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x4f, + 0xff, 0xff, 0xfe, 0x60, 0xf, 0xff, 0xff, 0xff, + 0xff, 0x94, 0x49, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xa0, 0x3, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, + 0x0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0x0, 0x0, 0xc, 0xc3, 0x2c, + 0xff, 0xff, 0xff, 0xff, 0xc2, 0x3c, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xff, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4, 0x89, 0x98, 0x40, 0x0, 0x0, 0x0, 0x0, + + /* U+F015 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x13, 0x10, + 0x0, 0x2, 0x44, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5f, 0xfe, 0x40, 0x0, 0xdf, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xff, 0xff, 0x70, 0xe, 0xff, 0xe0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0xff, + 0xff, 0xa0, 0xef, 0xfe, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0xcf, 0xff, 0xb3, 0xbf, 0xff, 0xce, + 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x3, 0xef, + 0xff, 0x90, 0x0, 0x9f, 0xff, 0xff, 0xfe, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xff, 0xff, 0x60, 0x5d, + 0x50, 0x6f, 0xff, 0xff, 0xe0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xfe, 0x30, 0x8f, 0xff, 0x70, 0x4e, + 0xff, 0xfe, 0x0, 0x0, 0x0, 0x1b, 0xff, 0xfd, + 0x20, 0xaf, 0xff, 0xff, 0xa0, 0x2d, 0xff, 0xfb, + 0x0, 0x0, 0x2d, 0xff, 0xfb, 0x1, 0xcf, 0xff, + 0xff, 0xff, 0xc1, 0xb, 0xff, 0xfd, 0x20, 0x4f, + 0xff, 0xf8, 0x3, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xe3, 0x8, 0xff, 0xfe, 0x4e, 0xff, 0xf5, 0x5, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x5, + 0xff, 0xfe, 0x4f, 0xe3, 0x8, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0x3, 0xef, 0x40, + 0x41, 0x7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0x1, 0x40, 0x0, 0x0, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x80, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, + 0xeb, 0xbb, 0xef, 0xff, 0xff, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xff, 0xff, 0xf4, 0x0, 0x4, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x8, + 0xff, 0xff, 0xff, 0x40, 0x0, 0x4f, 0xff, 0xff, + 0xf8, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xf4, 0x0, 0x4, 0xff, 0xff, 0xff, 0x80, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0x40, 0x0, + 0x4f, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xff, 0xff, 0xf3, 0x0, 0x3, 0xff, 0xff, + 0xff, 0x70, 0x0, 0x0, 0x0, 0x3, 0xbb, 0xbb, + 0xba, 0x10, 0x0, 0x1a, 0xbb, 0xbb, 0xb3, 0x0, + 0x0, + + /* U+F019 "" */ + 0x0, 0x0, 0x0, 0x0, 0x9, 0xdd, 0xdd, 0x90, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad, 0xdd, + 0xdf, 0xff, 0xff, 0xfd, 0xdd, 0xda, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x2d, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xd1, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0xfd, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1d, + 0xff, 0xff, 0xff, 0xff, 0xd1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0xdf, 0xff, 0xff, 0xfd, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1d, 0xff, 0xff, 0xd1, 0x0, 0x0, 0x0, 0x0, + 0x25, 0x55, 0x55, 0x55, 0x11, 0xdf, 0xfd, 0x11, + 0x55, 0x55, 0x55, 0x52, 0xef, 0xff, 0xff, 0xff, + 0xd1, 0x1d, 0xd1, 0x1d, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x10, 0x1, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf9, 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x71, 0xe7, 0x1e, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xb6, 0xfb, 0x6f, 0xff, 0xbf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + + /* U+F01C "" */ + 0x0, 0x0, 0x3, 0xcf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xd3, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe1, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa0, 0x0, + 0x0, 0x0, 0x5f, 0xff, 0x40, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0x50, 0x0, 0x0, 0x1e, + 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0xfe, 0x10, 0x0, 0xa, 0xff, 0xe0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xfa, + 0x0, 0x5, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4, 0xff, 0xf5, 0x1, 0xef, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x9, 0xff, 0xe1, 0xaf, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, + 0xff, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xa0, 0x0, + 0x0, 0x0, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x20, 0x0, 0x0, 0x2f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfa, 0x0, 0x0, 0xa, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xd3, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xd3, + + /* U+F021 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3, 0x32, 0x0, 0x0, 0x0, 0x0, + 0x3, 0x67, 0x75, 0x20, 0x0, 0x0, 0x4f, 0xff, + 0x0, 0x0, 0x0, 0x29, 0xff, 0xff, 0xff, 0xfd, + 0x70, 0x0, 0x4f, 0xff, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, 0x60, 0x3f, 0xff, + 0x0, 0x1, 0xcf, 0xff, 0xff, 0xfe, 0xef, 0xff, + 0xff, 0xfb, 0x3f, 0xff, 0x0, 0xd, 0xff, 0xff, + 0xb4, 0x0, 0x0, 0x5b, 0xff, 0xff, 0xdf, 0xff, + 0x0, 0xaf, 0xff, 0xe4, 0x0, 0x0, 0x0, 0x0, + 0x4d, 0xff, 0xff, 0xff, 0x4, 0xff, 0xfd, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0xff, + 0xc, 0xff, 0xf2, 0x0, 0x0, 0x0, 0x6, 0xff, + 0xee, 0xef, 0xff, 0xff, 0x1f, 0xff, 0x80, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x5f, 0xff, 0x10, 0x0, 0x0, 0x0, 0x7, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x4, 0x43, 0x0, 0x0, + 0x0, 0x0, 0x1, 0x44, 0x44, 0x44, 0x44, 0x43, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x34, 0x44, 0x44, 0x44, 0x44, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x34, 0x40, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x70, 0x0, 0x0, 0x0, 0x1, 0xff, 0xf5, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xf1, 0xff, 0xff, 0xfd, 0xee, + 0xff, 0x60, 0x0, 0x0, 0x0, 0x2f, 0xff, 0xb0, + 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0xdf, 0xff, 0x40, 0xff, 0xff, 0xff, 0xd3, + 0x0, 0x0, 0x0, 0x0, 0x4e, 0xff, 0xfa, 0x0, + 0xff, 0xfe, 0xff, 0xff, 0xb5, 0x0, 0x0, 0x4b, + 0xff, 0xff, 0xd0, 0x0, 0xff, 0xf3, 0xbf, 0xff, + 0xff, 0xfe, 0xef, 0xff, 0xff, 0xfc, 0x10, 0x0, + 0xff, 0xf3, 0x6, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0x0, 0x0, 0xff, 0xf4, 0x0, 0x17, + 0xdf, 0xff, 0xff, 0xff, 0xa2, 0x0, 0x0, 0x0, + 0xff, 0xf4, 0x0, 0x0, 0x2, 0x67, 0x76, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x23, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F026 "" */ + 0x0, 0x0, 0x0, 0x0, 0x1, 0xa7, 0x0, 0x0, + 0x0, 0x0, 0x1c, 0xff, 0x0, 0x0, 0x0, 0x1, + 0xcf, 0xff, 0x0, 0x0, 0x0, 0x1c, 0xff, 0xff, + 0x14, 0x44, 0x44, 0xcf, 0xff, 0xff, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0xbb, + 0xbb, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x5f, + 0xff, 0xff, 0x0, 0x0, 0x0, 0x5, 0xff, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x10, + + /* U+F027 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x96, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, + 0xff, 0x0, 0x0, 0x0, 0x13, 0x33, 0x33, 0xcf, + 0xff, 0xff, 0x0, 0x0, 0x0, 0xdf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x0, 0x4a, 0x20, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0xcf, 0xe1, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x3e, 0xfa, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x6, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x5, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x2e, 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x0, 0xcf, 0xf2, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x5b, 0x30, 0x7c, 0xcc, 0xcc, + 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5f, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xfd, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x21, + 0x0, 0x0, 0x0, + + /* U+F028 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0xb1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xff, 0xd1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1a, 0x70, 0x0, + 0x0, 0x0, 0x6, 0xff, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1c, 0xff, 0x0, 0x0, 0x6, 0x30, + 0x5, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x1c, + 0xff, 0xf0, 0x0, 0x3, 0xff, 0x70, 0x8, 0xff, + 0x40, 0x0, 0x0, 0x0, 0x1c, 0xff, 0xff, 0x0, + 0x0, 0xc, 0xff, 0x70, 0xc, 0xfc, 0x1, 0x44, + 0x44, 0x4c, 0xff, 0xff, 0xf0, 0x0, 0x0, 0xa, + 0xff, 0x30, 0x4f, 0xf3, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x5a, 0x20, 0xc, 0xfb, 0x0, + 0xdf, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0xc, 0xfe, 0x20, 0x4f, 0xf1, 0x8, 0xfb, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x2e, 0xfa, + 0x0, 0xff, 0x50, 0x5f, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0x0, 0x6f, 0xe0, 0xc, 0xf7, + 0x4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x6, 0xfe, 0x0, 0xcf, 0x70, 0x4f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x2, 0xef, + 0xa0, 0xf, 0xf5, 0x6, 0xfe, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x0, 0xcf, 0xe2, 0x4, 0xff, + 0x10, 0x9f, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x4, 0xa2, 0x0, 0xcf, 0xb0, 0xd, 0xf8, + 0x7b, 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x0, 0x0, + 0x0, 0xaf, 0xf3, 0x4, 0xff, 0x30, 0x0, 0x0, + 0x5, 0xff, 0xff, 0xf0, 0x0, 0x0, 0xcf, 0xf7, + 0x0, 0xcf, 0xc0, 0x0, 0x0, 0x0, 0x5, 0xff, + 0xff, 0x0, 0x0, 0x3f, 0xf7, 0x0, 0x6f, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xff, 0xf0, 0x0, + 0x0, 0x53, 0x0, 0x4f, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x6f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xfd, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x9, 0xfb, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3, 0x0, 0x0, 0x0, + + /* U+F03E "" */ + 0x3d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xd3, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0xca, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x0, 0x1d, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xc0, 0x0, 0x4, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xa0, 0x0, 0x2, + 0xff, 0xff, 0xff, 0xff, 0x9f, 0xff, 0xff, 0xff, + 0xff, 0xe1, 0x0, 0x8, 0xff, 0xff, 0xff, 0xf4, + 0x4, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x42, 0x8f, + 0xff, 0xff, 0xff, 0x40, 0x0, 0x4f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0x4, 0xff, 0xff, 0xff, 0xff, 0xff, 0x6b, + 0xff, 0xff, 0x40, 0x0, 0x0, 0x0, 0x4f, 0xff, + 0xff, 0xff, 0xf4, 0x0, 0xbf, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, 0x40, 0x0, + 0xb, 0x40, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xff, 0xff, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfd, 0x3d, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd3, + + /* U+F043 "" */ + 0x0, 0x0, 0x0, 0xc, 0xe3, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xff, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2f, 0xff, 0xf6, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x9, 0xff, 0xff, 0xd0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xff, 0xff, 0xff, + 0x50, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0xff, + 0xfe, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x0, 0x0, 0x1e, 0xff, 0xff, + 0xff, 0xff, 0xf3, 0x0, 0x0, 0xa, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe0, 0x0, 0x5, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x20, 0x5f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, 0xa, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe0, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x2f, + 0xff, 0x2d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + 0xef, 0xf1, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x3c, 0xff, 0x44, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf1, 0x8f, 0xfc, 0x7, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0x1, 0xff, 0xf9, 0x2, 0x7c, 0xff, 0xff, + 0xff, 0x50, 0x7, 0xff, 0xfb, 0x40, 0x6f, 0xff, + 0xff, 0xb0, 0x0, 0xa, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xd1, 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, + 0xff, 0xb0, 0x0, 0x0, 0x0, 0x2, 0x8d, 0xff, + 0xda, 0x40, 0x0, 0x0, + + /* U+F048 "" */ + 0x34, 0x40, 0x0, 0x0, 0x0, 0x0, 0x4, 0xf, + 0xff, 0x50, 0x0, 0x0, 0x0, 0x1d, 0xfb, 0xff, + 0xf6, 0x0, 0x0, 0x0, 0x2d, 0xff, 0xff, 0xff, + 0x60, 0x0, 0x0, 0x2e, 0xff, 0xff, 0xff, 0xf6, + 0x0, 0x0, 0x3f, 0xff, 0xff, 0xff, 0xff, 0x60, + 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x0, + 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x60, 0x6f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8e, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf6, 0x1d, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x60, 0x1c, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf6, 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x60, 0x0, 0xa, 0xff, 0xff, 0xff, 0xff, + 0xf6, 0x0, 0x0, 0x9, 0xff, 0xff, 0xff, 0xff, + 0x60, 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xf6, + 0x0, 0x0, 0x0, 0x6, 0xff, 0xea, 0xbb, 0x30, + 0x0, 0x0, 0x0, 0x5, 0xb4, + + /* U+F04B "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3, 0xdf, 0x91, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0xff, 0xe6, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xff, 0xff, 0xfc, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xa1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x0, 0x0, + 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xa2, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x50, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xb2, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x6f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, 0x20, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe5, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfb, 0x20, 0x0, 0x0, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xd4, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xfa, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xff, 0xff, 0xd3, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xd, 0xff, 0xfe, 0x60, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3d, 0xf9, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F04C "" */ + 0x19, 0xcc, 0xcc, 0xc9, 0x10, 0x0, 0x19, 0xcc, + 0xcc, 0xc9, 0x1b, 0xff, 0xff, 0xff, 0xfb, 0x0, + 0xb, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xfe, 0x0, 0xe, 0xff, 0xff, + 0xff, 0xfe, 0x5f, 0xff, 0xff, 0xff, 0x50, 0x0, + 0x5f, 0xff, 0xff, 0xff, 0x50, 0x13, 0x33, 0x33, + 0x10, 0x0, 0x0, 0x13, 0x33, 0x33, 0x10, + + /* U+F04D "" */ + 0x1, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x41, 0x6, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf6, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xb1, 0x8b, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x81, + + /* U+F051 "" */ + 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x44, 0x3b, + 0xfd, 0x10, 0x0, 0x0, 0x0, 0x5f, 0xff, 0xff, + 0xfd, 0x20, 0x0, 0x0, 0x6, 0xff, 0xff, 0xff, + 0xfe, 0x30, 0x0, 0x0, 0x6f, 0xff, 0xff, 0xff, + 0xff, 0x40, 0x0, 0x6, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x50, 0x0, 0x6f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x60, 0x6, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x70, 0x6f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x86, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x16, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0, 0x6f, 0xff, + 0xff, 0xff, 0xff, 0xfb, 0x0, 0x6, 0xff, 0xff, + 0xff, 0xff, 0xfa, 0x0, 0x0, 0x6f, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x0, 0x6, 0xff, 0xff, 0xff, + 0xf7, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xef, 0xf6, + 0x0, 0x0, 0x0, 0x6, 0xff, 0xf4, 0xb5, 0x0, + 0x0, 0x0, 0x0, 0x3b, 0xba, + + /* U+F052 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x37, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5f, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xff, 0xff, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, + 0xff, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2f, 0xff, 0xff, 0xff, 0xfe, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2e, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, 0x0, 0x1d, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x10, 0x0, + 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfc, 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0, 0x0, + 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfa, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0xd, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x0, 0x3d, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x0, + 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfb, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xe, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0x0, 0x4b, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0x40, + + /* U+F053 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0xb0, 0x0, 0x0, 0x0, + 0x0, 0xaf, 0xff, 0x80, 0x0, 0x0, 0x0, 0xaf, + 0xff, 0xf8, 0x0, 0x0, 0x0, 0xaf, 0xff, 0xfa, + 0x0, 0x0, 0x0, 0xaf, 0xff, 0xfa, 0x0, 0x0, + 0x0, 0xaf, 0xff, 0xfa, 0x0, 0x0, 0x0, 0xaf, + 0xff, 0xfa, 0x0, 0x0, 0x0, 0xaf, 0xff, 0xfa, + 0x0, 0x0, 0x0, 0xaf, 0xff, 0xfa, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xfa, 0x0, 0x0, 0x0, 0x8, + 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, 0xa, 0xff, + 0xff, 0xa0, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, + 0xa0, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, 0xa0, + 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, 0xa0, 0x0, + 0x0, 0x0, 0xa, 0xff, 0xff, 0xa0, 0x0, 0x0, + 0x0, 0xa, 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0xa, + 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0xa, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, + + /* U+F054 "" */ + 0x0, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xa0, + 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xa0, 0x0, + 0x0, 0x0, 0xa, 0xff, 0xff, 0xa0, 0x0, 0x0, + 0x0, 0xa, 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, 0xa, + 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, 0xa, 0xff, + 0xff, 0xa0, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, + 0xa0, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0xaf, 0xff, 0xf8, 0x0, 0x0, + 0x0, 0xaf, 0xff, 0xfa, 0x0, 0x0, 0x0, 0xaf, + 0xff, 0xfa, 0x0, 0x0, 0x0, 0xaf, 0xff, 0xfa, + 0x0, 0x0, 0x0, 0xaf, 0xff, 0xfa, 0x0, 0x0, + 0x0, 0xaf, 0xff, 0xfa, 0x0, 0x0, 0x0, 0xaf, + 0xff, 0xfa, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xfa, + 0x0, 0x0, 0x0, 0x8, 0xff, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xfa, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F067 "" */ + 0x0, 0x0, 0x0, 0x0, 0x3, 0x43, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0xff, + 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xbf, 0xff, 0xb0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xff, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, + 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xff, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0xff, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0xff, 0xc0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xd1, 0x77, 0x77, 0x77, 0x7d, 0xff, 0xfd, 0x77, + 0x77, 0x77, 0x71, 0x0, 0x0, 0x0, 0x0, 0xcf, + 0xff, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xff, 0xfc, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0xff, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xff, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xab, 0xa2, 0x0, 0x0, 0x0, 0x0, + + /* U+F068 "" */ + 0x16, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x76, 0x1d, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F06E "" */ + 0x0, 0x0, 0x0, 0x0, 0x16, 0xad, 0xef, 0xed, + 0xa6, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xff, 0xff, + 0xe9, 0x54, 0x59, 0xef, 0xff, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x2d, 0xff, 0xff, 0x90, 0x0, 0x0, + 0x0, 0x9f, 0xff, 0xfd, 0x20, 0x0, 0x0, 0x2e, + 0xff, 0xff, 0x70, 0x0, 0x14, 0x20, 0x0, 0x7f, + 0xff, 0xfe, 0x20, 0x0, 0x1e, 0xff, 0xff, 0xb0, + 0x0, 0x6, 0xff, 0xc2, 0x0, 0xbf, 0xff, 0xfe, + 0x10, 0xb, 0xff, 0xff, 0xf3, 0x0, 0x0, 0x5f, + 0xff, 0xe2, 0x3, 0xff, 0xff, 0xfb, 0x6, 0xff, + 0xff, 0xfe, 0x0, 0x0, 0x1c, 0xff, 0xff, 0xa0, + 0xe, 0xff, 0xff, 0xf5, 0xef, 0xff, 0xff, 0xc0, + 0xd, 0xcf, 0xff, 0xff, 0xfe, 0x0, 0xcf, 0xff, + 0xff, 0xee, 0xff, 0xff, 0xfc, 0x0, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0xc, 0xff, 0xff, 0xfe, 0x5f, + 0xff, 0xff, 0xe0, 0xc, 0xff, 0xff, 0xff, 0xfc, + 0x0, 0xef, 0xff, 0xff, 0x50, 0xbf, 0xff, 0xff, + 0x30, 0x4f, 0xff, 0xff, 0xff, 0x50, 0x3f, 0xff, + 0xff, 0xb0, 0x1, 0xdf, 0xff, 0xfb, 0x0, 0x7f, + 0xff, 0xff, 0x80, 0xb, 0xff, 0xff, 0xe1, 0x0, + 0x2, 0xef, 0xff, 0xf7, 0x0, 0x39, 0xb9, 0x30, + 0x7, 0xff, 0xff, 0xe2, 0x0, 0x0, 0x2, 0xcf, + 0xff, 0xf9, 0x0, 0x0, 0x0, 0x9, 0xff, 0xff, + 0xd2, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xff, 0xfe, + 0x95, 0x45, 0x9e, 0xff, 0xff, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2a, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfb, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0x6a, 0xdf, 0xfe, 0xda, 0x71, 0x0, + 0x0, 0x0, 0x0, + + /* U+F070 "" */ + 0x5, 0xe6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xff, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, + 0xff, 0xfc, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xff, 0xfe, 0x40, 0x0, 0x48, 0xce, 0xff, 0xeb, + 0x72, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xff, 0xff, 0x88, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xef, 0xff, 0xff, 0xff, 0xb6, 0x45, 0x7d, 0xff, + 0xff, 0xb1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xbf, 0xff, 0xfd, 0x20, 0x0, 0x0, 0x6, 0xff, + 0xff, 0xe4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8f, 0xff, 0xf6, 0x1, 0x76, 0x20, 0x4, 0xff, + 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, + 0x4e, 0xff, 0xfa, 0x1f, 0xff, 0x90, 0x8, 0xff, + 0xff, 0xf3, 0x0, 0x0, 0x0, 0x6e, 0x40, 0x0, + 0x2c, 0xff, 0xfd, 0xff, 0xff, 0x80, 0xf, 0xff, + 0xff, 0xe1, 0x0, 0x0, 0x2f, 0xff, 0x70, 0x0, + 0x9, 0xff, 0xff, 0xff, 0xff, 0x0, 0xbf, 0xff, + 0xff, 0x90, 0x0, 0x9, 0xff, 0xff, 0xb1, 0x0, + 0x6, 0xff, 0xff, 0xff, 0xf3, 0x9, 0xff, 0xff, + 0xff, 0x10, 0x0, 0x9f, 0xff, 0xff, 0xd1, 0x0, + 0x3, 0xdf, 0xff, 0xff, 0x30, 0x9f, 0xff, 0xff, + 0xf1, 0x0, 0x2, 0xff, 0xff, 0xff, 0x40, 0x0, + 0x1, 0xbf, 0xff, 0xf4, 0xb, 0xff, 0xff, 0xf9, + 0x0, 0x0, 0x7, 0xff, 0xff, 0xf9, 0x0, 0x0, + 0x0, 0x7f, 0xff, 0xf7, 0xff, 0xff, 0xfd, 0x0, + 0x0, 0x0, 0xa, 0xff, 0xff, 0xf1, 0x0, 0x0, + 0x0, 0x4e, 0xff, 0xff, 0xff, 0xff, 0x20, 0x0, + 0x0, 0x0, 0xb, 0xff, 0xff, 0xc0, 0x0, 0x0, + 0x0, 0x1c, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xff, 0xff, 0xc2, 0x0, 0x0, + 0x0, 0x9, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6, 0xff, 0xff, 0xfb, 0x64, 0x51, + 0x0, 0x5, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0x9f, 0xff, 0xff, 0xff, 0xe3, + 0x0, 0x2, 0xdf, 0xff, 0xc1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5, 0x9d, 0xef, 0xfe, 0xa1, + 0x0, 0x0, 0xaf, 0xff, 0xe4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0xff, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3e, 0xff, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1b, 0xc0, + + /* U+F071 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1c, 0xfc, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4, 0xff, 0xff, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xdf, 0xff, 0xff, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, + 0xff, 0xff, 0xff, 0x60, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1e, 0xff, 0xff, + 0xff, 0xfe, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xff, 0xff, 0xff, 0xff, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xff, 0xa4, 0x44, 0xaf, 0xff, 0xb0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, + 0xf7, 0x0, 0x7, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xd, 0xff, 0xff, 0x80, + 0x0, 0x8f, 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xff, 0xff, 0xf9, 0x0, 0x9, + 0xff, 0xff, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0xff, 0xff, 0xff, 0xa0, 0x0, 0xaf, 0xff, + 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0xff, 0xff, 0xfb, 0x0, 0xb, 0xff, 0xff, 0xff, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, 0xff, + 0xff, 0xc0, 0x0, 0xcf, 0xff, 0xff, 0xff, 0x30, + 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xfd, + 0x0, 0xd, 0xff, 0xff, 0xff, 0xfc, 0x0, 0x0, + 0x0, 0x5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0xf5, 0x0, 0x0, 0x0, + 0xef, 0xff, 0xff, 0xff, 0xfd, 0x10, 0x2d, 0xff, + 0xff, 0xff, 0xff, 0xe0, 0x0, 0x0, 0x7f, 0xff, + 0xff, 0xff, 0xff, 0x60, 0x0, 0x6f, 0xff, 0xff, + 0xff, 0xff, 0x70, 0x0, 0x1f, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x10, 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf5, 0x26, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x0, 0x3d, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfd, 0x30, + + /* U+F074 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x69, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xfc, 0x0, 0x9b, 0xbb, 0xbb, 0x30, + 0x0, 0x0, 0x0, 0x3b, 0xbb, 0xff, 0xff, 0xc0, + 0xff, 0xff, 0xff, 0xf3, 0x0, 0x0, 0x2, 0xef, + 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xfe, + 0x20, 0x0, 0x1e, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xe1, 0x1, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0xe3, 0x0, 0x0, 0x3e, 0xff, + 0xe2, 0xc, 0xff, 0xfe, 0x20, 0xff, 0xfe, 0x30, + 0x0, 0x0, 0x3, 0xff, 0x30, 0xaf, 0xff, 0xf3, + 0x0, 0xff, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x54, + 0x9, 0xff, 0xff, 0x40, 0x0, 0xbe, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0xff, 0xf6, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xff, 0xff, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xff, 0xf9, 0x4, 0x50, + 0x0, 0xbe, 0x30, 0x0, 0x0, 0x0, 0x3, 0xff, + 0xff, 0xa0, 0x3f, 0xf3, 0x0, 0xff, 0xe3, 0x0, + 0x0, 0x0, 0x2e, 0xff, 0xfc, 0x2, 0xef, 0xfe, + 0x30, 0xff, 0xfe, 0x30, 0xff, 0xff, 0xff, 0xff, + 0xd1, 0x1, 0xef, 0xff, 0xff, 0xff, 0xff, 0xe3, + 0xff, 0xff, 0xff, 0xfe, 0x10, 0x0, 0x2e, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xe2, + 0x0, 0x0, 0x3, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x9b, 0xbb, 0xbb, 0x30, 0x0, 0x0, 0x0, 0x3b, + 0xbb, 0xff, 0xff, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x69, 0x0, 0x0, + + /* U+F077 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xaf, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0xff, 0xff, 0x90, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0xff, + 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0xff, 0xfd, 0xff, 0xff, 0x90, 0x0, 0x0, 0x0, + 0x0, 0xaf, 0xff, 0xf9, 0xa, 0xff, 0xff, 0x90, + 0x0, 0x0, 0x0, 0xaf, 0xff, 0xf9, 0x0, 0xa, + 0xff, 0xff, 0x90, 0x0, 0x0, 0xaf, 0xff, 0xf9, + 0x0, 0x0, 0xa, 0xff, 0xff, 0x90, 0x0, 0xaf, + 0xff, 0xf9, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, + 0x90, 0x9f, 0xff, 0xf9, 0x0, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xff, 0x79, 0xff, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xa, 0xff, 0xf8, 0xb, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xfa, + 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0x0, + + /* U+F078 "" */ + 0x0, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x20, 0x0, 0xbf, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0xa0, 0x9f, 0xff, 0x90, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0x89, + 0xff, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0xff, 0xf7, 0xa, 0xff, 0xff, 0x90, 0x0, 0x0, + 0x0, 0xaf, 0xff, 0xf9, 0x0, 0xa, 0xff, 0xff, + 0x90, 0x0, 0x0, 0xaf, 0xff, 0xf9, 0x0, 0x0, + 0xa, 0xff, 0xff, 0x90, 0x0, 0xaf, 0xff, 0xf9, + 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, 0x90, 0xaf, + 0xff, 0xf9, 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, + 0xff, 0xdf, 0xff, 0xf9, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xff, 0xff, 0xff, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xff, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xf9, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+F079 "" */ + 0x0, 0x0, 0x3, 0xd9, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3, 0xef, 0xfa, 0x0, 0x0, 0x34, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x10, 0x0, 0x0, 0x0, + 0x3, 0xef, 0xff, 0xfa, 0x0, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x3, + 0xef, 0xff, 0xff, 0xfa, 0x5, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0x0, 0x0, 0x3, 0xff, + 0xff, 0xff, 0xff, 0xfa, 0x5, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbf, 0xff, 0x10, 0x0, 0x0, 0xef, 0xfe, + 0xdf, 0xfb, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xef, 0xf1, 0x0, 0x0, 0xd, 0xfe, 0x2b, + 0xff, 0x48, 0xff, 0x60, 0x0, 0x0, 0x0, 0x0, + 0xe, 0xff, 0x10, 0x0, 0x0, 0x17, 0x20, 0xbf, + 0xf4, 0x5, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xef, 0xf1, 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, + 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, + 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, + 0xf1, 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0xff, + 0x10, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0x70, 0xef, 0xf1, + 0x4f, 0xc0, 0x0, 0x0, 0xb, 0xff, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0xff, 0x6e, 0xff, 0x5f, + 0xff, 0x60, 0x0, 0x0, 0xbf, 0xf7, 0x44, 0x44, + 0x44, 0x44, 0x20, 0xcf, 0xff, 0xff, 0xff, 0xff, + 0xd1, 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x50, 0xbf, 0xff, 0xff, 0xff, 0xd1, + 0x0, 0x0, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x0, 0xbf, 0xff, 0xff, 0xd1, 0x0, + 0x0, 0x0, 0x4, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0x60, 0x0, 0xbf, 0xff, 0xd1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0xd1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, + + /* U+F07B "" */ + 0x3d, 0xff, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd3, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfd, 0x3d, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd3, + + /* U+F093 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xbf, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xff, 0xb0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, + 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0xff, 0xff, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xb0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x2, 0x22, + 0x2f, 0xff, 0xff, 0xf2, 0x22, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x25, 0x55, 0x55, 0x52, 0xf, 0xff, 0xff, 0xf0, + 0x25, 0x55, 0x55, 0x52, 0xef, 0xff, 0xff, 0xf9, + 0xc, 0xff, 0xff, 0xc0, 0x9f, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0x20, 0x1, 0x10, 0x2, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf9, 0x88, 0x88, 0x9f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x71, 0xe7, 0x1e, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xb6, 0xfb, 0x6f, 0xff, 0xbf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + + /* U+F095 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xea, 0x63, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0xff, + 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, + 0xff, 0xff, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xff, 0xff, 0xff, 0xff, 0xc0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, + 0xff, 0xff, 0xff, 0xf9, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x9f, 0xff, 0xff, 0xff, + 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6f, 0xff, 0xff, 0xf2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xff, 0xff, 0x60, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, + 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xdf, 0xff, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x1, 0x40, + 0x0, 0x0, 0x0, 0xaf, 0xff, 0xff, 0x30, 0x0, + 0x0, 0x0, 0x3a, 0xff, 0xa0, 0x0, 0x1, 0xbf, + 0xff, 0xff, 0x70, 0x0, 0x0, 0x5, 0xcf, 0xff, + 0xff, 0x70, 0x3, 0xdf, 0xff, 0xff, 0xa0, 0x0, + 0x0, 0xd, 0xff, 0xff, 0xff, 0xff, 0x6a, 0xff, + 0xff, 0xff, 0xb0, 0x0, 0x0, 0x0, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa0, 0x0, + 0x0, 0x0, 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x70, 0x0, 0x0, 0x0, 0x0, 0x6f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xe7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xff, 0xfc, 0x60, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xfe, 0xc9, + 0x62, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F0C4 "" */ + 0x0, 0x2, 0x42, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0xcf, 0xff, 0xc2, 0x0, + 0x0, 0x0, 0x0, 0x37, 0x73, 0x0, 0x2e, 0xff, + 0xff, 0xfe, 0x20, 0x0, 0x0, 0x8, 0xff, 0xff, + 0x90, 0xaf, 0xff, 0xcf, 0xff, 0xa0, 0x0, 0x0, + 0x9f, 0xff, 0xff, 0xb0, 0xef, 0xf4, 0x4, 0xff, + 0xe0, 0x0, 0x9, 0xff, 0xff, 0xfb, 0x0, 0xff, + 0xf1, 0x1, 0xff, 0xf0, 0x0, 0x9f, 0xff, 0xff, + 0xb0, 0x0, 0xcf, 0xfb, 0x5b, 0xff, 0xc0, 0x9, + 0xff, 0xff, 0xfb, 0x0, 0x0, 0x5f, 0xff, 0xff, + 0xff, 0xf5, 0x9f, 0xff, 0xff, 0xb0, 0x0, 0x0, + 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x39, 0xbe, 0xff, 0xff, + 0xff, 0xff, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xef, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0xff, 0xf5, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x49, 0xff, + 0xff, 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, 0x2, + 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x0, + 0x0, 0x0, 0x2e, 0xff, 0xff, 0xff, 0xfb, 0xef, + 0xff, 0xff, 0x50, 0x0, 0x0, 0xaf, 0xff, 0xcf, + 0xff, 0xd0, 0x2e, 0xff, 0xff, 0xf5, 0x0, 0x0, + 0xef, 0xf4, 0x4, 0xff, 0xe0, 0x2, 0xef, 0xff, + 0xff, 0x50, 0x0, 0xff, 0xf1, 0x1, 0xff, 0xf0, + 0x0, 0x2e, 0xff, 0xff, 0xf5, 0x0, 0xcf, 0xfb, + 0x5b, 0xff, 0xc0, 0x0, 0x2, 0xef, 0xff, 0xff, + 0x50, 0x5f, 0xff, 0xff, 0xff, 0x50, 0x0, 0x0, + 0x2e, 0xff, 0xff, 0xd0, 0x8, 0xff, 0xff, 0xf8, + 0x0, 0x0, 0x0, 0x1, 0xae, 0xea, 0x20, 0x0, + 0x39, 0xb9, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+F0C5 "" */ + 0x0, 0x0, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xf0, + 0x7a, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0x8, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8f, 0xfb, 0x0, + 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0x8, + 0xff, 0xfa, 0x47, 0x88, 0x40, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x48, 0x88, 0x7f, 0xff, 0xf8, 0xf, + 0xff, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfc, 0x4, 0x78, 0x88, 0x88, 0x88, 0x88, + 0x88, 0x74, 0xff, 0xff, 0xfa, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfb, 0x0, 0x0, 0x0, + + /* U+F0C7 "" */ + 0x1, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x42, + 0x0, 0x0, 0x6, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0x0, 0x0, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0xf, + 0xff, 0xcb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbd, 0xff, + 0xf8, 0x0, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xf, 0xff, 0xf8, 0xf, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0xf7, 0xff, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xef, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, + 0x54, 0x44, 0x44, 0x44, 0x44, 0x45, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0xce, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0, + 0x0, 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfa, 0x0, 0x0, 0xa, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, 0x0, + 0x2, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0x57, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xb1, 0x8b, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x81, + + /* U+F0C9 "" */ + 0x13, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x13, 0x33, 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x57, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x5f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfc, 0xee, 0xee, 0xee, 0xee, + 0xee, 0xee, 0xee, 0xee, 0xee, 0xeb, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x31, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe1, + 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, + 0x33, 0x31, + + /* U+F0E0 "" */ + 0x3d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xd3, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x2d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xd2, 0x0, 0x9f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, 0x0, + 0xe4, 0x5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x50, 0x4e, 0xff, 0x80, 0x2c, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xc2, 0x8, 0xff, + 0xff, 0xfc, 0x20, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xf9, 0x1, 0xcf, 0xff, 0xff, 0xff, 0xf5, 0x4, + 0xef, 0xff, 0xff, 0xfe, 0x40, 0x5e, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x90, 0x1c, 0xff, 0xff, 0xb1, + 0x9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0x20, 0x6d, 0xd6, 0x2, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf6, 0x0, 0x0, 0x6f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xd9, 0x9d, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfd, 0x3d, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd3, + + /* U+F0E7 "" */ + 0x0, 0x4f, 0xff, 0xff, 0xff, 0xf3, 0x0, 0x0, + 0x0, 0x9, 0xff, 0xff, 0xff, 0xff, 0x60, 0x0, + 0x0, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xf1, 0x0, + 0x0, 0x0, 0xd, 0xff, 0xff, 0xff, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0x70, + 0x0, 0x0, 0x0, 0x1f, 0xff, 0xff, 0xff, 0xf2, + 0x0, 0x0, 0x0, 0x3, 0xff, 0xff, 0xff, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, 0xff, 0xff, + 0xc8, 0x88, 0x87, 0x30, 0x8, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0xaf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xa0, 0xc, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf2, 0x0, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, 0x0, 0x0, 0x37, + 0x88, 0x88, 0xaf, 0xff, 0xff, 0x50, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0xff, 0xf3, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xf, 0xff, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xff, 0xff, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0xff, 0x70, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xd0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xfb, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xff, 0x20, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0x70, + 0x0, 0x0, 0x0, 0x0, + + /* U+F0EA "" */ + 0x0, 0x0, 0x3, 0xdf, 0xd3, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4, 0x78, 0x88, 0xff, 0xef, 0xf8, + 0x88, 0x74, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, + 0x90, 0x9f, 0xff, 0xff, 0xf0, 0x0, 0x0, 0xf, + 0xff, 0xff, 0xf9, 0x9, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, + 0xff, 0xf0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0xff, + 0xff, 0xff, 0xe5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xf, 0xff, 0xff, 0xf4, 0x7, 0x88, 0x88, + 0x88, 0x3, 0x30, 0x0, 0xff, 0xff, 0xff, 0x7, + 0xff, 0xff, 0xff, 0xf0, 0x8f, 0x40, 0xf, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0x8, 0xff, + 0x40, 0xff, 0xff, 0xff, 0x8, 0xff, 0xff, 0xff, + 0xf0, 0x8f, 0xff, 0x4f, 0xff, 0xff, 0xf0, 0x8f, + 0xff, 0xff, 0xff, 0x8, 0xff, 0xfe, 0xff, 0xff, + 0xff, 0x8, 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, + 0xb8, 0x88, 0x88, 0xff, 0xff, 0xff, 0x8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + 0x78, 0x88, 0x80, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfb, + + /* U+F0F3 "" */ + 0x0, 0x0, 0x0, 0x0, 0x8, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0x6f, 0xff, 0x51, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xf8, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, + 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf9, 0x0, 0x0, 0x0, + 0x4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, + 0x0, 0x0, 0x0, 0xaf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x90, 0x0, 0x0, 0xe, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x0, 0x1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf1, 0x0, 0x0, 0x4f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x0, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0, 0x5f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, + 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x3d, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0xdf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd2, + 0x78, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x88, 0x72, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6f, 0xff, 0xff, 0x60, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xff, 0xff, 0xe1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0xcf, 0xc3, + 0x0, 0x0, 0x0, 0x0, + + /* U+F11C "" */ + 0x3d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x3d, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x10, 0x1f, 0x90, 0x9, 0xf1, 0x1, + 0xf9, 0x0, 0x9f, 0x10, 0x1f, 0xff, 0xff, 0xf0, + 0x0, 0xf8, 0x0, 0x8f, 0x0, 0xf, 0x80, 0x8, + 0xf0, 0x0, 0xff, 0xff, 0xff, 0x10, 0x1f, 0x90, + 0x9, 0xf1, 0x1, 0xf9, 0x0, 0x9f, 0x10, 0x1f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xb8, 0x8f, 0xe8, 0x8b, 0xfb, 0x88, 0xfe, + 0x88, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0xcc, 0x0, 0x4f, 0x40, 0xc, 0xc0, 0x4, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x40, 0xc, 0xc0, 0x4, + 0xf4, 0x0, 0xcc, 0x0, 0x4f, 0xff, 0xff, 0xff, + 0xff, 0xfb, 0x88, 0xfe, 0x88, 0xbf, 0xb8, 0x8f, + 0xe8, 0x8b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0x1, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xf1, 0x1, 0xff, 0xff, + 0xff, 0x0, 0xf, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0x0, 0xf, 0xff, 0xff, 0xf1, 0x1, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xf1, + 0x1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xd3, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xd3, + + /* U+F124 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3a, + 0xfc, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4b, 0xff, 0xff, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5c, + 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6e, 0xff, 0xff, 0xff, 0xff, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x8e, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x2, 0x9f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x3, 0xaf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0x4, 0xcf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xc0, 0x0, 0x0, 0x6, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x50, 0x0, 0x3, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, 0x0, 0x0, 0xd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf6, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe0, 0x0, + 0x0, 0x9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x57, + 0x88, 0x88, 0x88, 0x8c, 0xff, 0xff, 0xff, 0xff, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xff, 0xff, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xff, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xa0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0xff, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x7, 0xff, 0xff, 0x60, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5, 0xff, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xd3, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+F15B "" */ + 0xbf, 0xff, 0xff, 0xff, 0xff, 0x80, 0xe4, 0x0, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0xff, + 0x40, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0xff, 0xf4, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x80, 0xff, 0xff, 0x40, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xf4, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x80, 0xff, 0xff, 0xfe, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + + /* U+F1EB "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3, 0x56, 0x77, 0x65, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0x7c, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xc7, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, + 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0x50, 0x0, 0x0, 0x0, 0x3, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfd, 0x30, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, + 0xc9, 0x65, 0x44, 0x56, 0x9c, 0xff, 0xff, 0xff, + 0xf8, 0x0, 0x1c, 0xff, 0xff, 0xfd, 0x61, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x16, 0xdf, 0xff, 0xff, + 0xc1, 0xdf, 0xff, 0xfe, 0x50, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xef, 0xff, 0xfd, + 0x9f, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x9, 0xff, 0xf9, 0x9, + 0xf6, 0x0, 0x0, 0x0, 0x48, 0xcd, 0xff, 0xdc, + 0x84, 0x0, 0x0, 0x0, 0x6f, 0x90, 0x0, 0x10, + 0x0, 0x0, 0x6e, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe6, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, + 0x3d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xd3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xff, + 0xff, 0xff, 0xfe, 0xcc, 0xef, 0xff, 0xff, 0xff, + 0x50, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xc5, 0x10, 0x0, 0x1, 0x5c, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xe4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4e, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0x60, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x32, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1d, 0xff, 0xc1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, 0xfb, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0xff, 0xfd, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5f, 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4, 0xaa, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F240 "" */ + 0x1, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x30, 0x0, 0x6f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x0, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x60, 0xff, 0xfb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbd, 0xff, 0xa1, 0xff, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xfe, 0xff, 0xf0, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8, + 0xff, 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5, 0xbf, + 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0xf, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0xf, 0xff, 0xff, + 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x2, 0x4f, 0xff, 0xff, 0xf0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xf4, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x4a, 0xff, 0xd7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x70, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x30, 0x18, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xa4, 0x0, + + /* U+F241 "" */ + 0x1, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x30, 0x0, 0x6f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x0, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x60, 0xff, 0xfb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbd, 0xff, 0xa1, 0xff, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xfe, 0xff, 0xf0, 0xbf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x8, + 0xff, 0xff, 0xff, 0xf0, 0xbf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x5, 0xbf, + 0xff, 0xff, 0xf0, 0xbf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xf0, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf4, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xf0, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf4, 0x0, 0x0, 0x2, 0x4f, 0xff, 0xff, 0xf0, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xf4, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x4a, 0xff, 0xd7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x70, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x30, 0x18, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xa4, 0x0, + + /* U+F242 "" */ + 0x1, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x30, 0x0, 0x6f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x0, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x60, 0xff, 0xfb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbd, 0xff, 0xa1, 0xff, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xfe, 0xff, 0xf0, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xbf, + 0xff, 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0x4f, 0xff, 0xff, 0xf0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xf4, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x4a, 0xff, 0xd7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x70, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x30, 0x18, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xa4, 0x0, + + /* U+F243 "" */ + 0x1, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x30, 0x0, 0x6f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x0, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x60, 0xff, 0xfb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbd, 0xff, 0xa1, 0xff, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xfe, 0xff, 0xf0, 0xbf, 0xff, 0xff, + 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0xff, 0xff, 0xf0, 0xbf, 0xff, 0xff, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xbf, + 0xff, 0xff, 0xf0, 0xbf, 0xff, 0xff, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xf0, 0xbf, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xf0, 0xbf, 0xff, 0xff, 0x40, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0x4f, 0xff, 0xff, 0xf0, + 0xbf, 0xff, 0xff, 0x40, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xf4, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x4a, 0xff, 0xd7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x70, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x30, 0x18, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xa4, 0x0, + + /* U+F244 "" */ + 0x1, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x30, 0x0, 0x6f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x0, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x60, 0xff, 0xfb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbd, 0xff, 0xa1, 0xff, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xfe, 0xff, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xbf, + 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0x4f, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xf4, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x4a, 0xff, 0xd7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x70, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x30, 0x18, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xa4, 0x0, + + /* U+F287 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2d, + 0xfe, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x27, 0x7d, 0xff, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xff, 0xff, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xe, 0xf5, 0x3a, 0xff, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xf6, 0x0, 0x9, 0xda, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, + 0x0, 0x0, 0xed, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xfe, 0x50, + 0x0, 0x6f, 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xa4, 0x0, 0x0, 0x8f, 0xff, 0xff, 0x30, + 0x1e, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xfa, 0x10, 0xe, 0xff, 0xff, 0xfd, 0xbe, + 0xfe, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xff, 0xff, 0x60, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfb, 0xa, 0xff, 0xff, 0xf5, 0x0, 0x0, + 0x1c, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xd4, 0x0, 0x1c, 0xff, 0xf9, 0x0, 0x0, 0x0, + 0x2f, 0xa0, 0x0, 0x0, 0x0, 0x0, 0xe, 0x70, + 0x0, 0x0, 0x4, 0x63, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xfb, 0x0, 0x8f, 0xff, 0xf5, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xf8, 0x4b, 0xff, 0xff, 0x60, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, + 0xff, 0xff, 0xff, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0x5c, 0xff, 0xff, 0x60, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x11, 0x10, 0x0, 0x0, 0x0, 0x0, + + /* U+F293 "" */ + 0x0, 0x0, 0x2, 0x8c, 0xef, 0xfe, 0xa6, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0x30, 0x0, 0x0, 0xc, 0xff, 0xff, 0xf4, + 0xff, 0xff, 0xff, 0x40, 0x0, 0xa, 0xff, 0xff, + 0xff, 0x5, 0xff, 0xff, 0xfe, 0x10, 0x2, 0xff, + 0xff, 0xff, 0xf0, 0x5, 0xff, 0xff, 0xf8, 0x0, + 0x9f, 0xff, 0xff, 0xff, 0x0, 0x6, 0xff, 0xff, + 0xe0, 0xe, 0xff, 0xfc, 0xff, 0xf0, 0x16, 0x7, + 0xff, 0xff, 0x21, 0xff, 0xf8, 0x9, 0xff, 0x1, + 0xf6, 0x7, 0xff, 0xf5, 0x4f, 0xff, 0xd1, 0x9, + 0xf0, 0x1f, 0x70, 0x6f, 0xff, 0x86, 0xff, 0xff, + 0xd1, 0x7, 0x1, 0x70, 0x5f, 0xff, 0xf9, 0x7f, + 0xff, 0xff, 0xd1, 0x0, 0x0, 0x3f, 0xff, 0xff, + 0xa7, 0xff, 0xff, 0xff, 0xc1, 0x0, 0x2e, 0xff, + 0xff, 0xfb, 0x7f, 0xff, 0xff, 0xff, 0x30, 0x5, + 0xff, 0xff, 0xff, 0xb7, 0xff, 0xff, 0xff, 0x40, + 0x0, 0x6, 0xff, 0xff, 0xfa, 0x6f, 0xff, 0xff, + 0x40, 0x30, 0x3, 0x7, 0xff, 0xff, 0xa4, 0xff, + 0xff, 0x40, 0x4e, 0x1, 0xe2, 0x8, 0xff, 0xf8, + 0x2f, 0xff, 0x70, 0x4f, 0xf0, 0x1f, 0x90, 0x2f, + 0xff, 0x60, 0xef, 0xff, 0x7f, 0xff, 0x1, 0xb0, + 0x2e, 0xff, 0xf3, 0xa, 0xff, 0xff, 0xff, 0xf0, + 0x0, 0x2e, 0xff, 0xff, 0x0, 0x4f, 0xff, 0xff, + 0xff, 0x0, 0x2e, 0xff, 0xff, 0x90, 0x0, 0xbf, + 0xff, 0xff, 0xf0, 0x2e, 0xff, 0xff, 0xf2, 0x0, + 0x1, 0xdf, 0xff, 0xff, 0x3e, 0xff, 0xff, 0xf7, + 0x0, 0x0, 0x0, 0xaf, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x0, 0x0, 0x0, 0x0, 0x28, 0xce, 0xff, + 0xec, 0x82, 0x0, 0x0, + + /* U+F2ED "" */ + 0x0, 0x0, 0x0, 0x1a, 0xcc, 0xcc, 0xca, 0x10, + 0x0, 0x0, 0x2, 0x44, 0x44, 0x49, 0xff, 0xff, + 0xff, 0xf9, 0x44, 0x44, 0x42, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x9b, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0x0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x8, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x8f, + 0xff, 0x66, 0xff, 0xd1, 0xdf, 0xf6, 0x6f, 0xff, + 0x80, 0x8, 0xff, 0xf4, 0x4f, 0xfc, 0xc, 0xff, + 0x44, 0xff, 0xf8, 0x0, 0x8f, 0xff, 0x44, 0xff, + 0xc0, 0xcf, 0xf4, 0x4f, 0xff, 0x80, 0x8, 0xff, + 0xf4, 0x4f, 0xfc, 0xc, 0xff, 0x44, 0xff, 0xf8, + 0x0, 0x8f, 0xff, 0x44, 0xff, 0xc0, 0xcf, 0xf4, + 0x4f, 0xff, 0x80, 0x8, 0xff, 0xf4, 0x4f, 0xfc, + 0xc, 0xff, 0x44, 0xff, 0xf8, 0x0, 0x8f, 0xff, + 0x44, 0xff, 0xc0, 0xcf, 0xf4, 0x4f, 0xff, 0x80, + 0x8, 0xff, 0xf4, 0x4f, 0xfc, 0xc, 0xff, 0x44, + 0xff, 0xf8, 0x0, 0x8f, 0xff, 0x44, 0xff, 0xc0, + 0xcf, 0xf4, 0x4f, 0xff, 0x80, 0x8, 0xff, 0xf4, + 0x4f, 0xfc, 0xc, 0xff, 0x44, 0xff, 0xf8, 0x0, + 0x8f, 0xff, 0x44, 0xff, 0xc0, 0xcf, 0xf4, 0x4f, + 0xff, 0x80, 0x8, 0xff, 0xf6, 0x6f, 0xfd, 0x1d, + 0xff, 0x66, 0xff, 0xf8, 0x0, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x5, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf5, 0x0, 0x9, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf9, 0x0, + + /* U+F304 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6e, 0xe5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xf6, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xff, 0xff, + 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x50, 0x3f, 0xff, 0xff, 0xff, 0xe0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xb0, 0x3f, + 0xff, 0xff, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xb0, 0x3f, 0xff, 0xff, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xb0, 0x3f, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xff, 0xb0, 0x3f, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xb0, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xdb, 0xa8, 0x50, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F55A "" */ + 0x0, 0x0, 0x0, 0x2, 0xbf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x80, 0x0, + 0x0, 0x0, 0x3e, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, + 0x3, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, 0x0, 0x0, 0x3e, + 0xff, 0xff, 0xff, 0xff, 0xcf, 0xff, 0xff, 0xfc, + 0xff, 0xff, 0xff, 0xff, 0x0, 0x3, 0xef, 0xff, + 0xff, 0xff, 0xf8, 0x6, 0xff, 0xff, 0x60, 0x8f, + 0xff, 0xff, 0xff, 0x0, 0x3e, 0xff, 0xff, 0xff, + 0xff, 0xc0, 0x0, 0x6f, 0xf6, 0x0, 0xc, 0xff, + 0xff, 0xff, 0x3, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xf6, 0x0, 0x6, 0x60, 0x0, 0x6f, 0xff, 0xff, + 0xff, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x60, 0x0, 0x0, 0x6, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, + 0x0, 0x0, 0x6f, 0xff, 0xff, 0xff, 0xff, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x0, + 0x0, 0x6f, 0xff, 0xff, 0xff, 0xff, 0x3f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x60, 0x0, 0x0, + 0x6, 0xff, 0xff, 0xff, 0xff, 0x3, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf6, 0x0, 0x6, 0x60, 0x0, + 0x6f, 0xff, 0xff, 0xff, 0x0, 0x3e, 0xff, 0xff, + 0xff, 0xff, 0xc0, 0x0, 0x6f, 0xf6, 0x0, 0xc, + 0xff, 0xff, 0xff, 0x0, 0x3, 0xef, 0xff, 0xff, + 0xff, 0xf8, 0x6, 0xff, 0xff, 0x60, 0x8f, 0xff, + 0xff, 0xff, 0x0, 0x0, 0x3e, 0xff, 0xff, 0xff, + 0xff, 0xcf, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xff, + 0xff, 0x0, 0x0, 0x3, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x0, 0x0, 0x0, 0x3e, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, + 0x0, 0x0, 0x2, 0xbf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, 0x80, + + /* U+F7C2 "" */ + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x80, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x0, 0x8f, 0xf4, 0x8, 0xf0, + 0xe, 0x90, 0xf, 0xff, 0x8, 0xff, 0xf4, 0x8, + 0xf0, 0xe, 0x90, 0xf, 0xff, 0x8f, 0xff, 0xf4, + 0x8, 0xf0, 0xe, 0x90, 0xf, 0xff, 0xff, 0xff, + 0xf4, 0x8, 0xf0, 0xe, 0x90, 0xf, 0xff, 0xff, + 0xff, 0xfa, 0x8c, 0xf8, 0x8f, 0xc8, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x8, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x80, + + /* U+F8A2 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x7, 0xff, 0x10, 0x0, 0x0, + 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xff, 0xf1, 0x0, 0x0, 0x1c, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0x10, 0x0, + 0x1d, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xf1, 0x0, 0x2d, 0xff, 0xf9, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0x10, + 0x2e, 0xff, 0xff, 0xa2, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x2b, 0xff, 0xf1, 0x3e, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x1d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf1, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x0, 0x8f, 0xff, 0xff, 0xd9, 0x99, 0x99, + 0x99, 0x99, 0x99, 0x99, 0x99, 0x60, 0x0, 0x7f, + 0xff, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, 0x90, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4a, 0x20, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 +}; + + +/*--------------------- + * GLYPH DESCRIPTION + *--------------------*/ + +static const lv_font_fmt_txt_glyph_dsc_t glyph_dsc[] = { + {.bitmap_index = 0, .adv_w = 0, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0} /* id = 0 reserved */, + {.bitmap_index = 0, .adv_w = 97, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 0, .adv_w = 111, .box_w = 3, .box_h = 19, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 29, .adv_w = 141, .box_w = 7, .box_h = 7, .ofs_x = 1, .ofs_y = 11}, + {.bitmap_index = 54, .adv_w = 222, .box_w = 14, .box_h = 18, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 180, .adv_w = 233, .box_w = 14, .box_h = 24, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 348, .adv_w = 358, .box_w = 20, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 538, .adv_w = 285, .box_w = 17, .box_h = 20, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 708, .adv_w = 75, .box_w = 3, .box_h = 7, .ofs_x = 1, .ofs_y = 11}, + {.bitmap_index = 719, .adv_w = 133, .box_w = 7, .box_h = 23, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 800, .adv_w = 133, .box_w = 7, .box_h = 23, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 881, .adv_w = 163, .box_w = 10, .box_h = 9, .ofs_x = 0, .ofs_y = 9}, + {.bitmap_index = 926, .adv_w = 241, .box_w = 13, .box_h = 13, .ofs_x = 1, .ofs_y = 2}, + {.bitmap_index = 1011, .adv_w = 194, .box_w = 10, .box_h = 2, .ofs_x = 1, .ofs_y = 7}, + {.bitmap_index = 1021, .adv_w = 117, .box_w = 4, .box_h = 3, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 1027, .adv_w = 108, .box_w = 7, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1094, .adv_w = 221, .box_w = 12, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1208, .adv_w = 180, .box_w = 7, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1275, .adv_w = 216, .box_w = 12, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1389, .adv_w = 218, .box_w = 12, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1503, .adv_w = 221, .box_w = 14, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1636, .adv_w = 218, .box_w = 12, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1750, .adv_w = 221, .box_w = 12, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1864, .adv_w = 218, .box_w = 12, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1978, .adv_w = 223, .box_w = 12, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2092, .adv_w = 221, .box_w = 12, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2206, .adv_w = 114, .box_w = 4, .box_h = 14, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 2234, .adv_w = 114, .box_w = 4, .box_h = 19, .ofs_x = 2, .ofs_y = -6}, + {.bitmap_index = 2272, .adv_w = 241, .box_w = 13, .box_h = 17, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2383, .adv_w = 236, .box_w = 13, .box_h = 8, .ofs_x = 1, .ofs_y = 5}, + {.bitmap_index = 2435, .adv_w = 239, .box_w = 13, .box_h = 17, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2546, .adv_w = 222, .box_w = 13, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2670, .adv_w = 366, .box_w = 21, .box_h = 22, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 2901, .adv_w = 271, .box_w = 17, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3063, .adv_w = 268, .box_w = 15, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3206, .adv_w = 293, .box_w = 17, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3368, .adv_w = 290, .box_w = 16, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3520, .adv_w = 268, .box_w = 14, .box_h = 19, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 3653, .adv_w = 247, .box_w = 13, .box_h = 19, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 3777, .adv_w = 312, .box_w = 18, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3948, .adv_w = 290, .box_w = 15, .box_h = 19, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 4091, .adv_w = 105, .box_w = 3, .box_h = 19, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 4120, .adv_w = 201, .box_w = 11, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4225, .adv_w = 268, .box_w = 16, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4377, .adv_w = 225, .box_w = 13, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4501, .adv_w = 336, .box_w = 19, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4682, .adv_w = 290, .box_w = 16, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4834, .adv_w = 314, .box_w = 18, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 5005, .adv_w = 268, .box_w = 14, .box_h = 19, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 5138, .adv_w = 314, .box_w = 18, .box_h = 24, .ofs_x = 1, .ofs_y = -6}, + {.bitmap_index = 5354, .adv_w = 290, .box_w = 16, .box_h = 19, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 5506, .adv_w = 268, .box_w = 15, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 5649, .adv_w = 247, .box_w = 15, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5792, .adv_w = 293, .box_w = 15, .box_h = 19, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 5935, .adv_w = 274, .box_w = 18, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6106, .adv_w = 382, .box_w = 24, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6334, .adv_w = 271, .box_w = 17, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6496, .adv_w = 268, .box_w = 17, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6658, .adv_w = 247, .box_w = 15, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6801, .adv_w = 108, .box_w = 6, .box_h = 25, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 6876, .adv_w = 108, .box_w = 7, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6943, .adv_w = 108, .box_w = 6, .box_h = 25, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 7018, .adv_w = 190, .box_w = 12, .box_h = 10, .ofs_x = 0, .ofs_y = 8}, + {.bitmap_index = 7078, .adv_w = 239, .box_w = 16, .box_h = 3, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 7102, .adv_w = 127, .box_w = 5, .box_h = 4, .ofs_x = 1, .ofs_y = 14}, + {.bitmap_index = 7112, .adv_w = 225, .box_w = 14, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7210, .adv_w = 222, .box_w = 13, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 7334, .adv_w = 203, .box_w = 13, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7425, .adv_w = 222, .box_w = 13, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7549, .adv_w = 225, .box_w = 14, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7647, .adv_w = 113, .box_w = 8, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7723, .adv_w = 225, .box_w = 13, .box_h = 19, .ofs_x = 0, .ofs_y = -6}, + {.bitmap_index = 7847, .adv_w = 222, .box_w = 12, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 7961, .adv_w = 84, .box_w = 3, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 7990, .adv_w = 84, .box_w = 6, .box_h = 24, .ofs_x = -2, .ofs_y = -6}, + {.bitmap_index = 8062, .adv_w = 201, .box_w = 12, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 8176, .adv_w = 84, .box_w = 3, .box_h = 19, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 8205, .adv_w = 333, .box_w = 19, .box_h = 14, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 8338, .adv_w = 225, .box_w = 12, .box_h = 14, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 8422, .adv_w = 225, .box_w = 14, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8520, .adv_w = 222, .box_w = 13, .box_h = 19, .ofs_x = 1, .ofs_y = -6}, + {.bitmap_index = 8644, .adv_w = 222, .box_w = 13, .box_h = 19, .ofs_x = 0, .ofs_y = -6}, + {.bitmap_index = 8768, .adv_w = 140, .box_w = 8, .box_h = 14, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 8824, .adv_w = 209, .box_w = 12, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8908, .adv_w = 111, .box_w = 7, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8975, .adv_w = 222, .box_w = 12, .box_h = 14, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 9059, .adv_w = 201, .box_w = 13, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 9150, .adv_w = 290, .box_w = 19, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 9283, .adv_w = 201, .box_w = 13, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 9374, .adv_w = 201, .box_w = 13, .box_h = 19, .ofs_x = 0, .ofs_y = -6}, + {.bitmap_index = 9498, .adv_w = 201, .box_w = 13, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 9589, .adv_w = 133, .box_w = 8, .box_h = 25, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 9689, .adv_w = 100, .box_w = 2, .box_h = 23, .ofs_x = 2, .ofs_y = -4}, + {.bitmap_index = 9712, .adv_w = 133, .box_w = 8, .box_h = 25, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 9812, .adv_w = 236, .box_w = 13, .box_h = 3, .ofs_x = 1, .ofs_y = 7}, + {.bitmap_index = 9832, .adv_w = 384, .box_w = 24, .box_h = 25, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 10132, .adv_w = 384, .box_w = 24, .box_h = 18, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 10348, .adv_w = 384, .box_w = 24, .box_h = 22, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 10612, .adv_w = 384, .box_w = 24, .box_h = 18, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 10828, .adv_w = 264, .box_w = 17, .box_h = 18, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 10981, .adv_w = 384, .box_w = 24, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 11269, .adv_w = 384, .box_w = 24, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 11557, .adv_w = 432, .box_w = 27, .box_h = 22, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 11854, .adv_w = 384, .box_w = 24, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 12142, .adv_w = 432, .box_w = 27, .box_h = 18, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 12385, .adv_w = 384, .box_w = 24, .box_h = 26, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 12697, .adv_w = 192, .box_w = 12, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 12811, .adv_w = 288, .box_w = 18, .box_h = 19, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 12982, .adv_w = 432, .box_w = 27, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 13306, .adv_w = 384, .box_w = 24, .box_h = 18, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 13522, .adv_w = 264, .box_w = 17, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 13726, .adv_w = 336, .box_w = 15, .box_h = 22, .ofs_x = 3, .ofs_y = -2}, + {.bitmap_index = 13891, .adv_w = 336, .box_w = 21, .box_h = 26, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 14164, .adv_w = 336, .box_w = 21, .box_h = 22, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 14395, .adv_w = 336, .box_w = 21, .box_h = 22, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 14626, .adv_w = 336, .box_w = 15, .box_h = 22, .ofs_x = 3, .ofs_y = -2}, + {.bitmap_index = 14791, .adv_w = 336, .box_w = 23, .box_h = 22, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 15044, .adv_w = 240, .box_w = 13, .box_h = 22, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 15187, .adv_w = 240, .box_w = 13, .box_h = 22, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 15330, .adv_w = 336, .box_w = 21, .box_h = 22, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 15561, .adv_w = 336, .box_w = 21, .box_h = 6, .ofs_x = 0, .ofs_y = 6}, + {.bitmap_index = 15624, .adv_w = 432, .box_w = 27, .box_h = 18, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 15867, .adv_w = 480, .box_w = 31, .box_h = 24, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 16239, .adv_w = 432, .box_w = 29, .box_h = 24, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 16587, .adv_w = 384, .box_w = 24, .box_h = 22, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 16851, .adv_w = 336, .box_w = 21, .box_h = 14, .ofs_x = 0, .ofs_y = 2}, + {.bitmap_index = 16998, .adv_w = 336, .box_w = 21, .box_h = 14, .ofs_x = 0, .ofs_y = 2}, + {.bitmap_index = 17145, .adv_w = 480, .box_w = 31, .box_h = 19, .ofs_x = -1, .ofs_y = -1}, + {.bitmap_index = 17440, .adv_w = 384, .box_w = 24, .box_h = 18, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 17656, .adv_w = 384, .box_w = 24, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 17944, .adv_w = 384, .box_w = 25, .box_h = 25, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 18257, .adv_w = 336, .box_w = 22, .box_h = 22, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 18499, .adv_w = 336, .box_w = 21, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 18751, .adv_w = 336, .box_w = 21, .box_h = 22, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 18982, .adv_w = 336, .box_w = 21, .box_h = 20, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 19192, .adv_w = 384, .box_w = 24, .box_h = 18, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 19408, .adv_w = 240, .box_w = 17, .box_h = 24, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 19612, .adv_w = 336, .box_w = 21, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 19864, .adv_w = 336, .box_w = 21, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 20116, .adv_w = 432, .box_w = 27, .box_h = 18, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 20359, .adv_w = 384, .box_w = 26, .box_h = 26, .ofs_x = -1, .ofs_y = -4}, + {.bitmap_index = 20697, .adv_w = 288, .box_w = 18, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 20913, .adv_w = 480, .box_w = 30, .box_h = 23, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 21258, .adv_w = 480, .box_w = 30, .box_h = 16, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 21498, .adv_w = 480, .box_w = 30, .box_h = 16, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 21738, .adv_w = 480, .box_w = 30, .box_h = 16, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 21978, .adv_w = 480, .box_w = 30, .box_h = 16, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 22218, .adv_w = 480, .box_w = 30, .box_h = 16, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 22458, .adv_w = 480, .box_w = 31, .box_h = 20, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 22768, .adv_w = 336, .box_w = 19, .box_h = 24, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 22996, .adv_w = 336, .box_w = 21, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 23248, .adv_w = 384, .box_w = 25, .box_h = 25, .ofs_x = -1, .ofs_y = -4}, + {.bitmap_index = 23561, .adv_w = 480, .box_w = 30, .box_h = 18, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 23831, .adv_w = 288, .box_w = 18, .box_h = 24, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 24047, .adv_w = 386, .box_w = 25, .box_h = 16, .ofs_x = 0, .ofs_y = 1} +}; + +/*--------------------- + * CHARACTER MAPPING + *--------------------*/ + +static const uint16_t unicode_list_2[] = { + 0x0, 0x7, 0xa, 0xb, 0xc, 0x10, 0x12, 0x14, + 0x18, 0x1b, 0x20, 0x25, 0x26, 0x27, 0x3d, 0x42, + 0x47, 0x4a, 0x4b, 0x4c, 0x50, 0x51, 0x52, 0x53, + 0x66, 0x67, 0x6d, 0x6f, 0x70, 0x73, 0x76, 0x77, + 0x78, 0x7a, 0x92, 0x94, 0xc3, 0xc4, 0xc6, 0xc8, + 0xdf, 0xe6, 0xe9, 0xf2, 0x11b, 0x123, 0x15a, 0x1ea, + 0x23f, 0x240, 0x241, 0x242, 0x243, 0x286, 0x292, 0x2ec, + 0x303, 0x559, 0x7c1, 0x8a1 +}; + +/*Collect the unicode lists and glyph_id offsets*/ +static const lv_font_fmt_txt_cmap_t cmaps[] = +{ + { + .range_start = 32, .range_length = 12, .glyph_id_start = 1, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 45, .range_length = 82, .glyph_id_start = 13, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 61441, .range_length = 2210, .glyph_id_start = 95, + .unicode_list = unicode_list_2, .glyph_id_ofs_list = NULL, .list_length = 60, .type = LV_FONT_FMT_TXT_CMAP_SPARSE_TINY + } +}; + + + +/*-------------------- + * ALL CUSTOM DATA + *--------------------*/ + +#if LV_VERSION_CHECK(8, 0, 0) +/*Store all the custom data of the font*/ +static lv_font_fmt_txt_glyph_cache_t cache; +static const lv_font_fmt_txt_dsc_t font_dsc = { +#else +static lv_font_fmt_txt_dsc_t font_dsc = { +#endif + .glyph_bitmap = glyph_bitmap, + .glyph_dsc = glyph_dsc, + .cmaps = cmaps, + .kern_dsc = NULL, + .kern_scale = 0, + .cmap_num = 3, + .bpp = 4, + .kern_classes = 0, + .bitmap_format = 0, +#if LV_VERSION_CHECK(8, 0, 0) + .cache = &cache +#endif +}; + + +/*----------------- + * PUBLIC FONT + *----------------*/ + +/*Initialize a public general font descriptor*/ +#if LV_VERSION_CHECK(8, 0, 0) +const lv_font_t lv_font_MI_LanTing_Regular_24 = { +#else +lv_font_t lv_font_MI_LanTing_Regular_24 = { +#endif + .get_glyph_dsc = lv_font_get_glyph_dsc_fmt_txt, /*Function pointer to get glyph's data*/ + .get_glyph_bitmap = lv_font_get_bitmap_fmt_txt, /*Function pointer to get glyph's bitmap*/ + .line_height = 24, /*The maximum line height required by the font default: (f.src.ascent - f.src.descent)*/ + .base_line = 4, /*Baseline measured from the bottom of the line*/ +#if !(LVGL_VERSION_MAJOR == 6 && LVGL_VERSION_MINOR == 0) + .subpx = LV_FONT_SUBPX_NONE, +#endif +#if LV_VERSION_CHECK(7, 4, 0) || LVGL_VERSION_MAJOR >= 8 + .underline_position = -2, + .underline_thickness = 1, +#endif + .dsc = &font_dsc /*The custom font data. Will be accessed by `get_glyph_bitmap/dsc` */ +}; + + + +#endif /*#if LV_FONT_MI_LANTING_REGULAR_24*/ + diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_28.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_28.c new file mode 100644 index 0000000000000000000000000000000000000000..8880ca22e6ee4674f174df628b03c53b23ed07f9 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_MI_LanTing_Regular_28.c @@ -0,0 +1,5829 @@ +/* + * Copyright 2024 NXP + * NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in + * accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, + * activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to + * comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license + * terms, then you may not retain, install, activate or otherwise use the software. + */ +/******************************************************************************* + * Size: 28 px + * Bpp: 4 + * Opts: --user-data-dir=C:\Users\hp\AppData\Roaming\gui-guider --app-path=C:\NXP\GUI-Guider-1.7.2-GA\resources\app.asar --no-sandbox --no-zygote --lang=zh-CN --device-scale-factor=1.5 --num-raster-threads=4 --enable-main-frame-before-activation --renderer-client-id=5 --time-ticks-at-unix-epoch=-1732015070561205 --launch-time-ticks=65380923608 --mojo-platform-channel-handle=3108 --field-trial-handle=1864,i,17219279099561217522,18026807573185265005,131072 --disable-features=SpareRendererForSitePerProcess,WinRetrieveSuggestionsOnlyOnDemand /prefetch:1 + ******************************************************************************/ + +#ifdef LV_LVGL_H_INCLUDE_SIMPLE +#include "lvgl.h" +#else +#include "lvgl.h" +#endif + +#ifndef LV_FONT_MI_LANTING_REGULAR_28 +#define LV_FONT_MI_LANTING_REGULAR_28 1 +#endif + +#if LV_FONT_MI_LANTING_REGULAR_28 + +/*----------------- + * BITMAPS + *----------------*/ + +/*Store the image of the glyphs*/ +static LV_ATTRIBUTE_LARGE_CONST const uint8_t glyph_bitmap[] = { + /* U+0020 " " */ + + /* U+0021 "!" */ + 0x4f, 0xf8, 0x4f, 0xf8, 0x3f, 0xf7, 0x3f, 0xf7, + 0x2f, 0xf6, 0x2f, 0xf5, 0x1f, 0xf5, 0xf, 0xf4, + 0xf, 0xf4, 0xf, 0xf3, 0xf, 0xf2, 0xe, 0xf2, + 0xe, 0xf1, 0xd, 0xf1, 0xc, 0xf0, 0x9, 0xb0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2e, 0xe5, + 0x2f, 0xf6, 0x2f, 0xf6, + + /* U+0022 "\"" */ + 0x8f, 0xf2, 0xb, 0xff, 0x7, 0xff, 0x10, 0xaf, + 0xe0, 0x6f, 0xf0, 0x9, 0xfd, 0x4, 0xff, 0x0, + 0x8f, 0xc0, 0x3f, 0xe0, 0x7, 0xfb, 0x2, 0xfd, + 0x0, 0x5f, 0xa0, 0x1f, 0xc0, 0x4, 0xf9, 0x0, + 0x85, 0x0, 0x28, 0x40, + + /* U+0023 "#" */ + 0x0, 0x0, 0x0, 0x9f, 0x30, 0x0, 0xfd, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xf0, 0x0, 0x2f, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0xfd, 0x0, 0x5, 0xf7, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xa0, 0x0, 0x8f, + 0x40, 0x0, 0x0, 0x0, 0x6, 0xf7, 0x0, 0xc, + 0xf1, 0x0, 0x0, 0x0, 0x0, 0x9f, 0x40, 0x0, + 0xfd, 0x0, 0x0, 0x0, 0xbb, 0xbe, 0xfc, 0xbb, + 0xbf, 0xeb, 0xbb, 0x0, 0x4f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xd0, 0x0, 0x0, 0x3f, 0xa0, + 0x0, 0x8f, 0x40, 0x0, 0x0, 0x0, 0x6, 0xf7, + 0x0, 0xb, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0x30, 0x0, 0xee, 0x0, 0x0, 0x0, 0x0, 0xc, + 0xf0, 0x0, 0x1f, 0xb0, 0x0, 0x0, 0x0, 0x0, + 0xed, 0x0, 0x4, 0xf8, 0x0, 0x0, 0x7, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, 0x7c, + 0xcd, 0xfd, 0xcc, 0xcf, 0xfc, 0xcc, 0x50, 0x0, + 0x0, 0x9f, 0x30, 0x0, 0xee, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xf0, 0x0, 0x2f, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0xfd, 0x0, 0x5, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0xa0, 0x0, 0x8f, 0x40, 0x0, + 0x0, 0x0, 0x6, 0xf6, 0x0, 0xc, 0xf1, 0x0, + 0x0, 0x0, 0x0, 0x9f, 0x30, 0x0, 0xfe, 0x0, + 0x0, 0x0, 0x0, + + /* U+0024 "$" */ + 0x0, 0x0, 0x0, 0x2f, 0x40, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x37, 0xbf, 0xb7, 0x20, 0x0, 0x0, 0x1, + 0xbf, 0xff, 0xff, 0xff, 0x90, 0x0, 0x1, 0xef, + 0xf9, 0x7f, 0x9b, 0xff, 0xa0, 0x0, 0x9f, 0xd1, + 0x2, 0xf4, 0x6, 0xff, 0x50, 0xf, 0xf3, 0x0, + 0x2f, 0x40, 0xa, 0xfd, 0x2, 0xff, 0x0, 0x2, + 0xf4, 0x0, 0x2f, 0xf2, 0x2f, 0xf0, 0x0, 0x2f, + 0x40, 0x0, 0x73, 0x0, 0xff, 0x60, 0x2, 0xf4, + 0x0, 0x0, 0x0, 0x8, 0xff, 0x81, 0x2f, 0x40, + 0x0, 0x0, 0x0, 0xa, 0xff, 0xfb, 0xf5, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xcf, 0xff, 0xfd, 0x71, + 0x0, 0x0, 0x0, 0x0, 0x28, 0xff, 0xff, 0xe4, + 0x0, 0x0, 0x0, 0x0, 0x2f, 0x55, 0xcf, 0xf5, + 0x0, 0x0, 0x0, 0x2, 0xf4, 0x0, 0x7f, 0xf1, + 0x0, 0x0, 0x0, 0x2f, 0x40, 0x0, 0x9f, 0x77, + 0xe3, 0x0, 0x2, 0xf4, 0x0, 0x5, 0xfb, 0xbf, + 0x70, 0x0, 0x2f, 0x40, 0x0, 0x6f, 0xc7, 0xfe, + 0x0, 0x2, 0xf4, 0x0, 0xa, 0xf9, 0x1f, 0xf9, + 0x0, 0x2f, 0x40, 0x3, 0xff, 0x30, 0x6f, 0xfb, + 0x43, 0xf4, 0x16, 0xef, 0xb0, 0x0, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xc1, 0x0, 0x0, 0x3a, 0xef, + 0xff, 0xfd, 0x70, 0x0, 0x0, 0x0, 0x0, 0x2f, + 0x61, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0x40, + 0x0, 0x0, 0x0, + + /* U+0025 "%" */ + 0x0, 0x3b, 0xef, 0xd7, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xb0, 0x0, 0x0, 0x3, 0xff, 0xec, 0xff, + 0x80, 0x0, 0x0, 0x0, 0xdf, 0x30, 0x0, 0x0, + 0xb, 0xf7, 0x0, 0x2e, 0xf1, 0x0, 0x0, 0x5, + 0xfa, 0x0, 0x0, 0x0, 0xf, 0xc0, 0x0, 0x7, + 0xf6, 0x0, 0x0, 0xd, 0xf2, 0x0, 0x0, 0x0, + 0x3f, 0x90, 0x0, 0x3, 0xf9, 0x0, 0x0, 0x6f, + 0x90, 0x0, 0x0, 0x0, 0x3f, 0x80, 0x0, 0x2, + 0xf9, 0x0, 0x0, 0xef, 0x10, 0x0, 0x0, 0x0, + 0x1f, 0xa0, 0x0, 0x4, 0xf8, 0x0, 0x7, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xf0, 0x0, 0x9, + 0xf5, 0x0, 0x1e, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x7, 0xfc, 0x31, 0x6f, 0xe0, 0x0, 0x8f, 0x70, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xff, 0xff, + 0x40, 0x1, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3, 0x8a, 0x71, 0x0, 0x9, 0xf6, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2f, 0xe0, 0x0, 0x3b, 0xff, 0xc5, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x60, 0x4, + 0xff, 0xcb, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xfd, 0x0, 0xd, 0xf4, 0x0, 0x2f, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xf5, 0x0, 0x2f, + 0xb0, 0x0, 0x9, 0xf3, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xc0, 0x0, 0x4f, 0x70, 0x0, 0x5, 0xf6, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0x40, 0x0, 0x5f, + 0x60, 0x0, 0x4, 0xf7, 0x0, 0x0, 0x0, 0x4, + 0xfb, 0x0, 0x0, 0x4f, 0x80, 0x0, 0x6, 0xf6, + 0x0, 0x0, 0x0, 0xd, 0xf3, 0x0, 0x0, 0x1f, + 0xc0, 0x0, 0xa, 0xf4, 0x0, 0x0, 0x0, 0x5f, + 0xb0, 0x0, 0x0, 0xb, 0xf7, 0x0, 0x4f, 0xe0, + 0x0, 0x0, 0x0, 0xdf, 0x20, 0x0, 0x0, 0x2, + 0xef, 0xed, 0xff, 0x50, 0x0, 0x0, 0x6, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x1a, 0xef, 0xc4, 0x0, + + /* U+0026 "&" */ + 0x0, 0x0, 0x6, 0xcf, 0xfc, 0x60, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0xfc, 0xdf, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xfc, 0x10, + 0x3, 0xff, 0x40, 0x0, 0x0, 0x0, 0x0, 0xc, + 0xf4, 0x0, 0x0, 0x8f, 0xa0, 0x0, 0x0, 0x0, + 0x0, 0xe, 0xf1, 0x0, 0x0, 0x5f, 0xd0, 0x0, + 0x0, 0x0, 0x0, 0xd, 0xf1, 0x0, 0x0, 0x6f, + 0xc0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xf6, 0x0, + 0x0, 0xcf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xfe, 0x10, 0x9, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0xb4, 0xcf, 0xd2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0xf9, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xcf, 0xff, + 0x90, 0x0, 0x0, 0xa, 0x92, 0x0, 0x0, 0x5f, + 0xfb, 0x3d, 0xf7, 0x0, 0x0, 0xe, 0xf4, 0x0, + 0x4, 0xff, 0x70, 0x1, 0xdf, 0x70, 0x0, 0x1f, + 0xf1, 0x0, 0xe, 0xf7, 0x0, 0x0, 0x1e, 0xf8, + 0x0, 0x4f, 0xd0, 0x0, 0x6f, 0xc0, 0x0, 0x0, + 0x2, 0xef, 0x90, 0x9f, 0x80, 0x0, 0xaf, 0x70, + 0x0, 0x0, 0x0, 0x2e, 0xfb, 0xff, 0x10, 0x0, + 0xbf, 0x70, 0x0, 0x0, 0x0, 0x1, 0xdf, 0xfa, + 0x0, 0x0, 0x8f, 0xb0, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xfe, 0x30, 0x0, 0x3f, 0xf3, 0x0, 0x0, + 0x0, 0x6, 0xff, 0xef, 0xf5, 0x0, 0xa, 0xfe, + 0x71, 0x0, 0x16, 0xcf, 0xf7, 0xb, 0xff, 0x80, + 0x0, 0xbf, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x0, + 0x9f, 0xf7, 0x0, 0x5, 0xbe, 0xfe, 0xd9, 0x40, + 0x0, 0x0, 0x7, 0xb0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+0027 "'" */ + 0x9f, 0xf1, 0x8f, 0xf0, 0x7f, 0xf0, 0x6f, 0xe0, + 0x5f, 0xd0, 0x3f, 0xc0, 0x2f, 0xa0, 0x8, 0x50, + + /* U+0028 "(" */ + 0x0, 0x0, 0x1, 0x75, 0x0, 0x0, 0xa, 0xf2, + 0x0, 0x0, 0x5f, 0x70, 0x0, 0x1, 0xed, 0x0, + 0x0, 0x8, 0xf5, 0x0, 0x0, 0x1f, 0xd0, 0x0, + 0x0, 0x7f, 0x70, 0x0, 0x0, 0xdf, 0x10, 0x0, + 0x2, 0xfc, 0x0, 0x0, 0x7, 0xf8, 0x0, 0x0, + 0xb, 0xf5, 0x0, 0x0, 0xd, 0xf3, 0x0, 0x0, + 0xf, 0xf2, 0x0, 0x0, 0xf, 0xf1, 0x0, 0x0, + 0xf, 0xf1, 0x0, 0x0, 0xe, 0xf2, 0x0, 0x0, + 0xb, 0xf3, 0x0, 0x0, 0x8, 0xf5, 0x0, 0x0, + 0x4, 0xf9, 0x0, 0x0, 0x0, 0xfd, 0x0, 0x0, + 0x0, 0xaf, 0x20, 0x0, 0x0, 0x4f, 0x80, 0x0, + 0x0, 0xd, 0xe0, 0x0, 0x0, 0x5, 0xf8, 0x0, + 0x0, 0x0, 0xbf, 0x20, 0x0, 0x0, 0x2f, 0xb0, + 0x0, 0x0, 0x5, 0xf7, + + /* U+0029 ")" */ + 0x8f, 0x40, 0x0, 0x0, 0xd, 0xe1, 0x0, 0x0, + 0x3, 0xfa, 0x0, 0x0, 0x0, 0xaf, 0x30, 0x0, + 0x0, 0x2f, 0xb0, 0x0, 0x0, 0xb, 0xf2, 0x0, + 0x0, 0x4, 0xf9, 0x0, 0x0, 0x0, 0xfe, 0x0, + 0x0, 0x0, 0xbf, 0x40, 0x0, 0x0, 0x7f, 0x80, + 0x0, 0x0, 0x5f, 0xb0, 0x0, 0x0, 0x3f, 0xd0, + 0x0, 0x0, 0x2f, 0xf0, 0x0, 0x0, 0x1f, 0xf0, + 0x0, 0x0, 0x2f, 0xf0, 0x0, 0x0, 0x2f, 0xd0, + 0x0, 0x0, 0x4f, 0xa0, 0x0, 0x0, 0x7f, 0x70, + 0x0, 0x0, 0xaf, 0x30, 0x0, 0x0, 0xee, 0x0, + 0x0, 0x3, 0xf9, 0x0, 0x0, 0xa, 0xf2, 0x0, + 0x0, 0x1f, 0xa0, 0x0, 0x0, 0x9f, 0x30, 0x0, + 0x2, 0xfa, 0x0, 0x0, 0xc, 0xe1, 0x0, 0x0, + 0x7f, 0x40, 0x0, 0x0, + + /* U+002A "*" */ + 0x0, 0x0, 0x4f, 0xf1, 0x0, 0x0, 0x0, 0x2, + 0xfe, 0x0, 0x0, 0x2, 0x0, 0xf, 0xb0, 0x0, + 0x10, 0xde, 0x70, 0xd9, 0x18, 0xe9, 0x1e, 0xff, + 0xfe, 0xdf, 0xff, 0xc0, 0x1, 0x37, 0xff, 0x52, + 0x0, 0x0, 0x2, 0xea, 0xdc, 0x0, 0x0, 0x2, + 0xef, 0x15, 0xfc, 0x0, 0x0, 0xdf, 0x80, 0xc, + 0xfa, 0x0, 0x2, 0xb1, 0x0, 0x4b, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+002B "+" */ + 0x0, 0x0, 0x0, 0xa, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf1, + 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf1, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0x0, 0x0, + + /* U+002D "-" */ + 0x1, 0x11, 0x11, 0x11, 0x11, 0x11, 0x5f, 0xff, + 0xff, 0xff, 0xff, 0xf9, 0x5f, 0xff, 0xff, 0xff, + 0xff, 0xf9, + + /* U+002E "." */ + 0x4, 0x43, 0x3f, 0xff, 0x3f, 0xff, 0x3f, 0xff, + + /* U+002F "/" */ + 0x0, 0x0, 0x0, 0xee, 0x0, 0x0, 0x0, 0x3f, + 0x90, 0x0, 0x0, 0x8, 0xf5, 0x0, 0x0, 0x0, + 0xcf, 0x0, 0x0, 0x0, 0x1f, 0xc0, 0x0, 0x0, + 0x5, 0xf7, 0x0, 0x0, 0x0, 0x9f, 0x30, 0x0, + 0x0, 0xe, 0xe0, 0x0, 0x0, 0x2, 0xfa, 0x0, + 0x0, 0x0, 0x7f, 0x60, 0x0, 0x0, 0xb, 0xf1, + 0x0, 0x0, 0x0, 0xfd, 0x0, 0x0, 0x0, 0x4f, + 0x80, 0x0, 0x0, 0x9, 0xf4, 0x0, 0x0, 0x0, + 0xdf, 0x0, 0x0, 0x0, 0x2f, 0xb0, 0x0, 0x0, + 0x6, 0xf7, 0x0, 0x0, 0x0, 0xaf, 0x20, 0x0, + 0x0, 0xf, 0xe0, 0x0, 0x0, 0x3, 0xf9, 0x0, + 0x0, 0x0, 0x8f, 0x50, 0x0, 0x0, 0xc, 0xf1, + 0x0, 0x0, 0x0, + + /* U+0030 "0" */ + 0x0, 0x0, 0x5c, 0xef, 0xd8, 0x10, 0x0, 0x0, + 0x0, 0xbf, 0xff, 0xff, 0xfe, 0x20, 0x0, 0x0, + 0xaf, 0xf6, 0x10, 0x3c, 0xfe, 0x10, 0x0, 0x4f, + 0xf3, 0x0, 0x0, 0xc, 0xfa, 0x0, 0xb, 0xf8, + 0x0, 0x0, 0x0, 0x2f, 0xf1, 0x1, 0xff, 0x10, + 0x0, 0x0, 0x0, 0xbf, 0x70, 0x4f, 0xc0, 0x0, + 0x0, 0x0, 0x6, 0xfb, 0x7, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0xd0, 0x9f, 0x70, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xa, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0xf, 0xf1, 0xbf, 0x50, 0x0, 0x0, 0x0, + 0x0, 0xef, 0x1a, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf1, 0x9f, 0x70, 0x0, 0x0, 0x0, 0x0, + 0xff, 0x7, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x3f, + 0xe0, 0x5f, 0xc0, 0x0, 0x0, 0x0, 0x6, 0xfb, + 0x1, 0xff, 0x10, 0x0, 0x0, 0x0, 0xbf, 0x70, + 0xb, 0xf8, 0x0, 0x0, 0x0, 0x2f, 0xf1, 0x0, + 0x4f, 0xf3, 0x0, 0x0, 0xc, 0xfa, 0x0, 0x0, + 0xaf, 0xe5, 0x0, 0x3c, 0xfe, 0x10, 0x0, 0x0, + 0xbf, 0xff, 0xff, 0xfe, 0x30, 0x0, 0x0, 0x0, + 0x5c, 0xef, 0xd8, 0x10, 0x0, 0x0, + + /* U+0031 "1" */ + 0x0, 0x1, 0x9f, 0xd0, 0x7, 0xff, 0xfd, 0x5d, + 0xff, 0xbf, 0xde, 0xfb, 0x24, 0xfd, 0xc4, 0x0, + 0x4f, 0xd0, 0x0, 0x4, 0xfd, 0x0, 0x0, 0x4f, + 0xd0, 0x0, 0x4, 0xfd, 0x0, 0x0, 0x4f, 0xd0, + 0x0, 0x4, 0xfd, 0x0, 0x0, 0x4f, 0xd0, 0x0, + 0x4, 0xfd, 0x0, 0x0, 0x4f, 0xd0, 0x0, 0x4, + 0xfd, 0x0, 0x0, 0x4f, 0xd0, 0x0, 0x4, 0xfd, + 0x0, 0x0, 0x4f, 0xd0, 0x0, 0x4, 0xfd, 0x0, + 0x0, 0x4f, 0xd0, 0x0, 0x4, 0xfd, 0x0, 0x0, + 0x4f, 0xd0, + + /* U+0032 "2" */ + 0x0, 0x3, 0xad, 0xff, 0xc7, 0x0, 0x0, 0x0, + 0x8f, 0xff, 0xff, 0xff, 0xd2, 0x0, 0x7, 0xff, + 0x93, 0x12, 0x5d, 0xfe, 0x0, 0x1f, 0xf5, 0x0, + 0x0, 0x0, 0xdf, 0x70, 0x6f, 0xc0, 0x0, 0x0, + 0x0, 0x5f, 0xc0, 0x8f, 0x80, 0x0, 0x0, 0x0, + 0x1f, 0xe0, 0x12, 0x10, 0x0, 0x0, 0x0, 0x2f, + 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xb0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xef, 0x40, 0x0, + 0x0, 0x0, 0x0, 0xa, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x6, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0xf4, 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0x50, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xef, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x1e, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xdf, 0xc0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xfd, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf4, 0x9f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf4, + + /* U+0033 "3" */ + 0x0, 0x1, 0x8d, 0xff, 0xd9, 0x20, 0x0, 0x0, + 0x7f, 0xff, 0xff, 0xff, 0xf6, 0x0, 0x6, 0xff, + 0x72, 0x0, 0x17, 0xef, 0x50, 0xe, 0xf4, 0x0, + 0x0, 0x0, 0x3f, 0xe0, 0x5, 0x50, 0x0, 0x0, + 0x0, 0xd, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xe, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x28, 0xff, 0xa0, + 0x0, 0x0, 0x3f, 0xff, 0xff, 0xfd, 0x10, 0x0, + 0x0, 0x3f, 0xff, 0xff, 0xb1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4c, 0xf9, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xe, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xfa, 0x1, 0x0, 0x0, 0x0, 0x0, 0x7, 0xfa, + 0x6f, 0x60, 0x0, 0x0, 0x0, 0xb, 0xf7, 0x6f, + 0xf4, 0x0, 0x0, 0x0, 0x4f, 0xf2, 0xb, 0xff, + 0x82, 0x0, 0x17, 0xff, 0x80, 0x0, 0xaf, 0xff, + 0xff, 0xff, 0xf9, 0x0, 0x0, 0x3, 0x9d, 0xff, + 0xd9, 0x30, 0x0, + + /* U+0034 "4" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xff, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1e, 0xff, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xfd, 0xcf, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x1e, 0xf4, 0xbf, 0x50, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0x90, 0xbf, 0x50, 0x0, + 0x0, 0x0, 0x6, 0xfd, 0x0, 0xbf, 0x50, 0x0, + 0x0, 0x0, 0x2f, 0xf3, 0x0, 0xbf, 0x50, 0x0, + 0x0, 0x0, 0xbf, 0x80, 0x0, 0xbf, 0x50, 0x0, + 0x0, 0x6, 0xfd, 0x0, 0x0, 0xbf, 0x50, 0x0, + 0x0, 0x2f, 0xf3, 0x0, 0x0, 0xbf, 0x50, 0x0, + 0x0, 0xcf, 0x80, 0x0, 0x0, 0xbf, 0x50, 0x0, + 0x7, 0xfd, 0x0, 0x0, 0x0, 0xbf, 0x50, 0x0, + 0x2f, 0xf3, 0x0, 0x0, 0x0, 0xbf, 0x50, 0x0, + 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0x50, 0x0, + + /* U+0035 "5" */ + 0x0, 0xef, 0xff, 0xff, 0xff, 0xff, 0xa0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, 0x2, 0xfe, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x7, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xf7, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xf5, 0x6b, 0xee, 0xb6, 0x0, 0x0, + 0xc, 0xfe, 0xff, 0xff, 0xff, 0xd2, 0x0, 0xe, + 0xff, 0x83, 0x0, 0x4c, 0xfe, 0x10, 0xf, 0xf3, + 0x0, 0x0, 0x0, 0xcf, 0x90, 0x3, 0x20, 0x0, + 0x0, 0x0, 0x2f, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xd, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xa, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf4, + 0x1, 0x10, 0x0, 0x0, 0x0, 0x2f, 0xf0, 0x3e, + 0xb0, 0x0, 0x0, 0x0, 0xcf, 0x90, 0xd, 0xfd, + 0x50, 0x0, 0x4c, 0xfe, 0x10, 0x2, 0xcf, 0xff, + 0xff, 0xff, 0xd2, 0x0, 0x0, 0x5, 0xbe, 0xfe, + 0xb6, 0x0, 0x0, + + /* U+0036 "6" */ + 0x0, 0x0, 0x5b, 0xef, 0xeb, 0x50, 0x0, 0x0, + 0xb, 0xff, 0xff, 0xff, 0xfb, 0x0, 0x0, 0xaf, + 0xe5, 0x0, 0x16, 0xef, 0xc0, 0x3, 0xfe, 0x10, + 0x0, 0x0, 0x1d, 0xf5, 0xa, 0xf6, 0x0, 0x0, + 0x0, 0x3, 0x61, 0xe, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xb0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5f, 0x80, 0x4a, 0xde, 0xc7, 0x10, 0x0, + 0x7f, 0x79, 0xff, 0xff, 0xff, 0xe4, 0x0, 0x9f, + 0xdf, 0xd5, 0x10, 0x3a, 0xff, 0x30, 0x9f, 0xfb, + 0x0, 0x0, 0x0, 0x8f, 0xd0, 0xaf, 0xf1, 0x0, + 0x0, 0x0, 0xd, 0xf4, 0xaf, 0xa0, 0x0, 0x0, + 0x0, 0x8, 0xf8, 0x9f, 0x80, 0x0, 0x0, 0x0, + 0x5, 0xfa, 0x8f, 0x70, 0x0, 0x0, 0x0, 0x5, + 0xfb, 0x6f, 0xa0, 0x0, 0x0, 0x0, 0x7, 0xf9, + 0x2f, 0xe0, 0x0, 0x0, 0x0, 0xc, 0xf5, 0xc, + 0xf9, 0x0, 0x0, 0x0, 0x6f, 0xe0, 0x3, 0xff, + 0xa2, 0x0, 0x29, 0xff, 0x50, 0x0, 0x4f, 0xff, + 0xff, 0xff, 0xf6, 0x0, 0x0, 0x1, 0x8d, 0xff, + 0xd9, 0x20, 0x0, + + /* U+0037 "7" */ + 0x6f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x5f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xdf, 0x50, 0x0, 0x0, + 0x0, 0x0, 0x4, 0xfe, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xb, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2f, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x6, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xd, 0xf5, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xe0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xbf, 0x80, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, 0x9, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf3, 0x0, + 0x0, 0x0, 0x0, + + /* U+0038 "8" */ + 0x0, 0x1, 0x8d, 0xff, 0xda, 0x30, 0x0, 0x0, + 0x5, 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0x2, + 0xff, 0xb3, 0x0, 0x18, 0xff, 0x70, 0x0, 0xaf, + 0xa0, 0x0, 0x0, 0x6, 0xfe, 0x0, 0xd, 0xf3, + 0x0, 0x0, 0x0, 0xf, 0xf2, 0x0, 0xcf, 0x40, + 0x0, 0x0, 0x0, 0xff, 0x10, 0x7, 0xfa, 0x0, + 0x0, 0x0, 0x7f, 0xc0, 0x0, 0xd, 0xfa, 0x20, + 0x1, 0x8f, 0xf3, 0x0, 0x0, 0x1a, 0xff, 0xff, + 0xff, 0xd3, 0x0, 0x0, 0x3, 0xcf, 0xff, 0xff, + 0xfe, 0x50, 0x0, 0x3, 0xff, 0xa3, 0x0, 0x28, + 0xff, 0x70, 0x0, 0xef, 0x70, 0x0, 0x0, 0x3, + 0xff, 0x30, 0x6f, 0xb0, 0x0, 0x0, 0x0, 0x7, + 0xfb, 0xb, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x1f, + 0xf0, 0xcf, 0x40, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x1c, 0xf5, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf0, + 0x8f, 0x90, 0x0, 0x0, 0x0, 0x5, 0xfc, 0x3, + 0xff, 0x40, 0x0, 0x0, 0x1, 0xef, 0x60, 0x9, + 0xff, 0x82, 0x0, 0x16, 0xef, 0xc0, 0x0, 0x9, + 0xff, 0xff, 0xff, 0xff, 0xb1, 0x0, 0x0, 0x3, + 0x9d, 0xff, 0xea, 0x40, 0x0, 0x0, + + /* U+0039 "9" */ + 0x0, 0x1, 0x8c, 0xff, 0xd8, 0x10, 0x0, 0x0, + 0x4f, 0xff, 0xff, 0xff, 0xe3, 0x0, 0x3, 0xff, + 0xa3, 0x0, 0x2a, 0xff, 0x20, 0xd, 0xf8, 0x0, + 0x0, 0x0, 0x9f, 0xb0, 0x4f, 0xe0, 0x0, 0x0, + 0x0, 0x1e, 0xf1, 0x8f, 0x90, 0x0, 0x0, 0x0, + 0xa, 0xf6, 0x9f, 0x70, 0x0, 0x0, 0x0, 0x8, + 0xf9, 0x8f, 0x80, 0x0, 0x0, 0x0, 0xa, 0xfa, + 0x5f, 0xc0, 0x0, 0x0, 0x0, 0xe, 0xfb, 0xe, + 0xf5, 0x0, 0x0, 0x0, 0x9f, 0xfb, 0x6, 0xff, + 0x71, 0x0, 0x3a, 0xff, 0xfa, 0x0, 0x8f, 0xff, + 0xff, 0xff, 0xc7, 0xf9, 0x0, 0x3, 0xae, 0xfe, + 0xc6, 0x8, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, + 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xf1, + 0x2a, 0x40, 0x0, 0x0, 0x0, 0x8f, 0xd0, 0x5f, + 0xd1, 0x0, 0x0, 0x3, 0xff, 0x60, 0xb, 0xfe, + 0x61, 0x0, 0x6e, 0xfc, 0x0, 0x0, 0xbf, 0xff, + 0xff, 0xff, 0xd2, 0x0, 0x0, 0x4, 0xbd, 0xfe, + 0xc7, 0x0, 0x0, + + /* U+003A ":" */ + 0x5f, 0xfe, 0x5f, 0xfe, 0x5f, 0xfe, 0x14, 0x43, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x13, 0x33, 0x5f, 0xfe, 0x5f, 0xfe, 0x5f, 0xfe, + + /* U+003B ";" */ + 0x5f, 0xfe, 0x5f, 0xfe, 0x5f, 0xfe, 0x14, 0x43, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x13, 0x33, 0x4f, 0xfe, 0x4f, 0xfe, 0x4f, 0xfe, + 0x0, 0x9d, 0x0, 0xca, 0x1, 0xf5, 0xb, 0xc0, + 0x3d, 0x20, 0x0, 0x0, + + /* U+003C "<" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0xd0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xaf, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x5e, 0xff, 0xa1, 0x0, + 0x0, 0x0, 0x0, 0x2b, 0xff, 0xc3, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xd5, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xef, 0xe7, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xcf, 0xf9, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xfb, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xd2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2d, 0xff, 0x91, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6e, 0xfe, 0x60, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0x9f, 0xfd, 0x40, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3, 0xcf, 0xfb, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xef, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x19, 0xff, 0xe6, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3c, 0xff, 0xd0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6e, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x90, + + /* U+003D "=" */ + 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x95, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf9, 0x5f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xa0, + + /* U+003E ">" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, + 0xb2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xaf, + 0xfe, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3c, + 0xff, 0xb2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, + 0xef, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xfe, 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x19, 0xff, 0xc3, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xbf, 0xf9, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4d, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5f, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xbf, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x19, 0xff, + 0xd3, 0x0, 0x0, 0x0, 0x0, 0x7e, 0xff, 0x70, + 0x0, 0x0, 0x0, 0x4, 0xdf, 0xfa, 0x10, 0x0, + 0x0, 0x0, 0x2b, 0xff, 0xd3, 0x0, 0x0, 0x0, + 0x1, 0x9f, 0xff, 0x60, 0x0, 0x0, 0x0, 0x3, + 0xef, 0xfa, 0x10, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0xd3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+003F "?" */ + 0x0, 0x0, 0x6b, 0xef, 0xeb, 0x50, 0x0, 0x0, + 0x3, 0xdf, 0xff, 0xdf, 0xff, 0xc1, 0x0, 0x3, + 0xff, 0xc3, 0x0, 0x6, 0xef, 0xd0, 0x0, 0xdf, + 0xb0, 0x0, 0x0, 0x3, 0xff, 0x60, 0x5f, 0xf1, + 0x0, 0x0, 0x0, 0xb, 0xfb, 0x7, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x8f, 0xd0, 0x0, 0x10, 0x0, + 0x0, 0x0, 0x9, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x7f, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xf5, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xe3, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xd, 0xf5, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0x76, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5b, 0xb1, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8f, 0xf2, 0x0, 0x0, 0x0, + + /* U+0040 "@" */ + 0x0, 0x0, 0x0, 0x0, 0x15, 0xac, 0xff, 0xec, + 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xaf, 0xff, 0xec, 0xcd, 0xff, 0xfd, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xff, 0xc7, 0x20, 0x0, + 0x0, 0x4a, 0xff, 0x90, 0x0, 0x0, 0x0, 0x9, + 0xfd, 0x40, 0x0, 0x0, 0x0, 0x0, 0x3, 0xdf, + 0x90, 0x0, 0x0, 0x7, 0xfb, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0xdf, 0x50, 0x0, 0x3, + 0xfd, 0x0, 0x0, 0x6, 0xcf, 0xe9, 0x1f, 0xc0, + 0x3, 0xfe, 0x0, 0x0, 0xcf, 0x20, 0x0, 0x2d, + 0xfe, 0xbc, 0xfb, 0xf9, 0x0, 0xb, 0xf5, 0x0, + 0x4f, 0x90, 0x0, 0x1e, 0xf7, 0x0, 0x6, 0xff, + 0x70, 0x0, 0x5f, 0xa0, 0xa, 0xf3, 0x0, 0xa, + 0xf8, 0x0, 0x0, 0xd, 0xf5, 0x0, 0x1, 0xfd, + 0x0, 0xee, 0x0, 0x1, 0xfe, 0x0, 0x0, 0x0, + 0xaf, 0x30, 0x0, 0xe, 0xf0, 0x2f, 0xc0, 0x0, + 0x6f, 0x90, 0x0, 0x0, 0xb, 0xf1, 0x0, 0x0, + 0xdf, 0x4, 0xf9, 0x0, 0xa, 0xf6, 0x0, 0x0, + 0x0, 0xef, 0x0, 0x0, 0xf, 0xd0, 0x5f, 0x90, + 0x0, 0xcf, 0x40, 0x0, 0x0, 0x2f, 0xd0, 0x0, + 0x1, 0xfa, 0x4, 0xfb, 0x0, 0xb, 0xf3, 0x0, + 0x0, 0x8, 0xfb, 0x0, 0x0, 0x6f, 0x50, 0x2f, + 0xd0, 0x0, 0x9f, 0x50, 0x0, 0x2, 0xef, 0xa0, + 0x0, 0xd, 0xe0, 0x0, 0xef, 0x10, 0x3, 0xfb, + 0x0, 0x2, 0xd6, 0xfc, 0x0, 0x9, 0xf5, 0x0, + 0x9, 0xf6, 0x0, 0x9, 0xfd, 0x8a, 0xfb, 0xb, + 0xfb, 0x9d, 0xf7, 0x0, 0x0, 0x3f, 0xd0, 0x0, + 0x6, 0xdf, 0xd7, 0x0, 0x1b, 0xee, 0xa3, 0x0, + 0x0, 0x0, 0xbf, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xef, + 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x70, 0x0, 0x0, 0x3, 0xff, 0x81, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xdf, 0x40, 0x0, 0x0, + 0x2, 0xdf, 0xf9, 0x52, 0x10, 0x1, 0x36, 0x9e, + 0xfb, 0x20, 0x0, 0x0, 0x0, 0x0, 0x6d, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x92, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0x68, 0x9a, 0x98, 0x62, + 0x0, 0x0, 0x0, 0x0, + + /* U+0041 "A" */ + 0x0, 0x0, 0x0, 0x0, 0x9f, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xf9, 0xef, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xf3, 0x8f, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0xc0, 0x1f, 0xe0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0x60, 0xb, + 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x0, 0x4, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6, 0xf9, 0x0, 0x0, 0xdf, 0x20, 0x0, 0x0, + 0x0, 0x0, 0xd, 0xf3, 0x0, 0x0, 0x7f, 0x90, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xd0, 0x0, 0x0, + 0x1f, 0xf0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x60, + 0x0, 0x0, 0xa, 0xf6, 0x0, 0x0, 0x0, 0x1, + 0xff, 0x10, 0x0, 0x0, 0x3, 0xfd, 0x0, 0x0, + 0x0, 0x7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x40, 0x0, 0x0, 0xd, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xa0, 0x0, 0x0, 0x4f, 0xd0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xf1, 0x0, 0x0, 0xbf, + 0x70, 0x0, 0x0, 0x0, 0x0, 0xb, 0xf8, 0x0, + 0x1, 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, 0x5, + 0xfe, 0x0, 0x8, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xef, 0x50, 0xe, 0xf5, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x9f, 0xc0, 0x5f, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xf2, + 0xbf, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xd, 0xf9, + + /* U+0042 "B" */ + 0xcf, 0xff, 0xff, 0xff, 0xfd, 0xa5, 0x0, 0x0, + 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x20, + 0x0, 0xcf, 0x61, 0x11, 0x11, 0x13, 0x7e, 0xfe, + 0x10, 0xc, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x1d, + 0xfa, 0x0, 0xcf, 0x60, 0x0, 0x0, 0x0, 0x0, + 0x6f, 0xf0, 0xc, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0x5, 0xff, 0x0, 0xcf, 0x60, 0x0, 0x0, 0x0, + 0x0, 0x9f, 0xc0, 0xc, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xf4, 0x0, 0xcf, 0x72, 0x22, 0x22, + 0x35, 0x9f, 0xf6, 0x0, 0xc, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x91, 0x0, 0x0, 0xcf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xc4, 0x0, 0xc, 0xf6, 0x0, + 0x0, 0x0, 0x14, 0x9f, 0xf7, 0x0, 0xcf, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x5f, 0xf3, 0xc, 0xf6, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xa0, 0xcf, + 0x60, 0x0, 0x0, 0x0, 0x0, 0x6, 0xfe, 0xc, + 0xf6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xf0, + 0xcf, 0x60, 0x0, 0x0, 0x0, 0x0, 0xa, 0xfc, + 0xc, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x3, 0xff, + 0x60, 0xcf, 0x60, 0x0, 0x0, 0x0, 0x17, 0xef, + 0xc0, 0xc, 0xff, 0xee, 0xee, 0xee, 0xff, 0xff, + 0xb0, 0x0, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xea, + 0x40, 0x0, 0x0, + + /* U+0043 "C" */ + 0x0, 0x0, 0x0, 0x49, 0xde, 0xfe, 0xb6, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2b, 0xff, 0xff, 0xef, + 0xff, 0xe5, 0x0, 0x0, 0x0, 0x2, 0xef, 0xf9, + 0x20, 0x0, 0x6e, 0xff, 0x70, 0x0, 0x0, 0x1e, + 0xfe, 0x20, 0x0, 0x0, 0x1, 0xdf, 0xf5, 0x0, + 0x0, 0xaf, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x1e, + 0xfe, 0x10, 0x2, 0xff, 0x60, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xff, 0x80, 0x8, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x85, 0x10, 0xd, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1f, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xf2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5f, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x68, 0x30, 0x9, 0xfd, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0xf0, + 0x3, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0x4, + 0xff, 0x90, 0x0, 0xbf, 0xe1, 0x0, 0x0, 0x0, + 0x0, 0xd, 0xff, 0x20, 0x0, 0x1e, 0xfd, 0x20, + 0x0, 0x0, 0x0, 0xbf, 0xf7, 0x0, 0x0, 0x2, + 0xef, 0xf9, 0x30, 0x2, 0x6e, 0xff, 0xa0, 0x0, + 0x0, 0x0, 0x1a, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x27, 0xbe, 0xfe, + 0xb7, 0x10, 0x0, 0x0, + + /* U+0044 "D" */ + 0xbf, 0xff, 0xff, 0xff, 0xfd, 0xa6, 0x10, 0x0, + 0x0, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0x0, 0x0, 0xbf, 0x90, 0x0, 0x0, 0x12, 0x6c, + 0xff, 0xb0, 0x0, 0xbf, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x5f, 0xf9, 0x0, 0xbf, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x4, 0xff, 0x40, 0xbf, 0x90, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0xc0, 0xbf, 0x90, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xf2, 0xbf, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0xf6, + 0xbf, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xf9, 0xbf, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9, 0xfb, 0xbf, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xfc, 0xbf, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x9, 0xfb, 0xbf, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xa, 0xf9, 0xbf, 0x90, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xd, 0xf6, 0xbf, 0x90, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xf3, 0xbf, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xd0, + 0xbf, 0x90, 0x0, 0x0, 0x0, 0x0, 0x3, 0xff, + 0x50, 0xbf, 0x90, 0x0, 0x0, 0x0, 0x0, 0x4f, + 0xfb, 0x0, 0xbf, 0x90, 0x0, 0x0, 0x2, 0x5b, + 0xff, 0xc1, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x0, 0xbf, 0xff, 0xff, 0xff, + 0xed, 0xb6, 0x10, 0x0, 0x0, + + /* U+0045 "E" */ + 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x80, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xfa, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0xa0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xa, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfb, 0x0, 0xaf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xb0, 0xa, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xa, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf1, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x10, + + /* U+0046 "F" */ + 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb9, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, 0x9f, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xa0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x9, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x9f, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x10, 0x9f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf1, 0x9, 0xfa, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x9, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, + 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+0047 "G" */ + 0x0, 0x0, 0x0, 0x38, 0xce, 0xff, 0xda, 0x50, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xaf, 0xff, 0xfd, + 0xef, 0xff, 0xe5, 0x0, 0x0, 0x0, 0x2, 0xdf, + 0xfb, 0x40, 0x0, 0x17, 0xef, 0xf8, 0x0, 0x0, + 0x0, 0xdf, 0xf5, 0x0, 0x0, 0x0, 0x1, 0xcf, + 0xf7, 0x0, 0x0, 0x8f, 0xf5, 0x0, 0x0, 0x0, + 0x0, 0x1, 0xdf, 0xf2, 0x0, 0x1f, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xff, 0x90, 0x7, + 0xff, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, + 0xa5, 0x0, 0xcf, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xff, + 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4, 0xff, 0x10, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x2f, 0xf2, + 0x0, 0x0, 0x0, 0xe, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2f, 0xf0, 0xc, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0xff, 0x0, 0x7f, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xf0, + 0x0, 0xef, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xff, 0x0, 0x6, 0xff, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xf0, 0x0, 0xa, 0xff, + 0x50, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xfe, 0x0, + 0x0, 0x9, 0xff, 0xc5, 0x10, 0x0, 0x26, 0xcf, + 0xfd, 0x20, 0x0, 0x0, 0x5, 0xdf, 0xff, 0xfe, + 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x49, 0xce, 0xfe, 0xc9, 0x51, 0x0, 0x0, + + /* U+0048 "H" */ + 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, + 0xea, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xfe, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6f, 0xea, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6, 0xfe, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6f, 0xea, 0xfa, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xfe, 0xaf, 0xa0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0xea, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6, 0xfe, 0xaf, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6f, 0xea, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, 0xaf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xea, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6, 0xfe, 0xaf, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xea, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xfe, 0xaf, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xea, + 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xfe, + 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, + 0xea, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xfe, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6f, 0xea, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6, 0xfe, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6f, 0xe0, + + /* U+0049 "I" */ + 0x3f, 0xf1, 0x3f, 0xf1, 0x3f, 0xf1, 0x3f, 0xf1, + 0x3f, 0xf1, 0x3f, 0xf1, 0x3f, 0xf1, 0x3f, 0xf1, + 0x3f, 0xf1, 0x3f, 0xf1, 0x3f, 0xf1, 0x3f, 0xf1, + 0x3f, 0xf1, 0x3f, 0xf1, 0x3f, 0xf1, 0x3f, 0xf1, + 0x3f, 0xf1, 0x3f, 0xf1, 0x3f, 0xf1, 0x3f, 0xf1, + 0x3f, 0xf1, + + /* U+004A "J" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x70, 0x0, + 0x0, 0x0, 0x0, 0xd, 0xf7, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, + 0xd, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, + 0x70, 0x0, 0x0, 0x0, 0x0, 0xd, 0xf7, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xdf, 0x70, 0x0, 0x0, + 0x0, 0x0, 0xd, 0xf7, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, 0xd, + 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x70, + 0x0, 0x0, 0x0, 0x0, 0xd, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, + 0x0, 0xd, 0xf7, 0x3, 0x60, 0x0, 0x0, 0x0, + 0xdf, 0x71, 0xff, 0x20, 0x0, 0x0, 0xe, 0xf6, + 0xe, 0xf6, 0x0, 0x0, 0x1, 0xff, 0x40, 0xaf, + 0xd0, 0x0, 0x0, 0x7f, 0xf1, 0x3, 0xff, 0xc4, + 0x23, 0x8f, 0xf9, 0x0, 0x7, 0xff, 0xff, 0xff, + 0xfc, 0x0, 0x0, 0x4, 0xbe, 0xfe, 0xc6, 0x0, + 0x0, + + /* U+004B "K" */ + 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, + 0x80, 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0xf8, 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, 0xa, + 0xff, 0x70, 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, + 0xaf, 0xf7, 0x0, 0x0, 0xdf, 0x70, 0x0, 0x0, + 0xa, 0xff, 0x70, 0x0, 0x0, 0xdf, 0x70, 0x0, + 0x0, 0xaf, 0xf6, 0x0, 0x0, 0x0, 0xdf, 0x70, + 0x0, 0xa, 0xff, 0x60, 0x0, 0x0, 0x0, 0xdf, + 0x70, 0x0, 0xaf, 0xf5, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0x70, 0x9, 0xff, 0x60, 0x0, 0x0, 0x0, + 0x0, 0xdf, 0x70, 0x9f, 0xff, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0x79, 0xff, 0x5c, 0xf9, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0xef, 0xf4, 0x2, 0xff, + 0x50, 0x0, 0x0, 0x0, 0xdf, 0xff, 0x40, 0x0, + 0x7f, 0xf2, 0x0, 0x0, 0x0, 0xdf, 0xf4, 0x0, + 0x0, 0xb, 0xfc, 0x0, 0x0, 0x0, 0xdf, 0x70, + 0x0, 0x0, 0x1, 0xff, 0x90, 0x0, 0x0, 0xdf, + 0x70, 0x0, 0x0, 0x0, 0x6f, 0xf5, 0x0, 0x0, + 0xdf, 0x70, 0x0, 0x0, 0x0, 0xb, 0xff, 0x20, + 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, 0x1, 0xef, + 0xd0, 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x5f, 0xfa, 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xff, 0x60, 0xdf, 0x70, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xef, 0xf2, + + /* U+004C "L" */ + 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, + 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x70, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x70, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xdf, 0x70, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, + 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x70, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x70, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xdf, 0x70, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, + 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x70, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf6, + + /* U+004D "M" */ + 0xcf, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xb, 0xff, 0x8c, 0xff, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xff, 0xf8, 0xcf, 0xff, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0x8c, + 0xfc, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, + 0xfc, 0xf8, 0xcf, 0x6f, 0xf1, 0x0, 0x0, 0x0, + 0x0, 0x4, 0xfb, 0xaf, 0x8c, 0xf6, 0x9f, 0x70, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0x5a, 0xf8, 0xcf, + 0x62, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xe0, + 0xaf, 0x8c, 0xf6, 0xc, 0xf4, 0x0, 0x0, 0x0, + 0x7, 0xf8, 0xa, 0xf8, 0xcf, 0x60, 0x5f, 0xa0, + 0x0, 0x0, 0x0, 0xef, 0x20, 0xaf, 0x8c, 0xf6, + 0x0, 0xef, 0x10, 0x0, 0x0, 0x4f, 0xb0, 0xa, + 0xf8, 0xcf, 0x60, 0x8, 0xf7, 0x0, 0x0, 0xa, + 0xf5, 0x0, 0xaf, 0x8c, 0xf6, 0x0, 0x2f, 0xd0, + 0x0, 0x1, 0xfe, 0x0, 0xa, 0xf8, 0xcf, 0x60, + 0x0, 0xbf, 0x40, 0x0, 0x7f, 0x80, 0x0, 0xaf, + 0x8c, 0xf6, 0x0, 0x5, 0xfa, 0x0, 0xd, 0xf2, + 0x0, 0xa, 0xf8, 0xcf, 0x60, 0x0, 0xe, 0xf1, + 0x3, 0xfb, 0x0, 0x0, 0xaf, 0x8c, 0xf6, 0x0, + 0x0, 0x8f, 0x70, 0xaf, 0x50, 0x0, 0xa, 0xf8, + 0xcf, 0x60, 0x0, 0x2, 0xfd, 0x1f, 0xe0, 0x0, + 0x0, 0xaf, 0x8c, 0xf6, 0x0, 0x0, 0xb, 0xfb, + 0xf8, 0x0, 0x0, 0xa, 0xf8, 0xcf, 0x60, 0x0, + 0x0, 0x5f, 0xff, 0x20, 0x0, 0x0, 0xaf, 0x8c, + 0xf6, 0x0, 0x0, 0x0, 0xef, 0xb0, 0x0, 0x0, + 0xa, 0xf8, 0xcf, 0x60, 0x0, 0x0, 0x8, 0xf5, + 0x0, 0x0, 0x0, 0xaf, 0x80, + + /* U+004E "N" */ + 0xcf, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, + 0xec, 0xff, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xfe, 0xcf, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x6f, 0xec, 0xf8, 0xef, 0x30, 0x0, 0x0, 0x0, + 0x6, 0xfe, 0xcf, 0x75, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0x6f, 0xec, 0xf7, 0xb, 0xf7, 0x0, 0x0, + 0x0, 0x6, 0xfe, 0xcf, 0x70, 0x1f, 0xf2, 0x0, + 0x0, 0x0, 0x6f, 0xec, 0xf7, 0x0, 0x6f, 0xc0, + 0x0, 0x0, 0x6, 0xfe, 0xcf, 0x70, 0x0, 0xcf, + 0x60, 0x0, 0x0, 0x6f, 0xec, 0xf7, 0x0, 0x2, + 0xff, 0x10, 0x0, 0x6, 0xfe, 0xcf, 0x70, 0x0, + 0x7, 0xfb, 0x0, 0x0, 0x6f, 0xec, 0xf7, 0x0, + 0x0, 0xc, 0xf5, 0x0, 0x6, 0xfe, 0xcf, 0x70, + 0x0, 0x0, 0x3f, 0xe1, 0x0, 0x6f, 0xec, 0xf7, + 0x0, 0x0, 0x0, 0x8f, 0xa0, 0x6, 0xfe, 0xcf, + 0x70, 0x0, 0x0, 0x0, 0xdf, 0x40, 0x6f, 0xec, + 0xf7, 0x0, 0x0, 0x0, 0x4, 0xfe, 0x6, 0xfe, + 0xcf, 0x70, 0x0, 0x0, 0x0, 0x9, 0xf9, 0x6f, + 0xec, 0xf7, 0x0, 0x0, 0x0, 0x0, 0xe, 0xf9, + 0xfe, 0xcf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0xff, 0xec, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xaf, 0xfe, 0xcf, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x1, 0xef, 0xe0, + + /* U+004F "O" */ + 0x0, 0x0, 0x0, 0x28, 0xce, 0xfe, 0xda, 0x50, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xaf, 0xff, 0xff, + 0xff, 0xff, 0xd4, 0x0, 0x0, 0x0, 0x2, 0xef, + 0xfc, 0x62, 0x1, 0x5b, 0xff, 0xf6, 0x0, 0x0, + 0x1, 0xef, 0xf5, 0x0, 0x0, 0x0, 0x4, 0xef, + 0xf4, 0x0, 0x0, 0xbf, 0xf3, 0x0, 0x0, 0x0, + 0x0, 0x2, 0xef, 0xe0, 0x0, 0x4f, 0xf7, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xff, 0x70, 0xb, + 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, + 0xfe, 0x0, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0xf2, 0x3f, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xff, 0x66, 0xff, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xf9, 0x7f, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0xb7, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xd, 0xfb, 0x6f, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, + 0x93, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1f, 0xf7, 0xf, 0xf7, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4, 0xff, 0x40, 0xbf, 0xd0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xf0, + 0x5, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1f, 0xf9, 0x0, 0xd, 0xfe, 0x20, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xff, 0x20, 0x0, 0x3f, 0xfe, + 0x40, 0x0, 0x0, 0x0, 0x1b, 0xff, 0x70, 0x0, + 0x0, 0x5f, 0xff, 0xb5, 0x20, 0x13, 0x8e, 0xff, + 0x90, 0x0, 0x0, 0x0, 0x4d, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x60, 0x0, 0x0, 0x0, 0x0, 0x5, + 0x9d, 0xef, 0xed, 0xa6, 0x0, 0x0, 0x0, + + /* U+0050 "P" */ + 0xaf, 0xff, 0xff, 0xff, 0xff, 0xec, 0x71, 0x0, + 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe4, + 0x0, 0xaf, 0x90, 0x0, 0x0, 0x0, 0x26, 0xdf, + 0xf2, 0xa, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0xb0, 0xaf, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xff, 0x2a, 0xf9, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xf, 0xf5, 0xaf, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0x5a, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5f, 0xf2, 0xaf, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x1d, 0xfc, 0xa, 0xf9, 0x0, 0x0, + 0x0, 0x2, 0x6e, 0xff, 0x30, 0xaf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x50, 0xa, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xc8, 0x10, 0x0, 0xaf, 0x90, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xaf, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xa, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xaf, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+0051 "Q" */ + 0x0, 0x0, 0x0, 0x49, 0xde, 0xfe, 0xd9, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xcf, 0xff, 0xfd, + 0xff, 0xff, 0xb2, 0x0, 0x0, 0x0, 0x5, 0xff, + 0xf8, 0x20, 0x0, 0x4a, 0xff, 0xe3, 0x0, 0x0, + 0x3, 0xff, 0xd2, 0x0, 0x0, 0x0, 0x4, 0xff, + 0xe1, 0x0, 0x0, 0xdf, 0xd1, 0x0, 0x0, 0x0, + 0x0, 0x3, 0xff, 0xa0, 0x0, 0x6f, 0xf3, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0x20, 0xd, + 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, + 0xf9, 0x2, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0xe0, 0x6f, 0xf1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6, 0xff, 0x28, 0xfe, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, + 0xf5, 0xaf, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0xff, 0x7b, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xf8, 0xaf, 0xd0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xff, + 0x68, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xf4, 0x4f, 0xf4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x7, 0xff, 0x0, 0xff, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xc0, + 0x9, 0xff, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xf6, 0x0, 0x2f, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xd, 0xfd, 0x0, 0x0, 0x6f, 0xfc, + 0x20, 0x0, 0x0, 0x0, 0x1c, 0xff, 0x30, 0x0, + 0x0, 0x8f, 0xff, 0x94, 0x10, 0x14, 0x8f, 0xff, + 0x60, 0x0, 0x0, 0x0, 0x6e, 0xff, 0xff, 0xff, + 0xff, 0xfd, 0x40, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xad, 0xff, 0xff, 0xd6, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xfd, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1d, + 0xfd, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xfd, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xfd, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xfc, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x65, 0x10, 0x0, + + /* U+0052 "R" */ + 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xb6, 0x0, + 0x0, 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0x30, 0x0, 0xaf, 0xa0, 0x0, 0x0, 0x0, + 0x1, 0x5d, 0xff, 0x20, 0xa, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xfb, 0x0, 0xaf, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf0, 0xa, + 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0xff, + 0x20, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5f, 0xf1, 0xa, 0xfa, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1d, 0xfd, 0x0, 0xaf, 0xa0, 0x0, 0x0, + 0x0, 0x2, 0x6e, 0xff, 0x50, 0xa, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0xaf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xea, 0x40, 0x0, + 0xa, 0xfa, 0x0, 0x0, 0x5, 0xff, 0x40, 0x0, + 0x0, 0x0, 0xaf, 0xa0, 0x0, 0x0, 0x9, 0xfe, + 0x10, 0x0, 0x0, 0xa, 0xfa, 0x0, 0x0, 0x0, + 0xd, 0xfc, 0x0, 0x0, 0x0, 0xaf, 0xa0, 0x0, + 0x0, 0x0, 0x2f, 0xf9, 0x0, 0x0, 0xa, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x6f, 0xf6, 0x0, 0x0, + 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xf3, + 0x0, 0xa, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0xe1, 0x0, 0xaf, 0xa0, 0x0, 0x0, 0x0, + 0x0, 0x3, 0xff, 0xc0, 0xa, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xff, 0x90, 0xaf, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, 0x60, + + /* U+0053 "S" */ + 0x0, 0x0, 0x4a, 0xdf, 0xff, 0xda, 0x40, 0x0, + 0x0, 0x0, 0x1c, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0x20, 0x0, 0x0, 0xdf, 0xf8, 0x30, 0x0, 0x39, + 0xff, 0xe2, 0x0, 0x6, 0xff, 0x30, 0x0, 0x0, + 0x0, 0x4f, 0xfc, 0x0, 0xb, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0x30, 0xd, 0xf8, 0x0, + 0x0, 0x0, 0x0, 0x1, 0xfb, 0x40, 0xc, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, + 0xff, 0xb1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xa5, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4, 0xcf, 0xff, 0xfe, 0xa6, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x2, 0x7b, 0xff, 0xff, + 0xfa, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0x7c, 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2c, 0xff, 0x40, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0xc0, 0x39, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xf0, 0x8f, + 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xf1, + 0x2f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0xd0, 0x9, 0xff, 0x50, 0x0, 0x0, 0x0, 0x3, + 0xff, 0x70, 0x0, 0xcf, 0xfa, 0x40, 0x0, 0x2, + 0x8f, 0xfc, 0x0, 0x0, 0x9, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x17, 0xbe, + 0xff, 0xec, 0x93, 0x0, 0x0, + + /* U+0054 "T" */ + 0x4f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0x0, 0x0, 0x0, 0x0, 0xff, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0x30, 0x0, 0x0, 0x0, + + /* U+0055 "U" */ + 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, + 0xf0, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xf0, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xf0, 0xaf, 0xa0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xf0, 0xaf, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xf0, 0xaf, 0xa0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf0, 0xaf, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf0, 0xaf, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf0, + 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, + 0xf0, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xf0, 0xaf, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xf0, 0xaf, 0xa0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xf0, 0x9f, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xf0, 0x8f, 0xb0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5f, 0xe0, 0x6f, 0xd0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xc0, 0x3f, + 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x90, + 0xe, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, + 0x30, 0x7, 0xff, 0x60, 0x0, 0x0, 0x0, 0x2e, + 0xfc, 0x0, 0x0, 0xbf, 0xfa, 0x41, 0x1, 0x38, + 0xff, 0xe2, 0x0, 0x0, 0xa, 0xff, 0xff, 0xff, + 0xff, 0xfd, 0x20, 0x0, 0x0, 0x0, 0x39, 0xde, + 0xff, 0xda, 0x50, 0x0, 0x0, + + /* U+0056 "V" */ + 0x4f, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xfa, 0xe, 0xf7, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xf4, 0x7, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xd0, 0x1, 0xff, + 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0x70, + 0x0, 0xbf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x5, + 0xff, 0x10, 0x0, 0x4f, 0xf1, 0x0, 0x0, 0x0, + 0x0, 0xb, 0xf9, 0x0, 0x0, 0xd, 0xf6, 0x0, + 0x0, 0x0, 0x0, 0x2f, 0xf3, 0x0, 0x0, 0x7, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xc0, 0x0, + 0x0, 0x1, 0xff, 0x30, 0x0, 0x0, 0x0, 0xef, + 0x60, 0x0, 0x0, 0x0, 0xaf, 0x90, 0x0, 0x0, + 0x4, 0xff, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xe0, + 0x0, 0x0, 0xa, 0xf9, 0x0, 0x0, 0x0, 0x0, + 0xd, 0xf5, 0x0, 0x0, 0x1f, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xfb, 0x0, 0x0, 0x7f, 0xb0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xff, 0x20, 0x0, + 0xdf, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0x80, 0x3, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xe0, 0xa, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xd, 0xf4, 0x1f, 0xf1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0xfa, 0x6f, + 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xff, 0xdf, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xf7, 0x0, 0x0, + 0x0, 0x0, + + /* U+0057 "W" */ + 0x6f, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf7, + 0x0, 0x0, 0x0, 0x0, 0xd, 0xf7, 0x2f, 0xf3, + 0x0, 0x0, 0x0, 0x0, 0x9f, 0xfb, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xf3, 0xd, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0xcf, 0x0, 0x0, 0x0, 0x0, + 0x6f, 0xe0, 0x9, 0xfb, 0x0, 0x0, 0x0, 0x2, + 0xfb, 0x7f, 0x40, 0x0, 0x0, 0x0, 0xaf, 0xa0, + 0x5, 0xfe, 0x0, 0x0, 0x0, 0x7, 0xf6, 0x3f, + 0x90, 0x0, 0x0, 0x0, 0xef, 0x50, 0x0, 0xff, + 0x30, 0x0, 0x0, 0xc, 0xf1, 0xe, 0xd0, 0x0, + 0x0, 0x2, 0xff, 0x10, 0x0, 0xcf, 0x70, 0x0, + 0x0, 0x1f, 0xc0, 0xa, 0xf2, 0x0, 0x0, 0x6, + 0xfc, 0x0, 0x0, 0x7f, 0xb0, 0x0, 0x0, 0x5f, + 0x70, 0x6, 0xf6, 0x0, 0x0, 0xb, 0xf7, 0x0, + 0x0, 0x3f, 0xf0, 0x0, 0x0, 0xaf, 0x30, 0x1, + 0xfb, 0x0, 0x0, 0xf, 0xf2, 0x0, 0x0, 0xe, + 0xf3, 0x0, 0x0, 0xee, 0x0, 0x0, 0xdf, 0x0, + 0x0, 0x3f, 0xe0, 0x0, 0x0, 0xa, 0xf7, 0x0, + 0x3, 0xf9, 0x0, 0x0, 0x8f, 0x40, 0x0, 0x7f, + 0x90, 0x0, 0x0, 0x5, 0xfb, 0x0, 0x8, 0xf4, + 0x0, 0x0, 0x4f, 0x80, 0x0, 0xbf, 0x50, 0x0, + 0x0, 0x1, 0xff, 0x0, 0xd, 0xf0, 0x0, 0x0, + 0xf, 0xd0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0x30, 0x1f, 0xb0, 0x0, 0x0, 0xb, 0xf1, + 0x4, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x8f, 0x70, + 0x6f, 0x60, 0x0, 0x0, 0x6, 0xf6, 0x8, 0xf7, + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xb0, 0xbf, 0x10, + 0x0, 0x0, 0x2, 0xfa, 0xc, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xf0, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0xde, 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x0, + 0xb, 0xf8, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0x8f, 0x90, 0x0, 0x0, 0x0, 0x0, 0x6, 0xff, + 0xf3, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xff, 0xe0, 0x0, + 0x0, 0x0, 0x0, 0xf, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0x90, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xfb, 0x0, 0x0, 0x0, + + /* U+0058 "X" */ + 0x6, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xff, 0x60, 0x0, 0xbf, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0xd, 0xfa, 0x0, 0x0, 0x1e, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x9f, 0xd1, 0x0, 0x0, 0x3, + 0xff, 0x50, 0x0, 0x0, 0x4, 0xff, 0x30, 0x0, + 0x0, 0x0, 0x7f, 0xf1, 0x0, 0x0, 0x1e, 0xf7, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xfc, 0x0, 0x0, + 0xbf, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xef, + 0x70, 0x6, 0xfe, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xf3, 0x2f, 0xf4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0xfd, 0xcf, 0x80, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5, 0xfe, 0xef, 0x50, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2f, 0xf3, 0x5f, 0xe2, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x70, 0xa, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, 0xfb, + 0x0, 0x0, 0xef, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xe1, 0x0, 0x0, 0x4f, 0xf5, 0x0, 0x0, + 0x0, 0x4, 0xff, 0x40, 0x0, 0x0, 0x8, 0xff, + 0x20, 0x0, 0x0, 0x1e, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0xdf, 0xd0, 0x0, 0x0, 0xcf, 0xd0, 0x0, + 0x0, 0x0, 0x0, 0x2f, 0xf9, 0x0, 0x9, 0xff, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x7, 0xff, 0x50, + 0x6f, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xf2, + + /* U+0059 "Y" */ + 0x7f, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xaf, 0xf2, 0xc, 0xfc, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5, 0xff, 0x50, 0x2, 0xff, 0x60, 0x0, + 0x0, 0x0, 0x0, 0x1e, 0xfa, 0x0, 0x0, 0x6f, + 0xf2, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xe1, 0x0, + 0x0, 0xb, 0xfb, 0x0, 0x0, 0x0, 0x5, 0xff, + 0x40, 0x0, 0x0, 0x1, 0xff, 0x60, 0x0, 0x0, + 0x1e, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xf2, + 0x0, 0x0, 0xaf, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0xa, 0xfb, 0x0, 0x5, 0xff, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xef, 0x60, 0x1e, 0xf6, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xf1, 0xbf, + 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xfe, 0xfe, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0xef, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xc0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xc0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0xc0, 0x0, 0x0, + 0x0, 0x0, + + /* U+005A "Z" */ + 0x3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe0, 0x3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xfe, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0xef, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xfc, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8f, 0xe1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1e, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xfe, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xef, + 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, + 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xe1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xff, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1e, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0xb0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xfe, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0xff, 0xee, 0xee, 0xee, + 0xee, 0xee, 0xee, 0xe4, 0x7f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf5, + + /* U+005B "[" */ + 0x88, 0x88, 0x85, 0xff, 0xff, 0xfa, 0xfe, 0x0, + 0x0, 0xfe, 0x0, 0x0, 0xfe, 0x0, 0x0, 0xfe, + 0x0, 0x0, 0xfe, 0x0, 0x0, 0xfe, 0x0, 0x0, + 0xfe, 0x0, 0x0, 0xfe, 0x0, 0x0, 0xfe, 0x0, + 0x0, 0xfe, 0x0, 0x0, 0xfe, 0x0, 0x0, 0xfe, + 0x0, 0x0, 0xfe, 0x0, 0x0, 0xfe, 0x0, 0x0, + 0xfe, 0x0, 0x0, 0xfe, 0x0, 0x0, 0xfe, 0x0, + 0x0, 0xfe, 0x0, 0x0, 0xfe, 0x0, 0x0, 0xfe, + 0x0, 0x0, 0xfe, 0x0, 0x0, 0xfe, 0x0, 0x0, + 0xfe, 0x0, 0x0, 0xff, 0x88, 0x86, 0xff, 0xff, + 0xfb, + + /* U+005C "\\" */ + 0xcf, 0x0, 0x0, 0x0, 0x8f, 0x40, 0x0, 0x0, + 0x3f, 0x90, 0x0, 0x0, 0xf, 0xd0, 0x0, 0x0, + 0xa, 0xf2, 0x0, 0x0, 0x6, 0xf6, 0x0, 0x0, + 0x2, 0xfb, 0x0, 0x0, 0x0, 0xdf, 0x0, 0x0, + 0x0, 0x9f, 0x30, 0x0, 0x0, 0x4f, 0x80, 0x0, + 0x0, 0xf, 0xc0, 0x0, 0x0, 0xb, 0xf1, 0x0, + 0x0, 0x7, 0xf5, 0x0, 0x0, 0x2, 0xfa, 0x0, + 0x0, 0x0, 0xee, 0x0, 0x0, 0x0, 0x9f, 0x20, + 0x0, 0x0, 0x5f, 0x70, 0x0, 0x0, 0x1f, 0xb0, + 0x0, 0x0, 0xc, 0xf0, 0x0, 0x0, 0x8, 0xf4, + 0x0, 0x0, 0x3, 0xf9, 0x0, 0x0, 0x0, 0xfd, + + /* U+005D "]" */ + 0x48, 0x88, 0x88, 0x8, 0xff, 0xff, 0xf1, 0x0, + 0x0, 0xdf, 0x10, 0x0, 0xd, 0xf1, 0x0, 0x0, + 0xdf, 0x10, 0x0, 0xd, 0xf1, 0x0, 0x0, 0xdf, + 0x10, 0x0, 0xd, 0xf1, 0x0, 0x0, 0xdf, 0x10, + 0x0, 0xd, 0xf1, 0x0, 0x0, 0xdf, 0x10, 0x0, + 0xd, 0xf1, 0x0, 0x0, 0xdf, 0x10, 0x0, 0xd, + 0xf1, 0x0, 0x0, 0xdf, 0x10, 0x0, 0xd, 0xf1, + 0x0, 0x0, 0xdf, 0x10, 0x0, 0xd, 0xf1, 0x0, + 0x0, 0xdf, 0x10, 0x0, 0xd, 0xf1, 0x0, 0x0, + 0xdf, 0x10, 0x0, 0xd, 0xf1, 0x0, 0x0, 0xdf, + 0x10, 0x0, 0xd, 0xf1, 0x0, 0x0, 0xdf, 0x15, + 0x88, 0x8e, 0xf1, 0x9f, 0xff, 0xff, 0x10, + + /* U+005E "^" */ + 0x0, 0x0, 0x0, 0x77, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5, 0xff, 0x40, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xff, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x4f, + 0xb9, 0xf3, 0x0, 0x0, 0x0, 0x0, 0xbf, 0x53, + 0xfa, 0x0, 0x0, 0x0, 0x2, 0xfe, 0x0, 0xcf, + 0x20, 0x0, 0x0, 0xa, 0xf7, 0x0, 0x5f, 0x90, + 0x0, 0x0, 0x1f, 0xf1, 0x0, 0xe, 0xf1, 0x0, + 0x0, 0x8f, 0x90, 0x0, 0x8, 0xf8, 0x0, 0x0, + 0xff, 0x30, 0x0, 0x2, 0xfe, 0x0, 0x7, 0xfc, + 0x0, 0x0, 0x0, 0xbf, 0x60, 0xe, 0xf5, 0x0, + 0x0, 0x0, 0x4f, 0xe0, + + /* U+005F "_" */ + 0x9a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf9, + + /* U+0060 "`" */ + 0x4f, 0xfa, 0x0, 0x8, 0xff, 0x10, 0x0, 0xcf, + 0x70, 0x0, 0x2f, 0xe0, 0x0, 0x5, 0xf5, + + /* U+0061 "a" */ + 0x0, 0x3, 0x9d, 0xff, 0xec, 0x70, 0x0, 0x0, + 0xa, 0xff, 0xfd, 0xcd, 0xff, 0xd1, 0x0, 0x8, + 0xff, 0x70, 0x0, 0x1, 0xcf, 0xb0, 0x1, 0xff, + 0x50, 0x0, 0x0, 0x2, 0xff, 0x10, 0x2a, 0xd0, + 0x0, 0x0, 0x0, 0xe, 0xf5, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0x60, 0x0, 0x0, 0x0, + 0x1, 0x36, 0xbf, 0xf6, 0x0, 0x0, 0x5a, 0xdf, + 0xff, 0xfe, 0xef, 0x60, 0x3, 0xef, 0xff, 0xdb, + 0x95, 0xc, 0xf6, 0x1, 0xff, 0xb4, 0x0, 0x0, + 0x0, 0xcf, 0x60, 0x9f, 0xc0, 0x0, 0x0, 0x0, + 0xe, 0xf6, 0xc, 0xf7, 0x0, 0x0, 0x0, 0x4, + 0xff, 0x60, 0xbf, 0x90, 0x0, 0x0, 0x1, 0xdf, + 0xf6, 0x5, 0xff, 0x82, 0x0, 0x16, 0xef, 0xbf, + 0x70, 0xa, 0xff, 0xff, 0xff, 0xfe, 0x46, 0xf9, + 0x0, 0x6, 0xcf, 0xfe, 0xc7, 0x10, 0x1f, 0xe0, + + /* U+0062 "b" */ + 0xf, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x20, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf2, 0x7, + 0xdf, 0xeb, 0x40, 0x0, 0x0, 0xff, 0x2c, 0xff, + 0xdf, 0xff, 0x90, 0x0, 0xf, 0xfc, 0xe5, 0x0, + 0x5, 0xef, 0x70, 0x0, 0xff, 0xf2, 0x0, 0x0, + 0x3, 0xff, 0x10, 0xf, 0xf9, 0x0, 0x0, 0x0, + 0x9, 0xf7, 0x0, 0xff, 0x50, 0x0, 0x0, 0x0, + 0x4f, 0xc0, 0xf, 0xf2, 0x0, 0x0, 0x0, 0x1, + 0xff, 0x0, 0xff, 0x20, 0x0, 0x0, 0x0, 0xf, + 0xf2, 0xf, 0xf2, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x20, 0xff, 0x20, 0x0, 0x0, 0x0, 0xf, 0xf1, + 0xf, 0xf4, 0x0, 0x0, 0x0, 0x3, 0xfe, 0x0, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x8f, 0xa0, 0xf, + 0xfe, 0x10, 0x0, 0x0, 0x1e, 0xf5, 0x0, 0xff, + 0xcc, 0x20, 0x0, 0x2c, 0xfc, 0x0, 0xf, 0xf3, + 0xdf, 0xcb, 0xcf, 0xfe, 0x10, 0x0, 0xff, 0x20, + 0x7c, 0xef, 0xd8, 0x10, 0x0, + + /* U+0063 "c" */ + 0x0, 0x1, 0x8d, 0xff, 0xd9, 0x20, 0x0, 0x0, + 0x3e, 0xff, 0xee, 0xff, 0xf7, 0x0, 0x1, 0xef, + 0x91, 0x0, 0x19, 0xff, 0x50, 0xa, 0xf9, 0x0, + 0x0, 0x0, 0xaf, 0xe0, 0x2f, 0xf1, 0x0, 0x0, + 0x0, 0x2e, 0x91, 0x7f, 0xb0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xc0, + 0x0, 0x0, 0x0, 0xa, 0x92, 0x3f, 0xf1, 0x0, + 0x0, 0x0, 0x1f, 0xf4, 0xc, 0xfa, 0x0, 0x0, + 0x0, 0x9f, 0xe0, 0x3, 0xff, 0xb3, 0x0, 0x29, + 0xff, 0x50, 0x0, 0x5f, 0xff, 0xff, 0xff, 0xf7, + 0x0, 0x0, 0x2, 0x9d, 0xff, 0xda, 0x30, 0x0, + + /* U+0064 "d" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xe, 0xf4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xe, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xe, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xe, 0xf4, 0x0, 0x3, 0xae, 0xfe, 0x81, 0xe, + 0xf4, 0x0, 0x7f, 0xff, 0xde, 0xfe, 0x2e, 0xf4, + 0x4, 0xff, 0x70, 0x0, 0x3c, 0xde, 0xf4, 0xd, + 0xf6, 0x0, 0x0, 0x0, 0xdf, 0xf4, 0x4f, 0xd0, + 0x0, 0x0, 0x0, 0x5f, 0xf4, 0x9f, 0x80, 0x0, + 0x0, 0x0, 0x1f, 0xf4, 0xcf, 0x50, 0x0, 0x0, + 0x0, 0xe, 0xf4, 0xef, 0x30, 0x0, 0x0, 0x0, + 0xe, 0xf4, 0xef, 0x30, 0x0, 0x0, 0x0, 0xe, + 0xf4, 0xcf, 0x50, 0x0, 0x0, 0x0, 0xe, 0xf4, + 0x9f, 0x80, 0x0, 0x0, 0x0, 0xf, 0xf4, 0x4f, + 0xd0, 0x0, 0x0, 0x0, 0x5f, 0xf4, 0xd, 0xf5, + 0x0, 0x0, 0x0, 0xcf, 0xf4, 0x3, 0xff, 0x60, + 0x0, 0x2b, 0xde, 0xf4, 0x0, 0x5f, 0xff, 0xde, + 0xfe, 0x3e, 0xf4, 0x0, 0x2, 0x9e, 0xfd, 0x81, + 0xe, 0xf4, + + /* U+0065 "e" */ + 0x0, 0x0, 0x39, 0xdf, 0xea, 0x30, 0x0, 0x0, + 0x0, 0x9f, 0xff, 0xdf, 0xff, 0x80, 0x0, 0x0, + 0xaf, 0xd4, 0x0, 0x4, 0xef, 0x70, 0x0, 0x6f, + 0xc0, 0x0, 0x0, 0x2, 0xff, 0x20, 0xe, 0xf3, + 0x0, 0x0, 0x0, 0x9, 0xf9, 0x4, 0xfd, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xe0, 0x9f, 0xa0, 0x0, + 0x0, 0x0, 0x1, 0xff, 0x2b, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf4, 0xdf, 0xec, 0xcc, 0xcc, + 0xcc, 0xcc, 0xcc, 0x4b, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8f, 0xb0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4, 0xff, 0x10, 0x0, 0x0, 0x0, + 0x5d, 0x90, 0xd, 0xfa, 0x0, 0x0, 0x0, 0x1e, + 0xfd, 0x0, 0x3f, 0xfa, 0x30, 0x0, 0x6e, 0xff, + 0x40, 0x0, 0x4f, 0xff, 0xfe, 0xff, 0xff, 0x50, + 0x0, 0x0, 0x17, 0xce, 0xff, 0xc8, 0x10, 0x0, + + /* U+0066 "f" */ + 0x0, 0x2, 0xbe, 0xfd, 0xa0, 0x0, 0xe, 0xff, + 0xdd, 0xc0, 0x0, 0x6f, 0xf2, 0x0, 0x0, 0x0, + 0x8f, 0xb0, 0x0, 0x0, 0x0, 0x9f, 0xa0, 0x0, + 0x0, 0x0, 0x9f, 0xa0, 0x0, 0x0, 0xff, 0xff, + 0xff, 0xfd, 0x0, 0xcd, 0xef, 0xed, 0xda, 0x0, + 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x9f, 0xa0, + 0x0, 0x0, 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x0, + 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x9f, 0xa0, 0x0, + 0x0, 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x9f, + 0xa0, 0x0, 0x0, 0x0, 0x9f, 0xa0, 0x0, 0x0, + 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x9f, 0xa0, + 0x0, 0x0, 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x0, + 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x9f, 0xa0, 0x0, + 0x0, 0x0, 0x9f, 0xa0, 0x0, 0x0, + + /* U+0067 "g" */ + 0x0, 0x0, 0x7, 0xcf, 0xea, 0x30, 0xaf, 0x80, + 0x0, 0x3e, 0xff, 0xde, 0xff, 0x6a, 0xf8, 0x0, + 0x3f, 0xf6, 0x0, 0x2, 0xaf, 0xdf, 0x80, 0xd, + 0xf4, 0x0, 0x0, 0x0, 0x9f, 0xf8, 0x5, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0xff, 0x80, 0xaf, 0x60, + 0x0, 0x0, 0x0, 0xc, 0xf8, 0xd, 0xf3, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0x80, 0xff, 0x20, 0x0, + 0x0, 0x0, 0xa, 0xf8, 0xe, 0xf3, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x80, 0xcf, 0x50, 0x0, 0x0, + 0x0, 0xc, 0xf8, 0x8, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0xff, 0x80, 0x3f, 0xf2, 0x0, 0x0, 0x0, + 0x7f, 0xf8, 0x0, 0xaf, 0xd3, 0x0, 0x0, 0x6f, + 0xdf, 0x80, 0x1, 0xcf, 0xfd, 0xbb, 0xef, 0x7a, + 0xf8, 0x0, 0x0, 0x7c, 0xff, 0xda, 0x30, 0xaf, + 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, 0xf6, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0x40, + 0x2, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xe0, 0x2, + 0xfb, 0x40, 0x0, 0x1, 0x9f, 0xf8, 0x0, 0x9, + 0xff, 0xfd, 0xce, 0xff, 0xfa, 0x0, 0x0, 0x2, + 0x9d, 0xff, 0xed, 0x93, 0x0, 0x0, + + /* U+0068 "h" */ + 0xf, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf2, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xf, 0xf2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xf2, 0x5, 0xbe, 0xfd, 0x92, + 0x0, 0xf, 0xf2, 0xaf, 0xfe, 0xef, 0xfe, 0x20, + 0xf, 0xfb, 0xf7, 0x10, 0x4, 0xef, 0xc0, 0xf, + 0xff, 0x40, 0x0, 0x0, 0x5f, 0xf2, 0xf, 0xf9, + 0x0, 0x0, 0x0, 0xf, 0xf5, 0xf, 0xf5, 0x0, + 0x0, 0x0, 0xc, 0xf6, 0xf, 0xf2, 0x0, 0x0, + 0x0, 0xc, 0xf6, 0xf, 0xf2, 0x0, 0x0, 0x0, + 0xc, 0xf6, 0xf, 0xf2, 0x0, 0x0, 0x0, 0xc, + 0xf6, 0xf, 0xf2, 0x0, 0x0, 0x0, 0xc, 0xf6, + 0xf, 0xf2, 0x0, 0x0, 0x0, 0xc, 0xf6, 0xf, + 0xf2, 0x0, 0x0, 0x0, 0xc, 0xf6, 0xf, 0xf2, + 0x0, 0x0, 0x0, 0xc, 0xf6, 0xf, 0xf2, 0x0, + 0x0, 0x0, 0xc, 0xf6, 0xf, 0xf2, 0x0, 0x0, + 0x0, 0xc, 0xf6, 0xf, 0xf2, 0x0, 0x0, 0x0, + 0xc, 0xf6, + + /* U+0069 "i" */ + 0xff, 0x3f, 0xf3, 0xcd, 0x20, 0x0, 0x0, 0x0, + 0x0, 0xff, 0x3f, 0xf3, 0xff, 0x3f, 0xf3, 0xff, + 0x3f, 0xf3, 0xff, 0x3f, 0xf3, 0xff, 0x3f, 0xf3, + 0xff, 0x3f, 0xf3, 0xff, 0x3f, 0xf3, 0xff, 0x3f, + 0xf3, + + /* U+006A "j" */ + 0x0, 0x0, 0xff, 0x30, 0x0, 0xf, 0xf3, 0x0, + 0x0, 0xcd, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x30, 0x0, 0xf, 0xf3, 0x0, 0x0, 0xff, 0x30, + 0x0, 0xf, 0xf3, 0x0, 0x0, 0xff, 0x30, 0x0, + 0xf, 0xf3, 0x0, 0x0, 0xff, 0x30, 0x0, 0xf, + 0xf3, 0x0, 0x0, 0xff, 0x30, 0x0, 0xf, 0xf3, + 0x0, 0x0, 0xff, 0x30, 0x0, 0xf, 0xf3, 0x0, + 0x0, 0xff, 0x30, 0x0, 0xf, 0xf3, 0x0, 0x0, + 0xff, 0x30, 0x0, 0xf, 0xf3, 0x0, 0x0, 0xff, + 0x30, 0x0, 0xf, 0xf3, 0x0, 0x3, 0xff, 0x15, + 0xbb, 0xff, 0xc0, 0x5c, 0xfe, 0xa1, 0x0, + + /* U+006B "k" */ + 0xf, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf2, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xf, 0xf2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xf2, 0x0, 0x0, 0x7, 0xff, + 0x90, 0xf, 0xf2, 0x0, 0x0, 0x6f, 0xf9, 0x0, + 0xf, 0xf2, 0x0, 0x5, 0xff, 0x90, 0x0, 0xf, + 0xf2, 0x0, 0x4f, 0xf9, 0x0, 0x0, 0xf, 0xf2, + 0x4, 0xff, 0x90, 0x0, 0x0, 0xf, 0xf2, 0x3f, + 0xf9, 0x0, 0x0, 0x0, 0xf, 0xf5, 0xef, 0xf6, + 0x0, 0x0, 0x0, 0xf, 0xff, 0xfb, 0xff, 0x10, + 0x0, 0x0, 0xf, 0xff, 0xa0, 0x9f, 0xb0, 0x0, + 0x0, 0xf, 0xfa, 0x0, 0x1e, 0xf6, 0x0, 0x0, + 0xf, 0xf2, 0x0, 0x6, 0xff, 0x10, 0x0, 0xf, + 0xf2, 0x0, 0x0, 0xcf, 0xb0, 0x0, 0xf, 0xf2, + 0x0, 0x0, 0x2f, 0xf5, 0x0, 0xf, 0xf2, 0x0, + 0x0, 0x8, 0xfe, 0x10, 0xf, 0xf2, 0x0, 0x0, + 0x0, 0xef, 0xb0, 0xf, 0xf2, 0x0, 0x0, 0x0, + 0x5f, 0xf5, + + /* U+006C "l" */ + 0x1f, 0xf1, 0x1f, 0xf1, 0x1f, 0xf1, 0x1f, 0xf1, + 0x1f, 0xf1, 0x1f, 0xf1, 0x1f, 0xf1, 0x1f, 0xf1, + 0x1f, 0xf1, 0x1f, 0xf1, 0x1f, 0xf1, 0x1f, 0xf1, + 0x1f, 0xf1, 0x1f, 0xf1, 0x1f, 0xf1, 0x1f, 0xf1, + 0x1f, 0xf1, 0x1f, 0xf1, 0x1f, 0xf1, 0x1f, 0xf1, + 0x1f, 0xf1, 0x1f, 0xf1, + + /* U+006D "m" */ + 0xf, 0xf1, 0x8, 0xdf, 0xd9, 0x20, 0x0, 0x6d, + 0xfe, 0xb5, 0x0, 0xf, 0xf2, 0xcf, 0xdb, 0xff, + 0xe3, 0xa, 0xfe, 0xbe, 0xff, 0x70, 0xf, 0xfb, + 0xc2, 0x0, 0x1c, 0xfc, 0x6e, 0x50, 0x0, 0x8f, + 0xf2, 0xf, 0xfe, 0x0, 0x0, 0x2, 0xff, 0xf4, + 0x0, 0x0, 0xd, 0xf7, 0xf, 0xf6, 0x0, 0x0, + 0x0, 0xef, 0xb0, 0x0, 0x0, 0x8, 0xfa, 0xf, + 0xf3, 0x0, 0x0, 0x0, 0xcf, 0x80, 0x0, 0x0, + 0x7, 0xfb, 0xf, 0xf1, 0x0, 0x0, 0x0, 0xcf, + 0x60, 0x0, 0x0, 0x7, 0xfb, 0xf, 0xf1, 0x0, + 0x0, 0x0, 0xcf, 0x60, 0x0, 0x0, 0x7, 0xfb, + 0xf, 0xf1, 0x0, 0x0, 0x0, 0xcf, 0x60, 0x0, + 0x0, 0x7, 0xfb, 0xf, 0xf1, 0x0, 0x0, 0x0, + 0xcf, 0x60, 0x0, 0x0, 0x7, 0xfb, 0xf, 0xf1, + 0x0, 0x0, 0x0, 0xcf, 0x60, 0x0, 0x0, 0x7, + 0xfb, 0xf, 0xf1, 0x0, 0x0, 0x0, 0xcf, 0x60, + 0x0, 0x0, 0x7, 0xfb, 0xf, 0xf1, 0x0, 0x0, + 0x0, 0xcf, 0x60, 0x0, 0x0, 0x7, 0xfb, 0xf, + 0xf1, 0x0, 0x0, 0x0, 0xcf, 0x60, 0x0, 0x0, + 0x7, 0xfb, 0xf, 0xf1, 0x0, 0x0, 0x0, 0xcf, + 0x60, 0x0, 0x0, 0x7, 0xfb, 0xf, 0xf1, 0x0, + 0x0, 0x0, 0xcf, 0x60, 0x0, 0x0, 0x7, 0xfb, + + /* U+006E "n" */ + 0xf, 0xf1, 0x5, 0xbe, 0xfe, 0x92, 0x0, 0xf, + 0xf2, 0xaf, 0xfe, 0xef, 0xfe, 0x30, 0xf, 0xfb, + 0xf7, 0x10, 0x3, 0xef, 0xc0, 0xf, 0xff, 0x30, + 0x0, 0x0, 0x4f, 0xf2, 0xf, 0xf9, 0x0, 0x0, + 0x0, 0xe, 0xf5, 0xf, 0xf4, 0x0, 0x0, 0x0, + 0xb, 0xf6, 0xf, 0xf1, 0x0, 0x0, 0x0, 0xb, + 0xf7, 0xf, 0xf1, 0x0, 0x0, 0x0, 0xb, 0xf7, + 0xf, 0xf1, 0x0, 0x0, 0x0, 0xb, 0xf7, 0xf, + 0xf1, 0x0, 0x0, 0x0, 0xb, 0xf7, 0xf, 0xf1, + 0x0, 0x0, 0x0, 0xb, 0xf7, 0xf, 0xf1, 0x0, + 0x0, 0x0, 0xb, 0xf7, 0xf, 0xf1, 0x0, 0x0, + 0x0, 0xb, 0xf7, 0xf, 0xf1, 0x0, 0x0, 0x0, + 0xb, 0xf7, 0xf, 0xf1, 0x0, 0x0, 0x0, 0xb, + 0xf7, 0xf, 0xf1, 0x0, 0x0, 0x0, 0xb, 0xf7, + + /* U+006F "o" */ + 0x0, 0x1, 0x7c, 0xef, 0xeb, 0x50, 0x0, 0x0, + 0x3, 0xef, 0xfc, 0xcf, 0xff, 0xb0, 0x0, 0x2, + 0xff, 0x70, 0x0, 0x8, 0xff, 0xa0, 0x0, 0xcf, + 0x70, 0x0, 0x0, 0x7, 0xff, 0x40, 0x4f, 0xe0, + 0x0, 0x0, 0x0, 0xd, 0xfb, 0x8, 0xf9, 0x0, + 0x0, 0x0, 0x0, 0x7f, 0xf0, 0xcf, 0x60, 0x0, + 0x0, 0x0, 0x3, 0xff, 0x2e, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xf4, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0xff, 0x4d, 0xf5, 0x0, 0x0, 0x0, + 0x0, 0x1f, 0xf3, 0x9f, 0x80, 0x0, 0x0, 0x0, + 0x4, 0xff, 0x5, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0xb0, 0xe, 0xf6, 0x0, 0x0, 0x0, 0x2f, + 0xf5, 0x0, 0x4f, 0xf7, 0x0, 0x0, 0x4e, 0xfb, + 0x0, 0x0, 0x6f, 0xff, 0xcc, 0xef, 0xfb, 0x0, + 0x0, 0x0, 0x29, 0xdf, 0xfe, 0xa4, 0x0, 0x0, + + /* U+0070 "p" */ + 0x1f, 0xf1, 0x7, 0xdf, 0xeb, 0x40, 0x0, 0x1, + 0xff, 0x2c, 0xff, 0xef, 0xff, 0x80, 0x0, 0x1f, + 0xfc, 0xe5, 0x0, 0x6, 0xff, 0x60, 0x1, 0xff, + 0xf2, 0x0, 0x0, 0x3, 0xff, 0x10, 0x1f, 0xf9, + 0x0, 0x0, 0x0, 0xa, 0xf7, 0x1, 0xff, 0x40, + 0x0, 0x0, 0x0, 0x4f, 0xc0, 0x1f, 0xf2, 0x0, + 0x0, 0x0, 0x1, 0xff, 0x1, 0xff, 0x10, 0x0, + 0x0, 0x0, 0xf, 0xf1, 0x1f, 0xf1, 0x0, 0x0, + 0x0, 0x0, 0xff, 0x21, 0xff, 0x20, 0x0, 0x0, + 0x0, 0x1f, 0xf0, 0x1f, 0xf4, 0x0, 0x0, 0x0, + 0x4, 0xfd, 0x1, 0xff, 0x80, 0x0, 0x0, 0x0, + 0x8f, 0x90, 0x1f, 0xfe, 0x10, 0x0, 0x0, 0x1f, + 0xf3, 0x1, 0xff, 0xbd, 0x30, 0x0, 0x3d, 0xf9, + 0x0, 0x1f, 0xf2, 0xcf, 0xed, 0xef, 0xfa, 0x0, + 0x1, 0xff, 0x10, 0x7c, 0xef, 0xb5, 0x0, 0x0, + 0x1f, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, + 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xff, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xf1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+0071 "q" */ + 0x0, 0x3, 0xae, 0xfd, 0x81, 0xe, 0xf4, 0x0, + 0x7f, 0xff, 0xdf, 0xfe, 0x2e, 0xf4, 0x5, 0xff, + 0x70, 0x0, 0x3d, 0xdf, 0xf4, 0xe, 0xf5, 0x0, + 0x0, 0x0, 0xdf, 0xf4, 0x5f, 0xc0, 0x0, 0x0, + 0x0, 0x5f, 0xf4, 0x9f, 0x70, 0x0, 0x0, 0x0, + 0x1f, 0xf4, 0xcf, 0x40, 0x0, 0x0, 0x0, 0xe, + 0xf4, 0xef, 0x20, 0x0, 0x0, 0x0, 0xe, 0xf4, + 0xef, 0x20, 0x0, 0x0, 0x0, 0xe, 0xf4, 0xcf, + 0x40, 0x0, 0x0, 0x0, 0xf, 0xf4, 0x9f, 0x70, + 0x0, 0x0, 0x0, 0x1f, 0xf4, 0x4f, 0xc0, 0x0, + 0x0, 0x0, 0x5f, 0xf4, 0xd, 0xf5, 0x0, 0x0, + 0x0, 0xdf, 0xf4, 0x4, 0xff, 0x60, 0x0, 0x3c, + 0xce, 0xf4, 0x0, 0x6f, 0xff, 0xef, 0xfe, 0x2e, + 0xf4, 0x0, 0x2, 0xae, 0xfd, 0x81, 0xe, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xe, 0xf4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xe, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xe, 0xf4, + + /* U+0072 "r" */ + 0x1f, 0xf1, 0x1a, 0xef, 0xc1, 0x1f, 0xf2, 0xdf, + 0xff, 0xd0, 0x1f, 0xf9, 0xe6, 0x35, 0x50, 0x1f, + 0xff, 0x20, 0x0, 0x0, 0x1f, 0xf9, 0x0, 0x0, + 0x0, 0x1f, 0xf4, 0x0, 0x0, 0x0, 0x1f, 0xf2, + 0x0, 0x0, 0x0, 0x1f, 0xf1, 0x0, 0x0, 0x0, + 0x1f, 0xf1, 0x0, 0x0, 0x0, 0x1f, 0xf1, 0x0, + 0x0, 0x0, 0x1f, 0xf1, 0x0, 0x0, 0x0, 0x1f, + 0xf1, 0x0, 0x0, 0x0, 0x1f, 0xf1, 0x0, 0x0, + 0x0, 0x1f, 0xf1, 0x0, 0x0, 0x0, 0x1f, 0xf1, + 0x0, 0x0, 0x0, 0x1f, 0xf1, 0x0, 0x0, 0x0, + + /* U+0073 "s" */ + 0x0, 0x19, 0xdf, 0xfd, 0xb4, 0x0, 0x0, 0x3f, + 0xff, 0xed, 0xff, 0xfa, 0x0, 0xd, 0xfc, 0x20, + 0x0, 0x8f, 0xf7, 0x3, 0xff, 0x10, 0x0, 0x0, + 0xaf, 0xe0, 0x5f, 0xe0, 0x0, 0x0, 0x2, 0x40, + 0x1, 0xff, 0x60, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xff, 0xb5, 0x10, 0x0, 0x0, 0x0, 0x6, 0xef, + 0xff, 0xeb, 0x60, 0x0, 0x0, 0x0, 0x59, 0xcf, + 0xff, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x4, 0xdf, + 0xf1, 0x1, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x8b, + 0xf6, 0x0, 0x0, 0x0, 0x9, 0xfa, 0x8f, 0xd0, + 0x0, 0x0, 0x0, 0xdf, 0x71, 0xef, 0xc3, 0x0, + 0x1, 0x9f, 0xf1, 0x3, 0xef, 0xfe, 0xde, 0xff, + 0xf5, 0x0, 0x1, 0x7c, 0xff, 0xfd, 0x82, 0x0, + + /* U+0074 "t" */ + 0x0, 0x0, 0x20, 0x0, 0x0, 0x3d, 0xa0, 0x0, + 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x9f, 0xa0, 0x0, + 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x9f, 0xa0, 0x0, + 0x9f, 0xff, 0xff, 0xf8, 0x7d, 0xef, 0xed, 0xd6, + 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x9f, 0xa0, 0x0, + 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x9f, 0xa0, 0x0, + 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x9f, 0xa0, 0x0, + 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x9f, 0xa0, 0x0, + 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x9f, 0xa0, 0x0, + 0x0, 0x8f, 0xa0, 0x0, 0x0, 0x6f, 0xd0, 0x0, + 0x0, 0x1f, 0xfc, 0x96, 0x0, 0x4, 0xcf, 0xe8, + + /* U+0075 "u" */ + 0x2f, 0xf0, 0x0, 0x0, 0x0, 0xd, 0xf4, 0x2f, + 0xf0, 0x0, 0x0, 0x0, 0xd, 0xf4, 0x2f, 0xf0, + 0x0, 0x0, 0x0, 0xd, 0xf4, 0x2f, 0xf0, 0x0, + 0x0, 0x0, 0xd, 0xf4, 0x2f, 0xf0, 0x0, 0x0, + 0x0, 0xd, 0xf4, 0x2f, 0xf0, 0x0, 0x0, 0x0, + 0xd, 0xf4, 0x2f, 0xf0, 0x0, 0x0, 0x0, 0xd, + 0xf4, 0x2f, 0xf0, 0x0, 0x0, 0x0, 0xd, 0xf4, + 0x2f, 0xf0, 0x0, 0x0, 0x0, 0xd, 0xf4, 0x2f, + 0xf0, 0x0, 0x0, 0x0, 0xd, 0xf4, 0x2f, 0xf0, + 0x0, 0x0, 0x0, 0xf, 0xf4, 0x1f, 0xf2, 0x0, + 0x0, 0x0, 0x4f, 0xf4, 0xe, 0xf8, 0x0, 0x0, + 0x0, 0xdf, 0xf4, 0x8, 0xff, 0x50, 0x0, 0x4d, + 0xdd, 0xf4, 0x0, 0xdf, 0xfe, 0xcf, 0xfd, 0x2d, + 0xf4, 0x0, 0x7, 0xdf, 0xfd, 0x70, 0xd, 0xf4, + + /* U+0076 "v" */ + 0x6f, 0xf0, 0x0, 0x0, 0x0, 0x1, 0xff, 0x31, + 0xff, 0x40, 0x0, 0x0, 0x0, 0x7f, 0xd0, 0xb, + 0xf9, 0x0, 0x0, 0x0, 0xc, 0xf7, 0x0, 0x5f, + 0xe0, 0x0, 0x0, 0x2, 0xff, 0x10, 0x0, 0xff, + 0x40, 0x0, 0x0, 0x7f, 0xb0, 0x0, 0x9, 0xf9, + 0x0, 0x0, 0xd, 0xf5, 0x0, 0x0, 0x4f, 0xe0, + 0x0, 0x3, 0xff, 0x0, 0x0, 0x0, 0xef, 0x40, + 0x0, 0x8f, 0x90, 0x0, 0x0, 0x8, 0xf9, 0x0, + 0xe, 0xf3, 0x0, 0x0, 0x0, 0x2f, 0xe0, 0x4, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x30, 0x9f, + 0x70, 0x0, 0x0, 0x0, 0x7, 0xf8, 0xe, 0xf1, + 0x0, 0x0, 0x0, 0x0, 0x1f, 0xd4, 0xfb, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0xdf, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xff, 0xe0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xf, 0xf9, 0x0, 0x0, 0x0, + + /* U+0077 "w" */ + 0xbf, 0x60, 0x0, 0x0, 0x9, 0xfe, 0x0, 0x0, + 0x0, 0x3f, 0xf1, 0x7f, 0xb0, 0x0, 0x0, 0xd, + 0xff, 0x10, 0x0, 0x0, 0x7f, 0xb0, 0x2f, 0xf0, + 0x0, 0x0, 0x1f, 0xdf, 0x50, 0x0, 0x0, 0xcf, + 0x60, 0xd, 0xf4, 0x0, 0x0, 0x5f, 0x6f, 0x90, + 0x0, 0x0, 0xff, 0x10, 0x8, 0xf8, 0x0, 0x0, + 0x9f, 0x1d, 0xd0, 0x0, 0x5, 0xfc, 0x0, 0x3, + 0xfd, 0x0, 0x0, 0xdd, 0x9, 0xf1, 0x0, 0x9, + 0xf7, 0x0, 0x0, 0xef, 0x10, 0x1, 0xf9, 0x6, + 0xf4, 0x0, 0xe, 0xf2, 0x0, 0x0, 0x9f, 0x60, + 0x5, 0xf5, 0x2, 0xf8, 0x0, 0x2f, 0xd0, 0x0, + 0x0, 0x5f, 0xa0, 0x9, 0xf1, 0x0, 0xec, 0x0, + 0x7f, 0x80, 0x0, 0x0, 0xf, 0xe0, 0xd, 0xd0, + 0x0, 0xbf, 0x0, 0xbf, 0x20, 0x0, 0x0, 0xb, + 0xf3, 0x1f, 0xa0, 0x0, 0x7f, 0x40, 0xfd, 0x0, + 0x0, 0x0, 0x6, 0xf7, 0x4f, 0x60, 0x0, 0x4f, + 0x74, 0xf8, 0x0, 0x0, 0x0, 0x1, 0xfc, 0x8f, + 0x20, 0x0, 0xf, 0xb9, 0xf3, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0xde, 0x0, 0x0, 0xd, 0xfd, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xfa, 0x0, 0x0, + 0x9, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x3f, + 0xf6, 0x0, 0x0, 0x5, 0xff, 0x40, 0x0, 0x0, + + /* U+0078 "x" */ + 0xb, 0xfc, 0x0, 0x0, 0x0, 0xb, 0xfc, 0x0, + 0x1e, 0xf6, 0x0, 0x0, 0x6, 0xff, 0x20, 0x0, + 0x4f, 0xf1, 0x0, 0x1, 0xef, 0x60, 0x0, 0x0, + 0x9f, 0xa0, 0x0, 0xaf, 0xa0, 0x0, 0x0, 0x0, + 0xdf, 0x40, 0x4f, 0xe1, 0x0, 0x0, 0x0, 0x3, + 0xfe, 0x1d, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xfe, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xff, + 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x8f, + 0xc0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xa0, 0x9f, + 0x80, 0x0, 0x0, 0x0, 0x5f, 0xe1, 0x0, 0xef, + 0x40, 0x0, 0x0, 0x2f, 0xf4, 0x0, 0x5, 0xfe, + 0x10, 0x0, 0xc, 0xfa, 0x0, 0x0, 0xb, 0xfb, + 0x0, 0x8, 0xfe, 0x10, 0x0, 0x0, 0x2f, 0xf6, + 0x4, 0xff, 0x50, 0x0, 0x0, 0x0, 0x7f, 0xf2, + + /* U+0079 "y" */ + 0x4f, 0xf1, 0x0, 0x0, 0x0, 0x0, 0xff, 0x50, + 0xef, 0x70, 0x0, 0x0, 0x0, 0x5f, 0xe0, 0x8, + 0xfc, 0x0, 0x0, 0x0, 0xb, 0xf8, 0x0, 0x2f, + 0xf2, 0x0, 0x0, 0x1, 0xff, 0x20, 0x0, 0xbf, + 0x80, 0x0, 0x0, 0x7f, 0xb0, 0x0, 0x5, 0xfd, + 0x0, 0x0, 0xc, 0xf5, 0x0, 0x0, 0xe, 0xf3, + 0x0, 0x2, 0xfe, 0x0, 0x0, 0x0, 0x8f, 0x90, + 0x0, 0x8f, 0x90, 0x0, 0x0, 0x2, 0xfe, 0x0, + 0xe, 0xf2, 0x0, 0x0, 0x0, 0xc, 0xf4, 0x4, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xa0, 0xaf, + 0x60, 0x0, 0x0, 0x0, 0x0, 0xff, 0x1f, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x9, 0xfb, 0xf9, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x9f, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5f, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x9b, + 0xdf, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x8, 0xef, + 0xd7, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+007A "z" */ + 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0, + 0xae, 0xee, 0xee, 0xee, 0xee, 0xff, 0x70, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9f, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5f, 0xf2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2f, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xd, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0xfe, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xef, 0x80, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9f, 0xe1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5f, 0xf3, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2f, 0xff, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0x16, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, + + /* U+007B "{" */ + 0x0, 0x0, 0x3, 0xad, 0xf2, 0x0, 0x0, 0x4f, + 0xfb, 0x91, 0x0, 0x0, 0xdf, 0x40, 0x0, 0x0, + 0x0, 0xfd, 0x0, 0x0, 0x0, 0x0, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0xfc, 0x0, 0x0, 0x0, 0x0, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0xfc, 0x0, 0x0, 0x0, 0x0, 0xfc, + 0x0, 0x0, 0x0, 0x2, 0xfa, 0x0, 0x0, 0x0, + 0x9, 0xf5, 0x0, 0x0, 0x19, 0xdf, 0x80, 0x0, + 0x0, 0x2f, 0xfb, 0x20, 0x0, 0x0, 0x1, 0x5e, + 0xe2, 0x0, 0x0, 0x0, 0x5, 0xf9, 0x0, 0x0, + 0x0, 0x1, 0xfb, 0x0, 0x0, 0x0, 0x0, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0xfc, 0x0, 0x0, 0x0, 0x0, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0xfc, 0x0, 0x0, 0x0, 0x0, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0xff, 0x10, 0x0, + 0x0, 0x0, 0x9f, 0xd6, 0x30, 0x0, 0x0, 0x9, + 0xff, 0xf2, 0x0, 0x0, 0x0, 0x3, 0x40, + + /* U+007C "|" */ + 0x18, 0x53, 0xfa, 0x3f, 0xa3, 0xfa, 0x3f, 0xa3, + 0xfa, 0x3f, 0xa3, 0xfa, 0x3f, 0xa3, 0xfa, 0x3f, + 0xa3, 0xfa, 0x3f, 0xa3, 0xfa, 0x3f, 0xa3, 0xfa, + 0x3f, 0xa3, 0xfa, 0x3f, 0xa3, 0xfa, 0x3f, 0xa3, + 0xfa, 0x3f, 0xa3, 0xfa, 0x3f, 0xa3, 0xfa, 0x3f, + 0xa0, + + /* U+007D "}" */ + 0x3f, 0xd9, 0x20, 0x0, 0x0, 0x19, 0xcf, 0xf3, + 0x0, 0x0, 0x0, 0x6, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0xee, 0x0, + 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, 0x0, 0x0, + 0xef, 0x0, 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, + 0x0, 0x0, 0xef, 0x0, 0x0, 0x0, 0x0, 0xdf, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0x0, 0x0, 0x0, + 0x0, 0x7f, 0x70, 0x0, 0x0, 0x0, 0x9, 0xfc, + 0x90, 0x0, 0x0, 0x2, 0xcf, 0xf1, 0x0, 0x0, + 0x3f, 0xd4, 0x10, 0x0, 0x0, 0xaf, 0x30, 0x0, + 0x0, 0x0, 0xdf, 0x0, 0x0, 0x0, 0x0, 0xef, + 0x0, 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, 0x0, + 0x0, 0xef, 0x0, 0x0, 0x0, 0x0, 0xef, 0x0, + 0x0, 0x0, 0x0, 0xef, 0x0, 0x0, 0x0, 0x0, + 0xee, 0x0, 0x0, 0x0, 0x2, 0xfd, 0x0, 0x0, + 0x3, 0x6e, 0xf8, 0x0, 0x0, 0x3f, 0xff, 0x80, + 0x0, 0x0, 0x14, 0x30, 0x0, 0x0, 0x0, + + /* U+007E "~" */ + 0x5, 0xbe, 0xfd, 0x93, 0x0, 0x0, 0x0, 0x30, + 0xaf, 0xff, 0xff, 0xff, 0xd7, 0x31, 0x39, 0xf1, + 0xcd, 0x62, 0x24, 0x9f, 0xff, 0xff, 0xff, 0xf0, + 0x50, 0x0, 0x0, 0x1, 0x7c, 0xef, 0xe9, 0x20, + + /* U+503C "值" */ + 0x0, 0x0, 0x2, 0x51, 0x0, 0x0, 0x0, 0x4, + 0x82, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, + 0xf7, 0x0, 0x0, 0x0, 0x9, 0xf5, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xf1, 0x0, 0x0, + 0x0, 0x9, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3f, 0xb0, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf2, 0x0, 0x0, 0xaf, 0x40, + 0x99, 0x99, 0x99, 0x9d, 0xfb, 0x99, 0x99, 0x99, + 0x91, 0x0, 0x1, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x9, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xf6, 0x0, 0x0, 0x0, 0x0, 0x9, 0xf5, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xf1, 0x0, 0x9, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x0, + 0x0, 0x7f, 0xf1, 0x0, 0xa, 0xf9, 0x88, 0x88, + 0x88, 0x88, 0x8b, 0xf6, 0x0, 0x0, 0xef, 0xf1, + 0x0, 0xa, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xf6, 0x0, 0x9, 0xff, 0xf1, 0x0, 0xa, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xf6, 0x0, 0x3f, + 0xdb, 0xf1, 0x0, 0xa, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf6, 0x0, 0xaf, 0x4b, 0xf1, 0x0, + 0xa, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x7b, 0xf6, + 0x0, 0x6a, 0xb, 0xf1, 0x0, 0xa, 0xf2, 0x0, + 0x0, 0x0, 0x0, 0x7, 0xf6, 0x0, 0x1, 0xb, + 0xf1, 0x0, 0xa, 0xf2, 0x0, 0x0, 0x0, 0x0, + 0x7, 0xf6, 0x0, 0x0, 0xb, 0xf1, 0x0, 0xa, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x0, + 0x0, 0xb, 0xf1, 0x0, 0xa, 0xf8, 0x77, 0x77, + 0x77, 0x77, 0x7b, 0xf6, 0x0, 0x0, 0xb, 0xf1, + 0x0, 0xa, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xf6, 0x0, 0x0, 0xb, 0xf1, 0x0, 0xa, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xf6, 0x0, 0x0, + 0xb, 0xf1, 0x0, 0xa, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf6, 0x0, 0x0, 0xb, 0xf1, 0x0, + 0xa, 0xf7, 0x66, 0x66, 0x66, 0x66, 0x6a, 0xf6, + 0x0, 0x0, 0xb, 0xf1, 0x0, 0xa, 0xf2, 0x0, + 0x0, 0x0, 0x0, 0x7, 0xf6, 0x0, 0x0, 0xb, + 0xf1, 0x0, 0xa, 0xf2, 0x0, 0x0, 0x0, 0x0, + 0x7, 0xf6, 0x0, 0x0, 0xb, 0xf1, 0x1f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0x0, 0xb, 0xf1, 0x8, 0x88, 0x88, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x85, + + /* U+50CF "像" */ + 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x45, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, + 0xe0, 0x0, 0x2, 0xfe, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xa0, 0x0, 0xc, + 0xfa, 0x66, 0x66, 0x66, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0x50, 0x0, 0x9f, 0xff, 0xff, 0xff, + 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0xef, 0x0, + 0x8, 0xf9, 0x0, 0x0, 0x1, 0xef, 0x30, 0x0, + 0x0, 0x0, 0x4, 0xfa, 0x0, 0x9f, 0xa0, 0x0, + 0x0, 0xc, 0xf5, 0x0, 0x0, 0x0, 0x0, 0xb, + 0xf4, 0x1c, 0xfe, 0x66, 0x66, 0x66, 0xaf, 0xc6, + 0x66, 0x65, 0x0, 0x0, 0x3f, 0xf1, 0x4f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x0, + 0x0, 0xbf, 0xf1, 0x2, 0xbf, 0x10, 0x0, 0x9, + 0xf3, 0x0, 0x0, 0xfd, 0x0, 0x3, 0xff, 0xf1, + 0x0, 0xbf, 0x10, 0x0, 0xe, 0xd0, 0x0, 0x0, + 0xfd, 0x0, 0xd, 0xfd, 0xf1, 0x0, 0xbf, 0xee, + 0xee, 0xef, 0xfe, 0xee, 0xee, 0xfd, 0x0, 0x7f, + 0xaa, 0xf1, 0x0, 0x57, 0x77, 0x7d, 0xfc, 0x77, + 0x77, 0x77, 0x85, 0x0, 0xcf, 0x1a, 0xf1, 0x0, + 0x0, 0x0, 0x9f, 0xf6, 0x0, 0x0, 0x7, 0xf3, + 0x0, 0x76, 0xa, 0xf1, 0x0, 0x0, 0x6e, 0xf8, + 0xcf, 0x40, 0x3, 0xcf, 0xc3, 0x0, 0x10, 0xa, + 0xf1, 0x3, 0x8e, 0xfc, 0x30, 0x8f, 0xe2, 0x9f, + 0xe6, 0x0, 0x0, 0x0, 0xa, 0xf1, 0x7f, 0xfb, + 0x40, 0xa, 0xfa, 0xff, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0xa, 0xf1, 0x7, 0x20, 0x4, 0xdf, 0x40, + 0xef, 0x28, 0xf1, 0x0, 0x0, 0x0, 0xa, 0xf1, + 0x0, 0x3, 0xbf, 0xc2, 0x5, 0xff, 0x13, 0xf7, + 0x0, 0x0, 0x0, 0xa, 0xf1, 0x17, 0xdf, 0xe7, + 0x0, 0x7f, 0xef, 0x50, 0xce, 0x0, 0x0, 0x0, + 0xa, 0xf1, 0x5f, 0xd7, 0x0, 0x1b, 0xf9, 0x5f, + 0x60, 0x4f, 0xa0, 0x0, 0x0, 0xa, 0xf1, 0x3, + 0x0, 0x6, 0xef, 0x60, 0x4f, 0x70, 0xb, 0xf7, + 0x0, 0x0, 0xa, 0xf1, 0x0, 0x5, 0xdf, 0xc2, + 0x0, 0x5f, 0x60, 0x1, 0xef, 0x80, 0x0, 0xa, + 0xf1, 0x17, 0xef, 0xe6, 0x0, 0x0, 0xbf, 0x40, + 0x0, 0x2e, 0xb0, 0x0, 0xa, 0xf1, 0x6f, 0xd6, + 0x2, 0x99, 0x9d, 0xfc, 0x0, 0x0, 0x2, 0x10, + 0x0, 0xa, 0xf1, 0x3, 0x0, 0x1, 0xff, 0xfe, + 0x91, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+51FD "函" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa0, 0x0, + 0x0, 0x9, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xae, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xcf, 0xd6, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0xef, + 0xd5, 0x0, 0x0, 0x0, 0x4, 0x30, 0x3, 0x0, + 0x0, 0x7, 0xff, 0xc4, 0x0, 0x0, 0x3, 0x40, + 0x1f, 0xd0, 0x6f, 0x90, 0x0, 0xb, 0xf5, 0x0, + 0x1, 0xd9, 0xc, 0xf1, 0x1f, 0xd0, 0x1b, 0xfc, + 0x10, 0xb, 0xf2, 0x0, 0x3e, 0xf8, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x9f, 0xe3, 0xb, 0xf2, 0x6, + 0xff, 0x50, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x7, + 0xf4, 0xb, 0xf2, 0x2f, 0xd3, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x0, 0x10, 0xb, 0xf2, 0x3, + 0x10, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x0, + 0x16, 0xb, 0xf2, 0x12, 0x0, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x5, 0xef, 0x3b, 0xf2, 0xbf, + 0x60, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x2, 0xbf, + 0xf7, 0xb, 0xf2, 0x4e, 0xfb, 0x10, 0xc, 0xf1, + 0x1f, 0xd0, 0x8f, 0xfb, 0x10, 0xb, 0xf2, 0x1, + 0xbf, 0xe4, 0xc, 0xf1, 0x1f, 0xd5, 0xfe, 0x50, + 0x0, 0xb, 0xf2, 0x0, 0x7, 0xff, 0x4c, 0xf1, + 0x1f, 0xd0, 0x70, 0x0, 0x0, 0xb, 0xf2, 0x0, + 0x0, 0x38, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x0, + 0x0, 0x2e, 0xf0, 0x0, 0x0, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0xe, 0xff, 0xff, 0xb0, 0x0, + 0x0, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0xa, + 0xcc, 0xb8, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xf1, 0x1f, 0xfa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xae, 0xf1, + 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf1, + + /* U+52A8 "动" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x24, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x22, 0x22, 0x22, 0x22, 0x21, + 0x0, 0x0, 0xaf, 0x20, 0x0, 0x0, 0x0, 0x1, + 0xff, 0xff, 0xff, 0xff, 0xfd, 0x0, 0x0, 0xaf, + 0x20, 0x0, 0x0, 0x0, 0x0, 0xaa, 0xaa, 0xaa, + 0xaa, 0xa8, 0x0, 0x0, 0xbf, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xbf, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2a, 0xaa, 0xef, 0xaa, 0xaa, 0xaf, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0x0, 0x0, 0xd, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x0, 0x0, + 0xd, 0xf0, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xc0, 0x0, 0xee, 0x0, 0x0, 0xd, 0xf0, 0x2a, + 0xaa, 0xaf, 0xfb, 0xaa, 0xaa, 0x80, 0x0, 0xfe, + 0x0, 0x0, 0xe, 0xf0, 0x0, 0x0, 0x3f, 0xd0, + 0x0, 0x0, 0x0, 0x0, 0xfc, 0x0, 0x0, 0xe, + 0xf0, 0x0, 0x0, 0x9f, 0x60, 0x0, 0x0, 0x0, + 0x2, 0xfb, 0x0, 0x0, 0xf, 0xf0, 0x0, 0x0, + 0xff, 0x0, 0x2, 0x0, 0x0, 0x4, 0xf9, 0x0, + 0x0, 0xf, 0xe0, 0x0, 0x5, 0xf9, 0x0, 0xde, + 0x0, 0x0, 0x7, 0xf6, 0x0, 0x0, 0xf, 0xe0, + 0x0, 0xc, 0xf2, 0x0, 0x9f, 0x60, 0x0, 0xa, + 0xf3, 0x0, 0x0, 0x1f, 0xd0, 0x0, 0x3f, 0xa0, + 0x0, 0x2f, 0xd0, 0x0, 0xe, 0xf0, 0x0, 0x0, + 0x1f, 0xd0, 0x0, 0xaf, 0x20, 0x0, 0xa, 0xf4, + 0x0, 0x3f, 0xb0, 0x0, 0x0, 0x2f, 0xc0, 0x3, + 0xfb, 0x0, 0x0, 0x5, 0xfb, 0x0, 0xaf, 0x50, + 0x0, 0x0, 0x3f, 0xc0, 0x1d, 0xfc, 0xbc, 0xef, + 0xff, 0xff, 0x22, 0xfe, 0x0, 0x0, 0x0, 0x4f, + 0xb0, 0xe, 0xff, 0xfd, 0xcb, 0x98, 0x9f, 0x9b, + 0xf7, 0x0, 0x0, 0x0, 0x6f, 0x90, 0x3, 0x31, + 0x0, 0x0, 0x0, 0x4, 0x6f, 0xd0, 0x1, 0x0, + 0x3, 0xef, 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xff, 0x40, 0xe, 0xff, 0xff, 0xfe, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xf9, 0x0, + 0x9, 0xff, 0xfe, 0xb2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x60, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+56DE "回" */ + 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0x1f, 0xfb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbf, 0xf1, + 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x1f, 0xff, 0xff, 0xff, 0xff, + 0xf1, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x1f, + 0xe8, 0x88, 0x88, 0x8d, 0xf1, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x1f, 0xb0, 0x0, 0x0, 0xb, + 0xf1, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x1f, + 0xb0, 0x0, 0x0, 0xb, 0xf1, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x1f, 0xb0, 0x0, 0x0, 0xb, + 0xf1, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x1f, + 0xb0, 0x0, 0x0, 0xb, 0xf1, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x1f, 0xb0, 0x0, 0x0, 0xb, + 0xf1, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x1f, + 0xb0, 0x0, 0x0, 0xb, 0xf1, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x1f, 0xff, 0xff, 0xff, 0xff, + 0xf1, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x9, + 0x99, 0x99, 0x99, 0x99, 0x90, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf1, + 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xf1, 0x1f, 0xd0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf1, + 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0x1f, 0xe9, 0x99, 0x99, + 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9e, 0xf1, + 0x1f, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xf1, + + /* U+5782 "垂" */ + 0x0, 0x0, 0x0, 0x11, 0x11, 0x22, 0x23, 0x34, + 0x55, 0x67, 0x78, 0x93, 0x0, 0x0, 0x6f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x0, 0x0, 0x2a, 0x99, 0x98, 0x87, 0x77, + 0xdf, 0x65, 0x43, 0x32, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0x88, 0x88, 0x88, 0x88, 0x88, 0xdf, + 0x98, 0x88, 0x88, 0x88, 0x88, 0x60, 0x5, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xd0, 0x0, 0x0, 0x4, 0xfa, 0x0, + 0x0, 0xbf, 0x20, 0x0, 0x3f, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x4, 0xf9, 0x0, 0x0, 0xbf, 0x20, + 0x0, 0x3f, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x4, + 0xf9, 0x0, 0x0, 0xbf, 0x20, 0x0, 0x3f, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xf9, 0x0, 0x0, + 0xbf, 0x20, 0x0, 0x3f, 0xa0, 0x0, 0x0, 0x2a, + 0xaa, 0xab, 0xfd, 0xaa, 0xaa, 0xef, 0xaa, 0xaa, + 0xbf, 0xda, 0xaa, 0xa7, 0x3f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfa, 0x0, 0x0, 0x4, 0xf9, 0x0, 0x0, 0xbf, + 0x20, 0x0, 0x3f, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x4, 0xf9, 0x0, 0x0, 0xbf, 0x20, 0x0, 0x3f, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x4, 0xf9, 0x0, + 0x0, 0xbf, 0x20, 0x0, 0x3f, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x4, 0xfa, 0x0, 0x0, 0xbf, 0x20, + 0x0, 0x3f, 0xa0, 0x0, 0x0, 0x7, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xe0, 0x3, 0x88, 0x88, 0x88, 0x88, 0x88, + 0xdf, 0x98, 0x88, 0x88, 0x88, 0x88, 0x70, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x27, 0x77, 0x77, 0x77, 0x77, 0xdf, + 0x87, 0x77, 0x77, 0x77, 0x75, 0x0, 0x0, 0x5f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+5E73 "平" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0x0, 0xac, 0xcc, 0xcc, 0xcc, 0xcc, + 0xff, 0xdc, 0xcc, 0xcc, 0xcc, 0xcc, 0x60, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, + 0x0, 0x0, 0xcf, 0x30, 0x0, 0x0, 0x1, 0x0, + 0x0, 0x0, 0x5, 0xf6, 0x0, 0x0, 0x0, 0xcf, + 0x30, 0x0, 0x0, 0x2e, 0xa0, 0x0, 0x0, 0x3, + 0xff, 0x30, 0x0, 0x0, 0xcf, 0x30, 0x0, 0x0, + 0xdf, 0x90, 0x0, 0x0, 0x0, 0x5f, 0xe2, 0x0, + 0x0, 0xcf, 0x30, 0x0, 0xa, 0xfb, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xfd, 0x0, 0x0, 0xcf, 0x30, + 0x0, 0x8f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xb0, 0x0, 0xcf, 0x30, 0x7, 0xfe, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1e, 0xe2, 0x0, + 0xcf, 0x30, 0x1e, 0xf3, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3, 0x10, 0x0, 0xcf, 0x30, 0x1, + 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1d, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xff, + 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0x1f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+5F0F "式" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x24, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0x60, 0x6, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x7f, 0x60, 0x2f, 0xf5, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0x60, + 0x3, 0xef, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6f, 0x70, 0x0, 0x3e, 0xc0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6f, 0x70, 0x0, 0x3, 0x10, 0x0, 0xaf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf1, 0x7b, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xcf, 0xdb, 0xbb, 0xbb, 0xbb, 0xb1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2f, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xf, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf1, 0xd, 0xf0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xcc, 0xcc, 0xff, 0xcc, 0xcc, 0xc1, + 0xb, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xdf, 0x10, 0x0, 0x0, 0x9, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x10, + 0x0, 0x0, 0x7, 0xf7, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0x10, 0x0, 0x0, 0x3, + 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0x10, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x10, 0x0, + 0x0, 0x0, 0xbf, 0x20, 0x0, 0x5, 0x81, 0x0, + 0x0, 0x0, 0xdf, 0x10, 0x0, 0x13, 0x10, 0x6f, + 0x80, 0x0, 0x9, 0xf3, 0x0, 0x0, 0x13, 0xdf, + 0x9a, 0xce, 0xff, 0x30, 0x1f, 0xe0, 0x0, 0xb, + 0xf0, 0x6c, 0xef, 0xff, 0xff, 0xff, 0xec, 0xa8, + 0x10, 0x9, 0xf7, 0x0, 0xf, 0xc0, 0x6f, 0xec, + 0xa8, 0x64, 0x20, 0x0, 0x0, 0x0, 0x1, 0xef, + 0x40, 0x6f, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xfd, 0xff, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3, 0xbe, 0xc3, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+6027 "性" */ + 0x0, 0x0, 0xbb, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x7c, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x5, + 0xb4, 0x0, 0xaf, 0x40, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xfe, 0x0, 0x0, 0xa, 0xf4, 0x0, 0xaf, + 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, + 0x0, 0xe, 0xf0, 0x0, 0xaf, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xfe, 0xd5, 0x0, 0x3f, 0xc0, + 0x0, 0xaf, 0x40, 0x0, 0x0, 0x0, 0x6, 0x80, + 0xfe, 0xdf, 0x20, 0x8f, 0xed, 0xdd, 0xff, 0xed, + 0xdd, 0xdd, 0xa0, 0xa, 0xc0, 0xfe, 0x3f, 0xd0, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, + 0xd, 0xa0, 0xfe, 0x7, 0x75, 0xfb, 0x0, 0x0, + 0xaf, 0x40, 0x0, 0x0, 0x0, 0xf, 0x70, 0xfe, + 0x0, 0xb, 0xf4, 0x0, 0x0, 0xaf, 0x40, 0x0, + 0x0, 0x0, 0x2f, 0x50, 0xfe, 0x0, 0x3f, 0xd0, + 0x0, 0x0, 0xaf, 0x40, 0x0, 0x0, 0x0, 0x5f, + 0x20, 0xfe, 0x0, 0x4d, 0x60, 0x0, 0x0, 0xaf, + 0x40, 0x0, 0x0, 0x0, 0x5c, 0x0, 0xfe, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xaf, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xfe, 0x0, 0x3, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x60, 0x0, 0x0, 0xfe, 0x0, 0x2, + 0xcc, 0xcc, 0xcc, 0xef, 0xdc, 0xcc, 0xcc, 0x40, + 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xaf, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x40, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xaf, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xfe, 0x0, 0xab, 0xbb, 0xbb, 0xbb, 0xef, 0xdb, + 0xbb, 0xbb, 0xb4, 0x0, 0x0, 0xfe, 0x0, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+624B "手" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x12, 0x34, 0x50, 0x0, 0x0, 0x59, 0x99, + 0xaa, 0xab, 0xbc, 0xcd, 0xee, 0xff, 0xff, 0xff, + 0xf4, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xed, 0xcc, 0xba, 0x98, 0x73, 0x0, 0x0, + 0x13, 0x33, 0x22, 0x11, 0x0, 0xaf, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x50, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0x50, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0x11, 0x11, 0x11, + 0x11, 0xaf, 0x61, 0x11, 0x11, 0x11, 0x10, 0x0, + 0x0, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x3b, 0xbb, + 0xbb, 0xbb, 0xbb, 0xef, 0xcb, 0xbb, 0xbb, 0xbb, + 0xb5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xaf, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x50, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2c, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xef, 0xdc, 0xcc, 0xcc, + 0xcc, 0xcc, 0xc9, 0x3f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0x50, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xaf, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0x50, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, + 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8e, 0xed, 0xef, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, + 0xfe, 0xb2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+62E9 "择" */ + 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfd, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xfd, 0x0, 0x7, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x10, 0x0, + 0x0, 0xfd, 0x0, 0x4, 0x9f, 0xf9, 0x99, 0x99, + 0x99, 0x9a, 0xff, 0x0, 0x0, 0x0, 0xfd, 0x0, + 0x0, 0x6, 0xfa, 0x0, 0x0, 0x0, 0x1d, 0xf6, + 0x0, 0x2a, 0xaa, 0xff, 0xaa, 0x90, 0x0, 0xaf, + 0x90, 0x0, 0x1, 0xdf, 0x80, 0x0, 0x3f, 0xff, + 0xff, 0xff, 0xe0, 0x0, 0xb, 0xfb, 0x0, 0x3e, + 0xf8, 0x0, 0x0, 0x0, 0x0, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0xea, 0xff, 0x60, 0x0, 0x0, + 0x0, 0x0, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x3d, + 0xff, 0xf9, 0x10, 0x0, 0x0, 0x0, 0x0, 0xfd, + 0x0, 0x0, 0x4, 0x8d, 0xff, 0xd9, 0xff, 0xfc, + 0x84, 0x10, 0x0, 0x0, 0xfd, 0x0, 0xb, 0xff, + 0xff, 0xa4, 0x0, 0x6, 0xbf, 0xff, 0xf6, 0x0, + 0x0, 0xfd, 0x0, 0x18, 0xea, 0x50, 0x0, 0x69, + 0x0, 0x0, 0x48, 0xb0, 0x0, 0x0, 0xfe, 0x8d, + 0xa0, 0x0, 0x0, 0x0, 0xcf, 0x10, 0x0, 0x0, + 0x0, 0x2, 0x6b, 0xff, 0xff, 0xa0, 0x0, 0x0, + 0x0, 0xcf, 0x10, 0x0, 0x0, 0x0, 0x5f, 0xff, + 0xfe, 0x72, 0x2, 0x99, 0x99, 0x99, 0xef, 0xa9, + 0x99, 0x99, 0x50, 0x4e, 0xa5, 0xfd, 0x0, 0x4, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, + 0x0, 0x0, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfd, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xfd, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xfd, 0x0, 0x7a, 0xaa, 0xaa, 0xaa, 0xef, + 0xaa, 0xaa, 0xaa, 0xa7, 0x0, 0x0, 0xfd, 0x0, + 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfb, 0x0, 0x0, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0x10, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0x10, + 0x0, 0x0, 0x0, 0x2d, 0xdf, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0x10, 0x0, 0x0, 0x0, + 0x1f, 0xfe, 0xb1, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+653E "放" */ + 0x0, 0x0, 0x1, 0x52, 0x0, 0x0, 0x0, 0x0, + 0x46, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xff, 0x0, 0x0, + 0x0, 0x2, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0x40, 0x0, 0x0, 0x7, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, + 0x70, 0x0, 0x0, 0xd, 0xf2, 0x0, 0x0, 0x0, + 0x0, 0x1e, 0xee, 0xee, 0xef, 0xee, 0xee, 0xb0, + 0x3f, 0xfc, 0xcc, 0xcc, 0xcc, 0xc9, 0x1d, 0xdd, + 0xfe, 0xdd, 0xdd, 0xdd, 0xa0, 0xaf, 0xff, 0xff, + 0xff, 0xff, 0xfc, 0x0, 0x4, 0xf6, 0x0, 0x0, + 0x0, 0x2, 0xfe, 0x0, 0x0, 0x3, 0xf9, 0x0, + 0x0, 0x4, 0xf6, 0x0, 0x0, 0x0, 0xb, 0xff, + 0x0, 0x0, 0x5, 0xf7, 0x0, 0x0, 0x5, 0xf6, + 0x0, 0x0, 0x0, 0x4f, 0xff, 0x20, 0x0, 0x7, + 0xf5, 0x0, 0x0, 0x6, 0xf5, 0x0, 0x0, 0x1, + 0xef, 0x9f, 0x50, 0x0, 0xa, 0xf3, 0x0, 0x0, + 0x6, 0xfd, 0xcc, 0xcc, 0xc6, 0xf9, 0x3f, 0x80, + 0x0, 0xe, 0xf0, 0x0, 0x0, 0x7, 0xff, 0xff, + 0xff, 0xf5, 0x41, 0xf, 0xc0, 0x0, 0x1f, 0xb0, + 0x0, 0x0, 0x8, 0xf2, 0x0, 0x8, 0xf4, 0x0, + 0xb, 0xf1, 0x0, 0x7f, 0x70, 0x0, 0x0, 0x9, + 0xf1, 0x0, 0x8, 0xf4, 0x0, 0x7, 0xf7, 0x0, + 0xdf, 0x20, 0x0, 0x0, 0xb, 0xf0, 0x0, 0x8, + 0xf3, 0x0, 0x1, 0xfd, 0x3, 0xfc, 0x0, 0x0, + 0x0, 0xd, 0xe0, 0x0, 0x9, 0xf3, 0x0, 0x0, + 0xbf, 0x6c, 0xf5, 0x0, 0x0, 0x0, 0xf, 0xc0, + 0x0, 0xa, 0xf2, 0x0, 0x0, 0x3f, 0xff, 0xc0, + 0x0, 0x0, 0x0, 0x2f, 0x90, 0x0, 0xa, 0xf2, + 0x0, 0x0, 0xa, 0xff, 0x30, 0x0, 0x0, 0x0, + 0x6f, 0x60, 0x0, 0xb, 0xf1, 0x0, 0x0, 0x1d, + 0xff, 0x60, 0x0, 0x0, 0x0, 0xbf, 0x20, 0x0, + 0xc, 0xf1, 0x0, 0x2, 0xdf, 0xdf, 0xf6, 0x0, + 0x0, 0x1, 0xfd, 0x0, 0x0, 0xe, 0xf0, 0x0, + 0x4f, 0xfc, 0x5, 0xff, 0x90, 0x0, 0x9, 0xf7, + 0x1, 0x11, 0x7f, 0xd0, 0x9, 0xff, 0xb0, 0x0, + 0x4f, 0xfd, 0x30, 0x2f, 0xe1, 0xe, 0xff, 0xff, + 0x64, 0xef, 0xf9, 0x0, 0x0, 0x3, 0xef, 0xf8, + 0x3f, 0x70, 0x9, 0xcb, 0x94, 0x7, 0xfe, 0x50, + 0x0, 0x0, 0x0, 0x1a, 0xf3, 0x2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x71, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x20, + + /* U+6570 "数" */ + 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, + 0x3, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1f, 0x90, 0x0, 0x0, 0x0, 0xc, 0xf0, 0x0, + 0x0, 0x0, 0x1, 0xd6, 0x0, 0x1f, 0x90, 0x1, + 0xd6, 0x0, 0xf, 0xb0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0x60, 0x1f, 0x90, 0x1d, 0xf4, 0x0, 0x5f, + 0x60, 0x0, 0x0, 0x0, 0x0, 0xc, 0xf5, 0x1f, + 0x91, 0xdf, 0x40, 0x0, 0xbf, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xa1, 0x1f, 0x90, 0x94, 0x0, + 0x1, 0xff, 0xcc, 0xcc, 0xcc, 0xc4, 0x7, 0x77, + 0x77, 0x8f, 0xc7, 0x77, 0x75, 0x7, 0xff, 0xff, + 0xff, 0xff, 0xf5, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfc, 0xe, 0xe0, 0x0, 0x7, 0xf4, 0x0, + 0x1, 0x11, 0x12, 0xdf, 0xa1, 0x11, 0x10, 0x6f, + 0xd0, 0x0, 0x8, 0xf2, 0x0, 0x0, 0x0, 0x2d, + 0xef, 0xa6, 0x0, 0x0, 0xef, 0xf0, 0x0, 0xa, + 0xf0, 0x0, 0x0, 0x5, 0xee, 0x3f, 0xef, 0xe5, + 0x8, 0xfd, 0xf2, 0x0, 0xd, 0xd0, 0x0, 0x3, + 0xbf, 0xc1, 0x1f, 0x93, 0xdf, 0xba, 0xd4, 0xf5, + 0x0, 0xf, 0xa0, 0x0, 0x1e, 0xf8, 0x0, 0xf, + 0x90, 0x8, 0xd1, 0x21, 0xf9, 0x0, 0x3f, 0x70, + 0x0, 0x4, 0x10, 0x1, 0x73, 0x0, 0x0, 0x0, + 0x0, 0xdd, 0x0, 0x8f, 0x30, 0x0, 0x0, 0x0, + 0xb, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x9f, 0x30, + 0xde, 0x0, 0x0, 0x3f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xe0, 0x0, 0x4f, 0x93, 0xf9, 0x0, 0x0, + 0x18, 0x89, 0xfd, 0x88, 0x88, 0x8f, 0xe0, 0x0, + 0xe, 0xfc, 0xf3, 0x0, 0x0, 0x0, 0xb, 0xf3, + 0x0, 0x0, 0x5f, 0x90, 0x0, 0x7, 0xff, 0xb0, + 0x0, 0x0, 0x0, 0x6f, 0xd2, 0x0, 0x0, 0xdf, + 0x20, 0x0, 0x1, 0xff, 0x60, 0x0, 0x0, 0x0, + 0x18, 0xef, 0xc5, 0xa, 0xf7, 0x0, 0x0, 0xb, + 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, 0x6, 0xef, + 0xff, 0xa0, 0x0, 0x0, 0xaf, 0xd8, 0xfd, 0x10, + 0x0, 0x0, 0x0, 0x1, 0x8f, 0xff, 0xf9, 0x20, + 0xa, 0xfe, 0x20, 0xaf, 0xd2, 0x0, 0x0, 0x4, + 0xaf, 0xfd, 0x35, 0xdf, 0xc1, 0xcf, 0xe2, 0x0, + 0xa, 0xfe, 0x50, 0x3b, 0xff, 0xfd, 0x60, 0x0, + 0x5, 0x5e, 0xfd, 0x20, 0x0, 0x0, 0x9f, 0xf4, + 0x1f, 0xe9, 0x30, 0x0, 0x0, 0x0, 0x1d, 0xb1, + 0x0, 0x0, 0x0, 0x6, 0xa0, 0x1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+6A21 "模" */ + 0x0, 0x1, 0xa6, 0x0, 0x0, 0x0, 0x29, 0x30, + 0x0, 0x9, 0x60, 0x0, 0x0, 0x0, 0x2, 0xf9, + 0x0, 0x0, 0x0, 0x4f, 0x60, 0x0, 0x1f, 0xa0, + 0x0, 0x0, 0x0, 0x2, 0xf9, 0x0, 0x45, 0x55, + 0x8f, 0x95, 0x55, 0x6f, 0xc5, 0x55, 0x51, 0x0, + 0x2, 0xf9, 0x0, 0xcf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf3, 0x0, 0x2, 0xf9, 0x0, + 0x23, 0x33, 0x7f, 0x83, 0x33, 0x4f, 0xb3, 0x33, + 0x30, 0x19, 0x9a, 0xfd, 0x99, 0x10, 0x0, 0x4f, + 0x60, 0x0, 0x1f, 0xa0, 0x0, 0x0, 0x3f, 0xff, + 0xff, 0xff, 0x30, 0x0, 0x2, 0x10, 0x0, 0x2, + 0x10, 0x0, 0x0, 0x17, 0x79, 0xfc, 0x77, 0x10, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x74, 0x0, + 0x0, 0x7, 0xf9, 0x0, 0x1, 0xff, 0xee, 0xee, + 0xee, 0xee, 0xee, 0xfa, 0x0, 0x0, 0xb, 0xf9, + 0x0, 0x1, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xfa, 0x0, 0x0, 0x1f, 0xfb, 0x10, 0x1, 0xfb, + 0x11, 0x11, 0x11, 0x11, 0x12, 0xfa, 0x0, 0x0, + 0x7f, 0xff, 0xd2, 0x1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfa, 0x0, 0x0, 0xda, 0xfc, 0xfe, + 0x31, 0xfc, 0x33, 0x33, 0x33, 0x33, 0x34, 0xfa, + 0x0, 0x5, 0xf5, 0xf9, 0x4f, 0xe2, 0xfb, 0x0, + 0x0, 0x0, 0x0, 0x1, 0xfa, 0x0, 0xd, 0xc2, + 0xf9, 0x5, 0x51, 0xfd, 0x77, 0x77, 0x77, 0x77, + 0x78, 0xfa, 0x0, 0x6f, 0x52, 0xf9, 0x0, 0x1, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, + 0x8d, 0x2, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x45, 0x2, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0xf9, 0x2, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x2, 0xf9, 0x1, 0x88, 0x88, 0x88, 0x9f, 0xff, + 0x98, 0x88, 0x88, 0x82, 0x0, 0x2, 0xf9, 0x0, + 0x0, 0x0, 0x0, 0x9f, 0xaf, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xf9, 0x0, 0x0, 0x0, 0x2b, + 0xfb, 0x7, 0xfd, 0x40, 0x0, 0x0, 0x0, 0x2, + 0xf9, 0x0, 0x0, 0x5a, 0xff, 0x90, 0x0, 0x5e, + 0xfc, 0x73, 0x0, 0x0, 0x2, 0xf9, 0x6, 0xcf, + 0xff, 0xb3, 0x0, 0x0, 0x1, 0x8e, 0xff, 0xf6, + 0x0, 0x2, 0xf9, 0x3, 0xfd, 0x82, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x48, 0xb0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+6C34 "水" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x33, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xff, + 0x10, 0x0, 0x0, 0x5, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0xff, 0x80, 0x0, 0x0, + 0x5f, 0xf6, 0x0, 0xe, 0xff, 0xff, 0xff, 0xf7, + 0x1, 0xff, 0xe0, 0x0, 0x5, 0xff, 0x70, 0x0, + 0xa, 0xbb, 0xbb, 0xbe, 0xf6, 0x1, 0xff, 0xf6, + 0x0, 0x7f, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xf2, 0x1, 0xfd, 0xdd, 0x9, 0xff, 0x50, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x1, + 0xfd, 0x7f, 0xdf, 0xe3, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0x90, 0x1, 0xfd, 0xe, 0xfc, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, + 0x40, 0x1, 0xfd, 0x7, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xfd, 0x0, 0x1, 0xfd, + 0x0, 0xdf, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xb, 0xf6, 0x0, 0x1, 0xfd, 0x0, 0x4f, 0xe1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xe0, 0x0, + 0x1, 0xfd, 0x0, 0x9, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0x70, 0x0, 0x1, 0xfd, 0x0, + 0x0, 0xdf, 0xb0, 0x0, 0x0, 0x0, 0x8, 0xfd, + 0x0, 0x0, 0x1, 0xfd, 0x0, 0x0, 0x1e, 0xfa, + 0x0, 0x0, 0x0, 0x5f, 0xf3, 0x0, 0x0, 0x1, + 0xfd, 0x0, 0x0, 0x3, 0xff, 0xb0, 0x0, 0x3, + 0xff, 0x70, 0x0, 0x0, 0x1, 0xfd, 0x0, 0x0, + 0x0, 0x3f, 0xfd, 0x20, 0x2e, 0xfa, 0x0, 0x0, + 0x0, 0x1, 0xfd, 0x0, 0x0, 0x0, 0x3, 0xef, + 0xf3, 0x9f, 0xc0, 0x0, 0x0, 0x0, 0x2, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x2d, 0xd0, 0xa, 0x10, + 0x0, 0x0, 0x0, 0x9, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x20, 0x0, 0x0, 0x0, 0x3e, 0xed, + 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xff, 0xfc, 0x60, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+6F14 "演" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x25, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x74, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0x80, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xff, 0x50, 0x0, 0x0, 0x0, + 0x0, 0x2f, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xf6, 0x8, 0x99, 0x99, 0x99, 0x9f, 0xf9, + 0x99, 0x99, 0x99, 0x70, 0x0, 0x4, 0xff, 0x2f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xc0, 0x0, 0x0, 0x43, 0xf, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xc0, 0x0, 0x0, + 0x0, 0xf, 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xf, 0xc0, 0x0, 0x0, 0x0, 0x6, 0x55, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x36, 0x50, + 0x1d, 0xb0, 0x0, 0x0, 0x2, 0x88, 0x88, 0x8f, + 0xd8, 0x88, 0x88, 0x20, 0x0, 0xa, 0xfc, 0x10, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0xd1, 0x0, 0x23, 0x33, + 0x33, 0x3f, 0xc3, 0x33, 0x33, 0x32, 0x0, 0x0, + 0xb, 0xe3, 0x0, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfa, 0x0, 0x0, 0x0, 0x10, 0x0, + 0xdf, 0x33, 0x33, 0x3f, 0xc3, 0x33, 0x34, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x0, 0x0, + 0xf, 0xb0, 0x0, 0x1, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0x33, 0x33, 0x3f, 0xc3, 0x33, + 0x34, 0xfa, 0x0, 0x0, 0x6, 0xd4, 0x0, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, + 0x0, 0xb, 0xf4, 0x0, 0xdf, 0x11, 0x11, 0x1f, + 0xb1, 0x11, 0x12, 0xfa, 0x0, 0x0, 0xf, 0xf0, + 0x0, 0xdf, 0x0, 0x0, 0xf, 0xb0, 0x0, 0x1, + 0xfa, 0x0, 0x0, 0x4f, 0xb0, 0x0, 0xdf, 0x55, + 0x55, 0x5f, 0xc5, 0x55, 0x56, 0xfa, 0x0, 0x0, + 0x8f, 0x60, 0x0, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfa, 0x0, 0x0, 0xdf, 0x10, 0x0, + 0x12, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, + 0x0, 0x2, 0xfd, 0x0, 0x0, 0x0, 0x5, 0xca, + 0x0, 0x2, 0xea, 0x40, 0x0, 0x0, 0x7, 0xf8, + 0x0, 0x0, 0x18, 0xef, 0xf9, 0x0, 0x3, 0xbf, + 0xfe, 0x71, 0x0, 0xc, 0xf4, 0x0, 0x5a, 0xff, + 0xe7, 0x10, 0x0, 0x0, 0x2, 0x8e, 0xff, 0xb2, + 0xb, 0xe0, 0x0, 0xaf, 0xc5, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5c, 0xe0, 0x0, 0x0, 0x0, + 0x13, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x10, + + /* U+753B "画" */ + 0x4f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf3, 0x3c, 0xcc, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, + 0xcc, 0xc2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x86, 0x0, 0x19, + 0x99, 0x99, 0x99, 0x99, 0x99, 0x91, 0x0, 0x77, + 0x0, 0x0, 0xfd, 0x0, 0x3f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf2, 0x0, 0xdf, 0x0, 0x0, 0xfd, + 0x0, 0x3f, 0x80, 0x0, 0xdc, 0x0, 0x9, 0xf2, + 0x0, 0xdf, 0x0, 0x0, 0xfd, 0x0, 0x3f, 0x80, + 0x0, 0xdc, 0x0, 0x9, 0xf2, 0x0, 0xdf, 0x0, + 0x0, 0xfd, 0x0, 0x3f, 0x80, 0x0, 0xdc, 0x0, + 0x9, 0xf2, 0x0, 0xdf, 0x0, 0x0, 0xfd, 0x0, + 0x3f, 0x80, 0x0, 0xdc, 0x0, 0x9, 0xf2, 0x0, + 0xdf, 0x0, 0x0, 0xfd, 0x0, 0x3f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf2, 0x0, 0xdf, 0x0, 0x0, + 0xfd, 0x0, 0x3f, 0xc8, 0x88, 0xee, 0x88, 0x8c, + 0xf2, 0x0, 0xdf, 0x0, 0x0, 0xfd, 0x0, 0x3f, + 0x80, 0x0, 0xdc, 0x0, 0x9, 0xf2, 0x0, 0xdf, + 0x0, 0x0, 0xfd, 0x0, 0x3f, 0x80, 0x0, 0xdc, + 0x0, 0x9, 0xf2, 0x0, 0xdf, 0x0, 0x0, 0xfd, + 0x0, 0x3f, 0x80, 0x0, 0xdc, 0x0, 0x9, 0xf2, + 0x0, 0xdf, 0x0, 0x0, 0xfd, 0x0, 0x3f, 0x80, + 0x0, 0xdc, 0x0, 0x9, 0xf2, 0x0, 0xdf, 0x0, + 0x0, 0xfd, 0x0, 0x3f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf2, 0x0, 0xdf, 0x0, 0x0, 0xfd, 0x0, + 0x17, 0x77, 0x77, 0x77, 0x77, 0x77, 0x71, 0x0, + 0xdf, 0x0, 0x0, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x0, 0x0, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0x0, 0x0, 0xff, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xff, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xdf, 0x0, + + /* U+76F4 "直" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x45, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0x20, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf2, 0x5, 0x88, 0x88, 0x88, + 0x88, 0x88, 0xdf, 0x98, 0x88, 0x88, 0x88, 0x88, + 0x81, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x0, + 0x0, 0x0, 0xff, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0xbf, 0x50, 0x0, 0x0, 0x0, 0xfe, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0x50, 0x0, 0x0, 0x0, 0xfe, 0x11, 0x11, 0x11, + 0x11, 0x11, 0x11, 0x11, 0x8f, 0x50, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, 0xff, 0x55, + 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xaf, 0x50, + 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8f, 0x50, 0x0, 0x0, 0x0, + 0xfe, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x9f, 0x50, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x0, + 0x0, 0x0, 0xff, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0xaf, 0x50, 0x0, 0x0, 0x0, 0xfe, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0x50, 0x0, 0x0, 0x0, 0xff, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, 0x9f, 0x50, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, 0xfe, 0x33, + 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x9f, 0x50, + 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8f, 0x50, 0x0, 0x28, 0x88, + 0xff, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0xcf, 0xa8, 0x86, 0x4f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+793A "示" */ + 0x0, 0x7, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xd1, 0x0, 0x0, 0x9, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4d, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xda, + 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x7f, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x20, 0x0, 0x0, 0x7f, 0x80, 0x0, + 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0xf9, + 0x0, 0x0, 0x7f, 0x80, 0x0, 0x6f, 0x70, 0x0, + 0x0, 0x0, 0x0, 0xe, 0xf7, 0x0, 0x0, 0x7f, + 0x80, 0x0, 0x3f, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x8f, 0xd0, 0x0, 0x0, 0x7f, 0x80, 0x0, 0x7, + 0xfe, 0x10, 0x0, 0x0, 0x3, 0xff, 0x30, 0x0, + 0x0, 0x7f, 0x80, 0x0, 0x0, 0xaf, 0xc0, 0x0, + 0x0, 0xd, 0xf8, 0x0, 0x0, 0x0, 0x7f, 0x80, + 0x0, 0x0, 0xd, 0xf9, 0x0, 0x0, 0x9f, 0xd0, + 0x0, 0x0, 0x0, 0x7f, 0x80, 0x0, 0x0, 0x3, + 0xff, 0x50, 0x4, 0xff, 0x30, 0x0, 0x0, 0x0, + 0x7f, 0x80, 0x0, 0x0, 0x0, 0x7f, 0xf2, 0x1e, + 0xf7, 0x0, 0x0, 0x0, 0x0, 0x7f, 0x80, 0x0, + 0x0, 0x0, 0xb, 0xf6, 0x9, 0xc0, 0x0, 0x0, + 0x0, 0x1, 0xcf, 0x70, 0x0, 0x0, 0x0, 0x1, + 0x40, 0x0, 0x0, 0x0, 0x9, 0xff, 0xff, 0xff, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xff, 0xff, 0xc5, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+7D20 "素" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x47, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0x20, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x22, 0x22, 0x22, 0x22, 0x22, + 0xbf, 0x42, 0x22, 0x22, 0x22, 0x22, 0x10, 0x2, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x44, 0x44, 0x44, + 0x44, 0x44, 0xcf, 0x64, 0x44, 0x44, 0x44, 0x44, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x0, 0x0, 0x4, 0x66, 0x66, 0x66, + 0x66, 0xcf, 0x76, 0x66, 0x66, 0x66, 0x60, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0x20, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x77, 0x77, + 0x77, 0x77, 0x77, 0xdf, 0x97, 0x77, 0x77, 0x77, + 0x77, 0x73, 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x0, + 0x0, 0x0, 0x0, 0x5a, 0xfe, 0xa2, 0x0, 0x0, + 0x34, 0x0, 0x0, 0x0, 0x0, 0x0, 0x36, 0xbf, + 0xc8, 0x30, 0x0, 0x2, 0x7d, 0xfe, 0x40, 0x0, + 0x0, 0x0, 0x7, 0xff, 0xfe, 0xde, 0xef, 0xff, + 0xff, 0xfa, 0x40, 0x0, 0x0, 0x0, 0x0, 0x1, + 0x87, 0x65, 0x54, 0x8d, 0xff, 0xc6, 0x10, 0x70, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x8e, + 0xfc, 0x72, 0x0, 0x7, 0xfe, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x38, 0xdf, 0xd7, 0x20, 0x0, 0x0, + 0x0, 0x5f, 0xf9, 0x0, 0x0, 0x0, 0x3e, 0xff, + 0xfd, 0xbb, 0xcc, 0xde, 0xee, 0xff, 0xff, 0xff, + 0xd2, 0x0, 0x0, 0xc, 0xcb, 0xaa, 0x99, 0x88, + 0xbf, 0xa6, 0x65, 0x54, 0x47, 0xff, 0x10, 0x0, + 0x0, 0x0, 0x3, 0x0, 0x0, 0x6f, 0x70, 0x0, + 0x40, 0x0, 0x46, 0x0, 0x0, 0x0, 0x3, 0xbf, + 0x80, 0x0, 0x6f, 0x70, 0x6, 0xfe, 0x71, 0x0, + 0x0, 0x0, 0x5, 0xcf, 0xfb, 0x30, 0x0, 0x6f, + 0x60, 0x1, 0x8f, 0xff, 0x92, 0x0, 0x19, 0xff, + 0xfa, 0x30, 0x0, 0x0, 0x8f, 0x60, 0x0, 0x1, + 0x7e, 0xff, 0xa2, 0xd, 0xe8, 0x10, 0x0, 0x8a, + 0xab, 0xff, 0x20, 0x0, 0x0, 0x0, 0x5d, 0xf2, + 0x2, 0x0, 0x0, 0x0, 0xaf, 0xfe, 0xd5, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x20, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+7EBF "线" */ + 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x32, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, + 0xf3, 0x0, 0x0, 0x2, 0xfb, 0x0, 0x57, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xc0, 0x0, 0x0, + 0x2, 0xfb, 0x0, 0xcf, 0xb1, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0x30, 0x0, 0x0, 0x2, 0xfb, 0x0, + 0x9, 0xfe, 0x30, 0x0, 0x0, 0x5, 0xf9, 0x0, + 0x0, 0x0, 0x1, 0xfc, 0x0, 0x0, 0x5e, 0x20, + 0x0, 0x0, 0xe, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0xfd, 0x0, 0x0, 0x1, 0x35, 0x50, 0x0, 0x8f, + 0x50, 0x4, 0xa2, 0x0, 0x2, 0xfe, 0x8a, 0xcd, + 0xff, 0xff, 0xd0, 0x3, 0xfb, 0x0, 0xd, 0xf4, + 0xde, 0xff, 0xff, 0xff, 0xec, 0xa8, 0x65, 0x20, + 0x1e, 0xf2, 0x1, 0x7f, 0x90, 0xbb, 0x97, 0xef, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, 0xff, + 0xfe, 0x0, 0x0, 0x0, 0xbf, 0x10, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xa9, 0x9e, 0xf4, 0x0, 0x0, + 0x0, 0xaf, 0x30, 0x0, 0x0, 0x0, 0x11, 0x0, + 0x0, 0x5f, 0xa0, 0x0, 0x0, 0x0, 0x8f, 0x51, + 0x36, 0x8a, 0xcf, 0xf8, 0x0, 0x1, 0xee, 0x0, + 0x0, 0x14, 0x68, 0xcf, 0xff, 0xff, 0xff, 0xdb, + 0x94, 0x0, 0xb, 0xf4, 0x0, 0x4, 0xff, 0xff, + 0xff, 0xe8, 0x64, 0x20, 0x0, 0x0, 0x0, 0x7f, + 0x80, 0x0, 0x1, 0x86, 0x31, 0xf, 0xd0, 0x0, + 0x0, 0xb8, 0x0, 0x6, 0xff, 0x66, 0x89, 0x90, + 0x0, 0x0, 0xc, 0xf1, 0x0, 0xc, 0xfa, 0x0, + 0xd, 0xff, 0xff, 0xff, 0xb0, 0x0, 0x0, 0x8, + 0xf5, 0x1, 0xcf, 0x90, 0x0, 0x5, 0x86, 0x42, + 0x10, 0x0, 0x0, 0x0, 0x3, 0xfa, 0x4e, 0xf7, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xef, 0xff, 0x50, 0x0, 0x82, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0xef, + 0xd2, 0x0, 0x1, 0xfb, 0x0, 0x1, 0x46, 0x9b, + 0xe5, 0x0, 0x3, 0xbf, 0xff, 0xe0, 0x0, 0x5, + 0xf8, 0x3d, 0xff, 0xff, 0xff, 0xd3, 0x5, 0xcf, + 0xfb, 0x2b, 0xf9, 0x0, 0x8, 0xf4, 0x1f, 0xeb, + 0x85, 0x30, 0x18, 0xef, 0xfc, 0x40, 0x1, 0xef, + 0x80, 0x1e, 0xf0, 0x1, 0x0, 0x0, 0x0, 0xd, + 0xfb, 0x40, 0x0, 0x0, 0x3f, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x2, 0x20, 0x0, 0x0, + 0x0, 0x2, 0xae, 0xe9, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+7F29 "缩" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x12, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6d, + 0x50, 0x0, 0x0, 0x0, 0x2, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xdf, 0x30, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x5, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, + 0x80, 0x0, 0x0, 0x0, 0x0, 0xd, 0xf2, 0x0, + 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe0, 0x0, 0x6f, 0x90, 0x0, 0xe, 0xe8, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x8e, 0xe0, 0x0, 0xee, + 0x10, 0x15, 0xe, 0xd0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xd, 0xe0, 0x8, 0xf6, 0x0, 0x9f, 0x6b, + 0xa4, 0xb3, 0x0, 0x0, 0x0, 0x0, 0x5, 0x50, + 0x3f, 0xc0, 0x2, 0xfd, 0x0, 0xa, 0xf4, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xc1, 0x9f, 0xff, 0xff, + 0xf4, 0x0, 0x1f, 0x92, 0xaa, 0xaa, 0xef, 0xba, + 0xaa, 0xa1, 0x4c, 0xa9, 0xcf, 0xa0, 0x0, 0x9f, + 0x20, 0x0, 0x0, 0xdf, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xef, 0x10, 0x2, 0xfe, 0x0, 0x0, 0x0, + 0xfb, 0x0, 0x0, 0x0, 0x0, 0x8, 0xf6, 0x0, + 0xb, 0xfe, 0x0, 0x48, 0x89, 0xfc, 0x88, 0x88, + 0x0, 0x0, 0x2f, 0xc0, 0x0, 0x6f, 0xfe, 0x0, + 0x9f, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0xbf, + 0x20, 0x2, 0xfe, 0xde, 0x0, 0x9f, 0x10, 0x0, + 0x0, 0xbf, 0x0, 0x8, 0xf7, 0x2, 0x46, 0xf4, + 0xce, 0x0, 0x9f, 0x10, 0x0, 0x0, 0xbf, 0x0, + 0x2f, 0xfe, 0xff, 0xf4, 0x50, 0xce, 0x0, 0x9f, + 0x10, 0x0, 0x0, 0xbf, 0x0, 0xd, 0xdb, 0x97, + 0x50, 0x0, 0xce, 0x0, 0x9f, 0x88, 0x88, 0x88, + 0xdf, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xce, + 0x0, 0x9f, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xce, 0x0, 0x9f, 0x10, + 0x0, 0x0, 0xbf, 0x0, 0x0, 0x0, 0x1, 0x46, + 0x0, 0xce, 0x0, 0x9f, 0x10, 0x0, 0x0, 0xbf, + 0x0, 0x48, 0xbd, 0xff, 0xff, 0x0, 0xce, 0x0, + 0x9f, 0x10, 0x0, 0x0, 0xbf, 0x0, 0x7f, 0xfe, + 0xc9, 0x74, 0x0, 0xce, 0x0, 0x9f, 0x88, 0x88, + 0x88, 0xdf, 0x0, 0x23, 0x10, 0x0, 0x0, 0x0, + 0xce, 0x0, 0x9f, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xce, 0x0, 0x9f, + 0x10, 0x0, 0x0, 0xaf, 0x0, + + /* U+8FD4 "返" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8c, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x12, 0x46, 0x79, + 0xab, 0x0, 0x0, 0x9f, 0x90, 0x0, 0x9, 0xde, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0x20, 0x0, + 0xd, 0xf5, 0x0, 0xb, 0xfc, 0xba, 0xa9, 0x87, + 0x65, 0x32, 0x0, 0x0, 0x0, 0x3, 0xfe, 0x10, + 0xb, 0xf2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9f, 0x60, 0xb, 0xf2, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3, 0x0, 0xb, 0xf2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, + 0xf9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x93, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf6, 0x0, 0x6a, 0xaa, 0xa1, + 0x0, 0xb, 0xf2, 0x11, 0x11, 0x11, 0x11, 0x1b, + 0xf5, 0x0, 0xaf, 0xff, 0xf3, 0x0, 0xc, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x2f, 0xe0, 0x0, 0x12, + 0x2b, 0xf3, 0x0, 0xd, 0xf0, 0x7e, 0x30, 0x0, + 0x0, 0xaf, 0x60, 0x0, 0x0, 0xa, 0xf3, 0x0, + 0xf, 0xd0, 0x6f, 0xf6, 0x0, 0x4, 0xfd, 0x0, + 0x0, 0x0, 0xa, 0xf3, 0x0, 0x2f, 0xa0, 0x4, + 0xef, 0xa0, 0x2e, 0xf3, 0x0, 0x0, 0x0, 0xa, + 0xf3, 0x0, 0x6f, 0x70, 0x0, 0x2d, 0xfc, 0xcf, + 0x80, 0x0, 0x0, 0x0, 0xa, 0xf3, 0x0, 0xcf, + 0x20, 0x0, 0x0, 0xbf, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xf3, 0x2, 0xfc, 0x0, 0x0, 0x3, + 0xef, 0xff, 0x60, 0x0, 0x0, 0x0, 0xa, 0xf3, + 0xa, 0xf6, 0x0, 0x0, 0x8f, 0xf9, 0x6f, 0xf9, + 0x0, 0x0, 0x0, 0xa, 0xf3, 0x4f, 0xe0, 0x0, + 0x6e, 0xfe, 0x50, 0x4, 0xff, 0xb1, 0x0, 0x0, + 0xa, 0xf3, 0x4f, 0x50, 0x7e, 0xff, 0xa1, 0x0, + 0x0, 0x2e, 0xfd, 0x10, 0x0, 0x3f, 0xf9, 0x3, + 0x0, 0xdf, 0xb3, 0x0, 0x0, 0x0, 0x1, 0xdb, + 0x0, 0x2, 0xef, 0xef, 0x60, 0x0, 0x23, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xf6, + 0x2f, 0xfb, 0x52, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x1, 0x11, 0x10, 0x9f, 0x90, 0x2, 0xcf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x4c, 0x0, 0x0, 0x3, 0x79, 0xab, 0xbb, 0xbb, + 0xbb, 0xbb, 0xcc, 0xcc, 0x80, 0x1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+9009 "选" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, + 0x52, 0x0, 0x0, 0x0, 0x0, 0x0, 0x17, 0x0, + 0x0, 0x0, 0x3, 0x0, 0x7, 0xf6, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0x80, 0x0, 0x0, 0x5f, + 0x80, 0x7, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1e, 0xf7, 0x0, 0x0, 0xaf, 0x30, 0x7, 0xf6, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0xff, 0x40, + 0x0, 0xfe, 0x0, 0x7, 0xf7, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5f, 0x70, 0x6, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x2, 0x0, 0xd, 0xf9, 0x99, 0x9c, 0xfc, 0x99, + 0x99, 0x99, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0x90, 0x0, 0x7, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xef, 0x20, 0x0, 0x7, + 0xf6, 0x0, 0x0, 0x0, 0x0, 0x7, 0x77, 0x75, + 0x0, 0x37, 0x0, 0x0, 0x7, 0xf6, 0x0, 0x0, + 0x0, 0x0, 0x1f, 0xff, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0x7, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x5, + 0x56, 0xfc, 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf2, 0x0, 0x1, 0xfc, 0x5, + 0x99, 0x99, 0xfe, 0x99, 0x9c, 0xfa, 0x99, 0x99, + 0x91, 0x0, 0x1, 0xfc, 0x0, 0x0, 0x0, 0xfb, + 0x0, 0x8, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xfc, 0x0, 0x0, 0x2, 0xfa, 0x0, 0x8, 0xf3, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xfc, 0x0, 0x0, + 0x5, 0xf7, 0x0, 0x8, 0xf3, 0x0, 0x5, 0x40, + 0x0, 0x1, 0xfc, 0x0, 0x0, 0xb, 0xf3, 0x0, + 0x8, 0xf3, 0x0, 0xa, 0xf1, 0x0, 0x1, 0xfc, + 0x0, 0x0, 0x5f, 0xd0, 0x0, 0x8, 0xf3, 0x0, + 0xb, 0xe0, 0x0, 0x1, 0xfc, 0x0, 0x6, 0xff, + 0x40, 0x0, 0x7, 0xf6, 0x0, 0x1f, 0xb0, 0x0, + 0x1, 0xfc, 0x1, 0xaf, 0xf6, 0x0, 0x0, 0x3, + 0xff, 0xbb, 0xef, 0x60, 0x0, 0xa, 0xff, 0x50, + 0xce, 0x40, 0x0, 0x0, 0x0, 0x6d, 0xee, 0xd8, + 0x0, 0x0, 0xbf, 0xcf, 0xf6, 0x11, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xfc, + 0x4, 0xff, 0xc6, 0x32, 0x21, 0x11, 0x11, 0x11, + 0x11, 0x11, 0x11, 0x3f, 0xc0, 0x0, 0x2c, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x8, 0x10, 0x0, 0x0, 0x26, 0x89, 0x9a, 0xaa, + 0xaa, 0xaa, 0xbb, 0xbb, 0xa0, + + /* U+975E "非" */ + 0x0, 0x0, 0x0, 0x0, 0x9, 0x80, 0x0, 0x7, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1f, 0xe0, 0x0, 0xd, 0xf1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xe0, + 0x0, 0xd, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0xd, 0xf1, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xaa, 0xaa, 0xaa, + 0xaf, 0xe0, 0x0, 0xd, 0xfa, 0xaa, 0xaa, 0xaa, + 0x80, 0xb, 0xff, 0xff, 0xff, 0xff, 0xe0, 0x0, + 0xd, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x1, 0x11, + 0x11, 0x11, 0x2f, 0xe0, 0x0, 0xd, 0xf2, 0x11, + 0x11, 0x11, 0x10, 0x0, 0x0, 0x0, 0x0, 0x1f, + 0xe0, 0x0, 0xd, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0xd, + 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1f, 0xe0, 0x0, 0xd, 0xf1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xe0, + 0x0, 0xd, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x4, + 0xbb, 0xbb, 0xbb, 0xcf, 0xe0, 0x0, 0xd, 0xfc, + 0xbb, 0xbb, 0xbb, 0x50, 0x6, 0xff, 0xff, 0xff, + 0xff, 0xe0, 0x0, 0xd, 0xff, 0xff, 0xff, 0xff, + 0x70, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, + 0xd, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1f, 0xe0, 0x0, 0xd, 0xf1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, + 0xe0, 0x0, 0xd, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0xd, + 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1f, 0xe0, 0x0, 0xd, 0xf1, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xe0, + 0x0, 0xd, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x3c, + 0xcc, 0xcc, 0xcc, 0xcf, 0xe0, 0x0, 0xd, 0xfc, + 0xcc, 0xcc, 0xcc, 0xc4, 0x0, 0x0, 0x0, 0x0, + 0x1f, 0xe0, 0x0, 0xd, 0xf1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, + 0xd, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1f, 0xe0, 0x0, 0xd, 0xf1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, + 0xe0, 0x0, 0xd, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1f, 0xe0, 0x0, 0xd, + 0xf1, 0x0, 0x0, 0x0, 0x0, + + /* U+F001 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x38, 0xdf, 0xf9, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x15, 0xae, 0xff, + 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0x7c, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x49, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x16, 0xbf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe9, 0xbf, 0xff, 0x0, 0x0, + 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0x73, 0x0, 0x8f, 0xff, 0x0, 0x0, 0x0, 0xf, + 0xff, 0xff, 0xff, 0xfe, 0xa5, 0x10, 0x0, 0x0, + 0x8f, 0xff, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xd8, 0x30, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0x0, 0x0, 0x0, 0xf, 0xff, 0xa2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0x0, 0x0, + 0x0, 0xf, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xff, 0x0, 0x0, 0x0, 0xf, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8f, 0xff, 0x0, 0x0, 0x0, 0xf, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0x0, 0x0, 0x0, 0xf, 0xff, 0x80, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0x0, 0x0, + 0x0, 0xf, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xff, 0x0, 0x0, 0x0, 0xf, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x1, 0x7a, 0xcb, + 0xcf, 0xff, 0x0, 0x0, 0x0, 0xf, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x5f, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0x0, 0xf, 0xff, 0x80, 0x0, 0x0, + 0x2, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x1, + 0x33, 0x2f, 0xff, 0x80, 0x0, 0x0, 0x7, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x3, 0xcf, 0xff, 0xff, + 0xff, 0x80, 0x0, 0x0, 0x5, 0xff, 0xff, 0xff, + 0xff, 0xfd, 0x5f, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xf4, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, + 0x0, 0x7, 0xef, 0xff, 0xfb, 0x20, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x1, 0x32, 0x0, 0x0, 0xaf, 0xff, 0xff, 0xff, + 0xff, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xff, 0xff, 0xff, 0xe4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x27, 0xaa, 0x95, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F008 "" */ + 0x9b, 0x0, 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xb0, 0x0, 0xb9, 0xfe, 0x44, + 0x4e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xe4, 0x44, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x88, 0x8f, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xef, 0xf8, 0x88, 0xff, + 0xfc, 0x0, 0xc, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xef, 0xb0, 0x0, 0xcf, 0xfc, 0x0, + 0xc, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xef, 0xb0, 0x0, 0xcf, 0xfd, 0x0, 0xd, 0xfd, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xd0, + 0x0, 0xdf, 0xff, 0xff, 0xff, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xcc, 0xcf, 0xfe, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xef, 0xfc, 0xcc, 0xff, 0xfc, 0x0, + 0xc, 0xff, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xff, 0xc0, 0x0, 0xcf, 0xfc, 0x0, 0xc, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb0, + 0x0, 0xcf, 0xfc, 0x0, 0xc, 0xff, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xff, 0xc0, 0x0, 0xcf, + 0xff, 0xcc, 0xcf, 0xfe, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xef, 0xfc, 0xcc, 0xff, 0xff, 0xff, + 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xef, 0xff, 0xff, 0xff, 0xfd, 0x0, 0xd, 0xfd, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xd0, + 0x0, 0xdf, 0xfc, 0x0, 0xc, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xef, 0xb0, 0x0, 0xcf, + 0xfc, 0x0, 0xc, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xef, 0xb0, 0x0, 0xcf, 0xff, 0x88, + 0x8f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xef, 0xf8, 0x88, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x44, 0x4e, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xe4, 0x44, 0xef, + 0xab, 0x0, 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xb0, 0x0, 0xb9, + + /* U+F00B "" */ + 0x9f, 0xff, 0xff, 0xfb, 0x0, 0xaf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, 0xff, 0xff, + 0xff, 0xff, 0x21, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x21, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x21, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x21, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x21, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xaf, 0xff, 0xff, 0xfc, + 0x0, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xff, + 0xff, 0xfb, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf9, 0xff, 0xff, 0xff, 0xff, + 0x21, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x21, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x21, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x21, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x21, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xaf, 0xff, 0xff, 0xfc, 0x0, 0xbf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, 0xff, 0xfc, + 0x0, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfa, 0xff, 0xff, 0xff, 0xff, 0x21, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x21, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x21, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x21, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x21, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x9f, 0xff, 0xff, 0xfb, 0x0, 0xaf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, + + /* U+F00C "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xe9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6f, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xff, + 0xff, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xff, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6, 0xff, 0xff, 0xff, + 0xf8, 0x0, 0x0, 0x8e, 0x50, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0xff, 0xff, 0xff, 0x80, 0x0, + 0xa, 0xff, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x9f, 0xff, + 0xff, 0x60, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xff, + 0xff, 0x80, 0x0, 0x0, 0xff, 0xff, 0xff, 0xf6, + 0x0, 0x0, 0x6, 0xff, 0xff, 0xff, 0xf8, 0x0, + 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, 0x60, 0x0, + 0x6f, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xff, 0xff, 0xf6, 0x6, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0xff, 0xff, 0xff, 0xaf, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xff, 0x70, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xff, 0xff, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xff, + 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xe7, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F00D "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x10, 0x0, 0x6, 0xff, 0x50, 0x0, 0x0, 0x0, + 0x0, 0x2d, 0xfa, 0x0, 0x6f, 0xff, 0xf5, 0x0, + 0x0, 0x0, 0x2, 0xef, 0xff, 0xa0, 0xef, 0xff, + 0xff, 0x50, 0x0, 0x0, 0x2e, 0xff, 0xff, 0xf2, + 0xcf, 0xff, 0xff, 0xf5, 0x0, 0x2, 0xef, 0xff, + 0xff, 0xf1, 0x2e, 0xff, 0xff, 0xff, 0x50, 0x2e, + 0xff, 0xff, 0xff, 0x50, 0x2, 0xef, 0xff, 0xff, + 0xf7, 0xef, 0xff, 0xff, 0xf5, 0x0, 0x0, 0x2e, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x0, + 0x0, 0x2, 0xef, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x0, 0x0, 0x0, 0x0, 0x2e, 0xff, 0xff, 0xff, + 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, + 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2e, 0xff, 0xff, 0xff, 0xff, 0x50, 0x0, 0x0, + 0x0, 0x2, 0xef, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x0, 0x0, 0x0, 0x2e, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x50, 0x0, 0x2, 0xef, 0xff, 0xff, + 0xf6, 0xef, 0xff, 0xff, 0xf5, 0x0, 0x2e, 0xff, + 0xff, 0xff, 0x40, 0x2e, 0xff, 0xff, 0xff, 0x50, + 0xcf, 0xff, 0xff, 0xf4, 0x0, 0x2, 0xef, 0xff, + 0xff, 0xf1, 0xef, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x2e, 0xff, 0xff, 0xf2, 0x6f, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0x2, 0xef, 0xff, 0xa0, 0x6, 0xff, + 0x40, 0x0, 0x0, 0x0, 0x0, 0x2d, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x10, 0x0, + + /* U+F011 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x69, 0x96, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0xff, 0xff, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3, 0xff, 0xff, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xa8, 0x0, 0x3, + 0xff, 0xff, 0x30, 0x0, 0x8a, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x3e, 0xff, 0x60, 0x3, 0xff, 0xff, + 0x30, 0x6, 0xff, 0xe3, 0x0, 0x0, 0x0, 0x2, + 0xef, 0xff, 0xe0, 0x3, 0xff, 0xff, 0x30, 0xe, + 0xff, 0xff, 0x30, 0x0, 0x0, 0xd, 0xff, 0xff, + 0xe0, 0x3, 0xff, 0xff, 0x30, 0xe, 0xff, 0xff, + 0xd1, 0x0, 0x0, 0x9f, 0xff, 0xfe, 0x30, 0x3, + 0xff, 0xff, 0x30, 0x3, 0xef, 0xff, 0xf9, 0x0, + 0x2, 0xff, 0xff, 0xe2, 0x0, 0x3, 0xff, 0xff, + 0x30, 0x0, 0x2e, 0xff, 0xff, 0x20, 0x9, 0xff, + 0xff, 0x50, 0x0, 0x3, 0xff, 0xff, 0x30, 0x0, + 0x5, 0xff, 0xff, 0x90, 0xe, 0xff, 0xfc, 0x0, + 0x0, 0x3, 0xff, 0xff, 0x30, 0x0, 0x0, 0xcf, + 0xff, 0xe0, 0x3f, 0xff, 0xf5, 0x0, 0x0, 0x3, + 0xff, 0xff, 0x30, 0x0, 0x0, 0x6f, 0xff, 0xf3, + 0x6f, 0xff, 0xf0, 0x0, 0x0, 0x3, 0xff, 0xff, + 0x30, 0x0, 0x0, 0xf, 0xff, 0xf6, 0x7f, 0xff, + 0xe0, 0x0, 0x0, 0x3, 0xff, 0xff, 0x30, 0x0, + 0x0, 0xe, 0xff, 0xf8, 0x8f, 0xff, 0xd0, 0x0, + 0x0, 0x2, 0xff, 0xff, 0x20, 0x0, 0x0, 0xd, + 0xff, 0xf8, 0x8f, 0xff, 0xe0, 0x0, 0x0, 0x0, + 0xef, 0xfe, 0x0, 0x0, 0x0, 0xe, 0xff, 0xf7, + 0x6f, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x2, 0x20, + 0x0, 0x0, 0x0, 0xf, 0xff, 0xf6, 0x3f, 0xff, + 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5f, 0xff, 0xf3, 0xe, 0xff, 0xfb, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0xff, 0xe0, 0x9, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, 0x90, + 0x2, 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2e, 0xff, 0xff, 0x20, 0x0, 0x9f, + 0xff, 0xfe, 0x30, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xef, 0xff, 0xf9, 0x0, 0x0, 0x1e, 0xff, 0xff, + 0xf8, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xd1, 0x0, 0x0, 0x3, 0xff, 0xff, 0xff, 0xfa, + 0x75, 0x57, 0xaf, 0xff, 0xff, 0xfe, 0x20, 0x0, + 0x0, 0x0, 0x3e, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe3, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x60, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x9d, + 0xff, 0xfe, 0xd9, 0x40, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F013 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2c, 0xff, 0xff, 0xd6, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, + 0xff, 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, 0xff, + 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xc1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xc8, 0x0, 0x5d, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x6d, 0x40, + 0x0, 0x0, 0xcf, 0xfe, 0xaf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfc, 0xcf, 0xfe, 0x20, 0x0, 0x7f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfb, 0x0, 0x1f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf4, 0x7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb0, 0xcf, + 0xff, 0xff, 0xff, 0xff, 0xe7, 0x32, 0x5d, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x13, 0xcf, 0xff, 0xff, + 0xff, 0xe1, 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, + 0xfe, 0x60, 0x0, 0x7f, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0xe, 0xff, 0xff, 0xfb, 0x10, 0x0, + 0x4, 0xff, 0xff, 0xfe, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0xff, 0xff, 0x90, 0x0, 0x0, 0x5f, 0xff, + 0xff, 0xc0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xfa, 0x0, 0x0, 0x4, 0xff, 0xff, 0xfe, 0x0, + 0x0, 0x0, 0x0, 0x9f, 0xff, 0xff, 0x80, 0x0, + 0x0, 0x7f, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, + 0xe, 0xff, 0xff, 0xfb, 0x10, 0x3, 0xcf, 0xff, + 0xff, 0xff, 0xe1, 0x0, 0x0, 0xb, 0xff, 0xff, + 0xff, 0xfe, 0x60, 0xcf, 0xff, 0xff, 0xff, 0xff, + 0xe7, 0x32, 0x5d, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x17, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xb0, 0x1e, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf4, 0x0, 0x7f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x0, 0x0, 0xcf, 0xfe, 0xaf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfc, 0xcf, 0xfe, 0x10, 0x0, 0x1, + 0xc8, 0x0, 0x5d, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0x0, 0x5d, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xff, 0xff, 0xc0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, + 0xff, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5, 0xff, 0xff, 0xff, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2c, 0xff, 0xff, 0xd6, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F015 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x37, + 0x60, 0x0, 0x0, 0x48, 0x88, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0xff, + 0xfd, 0x10, 0x0, 0xaf, 0xff, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xff, + 0xff, 0xe3, 0x0, 0xbf, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1c, 0xff, 0xff, + 0xff, 0xff, 0x60, 0xbf, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xef, 0xff, 0xf8, + 0xcf, 0xff, 0xf9, 0xbf, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xfe, 0x30, + 0xa, 0xff, 0xff, 0xff, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xd2, 0x3, + 0x10, 0x7f, 0xff, 0xff, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xbf, 0xff, 0xfa, 0x0, 0x8f, + 0xd2, 0x4, 0xff, 0xff, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x2d, 0xff, 0xff, 0x80, 0xb, 0xff, + 0xff, 0x40, 0x2d, 0xff, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x4, 0xff, 0xff, 0xf5, 0x2, 0xdf, 0xff, + 0xff, 0xf7, 0x1, 0xbf, 0xff, 0xfa, 0x0, 0x0, + 0x0, 0x7f, 0xff, 0xfe, 0x30, 0x3e, 0xff, 0xff, + 0xff, 0xff, 0xa0, 0x9, 0xff, 0xff, 0xc1, 0x0, + 0xa, 0xff, 0xff, 0xc1, 0x6, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfc, 0x10, 0x6f, 0xff, 0xfe, 0x30, + 0xbf, 0xff, 0xfa, 0x0, 0x9f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe3, 0x4, 0xef, 0xff, 0xf4, + 0xbf, 0xff, 0x70, 0x1b, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x50, 0x2d, 0xff, 0xf3, + 0xd, 0xf4, 0x2, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0xbf, 0x60, + 0x1, 0x20, 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0x3, 0x0, + 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0xcf, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xf2, 0x0, + 0x0, 0xaf, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xf2, 0x0, + 0x0, 0xaf, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xf2, 0x0, + 0x0, 0xaf, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xf2, 0x0, + 0x0, 0xaf, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xf2, 0x0, + 0x0, 0xaf, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xd0, 0x0, + 0x0, 0x6f, 0xff, 0xff, 0xfe, 0x10, 0x0, 0x0, + + /* U+F019 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x55, 0x55, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5f, 0xff, 0xff, 0xf5, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xf8, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xf8, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1c, 0xdd, 0xdd, 0xef, + 0xff, 0xff, 0xfe, 0xdd, 0xdd, 0xc1, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0x11, 0x11, 0x11, 0x10, 0x8, + 0xff, 0xff, 0x80, 0x1, 0x11, 0x11, 0x11, 0x10, + 0xbf, 0xff, 0xff, 0xff, 0xfd, 0x10, 0x8f, 0xf8, + 0x1, 0xdf, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe2, 0x6, 0x60, 0x2d, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x30, 0x3, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfd, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + 0x1e, 0xb0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x2e, 0xc1, + 0x8f, 0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x37, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0x73, + + /* U+F01C "" */ + 0x0, 0x0, 0x0, 0x2b, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x5f, 0xff, 0xd8, 0x88, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x9f, 0xff, 0xd0, 0x0, 0x0, + 0x0, 0x1, 0xef, 0xff, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xb, 0xff, 0xf8, 0x0, 0x0, + 0x0, 0xa, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0xef, 0xff, 0x30, 0x0, + 0x0, 0x5f, 0xff, 0xd0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, 0xd0, 0x0, + 0x1, 0xef, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xf8, 0x0, + 0xa, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xef, 0xff, 0x20, + 0x5f, 0xff, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, 0xd0, + 0xdf, 0xff, 0xb8, 0x88, 0x88, 0x70, 0x0, 0x0, + 0x0, 0x0, 0x48, 0x88, 0x88, 0x8e, 0xff, 0xf5, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0xef, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x0, 0x0, + 0x0, 0x7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x0, + 0x0, 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, + 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x50, + + /* U+F021 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x58, 0x86, 0x0, 0x0, + 0x0, 0x0, 0x4, 0x9d, 0xef, 0xfe, 0xb7, 0x20, + 0x0, 0x0, 0xdf, 0xff, 0x0, 0x0, 0x0, 0x6, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xfb, 0x30, 0x0, + 0xdf, 0xff, 0x0, 0x0, 0x1, 0xbf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfa, 0x10, 0xcf, 0xff, + 0x0, 0x0, 0x2e, 0xff, 0xff, 0xff, 0xfe, 0xef, + 0xff, 0xff, 0xff, 0xe3, 0xbf, 0xff, 0x0, 0x2, + 0xef, 0xff, 0xff, 0x94, 0x0, 0x0, 0x4b, 0xff, + 0xff, 0xfe, 0xdf, 0xff, 0x0, 0xd, 0xff, 0xff, + 0xc2, 0x0, 0x0, 0x0, 0x0, 0x3c, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x9f, 0xff, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, + 0x2, 0xff, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x11, 0x0, 0x8, 0xff, 0xff, 0xff, 0x9, 0xff, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0x3, 0xff, 0xff, + 0xee, 0xff, 0xff, 0xff, 0xe, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x3f, 0xff, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x2b, 0xcc, 0x60, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xbc, 0xcc, 0xcc, 0xcc, 0xcc, 0xca, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xac, 0xcc, 0xcc, 0xcc, 0xcc, 0xcb, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xbc, 0xb2, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, 0x0, + 0x0, 0xe, 0xff, 0xf2, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x40, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0xff, 0xe0, 0xff, 0xff, 0xff, 0xee, 0xff, 0xff, + 0x30, 0x0, 0x0, 0x0, 0x0, 0xdf, 0xff, 0x90, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x11, 0x0, 0x0, + 0x0, 0x0, 0xa, 0xff, 0xff, 0x20, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0xff, 0xf9, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xb2, 0x0, 0x0, 0x0, 0x0, 0x2c, 0xff, 0xff, + 0xd0, 0x0, 0xff, 0xfd, 0xef, 0xff, 0xff, 0xa4, + 0x0, 0x0, 0x4a, 0xff, 0xff, 0xfe, 0x20, 0x0, + 0xff, 0xfb, 0x3e, 0xff, 0xff, 0xff, 0xfe, 0xef, + 0xff, 0xff, 0xff, 0xe2, 0x0, 0x0, 0xff, 0xfc, + 0x1, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfb, 0x10, 0x0, 0x0, 0xff, 0xfd, 0x0, 0x3, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x60, 0x0, + 0x0, 0x0, 0xff, 0xfd, 0x0, 0x0, 0x2, 0x7c, + 0xff, 0xff, 0xd9, 0x40, 0x0, 0x0, 0x0, 0x0, + 0x68, 0x85, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F026 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xb6, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x3, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xff, 0xff, 0x0, 0x0, 0x0, 0x3, 0xff, + 0xff, 0xff, 0x38, 0x88, 0x88, 0x8f, 0xff, 0xff, + 0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x10, + + /* U+F027 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3b, 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3e, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x38, + 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0x0, 0x0, + 0x0, 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x1, 0xb9, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x0, 0x6f, 0xfc, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x1, 0xcf, + 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0xef, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0x0, 0xa, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0xdf, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x0, 0xbf, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x6f, 0xfd, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf0, 0x2, 0xdb, 0x10, + 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x20, 0x0, 0x0, + 0x0, 0x0, + + /* U+F028 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x18, 0x50, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x7f, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0xff, 0xc1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0xb6, 0x0, + 0x0, 0x0, 0x0, 0x2, 0xdf, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, 0x0, + 0x0, 0x0, 0x21, 0x0, 0x1c, 0xff, 0x90, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xff, 0xff, 0x0, + 0x0, 0x4, 0xfe, 0x50, 0x1, 0xef, 0xf3, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, 0xff, 0x0, + 0x0, 0x5, 0xff, 0xf6, 0x0, 0x4f, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x7f, 0xff, 0x40, 0xa, 0xff, 0x40, + 0x38, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x5, 0xff, 0xe0, 0x2, 0xff, 0xa0, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x1c, 0xa1, 0x0, 0x8f, 0xf6, 0x0, 0xcf, 0xf0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x6f, 0xfd, 0x0, 0x1f, 0xfc, 0x0, 0x8f, 0xf2, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x1c, 0xff, 0x80, 0xa, 0xff, 0x0, 0x4f, 0xf5, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x0, 0xdf, 0xd0, 0x7, 0xff, 0x20, 0x3f, 0xf7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x0, 0xaf, 0xf0, 0x6, 0xff, 0x30, 0x2f, 0xf7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x0, 0xdf, 0xd0, 0x7, 0xff, 0x20, 0x3f, 0xf7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x1c, 0xff, 0x80, 0xa, 0xff, 0x0, 0x4f, 0xf5, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x6f, 0xfd, 0x0, 0x1f, 0xfc, 0x0, 0x8f, 0xf2, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x1c, 0xa1, 0x0, 0x9f, 0xf6, 0x0, 0xdf, 0xe0, + 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x5, 0xff, 0xe0, 0x3, 0xff, 0xa0, + 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x7f, 0xff, 0x40, 0xa, 0xff, 0x40, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0x0, + 0x0, 0x5, 0xff, 0xf6, 0x0, 0x4f, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0x0, + 0x0, 0x4, 0xfe, 0x50, 0x1, 0xef, 0xf3, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0x0, + 0x0, 0x0, 0x21, 0x0, 0x1d, 0xff, 0x90, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x2, 0xdf, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x3f, 0xff, 0xc1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x7f, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x18, 0x50, 0x0, 0x0, 0x0, + + /* U+F03E "" */ + 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xb1, 0xbf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x93, 0x27, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf9, 0x0, 0x0, 0x5f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, + 0x0, 0x0, 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, 0x0, 0x0, + 0xe, 0xff, 0xff, 0xff, 0xff, 0xd8, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0x0, 0x0, 0x3f, 0xff, + 0xff, 0xff, 0xfc, 0x10, 0x6f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x50, 0x3, 0xdf, 0xff, 0xff, 0xff, + 0xc1, 0x0, 0x6, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xef, 0xff, 0xff, 0xff, 0xfc, 0x10, 0x0, + 0x0, 0x6f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xc1, 0x0, 0x0, 0x0, 0x6, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xc1, 0x3e, 0xff, + 0xfc, 0x10, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xff, + 0xff, 0xff, 0xfc, 0x10, 0x3, 0xef, 0xc1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, + 0xc1, 0x0, 0x0, 0x3b, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xff, 0xff, 0xfd, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8f, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xfc, + 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x88, 0x88, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xb1, + + /* U+F043 "" */ + 0x0, 0x0, 0x0, 0x0, 0x39, 0x50, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, + 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xff, 0xfe, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xff, 0xff, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xc0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xff, + 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xff, 0xff, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xff, 0xff, 0xff, 0xff, 0x60, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0xff, 0xff, + 0xff, 0xf1, 0x0, 0x0, 0x0, 0x7, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x3f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x0, + 0x0, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf3, 0x0, 0x7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfb, 0x0, 0xe, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0x6f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xe0, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0xff, 0xfa, 0xd, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xef, 0xf8, + 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, + 0xdf, 0xfc, 0x6, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf1, 0x9f, 0xff, 0x20, 0xcf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xd0, 0x4f, 0xff, 0xb0, 0x9, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0xc, 0xff, + 0xfa, 0x0, 0x2, 0xcf, 0xff, 0xff, 0xfe, 0x10, + 0x2, 0xff, 0xff, 0xd6, 0x10, 0xbf, 0xff, 0xff, + 0xf5, 0x0, 0x0, 0x5f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x4, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0x18, 0xff, 0xff, 0xff, 0xfa, 0x20, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4, 0x67, 0x64, 0x0, 0x0, + 0x0, 0x0, + + /* U+F048 "" */ + 0x48, 0x88, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0x70, 0xbf, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xf9, 0xbf, 0xff, 0x30, 0x0, 0x0, 0x0, + 0x1c, 0xff, 0xfc, 0xbf, 0xff, 0x30, 0x0, 0x0, + 0x1, 0xdf, 0xff, 0xfc, 0xbf, 0xff, 0x30, 0x0, + 0x0, 0x2e, 0xff, 0xff, 0xfc, 0xbf, 0xff, 0x30, + 0x0, 0x3, 0xef, 0xff, 0xff, 0xfc, 0xbf, 0xff, + 0x30, 0x0, 0x4f, 0xff, 0xff, 0xff, 0xfc, 0xbf, + 0xff, 0x30, 0x5, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xbf, 0xff, 0x30, 0x6f, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0xbf, 0xff, 0x37, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfc, 0xbf, 0xff, 0xbf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfc, 0xbf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfc, 0xbf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfc, 0xbf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0xbf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0xbf, + 0xff, 0x5d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xbf, 0xff, 0x31, 0xcf, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0xbf, 0xff, 0x30, 0xb, 0xff, 0xff, 0xff, + 0xff, 0xfc, 0xbf, 0xff, 0x30, 0x0, 0xaf, 0xff, + 0xff, 0xff, 0xfc, 0xbf, 0xff, 0x30, 0x0, 0x9, + 0xff, 0xff, 0xff, 0xfc, 0xbf, 0xff, 0x30, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xfc, 0xbf, 0xff, 0x30, + 0x0, 0x0, 0x6, 0xff, 0xff, 0xfc, 0xbf, 0xff, + 0x30, 0x0, 0x0, 0x0, 0x5f, 0xff, 0xfc, 0xbf, + 0xff, 0x30, 0x0, 0x0, 0x0, 0x4, 0xff, 0xfb, + 0x9f, 0xfe, 0x20, 0x0, 0x0, 0x0, 0x0, 0x3d, + 0xd3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+F04B "" */ + 0x3, 0x75, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xff, 0xfc, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xef, 0xff, 0xff, 0x91, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xe6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xa1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, + 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xb2, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x50, + 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xb2, 0x0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb2, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x50, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xb2, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x40, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xa1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xfd, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xff, 0xe6, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xff, 0xff, + 0x91, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xff, 0xfc, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x74, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+F04C "" */ + 0x1a, 0xef, 0xff, 0xff, 0xd5, 0x0, 0x0, 0x1a, + 0xef, 0xff, 0xff, 0xd5, 0xa, 0xff, 0xff, 0xff, + 0xff, 0xf2, 0x0, 0xa, 0xff, 0xff, 0xff, 0xff, + 0xf2, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x80, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x80, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0xef, 0xff, 0xff, 0xff, 0xff, + 0x60, 0x0, 0xef, 0xff, 0xff, 0xff, 0xff, 0x66, + 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0, 0x6, 0xff, + 0xff, 0xff, 0xff, 0xd0, 0x4, 0x89, 0x99, 0x98, + 0x71, 0x0, 0x0, 0x4, 0x89, 0x99, 0x98, 0x71, + 0x0, + + /* U+F04D "" */ + 0x3, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x60, 0x6, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xd0, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x6f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf2, 0x1a, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd5, + 0x0, + + /* U+F051 "" */ + 0x5, 0x81, 0x0, 0x0, 0x0, 0x0, 0x0, 0x68, + 0x87, 0x5f, 0xfe, 0x20, 0x0, 0x0, 0x0, 0x0, + 0xef, 0xff, 0x7f, 0xff, 0xe3, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0x8f, 0xff, 0xff, 0x40, 0x0, + 0x0, 0x0, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xf5, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x8f, 0xff, 0xff, + 0xff, 0x60, 0x0, 0x0, 0xff, 0xff, 0x8f, 0xff, + 0xff, 0xff, 0xf8, 0x0, 0x0, 0xff, 0xff, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, 0xff, + 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb0, + 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xe3, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x20, 0xff, + 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xd2, 0x0, + 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xfd, 0x10, + 0x0, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xc1, + 0x0, 0x0, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xfb, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x8f, 0xff, 0xff, + 0xa0, 0x0, 0x0, 0x0, 0xff, 0xff, 0x8f, 0xff, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0x7f, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, + 0x1c, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, + 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+F052 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x9a, 0x50, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1e, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xdf, + 0xff, 0xff, 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xf5, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfd, 0x10, 0x0, 0x0, 0x5, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xc0, 0x0, 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, 0x0, 0x3, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xa0, 0xc, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf5, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xa, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf3, 0x1, 0xbf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd1, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0xe, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, + 0x5, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xb0, + + /* U+F053 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x93, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xff, 0xc0, + 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, 0xfd, 0x10, + 0x0, 0x0, 0x0, 0x4f, 0xff, 0xff, 0xd1, 0x0, + 0x0, 0x0, 0x4, 0xff, 0xff, 0xfd, 0x10, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xff, 0xd1, 0x0, 0x0, + 0x0, 0x4, 0xff, 0xff, 0xfd, 0x10, 0x0, 0x0, + 0x0, 0x4f, 0xff, 0xff, 0xd1, 0x0, 0x0, 0x0, + 0x4, 0xff, 0xff, 0xfd, 0x10, 0x0, 0x0, 0x0, + 0x3f, 0xff, 0xff, 0xd1, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xff, 0xff, 0x70, 0x0, 0x0, 0x0, 0x0, + 0xb, 0xff, 0xff, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xbf, 0xff, 0xff, 0x60, 0x0, 0x0, 0x0, + 0x0, 0xb, 0xff, 0xff, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0xff, 0xff, 0x60, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xff, 0xff, 0xf6, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0xff, 0xff, 0x60, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, 0xf6, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0xff, 0x60, + 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20, 0x0, + + /* U+F054 "" */ + 0x0, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6f, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4f, 0xff, 0xff, 0xb0, 0x0, 0x0, 0x0, 0x0, + 0x7, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x7f, 0xff, 0xff, 0xb0, 0x0, 0x0, 0x0, + 0x0, 0x7, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0xff, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xff, 0xff, 0xfb, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x7f, 0xff, 0xff, 0xb0, 0x0, + 0x0, 0x0, 0x0, 0x7, 0xff, 0xff, 0xfb, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0xff, 0xff, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x1e, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x1, 0xcf, 0xff, 0xff, 0x50, + 0x0, 0x0, 0x0, 0x1c, 0xff, 0xff, 0xf5, 0x0, + 0x0, 0x0, 0x1, 0xcf, 0xff, 0xff, 0x50, 0x0, + 0x0, 0x0, 0x1c, 0xff, 0xff, 0xf5, 0x0, 0x0, + 0x0, 0x1, 0xcf, 0xff, 0xff, 0x50, 0x0, 0x0, + 0x0, 0x1c, 0xff, 0xff, 0xf5, 0x0, 0x0, 0x0, + 0x1, 0xdf, 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, + 0x1d, 0xff, 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, + 0x2f, 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x11, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F067 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5a, 0xa8, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3f, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xff, 0xff, + 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0xff, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xff, + 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6f, 0xff, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xff, 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xfe, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6, 0xff, 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xfe, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x9f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x20, 0x23, 0x33, 0x33, 0x33, + 0x8f, 0xff, 0xfe, 0x33, 0x33, 0x33, 0x33, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x6, 0xff, 0xff, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6f, 0xff, 0xfe, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xff, 0xff, + 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0xff, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xff, + 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6f, 0xff, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xff, 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8d, 0xdc, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F068 "" */ + 0x1, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x10, 0x8, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xe1, 0x1, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x10, 0x0, + + /* U+F06E "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x26, 0xad, 0xef, + 0xfe, 0xc9, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xa2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3c, 0xff, 0xff, 0xff, 0xba, + 0xbd, 0xff, 0xff, 0xff, 0x91, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xfd, 0x50, 0x0, + 0x0, 0x18, 0xff, 0xff, 0xfe, 0x40, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0xff, 0xff, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x3e, 0xff, 0xff, 0xf6, 0x0, 0x0, + 0x0, 0xc, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x39, + 0x95, 0x0, 0x2, 0xef, 0xff, 0xff, 0x70, 0x0, + 0x0, 0xaf, 0xff, 0xff, 0xe0, 0x0, 0x0, 0x3f, + 0xff, 0xd2, 0x0, 0x5f, 0xff, 0xff, 0xf5, 0x0, + 0x7, 0xff, 0xff, 0xff, 0x70, 0x0, 0x0, 0x3f, + 0xff, 0xfe, 0x10, 0xd, 0xff, 0xff, 0xff, 0x20, + 0x2f, 0xff, 0xff, 0xff, 0x20, 0x0, 0x0, 0xaf, + 0xff, 0xff, 0x80, 0x8, 0xff, 0xff, 0xff, 0xc0, + 0xbf, 0xff, 0xff, 0xff, 0x0, 0x48, 0x6b, 0xff, + 0xff, 0xff, 0xd0, 0x5, 0xff, 0xff, 0xff, 0xf5, + 0xff, 0xff, 0xff, 0xfe, 0x0, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0x4, 0xff, 0xff, 0xff, 0xf9, + 0xbf, 0xff, 0xff, 0xff, 0x0, 0x6f, 0xff, 0xff, + 0xff, 0xff, 0xe0, 0x5, 0xff, 0xff, 0xff, 0xf5, + 0x1f, 0xff, 0xff, 0xff, 0x20, 0x1f, 0xff, 0xff, + 0xff, 0xff, 0x90, 0x8, 0xff, 0xff, 0xff, 0xc0, + 0x6, 0xff, 0xff, 0xff, 0x70, 0x8, 0xff, 0xff, + 0xff, 0xff, 0x20, 0xd, 0xff, 0xff, 0xff, 0x20, + 0x0, 0xaf, 0xff, 0xff, 0xe0, 0x0, 0xaf, 0xff, + 0xff, 0xf4, 0x0, 0x5f, 0xff, 0xff, 0xf5, 0x0, + 0x0, 0xb, 0xff, 0xff, 0xfb, 0x0, 0x4, 0xad, + 0xc8, 0x10, 0x2, 0xef, 0xff, 0xff, 0x70, 0x0, + 0x0, 0x0, 0xbf, 0xff, 0xff, 0xa0, 0x0, 0x0, + 0x0, 0x0, 0x3e, 0xff, 0xff, 0xf6, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xff, 0xff, 0xfd, 0x50, 0x0, + 0x0, 0x18, 0xff, 0xff, 0xfe, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3c, 0xff, 0xff, 0xff, 0xba, + 0xac, 0xff, 0xff, 0xff, 0x91, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xa2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x26, 0xad, 0xff, + 0xfe, 0xc9, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F070 "" */ + 0x4, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xef, 0xff, 0xc1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xe3, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xff, + 0xff, 0xf7, 0x0, 0x0, 0x26, 0xad, 0xff, 0xed, + 0xb7, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xdf, 0xff, 0xfa, 0x16, 0xdf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xd7, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xaf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xba, 0xbe, 0xff, 0xff, 0xfe, 0x60, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xff, 0xff, + 0xff, 0xc5, 0x0, 0x0, 0x3, 0xbf, 0xff, 0xff, + 0xb1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3e, + 0xff, 0xff, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x7f, + 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1b, 0xff, 0xff, 0xc1, 0x6, 0xba, 0x50, + 0x0, 0x7f, 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xe4, 0x7f, + 0xff, 0xc1, 0x0, 0xbf, 0xff, 0xff, 0xd1, 0x0, + 0x0, 0x0, 0xad, 0x20, 0x0, 0x4, 0xff, 0xff, + 0xfc, 0xff, 0xff, 0xc0, 0x3, 0xff, 0xff, 0xff, + 0xb0, 0x0, 0x0, 0x5f, 0xff, 0x50, 0x0, 0x2, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0x50, 0xe, 0xff, + 0xff, 0xff, 0x50, 0x0, 0xe, 0xff, 0xff, 0x90, + 0x0, 0x0, 0xaf, 0xff, 0xff, 0xff, 0xfa, 0x0, + 0xbf, 0xff, 0xff, 0xfe, 0x0, 0x2, 0xff, 0xff, + 0xff, 0xc2, 0x0, 0x0, 0x6f, 0xff, 0xff, 0xff, + 0xb0, 0xa, 0xff, 0xff, 0xff, 0xf2, 0x0, 0xe, + 0xff, 0xff, 0xff, 0xc0, 0x0, 0x0, 0x3e, 0xff, + 0xff, 0xfa, 0x0, 0xcf, 0xff, 0xff, 0xfe, 0x0, + 0x0, 0x5f, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x1b, 0xff, 0xff, 0xd2, 0xe, 0xff, 0xff, 0xff, + 0x50, 0x0, 0x0, 0xbf, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0x7, 0xff, 0xff, 0xf8, 0xff, 0xff, + 0xff, 0x90, 0x0, 0x0, 0x0, 0xdf, 0xff, 0xff, + 0xc0, 0x0, 0x0, 0x0, 0x4, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xc0, 0x0, 0x0, 0x0, 0x2, 0xef, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x1, 0xcf, + 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xdf, 0xff, 0xff, 0x70, 0x0, 0x0, 0x0, + 0x0, 0x9f, 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xbf, 0xff, 0xff, 0xc4, 0x0, + 0x0, 0x0, 0x0, 0x5f, 0xff, 0xff, 0x60, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6e, 0xff, 0xff, + 0xfe, 0xba, 0xb5, 0x0, 0x0, 0x2d, 0xff, 0xff, + 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xdf, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, 0xa, + 0xff, 0xff, 0xd2, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x37, 0xbd, 0xef, 0xfd, 0xb4, 0x0, + 0x0, 0x7, 0xff, 0xff, 0xf5, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xef, 0xff, 0xf8, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xcf, 0xff, + 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8f, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x44, 0x0, + + /* U+F071 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, + 0x87, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, + 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xef, 0xff, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8f, 0xff, 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2f, 0xff, 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xb, 0xff, 0xff, 0xff, 0xff, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x9, 0xff, 0xff, 0x80, 0x0, 0x1e, 0xff, + 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0xff, 0xff, 0xf6, 0x0, 0x0, 0xef, + 0xff, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0xff, 0xff, 0x70, 0x0, 0xf, + 0xff, 0xff, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xff, 0xf8, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xd, 0xff, 0xff, 0xff, 0x80, 0x0, + 0xf, 0xff, 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xff, 0xff, 0xff, 0xf9, 0x0, + 0x1, 0xff, 0xff, 0xff, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xff, 0xff, 0xff, 0xff, 0xa0, + 0x0, 0x2f, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9f, 0xff, 0xff, 0xff, 0xfb, + 0x0, 0x3, 0xff, 0xff, 0xff, 0xff, 0xf1, 0x0, + 0x0, 0x0, 0x0, 0x2f, 0xff, 0xff, 0xff, 0xff, + 0xd1, 0x0, 0x6f, 0xff, 0xff, 0xff, 0xff, 0xa0, + 0x0, 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x30, 0x0, 0x0, 0x5, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0x1, 0xbf, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0x0, 0x0, 0x0, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0x0, 0x0, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xf6, 0x0, 0x0, 0x7f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x40, 0x0, 0xc, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xe0, 0x0, 0x1f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0x0, 0x1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x9, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf6, 0x13, 0xcf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x10, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf7, 0xe, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x60, 0x7f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xe0, 0x0, 0x48, + 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0x99, 0x98, 0x71, 0x0, + + /* U+F074 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6, 0xa2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xfe, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xe3, 0x0, 0x24, 0x44, 0x44, 0x30, 0x0, 0x0, + 0x0, 0x0, 0x2, 0x44, 0x4f, 0xff, 0xfe, 0x30, + 0xff, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xff, 0xff, 0xff, 0xff, 0xe3, 0xff, 0xff, + 0xff, 0xff, 0xa0, 0x0, 0x0, 0x3, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, + 0xf9, 0x0, 0x0, 0x2e, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x1, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd1, + 0x12, 0x22, 0x26, 0xff, 0xff, 0xa0, 0x1d, 0xff, + 0xff, 0xd2, 0x2f, 0xff, 0xfd, 0x10, 0x0, 0x0, + 0x0, 0x7f, 0xfb, 0x1, 0xdf, 0xff, 0xfd, 0x10, + 0xf, 0xff, 0xd1, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xc0, 0xc, 0xff, 0xff, 0xe2, 0x0, 0xe, 0xfd, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0xff, 0xfe, 0x20, 0x0, 0x4, 0x81, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, 0xf3, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x9f, 0xff, 0xff, 0x40, 0x0, 0x0, + 0x4, 0x81, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0xff, 0xf5, 0x5, 0xe2, 0x0, 0xe, 0xfe, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xff, 0xff, + 0x60, 0x4f, 0xfd, 0x10, 0xf, 0xff, 0xe2, 0x0, + 0x12, 0x22, 0x26, 0xff, 0xff, 0xf7, 0x3, 0xff, + 0xff, 0xd2, 0x2f, 0xff, 0xfe, 0x20, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x1, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe2, 0xff, 0xff, 0xff, 0xff, + 0xf9, 0x0, 0x0, 0x2e, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xa0, 0x0, + 0x0, 0x3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xff, 0xff, 0xff, 0xff, 0xe2, 0x24, 0x44, + 0x44, 0x30, 0x0, 0x0, 0x0, 0x0, 0x2, 0x44, + 0x4f, 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xfe, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6, 0xa2, 0x0, 0x0, + + /* U+F077 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0xb2, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xe2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xfa, 0x3f, 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xfa, 0x0, 0x3f, 0xff, + 0xff, 0xe2, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xfa, 0x0, 0x0, 0x3f, 0xff, 0xff, 0xe2, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xfa, 0x0, 0x0, 0x0, + 0x3f, 0xff, 0xff, 0xe2, 0x0, 0x8, 0xff, 0xff, + 0xfa, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, 0xff, + 0xe2, 0x6, 0xff, 0xff, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0xff, 0xff, 0xe0, 0x9f, 0xff, + 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, + 0xff, 0xff, 0x11, 0xdf, 0xfa, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, 0x60, 0x1, + 0xa8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3b, 0x50, 0x0, + + /* U+F078 "" */ + 0x1, 0xa8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3b, 0x60, 0x1, 0xdf, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, + 0x60, 0x9f, 0xff, 0xfa, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0xff, 0xff, 0x16, 0xff, 0xff, + 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0xff, + 0xff, 0xd0, 0x8, 0xff, 0xff, 0xfa, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0xff, 0xff, 0xe2, 0x0, 0x8, + 0xff, 0xff, 0xfa, 0x0, 0x0, 0x0, 0x3f, 0xff, + 0xff, 0xe2, 0x0, 0x0, 0x8, 0xff, 0xff, 0xfa, + 0x0, 0x0, 0x3f, 0xff, 0xff, 0xe2, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xfa, 0x0, 0x3f, 0xff, + 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xfa, 0x3f, 0xff, 0xff, 0xe2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xff, 0xff, 0xff, 0xe2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xff, 0xff, 0xe2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6, 0xa2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F079 "" */ + 0x0, 0x0, 0x0, 0x42, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x9f, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xff, 0xf4, + 0x0, 0x0, 0x57, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x60, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xff, + 0xff, 0xf4, 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x70, 0x0, 0x0, 0x0, 0x9f, + 0xff, 0xff, 0xff, 0xf4, 0x2, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf9, 0x0, 0x0, 0x0, + 0x9f, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x4, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, + 0x0, 0x9f, 0xff, 0xff, 0xff, 0xef, 0xff, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xf9, + 0x0, 0x0, 0xf, 0xff, 0xf4, 0xef, 0xf9, 0x9f, + 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, + 0xff, 0x90, 0x0, 0x0, 0x7f, 0xf5, 0xe, 0xff, + 0x90, 0xaf, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xef, 0xf9, 0x0, 0x0, 0x0, 0x32, 0x0, + 0xef, 0xf9, 0x0, 0x41, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xe, 0xff, 0x90, 0x0, 0x0, 0x0, + 0x0, 0xe, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xef, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xef, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0xff, 0x90, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xff, 0x90, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x19, 0x80, + 0xe, 0xff, 0x90, 0x2a, 0x70, 0x0, 0x0, 0xe, + 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, + 0xff, 0xa0, 0xef, 0xf9, 0x2e, 0xff, 0x60, 0x0, + 0x0, 0xef, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xef, 0xff, 0x9e, 0xff, 0xad, 0xff, 0xf9, + 0x0, 0x0, 0xe, 0xff, 0xc7, 0x77, 0x77, 0x77, + 0x77, 0x73, 0x4, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0x10, 0x0, 0x0, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0x4, 0xff, 0xff, 0xff, + 0xff, 0xfc, 0x10, 0x0, 0x0, 0xe, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x4, 0xff, + 0xff, 0xff, 0xfc, 0x10, 0x0, 0x0, 0x0, 0x9f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, + 0x3, 0xff, 0xff, 0xfc, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x3, 0xff, 0xfc, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xdb, 0x0, 0x0, + 0x0, + + /* U+F07B "" */ + 0x1b, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xc1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfc, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xd8, 0x88, 0x88, 0x88, 0x88, 0x87, 0x30, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xb1, + + /* U+F093 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0xe2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x7, 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, + 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7, 0xff, 0xff, 0xff, + 0xfe, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xe2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x2, 0x22, 0x22, 0xcf, + 0xff, 0xff, 0xf6, 0x22, 0x22, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, 0xff, + 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xbf, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, 0xff, + 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xbf, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0x11, 0x11, 0x11, 0x0, 0xbf, + 0xff, 0xff, 0xf4, 0x0, 0x11, 0x11, 0x11, 0x10, + 0xbf, 0xff, 0xff, 0xff, 0xc0, 0xaf, 0xff, 0xff, + 0xf3, 0xc, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, + 0xff, 0xff, 0xf1, 0x18, 0x99, 0x99, 0x60, 0x1f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0x10, 0x0, 0x0, 0x1, 0xcf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0xcc, 0xcc, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + 0x1e, 0xb0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x2e, 0xc1, + 0x8f, 0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x37, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0x73, + + /* U+F095 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6, 0x62, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4, 0xff, 0xfe, 0xb7, 0x30, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0xff, 0xff, 0xff, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xff, 0xff, 0xff, 0xff, + 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xff, + 0xff, 0xff, 0xff, 0xfa, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, 0xff, + 0xff, 0xff, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, 0xff, 0xff, + 0xf3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x7f, 0xff, 0xff, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0xff, + 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, 0xff, 0xff, + 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9f, 0xff, 0xff, 0xc0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6f, 0xff, 0xff, 0xf3, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x26, 0x10, 0x0, 0x0, 0x0, 0x5f, + 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x4, + 0xbf, 0xfc, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xff, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0x6d, 0xff, 0xff, + 0xfa, 0x0, 0x0, 0xaf, 0xff, 0xff, 0xfe, 0x10, + 0x0, 0x0, 0x7, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0x5, 0xef, 0xff, 0xff, 0xfe, 0x20, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, + 0xff, 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, 0xc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfd, 0x20, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xe6, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x91, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xe9, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x9, 0xff, 0xff, 0xff, 0xd9, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x17, + 0x76, 0x53, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F0C4 "" */ + 0x0, 0x5, 0x99, 0x72, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2d, 0xff, 0xff, + 0xf7, 0x0, 0x0, 0x0, 0x0, 0x1, 0x7b, 0xb8, + 0x10, 0x1e, 0xff, 0xff, 0xff, 0xf7, 0x0, 0x0, + 0x0, 0x2, 0xef, 0xff, 0xfe, 0x38, 0xff, 0xff, + 0xef, 0xff, 0xf1, 0x0, 0x0, 0x2, 0xef, 0xff, + 0xff, 0xf4, 0xdf, 0xfe, 0x10, 0x7f, 0xff, 0x50, + 0x0, 0x2, 0xef, 0xff, 0xff, 0xf5, 0xf, 0xff, + 0x80, 0x0, 0xff, 0xf7, 0x0, 0x2, 0xef, 0xff, + 0xff, 0xf5, 0x0, 0xef, 0xfc, 0x0, 0x4f, 0xff, + 0x60, 0x2, 0xef, 0xff, 0xff, 0xf5, 0x0, 0xa, + 0xff, 0xfd, 0xbf, 0xff, 0xf4, 0x3, 0xef, 0xff, + 0xff, 0xf5, 0x0, 0x0, 0x2f, 0xff, 0xff, 0xff, + 0xff, 0xe5, 0xef, 0xff, 0xff, 0xf5, 0x0, 0x0, + 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x18, 0xcd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x7, 0xff, 0xff, 0xff, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0xef, 0xff, + 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5, 0x99, 0xef, 0xff, 0xff, 0xff, 0xff, 0xe2, + 0x0, 0x0, 0x0, 0x0, 0x2d, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, + 0x1e, 0xff, 0xff, 0xff, 0xff, 0xf9, 0xff, 0xff, + 0xff, 0xe2, 0x0, 0x0, 0x8, 0xff, 0xff, 0xef, + 0xff, 0xf6, 0x5, 0xff, 0xff, 0xff, 0xe2, 0x0, + 0x0, 0xdf, 0xfe, 0x10, 0x7f, 0xff, 0x50, 0x5, + 0xff, 0xff, 0xff, 0xe2, 0x0, 0xf, 0xff, 0x80, + 0x0, 0xff, 0xf7, 0x0, 0x5, 0xff, 0xff, 0xff, + 0xe2, 0x0, 0xef, 0xfc, 0x0, 0x4f, 0xff, 0x60, + 0x0, 0x5, 0xff, 0xff, 0xff, 0xe2, 0xa, 0xff, + 0xfd, 0xbf, 0xff, 0xf2, 0x0, 0x0, 0x5, 0xff, + 0xff, 0xff, 0xe2, 0x2f, 0xff, 0xff, 0xff, 0xf9, + 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, 0xff, 0x40, + 0x4f, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xbe, 0xfb, 0x30, 0x0, 0x18, 0xcd, 0xb5, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F0C5 "" */ + 0x0, 0x0, 0x0, 0x1, 0x44, 0x44, 0x44, 0x44, + 0x42, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0x80, 0xeb, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0xe, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0xef, + 0xfb, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xf8, 0xe, 0xff, 0xfb, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0xef, 0xff, 0xf4, 0xaf, 0xff, 0xf4, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xfa, 0x0, 0x0, 0x0, 0xf, + 0xff, 0xff, 0x40, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0xbb, 0xbb, 0xb3, 0xff, 0xff, 0xf4, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x5f, 0xff, 0xff, 0x40, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xf4, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x5f, 0xff, 0xff, 0x40, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, + 0xf4, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x5f, 0xff, 0xff, 0x40, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, + 0xff, 0xf4, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x5f, 0xff, 0xff, 0x40, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0xff, 0xff, 0xf4, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x5f, 0xff, 0xff, 0x40, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf5, 0xff, 0xff, 0xf4, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x5f, 0xff, 0xff, + 0x40, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0xff, 0xff, 0xf4, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5f, 0xff, + 0xff, 0x40, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf5, 0xff, 0xff, 0xf5, 0xa, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x1f, + 0xff, 0xff, 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xa2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, + 0x0, 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x60, 0x0, 0x0, 0x0, 0x37, 0x88, + 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x60, 0x0, + 0x0, 0x0, 0x0, + + /* U+F0C7 "" */ + 0x4, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x87, 0x20, 0x0, 0x0, 0x6, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0x0, + 0x0, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x40, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x40, 0x0, 0xff, 0xf9, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xd, 0xff, 0xff, 0x40, 0xf, 0xff, + 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, + 0xff, 0xff, 0x30, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xb, 0xff, 0xff, 0xfe, 0xf, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xff, 0xff, 0xf3, 0xff, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, + 0x4f, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xbf, 0xff, 0xff, 0xf4, 0xff, 0xfd, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x7e, 0xff, 0xff, + 0xff, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x82, 0x15, 0xef, 0xff, + 0xff, 0xff, 0xff, 0x4f, 0xff, 0xff, 0xff, 0xff, + 0x70, 0x0, 0x3, 0xff, 0xff, 0xff, 0xff, 0xf4, + 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, 0xb, + 0xff, 0xff, 0xff, 0xff, 0x4f, 0xff, 0xff, 0xff, + 0xfc, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, 0xff, + 0xf4, 0xff, 0xff, 0xff, 0xff, 0xe0, 0x0, 0x0, + 0x9, 0xff, 0xff, 0xff, 0xff, 0x4f, 0xff, 0xff, + 0xff, 0xff, 0x30, 0x0, 0x0, 0xef, 0xff, 0xff, + 0xff, 0xf4, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x10, + 0x0, 0x9f, 0xff, 0xff, 0xff, 0xff, 0x4f, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0xa9, 0xdf, 0xff, 0xff, + 0xff, 0xff, 0xf4, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3a, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe0, 0x1a, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc3, + 0x0, + + /* U+F0C9 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xd, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0xae, 0xee, 0xee, 0xee, 0xee, 0xee, + 0xee, 0xee, 0xee, 0xee, 0xee, 0xed, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x7, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbb, 0xa2, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x61, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xae, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, + 0xee, 0xee, 0xee, 0xee, 0xed, 0x4f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8d, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F0E0 "" */ + 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xb1, 0xbf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x7, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x70, 0x0, 0x3e, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe3, 0x0, 0xe5, 0x1, 0xbf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, 0x10, 0x5e, + 0xff, 0x90, 0x7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x70, 0x9, 0xff, 0xff, 0xfd, + 0x20, 0x3d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xd3, 0x2, 0xdf, 0xff, 0xff, 0xff, 0xf6, 0x0, + 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, 0x6f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xa1, 0x6, 0xff, + 0xff, 0xff, 0xff, 0x60, 0xa, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x30, 0x2d, 0xff, 0xff, + 0xd2, 0x3, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf6, 0x0, 0x7e, 0xe7, 0x0, 0x7f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xb1, 0x0, 0x0, 0x1b, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x95, 0x59, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xb1, + + /* U+F0E7 "" */ + 0x0, 0x8, 0xbb, 0xbb, 0xbb, 0xbb, 0x80, 0x0, + 0x0, 0x0, 0x3, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x20, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, 0xaf, + 0xff, 0xff, 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, + 0xc, 0xff, 0xff, 0xff, 0xff, 0xf1, 0x0, 0x0, + 0x0, 0x0, 0xef, 0xff, 0xff, 0xff, 0xfb, 0x0, + 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, + 0x60, 0x0, 0x0, 0x0, 0x3, 0xff, 0xff, 0xff, + 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd2, 0x7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x70, 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf1, 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0x0, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfd, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x0, 0xaf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5f, 0xff, 0xff, 0xf2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcf, + 0xff, 0xfe, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0x60, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3, 0xff, 0xff, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x7f, 0xff, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xfb, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xff, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2f, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6, 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaf, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F0EA "" */ + 0x0, 0x0, 0x0, 0x1, 0x43, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xff, 0xfe, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x49, 0x99, 0x99, 0xff, 0xef, 0xfe, 0x99, + 0x99, 0x81, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xa0, 0x1e, 0xff, 0xff, 0xff, 0x90, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xfa, 0x1, 0xef, + 0xff, 0xff, 0xfa, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfa, 0x0, 0x0, 0x0, 0xf, + 0xff, 0xff, 0xff, 0xfc, 0x64, 0x44, 0x44, 0x44, + 0x30, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xff, 0x20, 0xaf, 0xff, 0xff, + 0xff, 0xa0, 0xd6, 0x0, 0x0, 0xff, 0xff, 0xff, + 0xf0, 0x1f, 0xff, 0xff, 0xff, 0xfa, 0xe, 0xf6, + 0x0, 0xf, 0xff, 0xff, 0xff, 0x1, 0xff, 0xff, + 0xff, 0xff, 0xa0, 0xef, 0xf6, 0x0, 0xff, 0xff, + 0xff, 0xf0, 0x1f, 0xff, 0xff, 0xff, 0xfa, 0xe, + 0xff, 0xf6, 0xf, 0xff, 0xff, 0xff, 0x1, 0xff, + 0xff, 0xff, 0xff, 0xa0, 0xef, 0xff, 0xf3, 0xff, + 0xff, 0xff, 0xf0, 0x1f, 0xff, 0xff, 0xff, 0xfa, + 0x4, 0x44, 0x44, 0x1f, 0xff, 0xff, 0xff, 0x1, + 0xff, 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xf0, 0x1f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x5f, 0xff, 0xff, 0xff, + 0x1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf5, 0xff, 0xff, 0xff, 0xf0, 0x1f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x5f, 0xff, 0xff, + 0xff, 0x1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0xff, 0xff, 0xff, 0xf0, 0x1f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5f, 0xff, + 0xff, 0xff, 0x1, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf5, 0xaf, 0xff, 0xff, 0xf0, 0x1f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, + 0x0, 0x0, 0x0, 0x1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, + 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x50, 0x0, 0x0, 0x0, 0x1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf5, 0x0, 0x0, 0x0, + 0x0, 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0x1, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x42, 0x0, + + /* U+F0F3 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0xa2, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5, 0xff, 0xd0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0x8d, 0xff, 0xfa, 0x50, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xff, 0xff, + 0xff, 0xff, 0xd4, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xd0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x0, + 0x0, 0x0, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x6, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, + 0x0, 0x0, 0x0, 0x7f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x0, 0x0, 0x0, 0x9f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x10, 0x0, 0x0, + 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf4, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x0, + 0x0, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfb, 0x0, 0x0, 0x9, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf1, + 0x0, 0x3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xa0, 0x1, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x70, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3e, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0x6f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xff, 0xff, 0xff, + 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xe, 0xff, 0xff, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3e, 0xff, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x15, 0x73, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+F11C "" */ + 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x50, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0xff, 0xfd, 0x88, 0x9f, 0xf8, 0x88, 0xff, 0x98, + 0x8e, 0xfa, 0x88, 0xbf, 0xd8, 0x89, 0xff, 0xf8, + 0xff, 0xf8, 0x0, 0xf, 0xc0, 0x0, 0xcf, 0x0, + 0xa, 0xf1, 0x0, 0x4f, 0x70, 0x0, 0xff, 0xf8, + 0xff, 0xf8, 0x0, 0xf, 0xc0, 0x0, 0xcf, 0x0, + 0xa, 0xf1, 0x0, 0x4f, 0x70, 0x0, 0xff, 0xf8, + 0xff, 0xf9, 0x0, 0x1f, 0xd0, 0x0, 0xdf, 0x10, + 0xc, 0xf3, 0x0, 0x6f, 0x90, 0x1, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xdc, 0xce, 0xfe, 0xcc, 0xdf, + 0xfc, 0xcd, 0xff, 0xcc, 0xcf, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0x20, 0x6, 0xf6, 0x0, 0x3f, + 0x80, 0x0, 0xfd, 0x0, 0xa, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0x20, 0x6, 0xf6, 0x0, 0x2f, + 0x80, 0x0, 0xed, 0x0, 0xa, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0x20, 0x6, 0xf6, 0x0, 0x3f, + 0x80, 0x0, 0xfd, 0x0, 0xa, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xdc, 0xce, 0xfe, 0xcc, 0xdf, + 0xfc, 0xcd, 0xff, 0xcc, 0xcf, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xf9, 0x0, 0x1f, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6f, 0x90, 0x1, 0xff, 0xf8, + 0xff, 0xf8, 0x0, 0xf, 0xc0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0x70, 0x0, 0xff, 0xf8, + 0xff, 0xf8, 0x0, 0xf, 0xc0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0x70, 0x0, 0xff, 0xf8, + 0xff, 0xfd, 0x88, 0x9f, 0xf8, 0x88, 0x88, 0x88, + 0x88, 0x88, 0x88, 0xbf, 0xd8, 0x89, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, + 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x50, + + /* U+F124 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x5, 0x72, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6, 0xef, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x18, 0xef, 0xff, 0xff, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x29, 0xff, + 0xff, 0xff, 0xff, 0xe0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x3a, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4c, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x6d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x7e, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x0, + 0x0, 0x0, 0x0, 0x1, 0x8f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x0, 0x0, + 0x0, 0x2, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x50, 0x0, 0x0, 0x4, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfd, 0x0, 0x0, 0x1, 0xbf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf6, 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, + 0x0, 0x0, 0xd, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x10, 0x0, + 0x0, 0x4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x3, 0x44, 0x44, 0x44, 0x44, 0x4d, 0xff, + 0xff, 0xff, 0xff, 0xf2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, + 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, + 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xff, 0xff, 0xff, 0xd0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xff, 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, + 0xff, 0xff, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, + 0xff, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xff, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x2, 0xff, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x17, 0x60, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+F15B "" */ + 0x14, 0x44, 0x44, 0x44, 0x44, 0x44, 0x10, 0x30, + 0x0, 0x0, 0xd, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf4, 0xf, 0xa0, 0x0, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x40, 0xff, 0xa0, 0x0, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0xf, 0xff, + 0xa0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x40, 0xff, 0xff, 0xa0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf4, 0xf, 0xff, 0xff, 0xa0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x40, 0xff, 0xff, + 0xff, 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + 0xb, 0xbb, 0xbb, 0xbb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x14, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x10, + + /* U+F1EB "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0x69, 0xab, 0xcb, 0xa9, 0x63, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x27, + 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc7, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xb3, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfc, 0x20, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xba, + 0xaa, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x1, 0xdf, 0xff, 0xff, 0xff, 0xc7, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x37, 0xcf, 0xff, 0xff, + 0xff, 0xd1, 0x3, 0xef, 0xff, 0xff, 0xf9, 0x20, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x29, + 0xff, 0xff, 0xff, 0xe3, 0xef, 0xff, 0xff, 0xb2, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0xbf, 0xff, 0xff, 0xe7, 0xff, 0xff, + 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xf7, 0x7, + 0xfe, 0x20, 0x0, 0x0, 0x0, 0x48, 0xbe, 0xff, + 0xfd, 0xb8, 0x40, 0x0, 0x0, 0x0, 0x2d, 0xf7, + 0x0, 0x4, 0x10, 0x0, 0x0, 0x18, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xe8, 0x10, 0x0, 0x0, + 0x14, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6e, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xbf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xb1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0xff, 0xff, 0xff, 0xc8, 0x76, 0x78, 0xcf, + 0xff, 0xff, 0xff, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xe7, 0x0, 0x0, 0x0, + 0x0, 0x7, 0xef, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0xff, 0x90, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x9f, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x47, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x7f, 0xff, 0x70, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xff, 0xff, + 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0xff, + 0xff, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xff, 0xff, 0xfc, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4f, 0xff, 0xff, 0x40, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3b, 0xdb, 0x30, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F240 "" */ + 0x2, 0x67, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x74, + 0x0, 0x5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf9, 0x0, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0xff, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, 0x9f, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, + 0xff, 0xff, 0xf8, 0xc, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x4, + 0xff, 0xff, 0xff, 0xff, 0x80, 0xcf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x28, 0xcf, 0xff, 0xff, 0xf8, 0xc, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x8, 0xff, 0xff, 0xff, 0x80, + 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0x0, 0x8f, 0xff, 0xff, + 0xf8, 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x8, 0xff, + 0xff, 0xff, 0x80, 0xcf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x3f, + 0xff, 0xff, 0xff, 0xf8, 0xc, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x4, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xfe, 0xff, 0xfb, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x79, 0xff, 0xfa, 0x3f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe0, 0x1, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xd3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F241 "" */ + 0x2, 0x67, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x74, + 0x0, 0x5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf9, 0x0, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0xff, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, 0x9f, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, + 0xff, 0xff, 0xf8, 0xe, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0x0, 0x4, + 0xff, 0xff, 0xff, 0xff, 0x80, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, 0x0, 0x0, + 0x0, 0x28, 0xcf, 0xff, 0xff, 0xf8, 0xe, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, + 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0x80, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xf8, 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x90, 0x0, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xff, 0x80, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf9, 0x0, 0x0, 0x0, 0x3f, + 0xff, 0xff, 0xff, 0xf8, 0xe, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0x0, + 0x4, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xfe, 0xff, 0xfb, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x79, 0xff, 0xfa, 0x3f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe0, 0x1, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xd3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F242 "" */ + 0x2, 0x67, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x74, + 0x0, 0x5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf9, 0x0, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0xff, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, 0x9f, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, + 0xff, 0xff, 0xf8, 0xe, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, + 0xff, 0xff, 0xff, 0xff, 0x80, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x28, 0xcf, 0xff, 0xff, 0xf8, 0xe, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf5, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0x80, + 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xf8, 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xff, 0x80, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, + 0xff, 0xff, 0xff, 0xf8, 0xe, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xfe, 0xff, 0xfb, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x79, 0xff, 0xfa, 0x3f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe0, 0x1, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xd3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F243 "" */ + 0x2, 0x67, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x74, + 0x0, 0x5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf9, 0x0, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0xff, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, 0x9f, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, + 0xff, 0xff, 0xf8, 0xe, 0xff, 0xff, 0xff, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, + 0xff, 0xff, 0xff, 0xff, 0x80, 0xef, 0xff, 0xff, + 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x28, 0xcf, 0xff, 0xff, 0xf8, 0xe, 0xff, + 0xff, 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0x80, + 0xef, 0xff, 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xf8, 0xe, 0xff, 0xff, 0xff, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xff, 0x80, 0xef, 0xff, 0xff, 0xf1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, + 0xff, 0xff, 0xff, 0xf8, 0xe, 0xff, 0xff, 0xff, + 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xfe, 0xff, 0xfb, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x79, 0xff, 0xfa, 0x3f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe0, 0x1, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xd3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F244 "" */ + 0x2, 0x67, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x74, + 0x0, 0x5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf9, 0x0, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf1, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0xff, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0xff, 0x9f, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, + 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, + 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x28, 0xcf, 0xff, 0xff, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, + 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xff, 0xfe, 0xff, 0xfb, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x79, 0xff, 0xfa, 0x3f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe0, 0x1, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xd3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F287 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x5e, 0xfe, 0x40, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1, 0x23, 0xff, 0xff, 0xf1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xbf, 0xff, 0xff, + 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, + 0xcd, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5f, 0xe1, 0x0, 0xcf, 0xff, 0xc0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0x50, 0x0, 0x7, 0xa7, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, + 0x10, 0x0, 0x0, 0x4, 0xfd, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4, 0xef, 0xfc, 0x20, 0x0, 0xc, 0xf5, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x40, + 0x0, 0x0, 0x4f, 0xff, 0xff, 0xe1, 0x0, 0x4f, + 0xe0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xfb, 0x20, 0x0, 0xcf, 0xff, 0xff, 0xfa, + 0x35, 0xef, 0x94, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x4d, 0xff, 0xf7, 0x0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, + 0xef, 0xff, 0xff, 0xfe, 0xbb, 0xbb, 0xbc, 0xff, + 0xcb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbf, 0xff, + 0xfe, 0x50, 0x8f, 0xff, 0xff, 0xf4, 0x0, 0x0, + 0x0, 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xff, 0x80, 0x0, 0xb, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0xe, 0xf2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xc, 0xb2, 0x0, 0x0, 0x0, 0x58, + 0x73, 0x0, 0x0, 0x0, 0x0, 0x7, 0xfa, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0xff, 0x20, 0x6, 0xdd, 0xdd, 0xc2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xc0, 0x9, 0xff, 0xff, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xc, 0xff, 0xde, 0xff, + 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0xaf, + 0xff, 0xff, 0xff, 0xf4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x19, 0xff, 0xff, 0xf4, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0xff, 0xf4, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F293 "" */ + 0x0, 0x0, 0x0, 0x0, 0x1, 0x34, 0x32, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3a, 0xef, + 0xff, 0xff, 0xfb, 0x50, 0x0, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x10, + 0x0, 0x0, 0x1, 0xcf, 0xff, 0xff, 0xc7, 0xff, + 0xff, 0xff, 0xd1, 0x0, 0x0, 0xb, 0xff, 0xff, + 0xff, 0xc0, 0x8f, 0xff, 0xff, 0xfc, 0x0, 0x0, + 0x5f, 0xff, 0xff, 0xff, 0xc0, 0x9, 0xff, 0xff, + 0xff, 0x50, 0x0, 0xcf, 0xff, 0xff, 0xff, 0xc0, + 0x0, 0xaf, 0xff, 0xff, 0xb0, 0x2, 0xff, 0xff, + 0xff, 0xff, 0xc0, 0x0, 0xb, 0xff, 0xff, 0xf1, + 0x6, 0xff, 0xff, 0xaf, 0xff, 0xc0, 0x39, 0x0, + 0xcf, 0xff, 0xf5, 0xa, 0xff, 0xf9, 0x3, 0xef, + 0xc0, 0x3f, 0x90, 0x1d, 0xff, 0xf8, 0xc, 0xff, + 0xfd, 0x10, 0x3e, 0xc0, 0x2f, 0xb0, 0xc, 0xff, + 0xfa, 0xe, 0xff, 0xff, 0xd1, 0x3, 0xb0, 0x2b, + 0x0, 0xaf, 0xff, 0xfc, 0xf, 0xff, 0xff, 0xfd, + 0x10, 0x10, 0x0, 0x9, 0xff, 0xff, 0xfd, 0xf, + 0xff, 0xff, 0xff, 0xd1, 0x0, 0x0, 0x7f, 0xff, + 0xff, 0xfe, 0x1f, 0xff, 0xff, 0xff, 0xfd, 0x10, + 0x5, 0xff, 0xff, 0xff, 0xfe, 0x1f, 0xff, 0xff, + 0xff, 0xfb, 0x0, 0x3, 0xff, 0xff, 0xff, 0xfe, + 0xf, 0xff, 0xff, 0xff, 0xb0, 0x0, 0x0, 0x3f, + 0xff, 0xff, 0xfd, 0xf, 0xff, 0xff, 0xfb, 0x0, + 0x20, 0x11, 0x4, 0xff, 0xff, 0xfd, 0xe, 0xff, + 0xff, 0xb0, 0x5, 0xc0, 0x2d, 0x10, 0x5f, 0xff, + 0xfc, 0xc, 0xff, 0xfb, 0x0, 0x5f, 0xc0, 0x2f, + 0xd0, 0x7, 0xff, 0xfa, 0x9, 0xff, 0xfb, 0x5, + 0xff, 0xc0, 0x3f, 0x60, 0x1d, 0xff, 0xf7, 0x5, + 0xff, 0xff, 0xdf, 0xff, 0xc0, 0x36, 0x1, 0xdf, + 0xff, 0xf4, 0x1, 0xff, 0xff, 0xff, 0xff, 0xd0, + 0x0, 0x1d, 0xff, 0xff, 0xf0, 0x0, 0xaf, 0xff, + 0xff, 0xff, 0xd0, 0x1, 0xdf, 0xff, 0xff, 0xa0, + 0x0, 0x2f, 0xff, 0xff, 0xff, 0xd0, 0x1d, 0xff, + 0xff, 0xff, 0x20, 0x0, 0x6, 0xff, 0xff, 0xff, + 0xd1, 0xcf, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0x6f, 0xff, 0xff, 0xec, 0xff, 0xff, 0xff, 0xb0, + 0x0, 0x0, 0x0, 0x2, 0xaf, 0xff, 0xff, 0xff, + 0xff, 0xe7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0x58, 0xab, 0xba, 0x84, 0x0, 0x0, 0x0, + + /* U+F2ED "" */ + 0x0, 0x0, 0x0, 0x0, 0x14, 0x44, 0x44, 0x43, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1f, 0xff, 0xff, 0xff, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x58, 0x88, 0x88, 0x8c, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0x88, 0x88, 0x88, 0x1f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8b, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xe4, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x28, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x88, 0x88, 0x86, 0x0, 0x4, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, + 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfc, 0x0, 0x4, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xc0, 0x0, 0x4f, 0xff, 0xf5, 0x5f, 0xff, 0x92, + 0xff, 0xfc, 0x1c, 0xff, 0xfc, 0x0, 0x4, 0xff, + 0xff, 0x22, 0xff, 0xf6, 0xe, 0xff, 0xa0, 0xaf, + 0xff, 0xc0, 0x0, 0x4f, 0xff, 0xf2, 0x2f, 0xff, + 0x60, 0xef, 0xfa, 0xa, 0xff, 0xfc, 0x0, 0x4, + 0xff, 0xff, 0x22, 0xff, 0xf6, 0xe, 0xff, 0xa0, + 0xaf, 0xff, 0xc0, 0x0, 0x4f, 0xff, 0xf2, 0x2f, + 0xff, 0x60, 0xef, 0xfa, 0xa, 0xff, 0xfc, 0x0, + 0x4, 0xff, 0xff, 0x22, 0xff, 0xf6, 0xe, 0xff, + 0xa0, 0xaf, 0xff, 0xc0, 0x0, 0x4f, 0xff, 0xf2, + 0x2f, 0xff, 0x60, 0xef, 0xfa, 0xa, 0xff, 0xfc, + 0x0, 0x4, 0xff, 0xff, 0x22, 0xff, 0xf6, 0xe, + 0xff, 0xa0, 0xaf, 0xff, 0xc0, 0x0, 0x4f, 0xff, + 0xf2, 0x2f, 0xff, 0x60, 0xef, 0xfa, 0xa, 0xff, + 0xfc, 0x0, 0x4, 0xff, 0xff, 0x22, 0xff, 0xf6, + 0xe, 0xff, 0xa0, 0xaf, 0xff, 0xc0, 0x0, 0x4f, + 0xff, 0xf2, 0x2f, 0xff, 0x60, 0xef, 0xfa, 0xa, + 0xff, 0xfc, 0x0, 0x4, 0xff, 0xff, 0x22, 0xff, + 0xf6, 0xe, 0xff, 0xa0, 0xaf, 0xff, 0xc0, 0x0, + 0x4f, 0xff, 0xf2, 0x2f, 0xff, 0x60, 0xef, 0xfa, + 0xa, 0xff, 0xfc, 0x0, 0x4, 0xff, 0xff, 0x55, + 0xff, 0xf9, 0x2f, 0xff, 0xc1, 0xcf, 0xff, 0xc0, + 0x0, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfb, 0x0, 0x2, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xa0, 0x0, 0x9, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf2, 0x0, 0x0, 0x4, + 0x78, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, + 0x61, 0x0, 0x0, + + /* U+F304 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x66, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xdf, 0xfe, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, + 0xff, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, 0xff, 0xff, + 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9f, 0xff, 0xff, 0xff, 0xff, + 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0x0, 0xbf, 0xff, 0xff, 0xff, 0xfc, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xec, + 0x0, 0xbf, 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, 0xfc, 0x0, + 0xbf, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xef, 0xff, 0xfc, 0x0, 0xbf, + 0xff, 0xfe, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xef, 0xff, 0xff, 0xfc, 0x0, 0xbf, 0xfe, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, + 0xff, 0xff, 0xff, 0xfc, 0x0, 0xbe, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xfc, 0x0, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xdf, 0xff, 0xff, 0xff, 0xfe, + 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xf, 0xff, 0xff, 0xff, 0xfe, 0x20, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xef, 0xff, 0xff, 0xec, 0x20, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x76, + 0x42, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F55A "" */ + 0x0, 0x0, 0x0, 0x0, 0x8, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xd5, 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf5, 0x0, 0x0, 0x0, 0xb, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0, 0x0, 0xb, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0x0, + 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x99, 0xff, + 0xff, 0xff, 0x99, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x8, 0xff, 0xff, 0x80, 0x7, 0xff, 0xff, 0xff, + 0xff, 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe0, 0x0, 0x8, 0xff, 0x80, 0x0, 0xe, 0xff, + 0xff, 0xff, 0xf0, 0xb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x8, 0x80, 0x0, 0x8, + 0xff, 0xff, 0xff, 0xff, 0xb, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, + 0x8, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x0, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x40, 0x0, 0x4, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0x0, 0x0, 0x8, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x8, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xb, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x0, 0x8, 0x80, 0x0, + 0x8, 0xff, 0xff, 0xff, 0xff, 0x0, 0xb, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xe0, 0x0, 0x8, 0xff, + 0x80, 0x0, 0xe, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x8, + 0xff, 0xff, 0x80, 0x8, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x99, 0xff, 0xff, 0xff, 0x99, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x0, 0x0, 0xb, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0xb, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x0, 0x0, + 0x0, 0x0, 0x8, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd5, 0x0, + + /* U+F7C2 "" */ + 0x0, 0x0, 0x0, 0x17, 0x88, 0x88, 0x88, 0x88, + 0x87, 0x50, 0x0, 0x0, 0x0, 0x1d, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xc1, 0x0, 0x0, 0x2d, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa0, + 0x0, 0x2e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x2e, 0xff, 0x20, 0x1f, 0xa0, + 0xe, 0xd0, 0x8, 0xff, 0xf0, 0x2e, 0xff, 0xf2, + 0x1, 0xfa, 0x0, 0xed, 0x0, 0x8f, 0xff, 0x3e, + 0xff, 0xff, 0x20, 0x1f, 0xa0, 0xe, 0xd0, 0x8, + 0xff, 0xfe, 0xff, 0xff, 0xf2, 0x1, 0xfa, 0x0, + 0xed, 0x0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0x20, + 0x1f, 0xa0, 0xe, 0xd0, 0x8, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0xaf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0x24, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x20, + 0x0, + + /* U+F8A2 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xf1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x9, 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, + 0xff, 0xf1, 0x0, 0x0, 0x0, 0x5c, 0x50, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0xff, 0xff, + 0x10, 0x0, 0x0, 0x7f, 0xfd, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4f, 0xff, 0xf1, 0x0, + 0x0, 0x8f, 0xff, 0xd0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4, 0xff, 0xff, 0x10, 0x0, 0x9f, + 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xff, 0xf1, 0x0, 0xaf, 0xff, 0xff, + 0xd0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, + 0xff, 0xff, 0x10, 0xbf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf1, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1c, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf1, 0x2e, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x0, 0x1d, 0xff, 0xff, + 0xfe, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, + 0x55, 0x55, 0x10, 0x0, 0x1c, 0xff, 0xff, 0xd0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xff, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xff, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xa, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+FF1A "：" */ + 0x4a, 0xaa, 0x7, 0xff, 0xf1, 0x7f, 0xff, 0x17, + 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11, + 0x10, 0x7f, 0xff, 0x17, 0xff, 0xf1, 0x7f, 0xff, + 0x14, 0x99, 0x91 +}; + + +/*--------------------- + * GLYPH DESCRIPTION + *--------------------*/ + +static const lv_font_fmt_txt_glyph_dsc_t glyph_dsc[] = { + {.bitmap_index = 0, .adv_w = 0, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0} /* id = 0 reserved */, + {.bitmap_index = 0, .adv_w = 113, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 0, .adv_w = 130, .box_w = 4, .box_h = 22, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 44, .adv_w = 165, .box_w = 9, .box_h = 8, .ofs_x = 1, .ofs_y = 13}, + {.bitmap_index = 80, .adv_w = 259, .box_w = 17, .box_h = 21, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 259, .adv_w = 272, .box_w = 15, .box_h = 27, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 462, .adv_w = 418, .box_w = 24, .box_h = 22, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 726, .adv_w = 333, .box_w = 20, .box_h = 23, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 956, .adv_w = 88, .box_w = 4, .box_h = 8, .ofs_x = 1, .ofs_y = 13}, + {.bitmap_index = 972, .adv_w = 155, .box_w = 8, .box_h = 27, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 1080, .adv_w = 155, .box_w = 8, .box_h = 27, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 1188, .adv_w = 190, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = 10}, + {.bitmap_index = 1249, .adv_w = 281, .box_w = 16, .box_h = 15, .ofs_x = 1, .ofs_y = 2}, + {.bitmap_index = 1369, .adv_w = 227, .box_w = 12, .box_h = 3, .ofs_x = 1, .ofs_y = 9}, + {.bitmap_index = 1387, .adv_w = 136, .box_w = 4, .box_h = 4, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 1395, .adv_w = 126, .box_w = 9, .box_h = 22, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1494, .adv_w = 257, .box_w = 15, .box_h = 21, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1652, .adv_w = 210, .box_w = 7, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 1726, .adv_w = 252, .box_w = 14, .box_h = 21, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 1873, .adv_w = 254, .box_w = 14, .box_h = 21, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2020, .adv_w = 257, .box_w = 16, .box_h = 21, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 2188, .adv_w = 254, .box_w = 14, .box_h = 21, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2335, .adv_w = 257, .box_w = 14, .box_h = 21, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2482, .adv_w = 254, .box_w = 14, .box_h = 21, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2629, .adv_w = 260, .box_w = 15, .box_h = 21, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2787, .adv_w = 257, .box_w = 14, .box_h = 21, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 2934, .adv_w = 133, .box_w = 4, .box_h = 16, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 2966, .adv_w = 133, .box_w = 4, .box_h = 22, .ofs_x = 2, .ofs_y = -7}, + {.bitmap_index = 3010, .adv_w = 281, .box_w = 16, .box_h = 20, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 3170, .adv_w = 275, .box_w = 15, .box_h = 9, .ofs_x = 1, .ofs_y = 5}, + {.bitmap_index = 3238, .adv_w = 279, .box_w = 15, .box_h = 20, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 3388, .adv_w = 259, .box_w = 15, .box_h = 22, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 3553, .adv_w = 427, .box_w = 25, .box_h = 24, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 3853, .adv_w = 316, .box_w = 20, .box_h = 21, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4063, .adv_w = 313, .box_w = 17, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 4242, .adv_w = 342, .box_w = 20, .box_h = 22, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 4462, .adv_w = 338, .box_w = 18, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 4651, .adv_w = 313, .box_w = 17, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 4830, .adv_w = 288, .box_w = 15, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 4988, .adv_w = 364, .box_w = 21, .box_h = 22, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 5219, .adv_w = 338, .box_w = 17, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 5398, .adv_w = 123, .box_w = 4, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 5440, .adv_w = 235, .box_w = 13, .box_h = 21, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5577, .adv_w = 313, .box_w = 18, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 5766, .adv_w = 263, .box_w = 14, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 5913, .adv_w = 392, .box_w = 21, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 6134, .adv_w = 338, .box_w = 17, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 6313, .adv_w = 367, .box_w = 21, .box_h = 22, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 6544, .adv_w = 313, .box_w = 17, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 6723, .adv_w = 367, .box_w = 21, .box_h = 28, .ofs_x = 1, .ofs_y = -7}, + {.bitmap_index = 7017, .adv_w = 338, .box_w = 19, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 7217, .adv_w = 313, .box_w = 18, .box_h = 21, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 7406, .adv_w = 288, .box_w = 18, .box_h = 21, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7595, .adv_w = 342, .box_w = 18, .box_h = 21, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 7784, .adv_w = 319, .box_w = 20, .box_h = 21, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7994, .adv_w = 446, .box_w = 28, .box_h = 21, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8288, .adv_w = 316, .box_w = 20, .box_h = 21, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8498, .adv_w = 313, .box_w = 20, .box_h = 21, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8708, .adv_w = 288, .box_w = 18, .box_h = 21, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8897, .adv_w = 126, .box_w = 6, .box_h = 27, .ofs_x = 2, .ofs_y = -4}, + {.bitmap_index = 8978, .adv_w = 126, .box_w = 8, .box_h = 22, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 9066, .adv_w = 126, .box_w = 7, .box_h = 27, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 9161, .adv_w = 221, .box_w = 14, .box_h = 12, .ofs_x = 0, .ofs_y = 9}, + {.bitmap_index = 9245, .adv_w = 279, .box_w = 18, .box_h = 2, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 9263, .adv_w = 148, .box_w = 6, .box_h = 5, .ofs_x = 1, .ofs_y = 16}, + {.bitmap_index = 9278, .adv_w = 263, .box_w = 15, .box_h = 16, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 9398, .adv_w = 259, .box_w = 15, .box_h = 22, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 9563, .adv_w = 237, .box_w = 14, .box_h = 16, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 9675, .adv_w = 259, .box_w = 14, .box_h = 22, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 9829, .adv_w = 263, .box_w = 15, .box_h = 16, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 9949, .adv_w = 132, .box_w = 10, .box_h = 22, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 10059, .adv_w = 263, .box_w = 15, .box_h = 21, .ofs_x = 0, .ofs_y = -6}, + {.bitmap_index = 10217, .adv_w = 259, .box_w = 14, .box_h = 22, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 10371, .adv_w = 98, .box_w = 3, .box_h = 22, .ofs_x = 2, .ofs_y = -1}, + {.bitmap_index = 10404, .adv_w = 98, .box_w = 7, .box_h = 27, .ofs_x = -2, .ofs_y = -6}, + {.bitmap_index = 10499, .adv_w = 235, .box_w = 14, .box_h = 22, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 10653, .adv_w = 98, .box_w = 4, .box_h = 22, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 10697, .adv_w = 389, .box_w = 22, .box_h = 16, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 10873, .adv_w = 263, .box_w = 14, .box_h = 16, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 10985, .adv_w = 263, .box_w = 15, .box_h = 16, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 11105, .adv_w = 259, .box_w = 15, .box_h = 21, .ofs_x = 1, .ofs_y = -6}, + {.bitmap_index = 11263, .adv_w = 259, .box_w = 14, .box_h = 21, .ofs_x = 1, .ofs_y = -6}, + {.bitmap_index = 11410, .adv_w = 164, .box_w = 10, .box_h = 16, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 11490, .adv_w = 244, .box_w = 13, .box_h = 16, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 11594, .adv_w = 130, .box_w = 8, .box_h = 22, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 11682, .adv_w = 259, .box_w = 14, .box_h = 16, .ofs_x = 1, .ofs_y = -1}, + {.bitmap_index = 11794, .adv_w = 235, .box_w = 15, .box_h = 16, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 11914, .adv_w = 338, .box_w = 22, .box_h = 16, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 12090, .adv_w = 235, .box_w = 15, .box_h = 16, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 12210, .adv_w = 235, .box_w = 15, .box_h = 21, .ofs_x = 0, .ofs_y = -6}, + {.bitmap_index = 12368, .adv_w = 235, .box_w = 15, .box_h = 16, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 12488, .adv_w = 155, .box_w = 10, .box_h = 27, .ofs_x = 0, .ofs_y = -5}, + {.bitmap_index = 12623, .adv_w = 117, .box_w = 3, .box_h = 27, .ofs_x = 2, .ofs_y = -4}, + {.bitmap_index = 12664, .adv_w = 155, .box_w = 10, .box_h = 27, .ofs_x = 0, .ofs_y = -5}, + {.bitmap_index = 12799, .adv_w = 275, .box_w = 16, .box_h = 4, .ofs_x = 1, .ofs_y = 8}, + {.bitmap_index = 12831, .adv_w = 448, .box_w = 26, .box_h = 25, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 13156, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 13494, .adv_w = 448, .box_w = 24, .box_h = 24, .ofs_x = 2, .ofs_y = -2}, + {.bitmap_index = 13782, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 14120, .adv_w = 448, .box_w = 24, .box_h = 23, .ofs_x = 2, .ofs_y = -2}, + {.bitmap_index = 14396, .adv_w = 448, .box_w = 26, .box_h = 24, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 14708, .adv_w = 448, .box_w = 26, .box_h = 24, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 15020, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 15358, .adv_w = 448, .box_w = 26, .box_h = 25, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 15683, .adv_w = 448, .box_w = 26, .box_h = 24, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 15995, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 16333, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 16671, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 17009, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 17347, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 17685, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 18023, .adv_w = 448, .box_w = 26, .box_h = 23, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 18322, .adv_w = 448, .box_w = 26, .box_h = 25, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 18647, .adv_w = 448, .box_w = 26, .box_h = 24, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 18959, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 19297, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 19635, .adv_w = 448, .box_w = 26, .box_h = 25, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 19960, .adv_w = 448, .box_w = 26, .box_h = 26, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 20298, .adv_w = 448, .box_w = 26, .box_h = 25, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 20623, .adv_w = 448, .box_w = 26, .box_h = 25, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 20948, .adv_w = 448, .box_w = 28, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 21354, .adv_w = 448, .box_w = 28, .box_h = 21, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 21648, .adv_w = 448, .box_w = 28, .box_h = 25, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 21998, .adv_w = 448, .box_w = 28, .box_h = 21, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 22292, .adv_w = 308, .box_w = 20, .box_h = 21, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 22502, .adv_w = 448, .box_w = 28, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 22908, .adv_w = 448, .box_w = 27, .box_h = 29, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 23300, .adv_w = 504, .box_w = 32, .box_h = 25, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 23700, .adv_w = 448, .box_w = 28, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 24106, .adv_w = 504, .box_w = 32, .box_h = 21, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 24442, .adv_w = 448, .box_w = 28, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 24848, .adv_w = 224, .box_w = 14, .box_h = 23, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 25009, .adv_w = 336, .box_w = 21, .box_h = 23, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 25251, .adv_w = 504, .box_w = 32, .box_h = 27, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 25683, .adv_w = 448, .box_w = 28, .box_h = 21, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 25977, .adv_w = 308, .box_w = 20, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 26267, .adv_w = 392, .box_w = 18, .box_h = 26, .ofs_x = 3, .ofs_y = -3}, + {.bitmap_index = 26501, .adv_w = 392, .box_w = 25, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 26864, .adv_w = 392, .box_w = 25, .box_h = 25, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 27177, .adv_w = 392, .box_w = 25, .box_h = 25, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 27490, .adv_w = 392, .box_w = 18, .box_h = 26, .ofs_x = 3, .ofs_y = -3}, + {.bitmap_index = 27724, .adv_w = 392, .box_w = 26, .box_h = 25, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 28049, .adv_w = 280, .box_w = 16, .box_h = 25, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 28249, .adv_w = 280, .box_w = 16, .box_h = 25, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 28449, .adv_w = 392, .box_w = 25, .box_h = 25, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 28762, .adv_w = 392, .box_w = 25, .box_h = 7, .ofs_x = 0, .ofs_y = 7}, + {.bitmap_index = 28850, .adv_w = 504, .box_w = 32, .box_h = 21, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 29186, .adv_w = 560, .box_w = 35, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 29694, .adv_w = 504, .box_w = 33, .box_h = 29, .ofs_x = -1, .ofs_y = -4}, + {.bitmap_index = 30173, .adv_w = 448, .box_w = 28, .box_h = 25, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 30523, .adv_w = 392, .box_w = 25, .box_h = 15, .ofs_x = 0, .ofs_y = 3}, + {.bitmap_index = 30711, .adv_w = 392, .box_w = 25, .box_h = 15, .ofs_x = 0, .ofs_y = 3}, + {.bitmap_index = 30899, .adv_w = 560, .box_w = 35, .box_h = 22, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 31284, .adv_w = 448, .box_w = 28, .box_h = 21, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 31578, .adv_w = 448, .box_w = 28, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 31984, .adv_w = 448, .box_w = 29, .box_h = 29, .ofs_x = -1, .ofs_y = -4}, + {.bitmap_index = 32405, .adv_w = 392, .box_w = 25, .box_h = 25, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 32718, .adv_w = 392, .box_w = 25, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 33081, .adv_w = 392, .box_w = 25, .box_h = 25, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 33394, .adv_w = 392, .box_w = 25, .box_h = 23, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 33682, .adv_w = 448, .box_w = 28, .box_h = 21, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 33976, .adv_w = 280, .box_w = 19, .box_h = 29, .ofs_x = -1, .ofs_y = -4}, + {.bitmap_index = 34252, .adv_w = 392, .box_w = 25, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 34615, .adv_w = 392, .box_w = 25, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 34978, .adv_w = 504, .box_w = 32, .box_h = 21, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 35314, .adv_w = 448, .box_w = 30, .box_h = 29, .ofs_x = -1, .ofs_y = -4}, + {.bitmap_index = 35749, .adv_w = 336, .box_w = 21, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 36054, .adv_w = 560, .box_w = 35, .box_h = 26, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 36509, .adv_w = 560, .box_w = 35, .box_h = 19, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 36842, .adv_w = 560, .box_w = 35, .box_h = 19, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 37175, .adv_w = 560, .box_w = 35, .box_h = 19, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 37508, .adv_w = 560, .box_w = 35, .box_h = 19, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 37841, .adv_w = 560, .box_w = 35, .box_h = 19, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 38174, .adv_w = 560, .box_w = 36, .box_h = 23, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 38588, .adv_w = 392, .box_w = 22, .box_h = 29, .ofs_x = 1, .ofs_y = -4}, + {.bitmap_index = 38907, .adv_w = 392, .box_w = 25, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 39270, .adv_w = 448, .box_w = 29, .box_h = 29, .ofs_x = -1, .ofs_y = -4}, + {.bitmap_index = 39691, .adv_w = 560, .box_w = 35, .box_h = 21, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 40059, .adv_w = 336, .box_w = 21, .box_h = 29, .ofs_x = 0, .ofs_y = -4}, + {.bitmap_index = 40364, .adv_w = 451, .box_w = 29, .box_h = 19, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 40640, .adv_w = 336, .box_w = 5, .box_h = 14, .ofs_x = 5, .ofs_y = -1} +}; + +/*--------------------- + * CHARACTER MAPPING + *--------------------*/ + +static const uint16_t unicode_list_2[] = { + 0x0, 0x93, 0x1c1, 0x26c, 0x6a2, 0x746, 0xe37, 0xed3, + 0xfeb, 0x120f, 0x12ad, 0x1502, 0x1534, 0x19e5, 0x1bf8, 0x1ed8, + 0x24ff, 0x26b8, 0x28fe, 0x2ce4, 0x2e83, 0x2eed, 0x3f98, 0x3fcd, + 0x4722, 0x9fc5, 0x9fcc, 0x9fcf, 0x9fd0, 0x9fd1, 0x9fd5, 0x9fd7, + 0x9fd9, 0x9fdd, 0x9fe0, 0x9fe5, 0x9fea, 0x9feb, 0x9fec, 0xa002, + 0xa007, 0xa00c, 0xa00f, 0xa010, 0xa011, 0xa015, 0xa016, 0xa017, + 0xa018, 0xa02b, 0xa02c, 0xa032, 0xa034, 0xa035, 0xa038, 0xa03b, + 0xa03c, 0xa03d, 0xa03f, 0xa057, 0xa059, 0xa088, 0xa089, 0xa08b, + 0xa08d, 0xa0a4, 0xa0ab, 0xa0ae, 0xa0b7, 0xa0e0, 0xa0e8, 0xa11f, + 0xa1af, 0xa204, 0xa205, 0xa206, 0xa207, 0xa208, 0xa24b, 0xa257, + 0xa2b1, 0xa2c8, 0xa51e, 0xa786, 0xa866, 0xaede +}; + +/*Collect the unicode lists and glyph_id offsets*/ +static const lv_font_fmt_txt_cmap_t cmaps[] = +{ + { + .range_start = 32, .range_length = 12, .glyph_id_start = 1, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 45, .range_length = 82, .glyph_id_start = 13, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 20540, .range_length = 44767, .glyph_id_start = 95, + .unicode_list = unicode_list_2, .glyph_id_ofs_list = NULL, .list_length = 86, .type = LV_FONT_FMT_TXT_CMAP_SPARSE_TINY + } +}; + + + +/*-------------------- + * ALL CUSTOM DATA + *--------------------*/ + +#if LV_VERSION_CHECK(8, 0, 0) +/*Store all the custom data of the font*/ +static lv_font_fmt_txt_glyph_cache_t cache; +static const lv_font_fmt_txt_dsc_t font_dsc = { +#else +static lv_font_fmt_txt_dsc_t font_dsc = { +#endif + .glyph_bitmap = glyph_bitmap, + .glyph_dsc = glyph_dsc, + .cmaps = cmaps, + .kern_dsc = NULL, + .kern_scale = 0, + .cmap_num = 3, + .bpp = 4, + .kern_classes = 0, + .bitmap_format = 0, +#if LV_VERSION_CHECK(8, 0, 0) + .cache = &cache +#endif +}; + + +/*----------------- + * PUBLIC FONT + *----------------*/ + +/*Initialize a public general font descriptor*/ +#if LV_VERSION_CHECK(8, 0, 0) +const lv_font_t lv_font_MI_LanTing_Regular_28 = { +#else +lv_font_t lv_font_MI_LanTing_Regular_28 = { +#endif + .get_glyph_dsc = lv_font_get_glyph_dsc_fmt_txt, /*Function pointer to get glyph's data*/ + .get_glyph_bitmap = lv_font_get_bitmap_fmt_txt, /*Function pointer to get glyph's bitmap*/ + .line_height = 28, /*The maximum line height required by the font default: (f.src.ascent - f.src.descent)*/ + .base_line = 5, /*Baseline measured from the bottom of the line*/ +#if !(LVGL_VERSION_MAJOR == 6 && LVGL_VERSION_MINOR == 0) + .subpx = LV_FONT_SUBPX_NONE, +#endif +#if LV_VERSION_CHECK(7, 4, 0) || LVGL_VERSION_MAJOR >= 8 + .underline_position = -3, + .underline_thickness = 1, +#endif + .dsc = &font_dsc /*The custom font data. Will be accessed by `get_glyph_bitmap/dsc` */ +}; + + + +#endif /*#if LV_FONT_MI_LANTING_REGULAR_28*/ + diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_montserratMedium_12.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_montserratMedium_12.c new file mode 100644 index 0000000000000000000000000000000000000000..aaf090c7642e7445c8a16d5b815c66ab808d9502 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_montserratMedium_12.c @@ -0,0 +1,1914 @@ +/* + * Copyright 2024 NXP + * NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in + * accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, + * activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to + * comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license + * terms, then you may not retain, install, activate or otherwise use the software. + */ +/******************************************************************************* + * Size: 12 px + * Bpp: 4 + * Opts: --user-data-dir=C:\Users\hp\AppData\Roaming\gui-guider --app-path=C:\NXP\GUI-Guider-1.7.2-GA\resources\app.asar --no-sandbox --no-zygote --lang=zh-CN --device-scale-factor=1.5 --num-raster-threads=4 --enable-main-frame-before-activation --renderer-client-id=5 --time-ticks-at-unix-epoch=-1732015070561205 --launch-time-ticks=65380923608 --mojo-platform-channel-handle=3108 --field-trial-handle=1864,i,17219279099561217522,18026807573185265005,131072 --disable-features=SpareRendererForSitePerProcess,WinRetrieveSuggestionsOnlyOnDemand /prefetch:1 + ******************************************************************************/ + +#ifdef LV_LVGL_H_INCLUDE_SIMPLE +#include "lvgl.h" +#else +#include "lvgl.h" +#endif + +#ifndef LV_FONT_MONTSERRATMEDIUM_12 +#define LV_FONT_MONTSERRATMEDIUM_12 1 +#endif + +#if LV_FONT_MONTSERRATMEDIUM_12 + +/*----------------- + * BITMAPS + *----------------*/ + +/*Store the image of the glyphs*/ +static LV_ATTRIBUTE_LARGE_CONST const uint8_t glyph_bitmap[] = { + /* U+0020 " " */ + + /* U+0021 "!" */ + 0xf, 0x40, 0xf3, 0xf, 0x30, 0xf2, 0xe, 0x20, + 0xd1, 0x3, 0x0, 0x81, 0x1e, 0x30, + + /* U+0022 "\"" */ + 0x3c, 0x1e, 0x3b, 0xe, 0x3b, 0xe, 0x15, 0x7, + + /* U+0023 "#" */ + 0x0, 0x48, 0x3, 0xa0, 0x0, 0x6, 0x60, 0x58, + 0x0, 0x4f, 0xff, 0xff, 0xff, 0x10, 0xa, 0x20, + 0x84, 0x0, 0x0, 0xc1, 0xa, 0x30, 0x0, 0xd, + 0x0, 0xb1, 0x0, 0xaf, 0xff, 0xff, 0xfb, 0x0, + 0x1c, 0x0, 0xd0, 0x0, 0x3, 0xa0, 0x1c, 0x0, + 0x0, + + /* U+0024 "$" */ + 0x0, 0x9, 0x20, 0x0, 0x0, 0x92, 0x0, 0x3, + 0xcf, 0xfb, 0x31, 0xf7, 0xa5, 0x74, 0x4e, 0x9, + 0x20, 0x1, 0xf9, 0xb2, 0x0, 0x2, 0xbf, 0xe8, + 0x0, 0x0, 0x97, 0xda, 0x0, 0x9, 0x24, 0xe5, + 0xb4, 0xa5, 0xba, 0x8, 0xef, 0xfa, 0x10, 0x0, + 0x92, 0x0, 0x0, 0x4, 0x10, 0x0, + + /* U+0025 "%" */ + 0xa, 0xc8, 0x0, 0xc, 0x10, 0x66, 0xa, 0x20, + 0x76, 0x0, 0x83, 0x7, 0x42, 0xc0, 0x0, 0x57, + 0xa, 0x2b, 0x20, 0x0, 0x9, 0xc6, 0x68, 0x5c, + 0x90, 0x0, 0x1, 0xc1, 0xc0, 0x67, 0x0, 0xa, + 0x43, 0x90, 0x2a, 0x0, 0x49, 0x1, 0xb0, 0x47, + 0x0, 0xc1, 0x0, 0x7b, 0xb1, + + /* U+0026 "&" */ + 0x0, 0x9e, 0xd4, 0x0, 0x0, 0x5c, 0x3, 0xd0, + 0x0, 0x4, 0xc0, 0x5c, 0x0, 0x0, 0xc, 0xbd, + 0x20, 0x0, 0x3, 0xde, 0x80, 0x10, 0x1, 0xe3, + 0x1d, 0x78, 0x80, 0x6b, 0x0, 0x1d, 0xf2, 0x4, + 0xf4, 0x13, 0xcf, 0x60, 0x6, 0xdf, 0xd6, 0x2b, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+0027 "'" */ + 0x3c, 0x3b, 0x3b, 0x15, + + /* U+0028 "(" */ + 0xa, 0x71, 0xf1, 0x5c, 0x9, 0x80, 0xb6, 0xc, + 0x40, 0xd4, 0xc, 0x40, 0xb6, 0x9, 0x80, 0x5b, + 0x1, 0xf1, 0xa, 0x70, + + /* U+0029 ")" */ + 0x6b, 0x0, 0xf2, 0xb, 0x60, 0x7a, 0x5, 0xc0, + 0x4d, 0x3, 0xe0, 0x4d, 0x5, 0xc0, 0x7a, 0xb, + 0x60, 0xf1, 0x6b, 0x0, + + /* U+002A "*" */ + 0x0, 0xb0, 0x8, 0x9c, 0xb5, 0xb, 0xf8, 0x8, + 0x7c, 0x95, 0x0, 0xa0, 0x0, + + /* U+002B "+" */ + 0x0, 0xb, 0x0, 0x0, 0x0, 0xf0, 0x0, 0x0, + 0xf, 0x0, 0x2, 0xee, 0xfe, 0xe2, 0x1, 0x1f, + 0x11, 0x0, 0x0, 0xf0, 0x0, + + /* U+002D "-" */ + 0x4f, 0xfd, 0x2, 0x22, + + /* U+002E "." */ + 0x2a, 0x4, 0xd0, + + /* U+002F "/" */ + 0x0, 0x0, 0x34, 0x0, 0x0, 0xb5, 0x0, 0x0, + 0xf0, 0x0, 0x5, 0xb0, 0x0, 0xa, 0x60, 0x0, + 0xe, 0x10, 0x0, 0x4c, 0x0, 0x0, 0x97, 0x0, + 0x0, 0xe2, 0x0, 0x3, 0xd0, 0x0, 0x8, 0x70, + 0x0, 0xd, 0x20, 0x0, 0x2d, 0x0, 0x0, + + /* U+0030 "0" */ + 0x0, 0x9e, 0xe9, 0x0, 0xa, 0xd4, 0x4d, 0xa0, + 0x1f, 0x20, 0x2, 0xf1, 0x5e, 0x0, 0x0, 0xd5, + 0x6c, 0x0, 0x0, 0xc6, 0x5e, 0x0, 0x0, 0xd5, + 0x1f, 0x20, 0x2, 0xf1, 0xa, 0xd4, 0x4d, 0xa0, + 0x0, 0x9e, 0xe9, 0x0, + + /* U+0031 "1" */ + 0xef, 0xf3, 0x22, 0xf3, 0x0, 0xf3, 0x0, 0xf3, + 0x0, 0xf3, 0x0, 0xf3, 0x0, 0xf3, 0x0, 0xf3, + 0x0, 0xf3, + + /* U+0032 "2" */ + 0x19, 0xef, 0xc2, 0x8, 0xb4, 0x3a, 0xe0, 0x0, + 0x0, 0x2f, 0x10, 0x0, 0x5, 0xe0, 0x0, 0x2, + 0xe5, 0x0, 0x1, 0xd7, 0x0, 0x1, 0xd8, 0x0, + 0x1, 0xda, 0x22, 0x21, 0x8f, 0xff, 0xff, 0x70, + + /* U+0033 "3" */ + 0x9f, 0xff, 0xff, 0x1, 0x22, 0x2d, 0x80, 0x0, + 0x9, 0xb0, 0x0, 0x5, 0xf2, 0x0, 0x0, 0x7c, + 0xf8, 0x0, 0x0, 0x2, 0xf2, 0x0, 0x0, 0xe, + 0x4b, 0x94, 0x39, 0xf1, 0x3b, 0xff, 0xc3, 0x0, + + /* U+0034 "4" */ + 0x0, 0x0, 0x9b, 0x0, 0x0, 0x4, 0xe1, 0x0, + 0x0, 0x1e, 0x50, 0x0, 0x0, 0xaa, 0x0, 0x0, + 0x5, 0xe1, 0xd, 0x40, 0x1e, 0x40, 0xd, 0x40, + 0x8f, 0xff, 0xff, 0xfd, 0x12, 0x22, 0x2e, 0x62, + 0x0, 0x0, 0xe, 0x40, + + /* U+0035 "5" */ + 0xc, 0xff, 0xff, 0x0, 0xe5, 0x22, 0x20, 0xf, + 0x10, 0x0, 0x1, 0xff, 0xeb, 0x30, 0x2, 0x23, + 0x9f, 0x10, 0x0, 0x0, 0xd6, 0x0, 0x0, 0xd, + 0x69, 0xb4, 0x38, 0xf1, 0x2a, 0xef, 0xc4, 0x0, + + /* U+0036 "6" */ + 0x0, 0x6d, 0xfd, 0x50, 0x8, 0xd5, 0x23, 0x20, + 0x1f, 0x20, 0x0, 0x0, 0x4d, 0x6d, 0xea, 0x10, + 0x6f, 0xc4, 0x3c, 0xa0, 0x5f, 0x30, 0x2, 0xf0, + 0x2f, 0x20, 0x2, 0xf0, 0xa, 0xc3, 0x2b, 0xa0, + 0x1, 0xaf, 0xfa, 0x10, + + /* U+0037 "7" */ + 0xaf, 0xff, 0xff, 0xba, 0x92, 0x22, 0xd7, 0x76, + 0x0, 0x3f, 0x10, 0x0, 0xa, 0x90, 0x0, 0x1, + 0xf2, 0x0, 0x0, 0x7c, 0x0, 0x0, 0xe, 0x50, + 0x0, 0x5, 0xe0, 0x0, 0x0, 0xc8, 0x0, 0x0, + + /* U+0038 "8" */ + 0x3, 0xcf, 0xea, 0x10, 0xe, 0x81, 0x2c, 0xa0, + 0x2f, 0x10, 0x5, 0xd0, 0xe, 0x70, 0x1b, 0x90, + 0x6, 0xff, 0xff, 0x20, 0x3f, 0x50, 0x18, 0xe0, + 0x6c, 0x0, 0x0, 0xf2, 0x3f, 0x61, 0x29, 0xe0, + 0x5, 0xcf, 0xfb, 0x20, + + /* U+0039 "9" */ + 0x7, 0xef, 0xc3, 0x6, 0xe3, 0x15, 0xe1, 0x98, + 0x0, 0xb, 0x87, 0xd2, 0x3, 0xfb, 0xa, 0xff, + 0xd9, 0xc0, 0x0, 0x10, 0x8b, 0x0, 0x0, 0xd, + 0x70, 0x62, 0x4b, 0xd0, 0x1c, 0xfe, 0xa1, 0x0, + + /* U+003A ":" */ + 0x4e, 0x2, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xa0, 0x4d, 0x0, + + /* U+003B ";" */ + 0x4e, 0x2, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0x80, 0x4f, 0x10, 0xd0, 0x38, 0x0, + + /* U+003C "<" */ + 0x0, 0x0, 0x2, 0x10, 0x0, 0x4b, 0xe1, 0x7, + 0xdc, 0x50, 0x3, 0xf8, 0x0, 0x0, 0x4, 0xbe, + 0x71, 0x0, 0x0, 0x29, 0xe2, 0x0, 0x0, 0x0, + 0x0, + + /* U+003D "=" */ + 0x3f, 0xff, 0xff, 0x30, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xee, 0xee, 0xe2, 0x1, 0x11, + 0x11, 0x0, + + /* U+003E ">" */ + 0x12, 0x0, 0x0, 0x2, 0xeb, 0x40, 0x0, 0x0, + 0x5c, 0xd6, 0x0, 0x0, 0x8, 0xf2, 0x1, 0x7e, + 0xb4, 0x2, 0xe9, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+003F "?" */ + 0x1a, 0xef, 0xc3, 0x9, 0xa3, 0x2a, 0xe0, 0x0, + 0x0, 0x3f, 0x0, 0x0, 0xa, 0xa0, 0x0, 0x9, + 0xc0, 0x0, 0x2, 0xf1, 0x0, 0x0, 0x1, 0x0, + 0x0, 0x2, 0x80, 0x0, 0x0, 0x4d, 0x0, 0x0, + + /* U+0040 "@" */ + 0x0, 0x4, 0xbd, 0xdd, 0x81, 0x0, 0x0, 0x9b, + 0x30, 0x0, 0x6d, 0x30, 0x7, 0xa0, 0x8e, 0xe8, + 0xd5, 0xd1, 0xd, 0x7, 0xd2, 0x19, 0xf3, 0x77, + 0x4a, 0xd, 0x40, 0x0, 0xf3, 0x1b, 0x58, 0xf, + 0x20, 0x0, 0xd3, 0xc, 0x58, 0xd, 0x40, 0x0, + 0xf3, 0x1b, 0x3a, 0x7, 0xd2, 0x1a, 0xf5, 0x77, + 0xd, 0x0, 0x8e, 0xe8, 0x5f, 0xb0, 0x6, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9b, 0x30, 0x2, + 0x40, 0x0, 0x0, 0x5, 0xbd, 0xed, 0x60, 0x0, + + /* U+0041 "A" */ + 0x0, 0x0, 0x6f, 0x30, 0x0, 0x0, 0x0, 0xdd, + 0x90, 0x0, 0x0, 0x4, 0xe3, 0xf1, 0x0, 0x0, + 0xb, 0x80, 0xc7, 0x0, 0x0, 0x1f, 0x20, 0x6e, + 0x0, 0x0, 0x8c, 0x0, 0x1f, 0x50, 0x0, 0xef, + 0xee, 0xef, 0xb0, 0x6, 0xe2, 0x11, 0x14, 0xf2, + 0xc, 0x70, 0x0, 0x0, 0xb9, + + /* U+0042 "B" */ + 0xbf, 0xff, 0xfb, 0x20, 0xb7, 0x11, 0x2a, 0xd0, + 0xb7, 0x0, 0x3, 0xf0, 0xb7, 0x0, 0x8, 0xc0, + 0xbf, 0xff, 0xff, 0x50, 0xb8, 0x22, 0x26, 0xf2, + 0xb7, 0x0, 0x0, 0xc7, 0xb7, 0x11, 0x15, 0xf4, + 0xbf, 0xff, 0xfd, 0x60, + + /* U+0043 "C" */ + 0x0, 0x3b, 0xef, 0xb3, 0x0, 0x5f, 0x93, 0x38, + 0xe0, 0xe, 0x60, 0x0, 0x0, 0x4, 0xe0, 0x0, + 0x0, 0x0, 0x6c, 0x0, 0x0, 0x0, 0x4, 0xe0, + 0x0, 0x0, 0x0, 0xe, 0x60, 0x0, 0x0, 0x0, + 0x5f, 0x93, 0x38, 0xe0, 0x0, 0x3b, 0xff, 0xb3, + 0x0, + + /* U+0044 "D" */ + 0xbf, 0xff, 0xea, 0x30, 0xb, 0x82, 0x23, 0x9f, + 0x40, 0xb7, 0x0, 0x0, 0x7e, 0xb, 0x70, 0x0, + 0x0, 0xf3, 0xb7, 0x0, 0x0, 0xe, 0x5b, 0x70, + 0x0, 0x0, 0xf3, 0xb7, 0x0, 0x0, 0x7e, 0xb, + 0x82, 0x23, 0x9f, 0x40, 0xbf, 0xff, 0xeb, 0x30, + 0x0, + + /* U+0045 "E" */ + 0xbf, 0xff, 0xff, 0x3b, 0x82, 0x22, 0x20, 0xb7, + 0x0, 0x0, 0xb, 0x70, 0x0, 0x0, 0xbf, 0xff, + 0xfa, 0xb, 0x82, 0x22, 0x10, 0xb7, 0x0, 0x0, + 0xb, 0x82, 0x22, 0x20, 0xbf, 0xff, 0xff, 0x50, + + /* U+0046 "F" */ + 0xbf, 0xff, 0xff, 0x3b, 0x82, 0x22, 0x20, 0xb7, + 0x0, 0x0, 0xb, 0x70, 0x0, 0x0, 0xbf, 0xff, + 0xfa, 0xb, 0x82, 0x22, 0x10, 0xb7, 0x0, 0x0, + 0xb, 0x70, 0x0, 0x0, 0xb7, 0x0, 0x0, 0x0, + + /* U+0047 "G" */ + 0x0, 0x3b, 0xef, 0xc4, 0x0, 0x5f, 0x94, 0x38, + 0xe1, 0xe, 0x70, 0x0, 0x0, 0x4, 0xe0, 0x0, + 0x0, 0x0, 0x6c, 0x0, 0x0, 0x8, 0x24, 0xe0, + 0x0, 0x0, 0xe3, 0xe, 0x60, 0x0, 0xe, 0x30, + 0x5f, 0x93, 0x37, 0xf3, 0x0, 0x3b, 0xef, 0xc4, + 0x0, + + /* U+0048 "H" */ + 0xb7, 0x0, 0x0, 0xb7, 0xb7, 0x0, 0x0, 0xb7, + 0xb7, 0x0, 0x0, 0xb7, 0xb7, 0x0, 0x0, 0xb7, + 0xbf, 0xff, 0xff, 0xf7, 0xb8, 0x22, 0x22, 0xc7, + 0xb7, 0x0, 0x0, 0xb7, 0xb7, 0x0, 0x0, 0xb7, + 0xb7, 0x0, 0x0, 0xb7, + + /* U+0049 "I" */ + 0xb7, 0xb7, 0xb7, 0xb7, 0xb7, 0xb7, 0xb7, 0xb7, + 0xb7, + + /* U+004A "J" */ + 0x4, 0xff, 0xff, 0x0, 0x22, 0x5f, 0x0, 0x0, + 0x3f, 0x0, 0x0, 0x3f, 0x0, 0x0, 0x3f, 0x0, + 0x0, 0x3f, 0x0, 0x0, 0x4e, 0xd, 0x52, 0xba, + 0x5, 0xdf, 0xb2, + + /* U+004B "K" */ + 0xb7, 0x0, 0x7, 0xd1, 0xb7, 0x0, 0x5e, 0x20, + 0xb7, 0x4, 0xe3, 0x0, 0xb7, 0x3e, 0x40, 0x0, + 0xb9, 0xef, 0x20, 0x0, 0xbf, 0x89, 0xd0, 0x0, + 0xba, 0x0, 0xca, 0x0, 0xb7, 0x0, 0x1e, 0x70, + 0xb7, 0x0, 0x3, 0xf3, + + /* U+004C "L" */ + 0xb7, 0x0, 0x0, 0xb, 0x70, 0x0, 0x0, 0xb7, + 0x0, 0x0, 0xb, 0x70, 0x0, 0x0, 0xb7, 0x0, + 0x0, 0xb, 0x70, 0x0, 0x0, 0xb7, 0x0, 0x0, + 0xb, 0x82, 0x22, 0x20, 0xbf, 0xff, 0xff, 0x0, + + /* U+004D "M" */ + 0xb8, 0x0, 0x0, 0x1, 0xf3, 0xbf, 0x10, 0x0, + 0x9, 0xf3, 0xbe, 0xa0, 0x0, 0x2e, 0xf3, 0xb7, + 0xe3, 0x0, 0xb7, 0xf3, 0xb6, 0x7b, 0x4, 0xd0, + 0xf3, 0xb6, 0xd, 0x4c, 0x50, 0xf3, 0xb6, 0x5, + 0xfc, 0x0, 0xf3, 0xb6, 0x0, 0xb3, 0x0, 0xf3, + 0xb6, 0x0, 0x0, 0x0, 0xf3, + + /* U+004E "N" */ + 0xb9, 0x0, 0x0, 0xb7, 0xbf, 0x50, 0x0, 0xb7, + 0xbc, 0xf2, 0x0, 0xb7, 0xb7, 0xad, 0x0, 0xb7, + 0xb7, 0xd, 0x90, 0xb7, 0xb7, 0x2, 0xf5, 0xb7, + 0xb7, 0x0, 0x6f, 0xd7, 0xb7, 0x0, 0xa, 0xf7, + 0xb7, 0x0, 0x0, 0xd7, + + /* U+004F "O" */ + 0x0, 0x3b, 0xef, 0xb4, 0x0, 0x5, 0xf9, 0x33, + 0x8f, 0x60, 0xe, 0x60, 0x0, 0x5, 0xf1, 0x4e, + 0x0, 0x0, 0x0, 0xd5, 0x6c, 0x0, 0x0, 0x0, + 0xb7, 0x4e, 0x0, 0x0, 0x0, 0xd5, 0xe, 0x60, + 0x0, 0x5, 0xf1, 0x5, 0xf9, 0x33, 0x8f, 0x60, + 0x0, 0x3b, 0xef, 0xb4, 0x0, + + /* U+0050 "P" */ + 0xbf, 0xff, 0xd8, 0x0, 0xb8, 0x22, 0x5d, 0x90, + 0xb7, 0x0, 0x4, 0xe0, 0xb7, 0x0, 0x3, 0xf0, + 0xb7, 0x0, 0x2c, 0xa0, 0xbf, 0xff, 0xfa, 0x10, + 0xb8, 0x22, 0x0, 0x0, 0xb7, 0x0, 0x0, 0x0, + 0xb7, 0x0, 0x0, 0x0, + + /* U+0051 "Q" */ + 0x0, 0x3b, 0xef, 0xb4, 0x0, 0x4, 0xf9, 0x33, + 0x8f, 0x60, 0xe, 0x60, 0x0, 0x5, 0xf1, 0x4e, + 0x0, 0x0, 0x0, 0xd5, 0x6c, 0x0, 0x0, 0x0, + 0xb7, 0x4e, 0x0, 0x0, 0x0, 0xd6, 0xf, 0x60, + 0x0, 0x5, 0xf1, 0x5, 0xf8, 0x32, 0x7f, 0x60, + 0x0, 0x4c, 0xff, 0xc5, 0x0, 0x0, 0x0, 0xc, + 0xb0, 0x28, 0x0, 0x0, 0x1, 0xbf, 0xe5, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+0052 "R" */ + 0xbf, 0xff, 0xd8, 0x0, 0xb8, 0x22, 0x5d, 0x90, + 0xb7, 0x0, 0x4, 0xe0, 0xb7, 0x0, 0x3, 0xf0, + 0xb7, 0x0, 0x1b, 0xb0, 0xbf, 0xff, 0xfb, 0x10, + 0xb8, 0x22, 0xb9, 0x0, 0xb7, 0x0, 0x1f, 0x30, + 0xb7, 0x0, 0x7, 0xd0, + + /* U+0053 "S" */ + 0x3, 0xcf, 0xeb, 0x31, 0xf7, 0x23, 0x74, 0x4e, + 0x0, 0x0, 0x1, 0xf9, 0x20, 0x0, 0x2, 0xbf, + 0xd7, 0x0, 0x0, 0x4, 0xca, 0x0, 0x0, 0x4, + 0xe5, 0xb4, 0x23, 0xbb, 0x8, 0xdf, 0xea, 0x10, + + /* U+0054 "T" */ + 0xff, 0xff, 0xff, 0xf2, 0x23, 0xf3, 0x22, 0x0, + 0x1f, 0x10, 0x0, 0x1, 0xf1, 0x0, 0x0, 0x1f, + 0x10, 0x0, 0x1, 0xf1, 0x0, 0x0, 0x1f, 0x10, + 0x0, 0x1, 0xf1, 0x0, 0x0, 0x1f, 0x10, 0x0, + + /* U+0055 "U" */ + 0xd6, 0x0, 0x0, 0xe4, 0xd6, 0x0, 0x0, 0xe4, + 0xd6, 0x0, 0x0, 0xe4, 0xd6, 0x0, 0x0, 0xe4, + 0xd6, 0x0, 0x0, 0xe4, 0xc7, 0x0, 0x0, 0xf3, + 0x9a, 0x0, 0x2, 0xf1, 0x2f, 0x83, 0x5d, 0xa0, + 0x4, 0xcf, 0xd8, 0x0, + + /* U+0056 "V" */ + 0xc, 0x70, 0x0, 0x0, 0xd5, 0x6, 0xe0, 0x0, + 0x4, 0xe0, 0x0, 0xf4, 0x0, 0xa, 0x80, 0x0, + 0x9b, 0x0, 0x1f, 0x20, 0x0, 0x2f, 0x20, 0x7b, + 0x0, 0x0, 0xc, 0x80, 0xe4, 0x0, 0x0, 0x5, + 0xe5, 0xe0, 0x0, 0x0, 0x0, 0xee, 0x70, 0x0, + 0x0, 0x0, 0x8f, 0x10, 0x0, + + /* U+0057 "W" */ + 0x7c, 0x0, 0x0, 0xe8, 0x0, 0x2, 0xf0, 0x2f, + 0x10, 0x3, 0xfd, 0x0, 0x7, 0xa0, 0xd, 0x60, + 0x8, 0x9f, 0x20, 0xc, 0x50, 0x8, 0xb0, 0xe, + 0x3b, 0x70, 0x1f, 0x0, 0x3, 0xf0, 0x3e, 0x6, + 0xc0, 0x6b, 0x0, 0x0, 0xe5, 0x89, 0x1, 0xf1, + 0xb6, 0x0, 0x0, 0x9a, 0xd4, 0x0, 0xb7, 0xf1, + 0x0, 0x0, 0x4f, 0xe0, 0x0, 0x6f, 0xc0, 0x0, + 0x0, 0xf, 0xa0, 0x0, 0x1f, 0x70, 0x0, + + /* U+0058 "X" */ + 0x5f, 0x10, 0x0, 0xe5, 0xa, 0xb0, 0x9, 0xa0, + 0x1, 0xe6, 0x4e, 0x10, 0x0, 0x4f, 0xe4, 0x0, + 0x0, 0xd, 0xe0, 0x0, 0x0, 0x7d, 0xd8, 0x0, + 0x2, 0xf3, 0x2f, 0x30, 0xc, 0x80, 0x7, 0xd0, + 0x8d, 0x0, 0x0, 0xc9, + + /* U+0059 "Y" */ + 0xc, 0x80, 0x0, 0xa, 0x80, 0x3f, 0x10, 0x3, + 0xe0, 0x0, 0xaa, 0x0, 0xc6, 0x0, 0x1, 0xf3, + 0x5d, 0x0, 0x0, 0x7, 0xce, 0x40, 0x0, 0x0, + 0xe, 0xb0, 0x0, 0x0, 0x0, 0xb7, 0x0, 0x0, + 0x0, 0xb, 0x70, 0x0, 0x0, 0x0, 0xb7, 0x0, + 0x0, + + /* U+005A "Z" */ + 0x6f, 0xff, 0xff, 0xf5, 0x2, 0x22, 0x29, 0xd0, + 0x0, 0x0, 0x3f, 0x30, 0x0, 0x1, 0xe6, 0x0, + 0x0, 0xb, 0xa0, 0x0, 0x0, 0x8d, 0x0, 0x0, + 0x4, 0xf2, 0x0, 0x0, 0x1e, 0x82, 0x22, 0x21, + 0x7f, 0xff, 0xff, 0xf8, + + /* U+005B "[" */ + 0xbf, 0xcb, 0x60, 0xb6, 0xb, 0x60, 0xb6, 0xb, + 0x60, 0xb6, 0xb, 0x60, 0xb6, 0xb, 0x60, 0xb6, + 0xb, 0x60, 0xbf, 0xc0, + + /* U+005C "\\" */ + 0x35, 0x0, 0x0, 0x2e, 0x0, 0x0, 0xd, 0x30, + 0x0, 0x8, 0x80, 0x0, 0x3, 0xd0, 0x0, 0x0, + 0xd2, 0x0, 0x0, 0x87, 0x0, 0x0, 0x3c, 0x0, + 0x0, 0xe, 0x10, 0x0, 0x9, 0x70, 0x0, 0x4, + 0xc0, 0x0, 0x0, 0xe1, 0x0, 0x0, 0xa6, + + /* U+005D "]" */ + 0xcf, 0xb0, 0x7b, 0x6, 0xb0, 0x6b, 0x6, 0xb0, + 0x6b, 0x6, 0xb0, 0x6b, 0x6, 0xb0, 0x6b, 0x6, + 0xb0, 0x7b, 0xcf, 0xb0, + + /* U+005E "^" */ + 0x0, 0x7, 0x0, 0x0, 0x5, 0xe5, 0x0, 0x0, + 0xb4, 0xb0, 0x0, 0x2c, 0xc, 0x20, 0x8, 0x60, + 0x68, 0x0, 0xd0, 0x0, 0xd0, + + /* U+005F "_" */ + 0xdd, 0xdd, 0xdd, + + /* U+0060 "`" */ + 0x27, 0x10, 0x5, 0xc1, + + /* U+0061 "a" */ + 0x8, 0xdf, 0xc3, 0x0, 0xa4, 0x29, 0xd0, 0x0, + 0x0, 0x1f, 0x10, 0x8d, 0xee, 0xf2, 0x4e, 0x10, + 0xf, 0x24, 0xe0, 0x7, 0xf2, 0x9, 0xed, 0x8f, + 0x20, + + /* U+0062 "b" */ + 0xe4, 0x0, 0x0, 0xe, 0x40, 0x0, 0x0, 0xe4, + 0x0, 0x0, 0xe, 0x7c, 0xfc, 0x40, 0xef, 0x52, + 0x8f, 0x2e, 0x60, 0x0, 0xb8, 0xe4, 0x0, 0x8, + 0xae, 0x60, 0x0, 0xb8, 0xef, 0x52, 0x8f, 0x2e, + 0x6d, 0xfc, 0x40, + + /* U+0063 "c" */ + 0x2, 0xbf, 0xe8, 0x0, 0xda, 0x24, 0xc3, 0x5d, + 0x0, 0x0, 0x7, 0xb0, 0x0, 0x0, 0x5d, 0x0, + 0x0, 0x0, 0xda, 0x24, 0xd3, 0x2, 0xbf, 0xe8, + 0x0, + + /* U+0064 "d" */ + 0x0, 0x0, 0x1, 0xf1, 0x0, 0x0, 0x1, 0xf1, + 0x0, 0x0, 0x1, 0xf1, 0x2, 0xbf, 0xd6, 0xf1, + 0xe, 0x92, 0x3d, 0xf1, 0x5d, 0x0, 0x4, 0xf1, + 0x7b, 0x0, 0x1, 0xf1, 0x5d, 0x0, 0x3, 0xf1, + 0xe, 0x91, 0x2d, 0xf1, 0x2, 0xbf, 0xe6, 0xf1, + + /* U+0065 "e" */ + 0x2, 0xbf, 0xd5, 0x0, 0xe8, 0x14, 0xe4, 0x5c, + 0x0, 0x6, 0xb7, 0xfe, 0xee, 0xec, 0x5d, 0x0, + 0x0, 0x0, 0xe9, 0x23, 0xa2, 0x2, 0xbf, 0xe9, + 0x0, + + /* U+0066 "f" */ + 0x1, 0xcf, 0x60, 0x9a, 0x11, 0xb, 0x60, 0xd, + 0xff, 0xf3, 0xb, 0x60, 0x0, 0xb6, 0x0, 0xb, + 0x60, 0x0, 0xb6, 0x0, 0xb, 0x60, 0x0, 0xb6, + 0x0, + + /* U+0067 "g" */ + 0x2, 0xbf, 0xe6, 0xe2, 0xe, 0xa2, 0x3c, 0xf2, + 0x5d, 0x0, 0x2, 0xf2, 0x7b, 0x0, 0x0, 0xf2, + 0x5d, 0x0, 0x2, 0xf2, 0xe, 0xa2, 0x3d, 0xf2, + 0x2, 0xbf, 0xe5, 0xf2, 0x0, 0x0, 0x2, 0xf0, + 0xc, 0x62, 0x3b, 0xa0, 0x6, 0xdf, 0xea, 0x10, + + /* U+0068 "h" */ + 0xe4, 0x0, 0x0, 0xe, 0x40, 0x0, 0x0, 0xe4, + 0x0, 0x0, 0xe, 0x7d, 0xfc, 0x20, 0xee, 0x42, + 0xac, 0xe, 0x60, 0x2, 0xf0, 0xe4, 0x0, 0xf, + 0x1e, 0x40, 0x0, 0xf2, 0xe4, 0x0, 0xf, 0x2e, + 0x40, 0x0, 0xf2, + + /* U+0069 "i" */ + 0xd, 0x40, 0x82, 0x0, 0x0, 0xe4, 0xe, 0x40, + 0xe4, 0xe, 0x40, 0xe4, 0xe, 0x40, 0xe4, + + /* U+006A "j" */ + 0x0, 0xd, 0x50, 0x0, 0x72, 0x0, 0x0, 0x0, + 0x0, 0xd4, 0x0, 0xd, 0x40, 0x0, 0xd4, 0x0, + 0xd, 0x40, 0x0, 0xd4, 0x0, 0xd, 0x40, 0x0, + 0xd4, 0x0, 0xd, 0x40, 0x22, 0xf2, 0xd, 0xf8, + 0x0, + + /* U+006B "k" */ + 0xe4, 0x0, 0x0, 0xe, 0x40, 0x0, 0x0, 0xe4, + 0x0, 0x0, 0xe, 0x40, 0xb, 0xa0, 0xe4, 0xb, + 0xb0, 0xe, 0x4b, 0xc0, 0x0, 0xee, 0xfd, 0x0, + 0xe, 0xc1, 0xd9, 0x0, 0xe4, 0x2, 0xf4, 0xe, + 0x40, 0x6, 0xe1, + + /* U+006C "l" */ + 0xe4, 0xe4, 0xe4, 0xe4, 0xe4, 0xe4, 0xe4, 0xe4, + 0xe4, 0xe4, + + /* U+006D "m" */ + 0xe7, 0xdf, 0xb2, 0x9e, 0xe8, 0xe, 0xd3, 0x2c, + 0xfb, 0x23, 0xe5, 0xe6, 0x0, 0x4f, 0x10, 0x9, + 0x9e, 0x40, 0x3, 0xf0, 0x0, 0x8a, 0xe4, 0x0, + 0x3f, 0x0, 0x8, 0xae, 0x40, 0x3, 0xf0, 0x0, + 0x8a, 0xe4, 0x0, 0x3f, 0x0, 0x8, 0xa0, + + /* U+006E "n" */ + 0xe6, 0xdf, 0xc2, 0xe, 0xe4, 0x1a, 0xc0, 0xe6, + 0x0, 0x1f, 0xe, 0x40, 0x0, 0xf1, 0xe4, 0x0, + 0xf, 0x2e, 0x40, 0x0, 0xf2, 0xe4, 0x0, 0xf, + 0x20, + + /* U+006F "o" */ + 0x2, 0xbf, 0xe8, 0x0, 0xe, 0xa2, 0x3e, 0x80, + 0x5d, 0x0, 0x4, 0xf0, 0x7b, 0x0, 0x1, 0xf1, + 0x5d, 0x0, 0x4, 0xf0, 0xd, 0xa2, 0x3e, 0x80, + 0x2, 0xbf, 0xe8, 0x0, + + /* U+0070 "p" */ + 0xe7, 0xdf, 0xc4, 0xe, 0xf4, 0x16, 0xf2, 0xe6, + 0x0, 0xa, 0x8e, 0x40, 0x0, 0x8a, 0xe7, 0x0, + 0xb, 0x8e, 0xf5, 0x28, 0xf2, 0xe6, 0xcf, 0xc4, + 0xe, 0x40, 0x0, 0x0, 0xe4, 0x0, 0x0, 0xe, + 0x40, 0x0, 0x0, + + /* U+0071 "q" */ + 0x2, 0xbf, 0xd5, 0xf1, 0xe, 0xa2, 0x3e, 0xf1, + 0x5d, 0x0, 0x4, 0xf1, 0x7b, 0x0, 0x1, 0xf1, + 0x5d, 0x0, 0x4, 0xf1, 0xe, 0xa2, 0x3e, 0xf1, + 0x2, 0xbf, 0xd5, 0xf1, 0x0, 0x0, 0x1, 0xf1, + 0x0, 0x0, 0x1, 0xf1, 0x0, 0x0, 0x1, 0xf1, + + /* U+0072 "r" */ + 0xe6, 0xd8, 0xee, 0x61, 0xe7, 0x0, 0xe4, 0x0, + 0xe4, 0x0, 0xe4, 0x0, 0xe4, 0x0, + + /* U+0073 "s" */ + 0x9, 0xef, 0xc2, 0x6d, 0x22, 0x61, 0x7d, 0x20, + 0x0, 0x9, 0xfe, 0x91, 0x0, 0x2, 0xc9, 0x56, + 0x22, 0xb8, 0x4c, 0xfe, 0xa0, + + /* U+0074 "t" */ + 0x5, 0x30, 0x0, 0xb6, 0x0, 0xdf, 0xff, 0x30, + 0xb6, 0x0, 0xb, 0x60, 0x0, 0xb6, 0x0, 0xb, + 0x60, 0x0, 0xaa, 0x11, 0x2, 0xdf, 0x60, + + /* U+0075 "u" */ + 0xf3, 0x0, 0x2f, 0xf, 0x30, 0x2, 0xf0, 0xf3, + 0x0, 0x2f, 0xf, 0x30, 0x2, 0xf0, 0xe4, 0x0, + 0x4f, 0xa, 0xb2, 0x2c, 0xf0, 0x1b, 0xfe, 0x6f, + 0x0, + + /* U+0076 "v" */ + 0xd, 0x50, 0x0, 0x98, 0x6, 0xc0, 0x0, 0xf2, + 0x1, 0xf2, 0x6, 0xb0, 0x0, 0xa8, 0xc, 0x50, + 0x0, 0x3e, 0x3e, 0x0, 0x0, 0xd, 0xd8, 0x0, + 0x0, 0x6, 0xf2, 0x0, + + /* U+0077 "w" */ + 0xc5, 0x0, 0x3f, 0x10, 0x7, 0x86, 0xa0, 0x9, + 0xf6, 0x0, 0xd3, 0x1f, 0x0, 0xe7, 0xb0, 0x2d, + 0x0, 0xb5, 0x4c, 0xe, 0x18, 0x80, 0x6, 0xa9, + 0x60, 0xa6, 0xd3, 0x0, 0x1f, 0xe1, 0x4, 0xed, + 0x0, 0x0, 0xbb, 0x0, 0xe, 0x80, 0x0, + + /* U+0078 "x" */ + 0x5d, 0x0, 0x4e, 0x10, 0xa9, 0x1e, 0x40, 0x1, + 0xed, 0x90, 0x0, 0x8, 0xf1, 0x0, 0x2, 0xeb, + 0xa0, 0x0, 0xc7, 0xd, 0x60, 0x7c, 0x0, 0x3f, + 0x20, + + /* U+0079 "y" */ + 0xd, 0x50, 0x0, 0x98, 0x7, 0xb0, 0x0, 0xe2, + 0x1, 0xf2, 0x5, 0xc0, 0x0, 0xa7, 0xb, 0x50, + 0x0, 0x4d, 0x1e, 0x0, 0x0, 0xe, 0xb9, 0x0, + 0x0, 0x8, 0xf3, 0x0, 0x0, 0x5, 0xd0, 0x0, + 0x5, 0x2c, 0x60, 0x0, 0x1c, 0xf9, 0x0, 0x0, + + /* U+007A "z" */ + 0x7f, 0xff, 0xfb, 0x0, 0x2, 0xf3, 0x0, 0xc, + 0x70, 0x0, 0x9b, 0x0, 0x4, 0xe1, 0x0, 0x1e, + 0x50, 0x0, 0x8f, 0xff, 0xfd, + + /* U+007B "{" */ + 0x0, 0xbf, 0x4, 0xe1, 0x5, 0xc0, 0x5, 0xc0, + 0x5, 0xc0, 0x6, 0xc0, 0x4f, 0x60, 0x8, 0xc0, + 0x5, 0xc0, 0x5, 0xc0, 0x5, 0xc0, 0x4, 0xe1, + 0x0, 0xbf, + + /* U+007C "|" */ + 0xb5, 0xb5, 0xb5, 0xb5, 0xb5, 0xb5, 0xb5, 0xb5, + 0xb5, 0xb5, 0xb5, 0xb5, 0xb5, + + /* U+007D "}" */ + 0xcd, 0x10, 0xc, 0x70, 0x9, 0x90, 0x9, 0x90, + 0x9, 0x90, 0x8, 0xa0, 0x3, 0xf7, 0x8, 0xb0, + 0x9, 0x90, 0x9, 0x90, 0x9, 0x90, 0xc, 0x80, + 0xcd, 0x20, + + /* U+007E "~" */ + 0xb, 0xe8, 0xa, 0x33, 0x91, 0x8d, 0xa0, + + /* U+F001 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x12, 0x0, 0x0, + 0x0, 0x3, 0x7c, 0xff, 0x0, 0x0, 0x59, 0xef, + 0xff, 0xff, 0x0, 0xe, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xf, 0xff, 0xfd, 0x84, 0x8f, 0x0, 0xf, + 0xd7, 0x20, 0x0, 0x8f, 0x0, 0xf, 0x80, 0x0, + 0x0, 0x8f, 0x0, 0xf, 0x80, 0x0, 0x0, 0x8f, + 0x0, 0xf, 0x80, 0x0, 0x7b, 0xdf, 0x2, 0x3f, + 0x80, 0x6, 0xff, 0xff, 0xaf, 0xff, 0x80, 0x2, + 0xef, 0xf9, 0xef, 0xff, 0x60, 0x0, 0x2, 0x10, + 0x29, 0xa7, 0x0, 0x0, 0x0, 0x0, + + /* U+F008 "" */ + 0xb4, 0xdf, 0xff, 0xff, 0xfd, 0x4b, 0xe8, 0xe7, + 0x22, 0x22, 0x7e, 0x8e, 0xc0, 0xc5, 0x0, 0x0, + 0x6c, 0xc, 0xfc, 0xf6, 0x11, 0x11, 0x7f, 0xcf, + 0xc0, 0xcf, 0xff, 0xff, 0xfb, 0xc, 0xfc, 0xf6, + 0x11, 0x11, 0x7f, 0xcf, 0xc0, 0xc5, 0x0, 0x0, + 0x6c, 0xc, 0xe8, 0xe7, 0x22, 0x22, 0x7e, 0x8e, + 0xb4, 0xdf, 0xff, 0xff, 0xfd, 0x4b, + + /* U+F00B "" */ + 0xdf, 0xf6, 0x9f, 0xff, 0xff, 0xfd, 0xff, 0xf8, + 0xcf, 0xff, 0xff, 0xff, 0xef, 0xf6, 0xaf, 0xff, + 0xff, 0xfe, 0x13, 0x20, 0x3, 0x33, 0x33, 0x31, + 0xff, 0xf7, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xcf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xbf, 0xff, + 0xff, 0xff, 0x13, 0x20, 0x3, 0x33, 0x33, 0x31, + 0xef, 0xf6, 0xaf, 0xff, 0xff, 0xfe, 0xff, 0xf8, + 0xcf, 0xff, 0xff, 0xff, 0xdf, 0xf6, 0xaf, 0xff, + 0xff, 0xfd, + + /* U+F00C "" */ + 0x0, 0x0, 0x0, 0x0, 0x3, 0xd4, 0x0, 0x0, + 0x0, 0x0, 0x3f, 0xfe, 0x0, 0x0, 0x0, 0x3, + 0xff, 0xf4, 0x4d, 0x30, 0x0, 0x3f, 0xff, 0x40, + 0xef, 0xf3, 0x3, 0xff, 0xf4, 0x0, 0x4f, 0xff, + 0x6f, 0xff, 0x40, 0x0, 0x4, 0xff, 0xff, 0xf4, + 0x0, 0x0, 0x0, 0x4f, 0xff, 0x40, 0x0, 0x0, + 0x0, 0x3, 0xd3, 0x0, 0x0, 0x0, + + /* U+F00D "" */ + 0x14, 0x0, 0x0, 0x22, 0xd, 0xf7, 0x0, 0x4f, + 0xf1, 0x9f, 0xf7, 0x4f, 0xfd, 0x0, 0xaf, 0xff, + 0xfd, 0x10, 0x0, 0xbf, 0xfe, 0x10, 0x0, 0x4f, + 0xff, 0xf7, 0x0, 0x4f, 0xfd, 0xaf, 0xf7, 0xe, + 0xfd, 0x10, 0xaf, 0xf2, 0x5b, 0x10, 0x0, 0x99, + 0x0, + + /* U+F011 "" */ + 0x0, 0x0, 0x7, 0x70, 0x0, 0x0, 0x0, 0x32, + 0xf, 0xf0, 0x24, 0x0, 0x5, 0xfc, 0xf, 0xf0, + 0xcf, 0x50, 0x1f, 0xf4, 0xf, 0xf0, 0x5f, 0xf1, + 0x7f, 0x80, 0xf, 0xf0, 0x8, 0xf7, 0xbf, 0x20, + 0xf, 0xf0, 0x2, 0xfb, 0xcf, 0x10, 0xe, 0xe0, + 0x1, 0xfc, 0xaf, 0x40, 0x1, 0x10, 0x4, 0xfa, + 0x5f, 0xb0, 0x0, 0x0, 0xb, 0xf6, 0xd, 0xfa, + 0x10, 0x1, 0xaf, 0xd0, 0x2, 0xdf, 0xfc, 0xcf, + 0xfd, 0x20, 0x0, 0x8, 0xef, 0xfe, 0x91, 0x0, + 0x0, 0x0, 0x1, 0x10, 0x0, 0x0, + + /* U+F013 "" */ + 0x0, 0x0, 0x14, 0x41, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xf7, 0x0, 0x0, 0x3, 0x43, 0xdf, 0xfd, + 0x34, 0x30, 0xe, 0xff, 0xff, 0xff, 0xff, 0xe0, + 0x6f, 0xff, 0xfb, 0xbf, 0xff, 0xf6, 0x1b, 0xff, + 0x70, 0x7, 0xff, 0xb1, 0x7, 0xff, 0x20, 0x2, + 0xff, 0x70, 0x1b, 0xff, 0x70, 0x7, 0xff, 0xb1, + 0x6f, 0xff, 0xfb, 0xbf, 0xff, 0xf6, 0xe, 0xff, + 0xff, 0xff, 0xff, 0xe0, 0x3, 0x42, 0xcf, 0xfc, + 0x23, 0x30, 0x0, 0x0, 0x7f, 0xf7, 0x0, 0x0, + 0x0, 0x0, 0x4, 0x41, 0x0, 0x0, + + /* U+F015 "" */ + 0x0, 0x0, 0x0, 0x73, 0x3, 0x83, 0x0, 0x0, + 0x0, 0x1d, 0xff, 0x67, 0xf7, 0x0, 0x0, 0x3, + 0xee, 0x5a, 0xfe, 0xf7, 0x0, 0x0, 0x6f, 0xd3, + 0xb5, 0x7f, 0xf7, 0x0, 0x9, 0xfb, 0x3d, 0xff, + 0x85, 0xfe, 0x30, 0xbf, 0x95, 0xff, 0xff, 0xfb, + 0x3e, 0xf4, 0x76, 0x6f, 0xff, 0xff, 0xff, 0xd2, + 0xa1, 0x0, 0xcf, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0xcf, 0xfa, 0x2, 0xff, 0xf4, 0x0, 0x0, + 0xcf, 0xfa, 0x2, 0xff, 0xf4, 0x0, 0x0, 0xaf, + 0xf8, 0x1, 0xff, 0xf3, 0x0, + + /* U+F019 "" */ + 0x0, 0x0, 0x27, 0x72, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xf7, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xf8, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0xf8, 0x0, 0x0, 0x0, 0xdf, + 0xff, 0xff, 0xfd, 0x0, 0x0, 0x4f, 0xff, 0xff, + 0xf4, 0x0, 0x0, 0x4, 0xff, 0xff, 0x40, 0x0, + 0x23, 0x33, 0x5f, 0xf5, 0x33, 0x32, 0xff, 0xff, + 0xa4, 0x4a, 0xff, 0xff, 0xff, 0xff, 0xfc, 0xcf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5c, 0x8f, + 0x9a, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, + + /* U+F01C "" */ + 0x0, 0x4f, 0xff, 0xff, 0xff, 0xb0, 0x0, 0x1, + 0xed, 0x88, 0x88, 0x89, 0xf8, 0x0, 0xa, 0xf2, + 0x0, 0x0, 0x0, 0xaf, 0x30, 0x5f, 0x70, 0x0, + 0x0, 0x0, 0x1e, 0xc0, 0xef, 0x88, 0x60, 0x0, + 0x28, 0x8b, 0xf6, 0xff, 0xff, 0xf3, 0x0, 0xbf, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + + /* U+F021 "" */ + 0x0, 0x0, 0x1, 0x10, 0x0, 0x59, 0x0, 0x19, + 0xef, 0xfd, 0x70, 0x9f, 0x3, 0xef, 0xda, 0x9d, + 0xfe, 0xbf, 0xe, 0xf6, 0x0, 0x0, 0x5f, 0xff, + 0x7f, 0x70, 0x0, 0x3f, 0xff, 0xff, 0x69, 0x0, + 0x0, 0x2a, 0xaa, 0xa9, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xaa, 0xaa, 0xa2, 0x0, 0x0, 0xa6, + 0xff, 0xfe, 0xf3, 0x0, 0x7, 0xf7, 0xff, 0xf5, + 0x0, 0x0, 0x7f, 0xe0, 0xfb, 0xef, 0xd9, 0xad, + 0xfe, 0x30, 0xfa, 0x8, 0xef, 0xfe, 0x91, 0x0, + 0x95, 0x0, 0x1, 0x10, 0x0, 0x0, + + /* U+F026 "" */ + 0x0, 0x0, 0x2a, 0x0, 0x2, 0xef, 0x78, 0x8e, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xdf, 0xff, 0xff, 0x0, 0x7, 0xff, + 0x0, 0x0, 0x7f, 0x0, 0x0, 0x1, + + /* U+F027 "" */ + 0x0, 0x0, 0x2a, 0x0, 0x0, 0x0, 0x2e, 0xf0, + 0x0, 0x78, 0x8e, 0xff, 0x3, 0xf, 0xff, 0xff, + 0xf0, 0xba, 0xff, 0xff, 0xff, 0x3, 0xff, 0xff, + 0xff, 0xf0, 0xaa, 0xdf, 0xff, 0xff, 0x4, 0x0, + 0x0, 0x8f, 0xf0, 0x0, 0x0, 0x0, 0x8f, 0x0, + 0x0, 0x0, 0x0, 0x10, 0x0, + + /* U+F028 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6, 0xd2, 0x0, 0x0, 0x0, + 0x2a, 0x0, 0x11, 0x8e, 0x10, 0x0, 0x2, 0xef, + 0x0, 0x7d, 0x2b, 0x90, 0x78, 0x8e, 0xff, 0x3, + 0xa, 0xb3, 0xf0, 0xff, 0xff, 0xff, 0xb, 0xa1, + 0xf1, 0xe3, 0xff, 0xff, 0xff, 0x3, 0xf0, 0xe3, + 0xc5, 0xff, 0xff, 0xff, 0xb, 0xa1, 0xf1, 0xe3, + 0xdf, 0xff, 0xff, 0x3, 0xa, 0xb3, 0xf0, 0x0, + 0x7, 0xff, 0x0, 0x7d, 0x2b, 0x90, 0x0, 0x0, + 0x7f, 0x0, 0x11, 0x9e, 0x10, 0x0, 0x0, 0x1, + 0x0, 0x6, 0xd2, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + + /* U+F03E "" */ + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xfd, 0x5b, + 0xff, 0xff, 0xff, 0xff, 0xf5, 0x1, 0xff, 0xff, + 0xef, 0xff, 0xfb, 0x18, 0xff, 0xf6, 0x1c, 0xff, + 0xff, 0xfc, 0xff, 0x60, 0x1, 0xdf, 0xff, 0x60, + 0x96, 0x0, 0x0, 0x8f, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xfc, 0x88, 0x88, 0x88, 0x88, 0xcf, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xfb, + + /* U+F043 "" */ + 0x0, 0x2, 0x40, 0x0, 0x0, 0x0, 0xcf, 0x10, + 0x0, 0x0, 0x3f, 0xf7, 0x0, 0x0, 0xa, 0xff, + 0xe0, 0x0, 0x4, 0xff, 0xff, 0x80, 0x0, 0xef, + 0xff, 0xff, 0x30, 0x8f, 0xff, 0xff, 0xfc, 0xe, + 0xff, 0xff, 0xff, 0xf2, 0xf9, 0xcf, 0xff, 0xff, + 0x3d, 0xc5, 0xff, 0xff, 0xf1, 0x6f, 0xa3, 0xbf, + 0xfa, 0x0, 0x8f, 0xff, 0xfb, 0x0, 0x0, 0x26, + 0x74, 0x0, 0x0, + + /* U+F048 "" */ + 0x58, 0x0, 0x0, 0x35, 0x9f, 0x10, 0x5, 0xfe, + 0x9f, 0x10, 0x6f, 0xfe, 0x9f, 0x17, 0xff, 0xfe, + 0x9f, 0x9f, 0xff, 0xfe, 0x9f, 0xff, 0xff, 0xfe, + 0x9f, 0xef, 0xff, 0xfe, 0x9f, 0x2d, 0xff, 0xfe, + 0x9f, 0x10, 0xcf, 0xfe, 0x9f, 0x10, 0xb, 0xfe, + 0x8f, 0x0, 0x0, 0x9b, 0x0, 0x0, 0x0, 0x0, + + /* U+F04B "" */ + 0x46, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0x40, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xa1, 0x0, 0x0, + 0xf, 0xff, 0xff, 0xf7, 0x0, 0x0, 0xff, 0xff, + 0xff, 0xfd, 0x50, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xb1, 0xff, 0xff, 0xff, 0xff, 0xff, 0x6f, 0xff, + 0xff, 0xff, 0xff, 0xb1, 0xff, 0xff, 0xff, 0xfd, + 0x40, 0xf, 0xff, 0xff, 0xf7, 0x0, 0x0, 0xff, + 0xff, 0xa1, 0x0, 0x0, 0xf, 0xfd, 0x40, 0x0, + 0x0, 0x0, 0x36, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F04C "" */ + 0xaf, 0xfe, 0x30, 0xaf, 0xfe, 0x3f, 0xff, 0xf7, + 0xf, 0xff, 0xf7, 0xff, 0xff, 0x80, 0xff, 0xff, + 0x8f, 0xff, 0xf8, 0xf, 0xff, 0xf8, 0xff, 0xff, + 0x80, 0xff, 0xff, 0x8f, 0xff, 0xf8, 0xf, 0xff, + 0xf8, 0xff, 0xff, 0x80, 0xff, 0xff, 0x8f, 0xff, + 0xf8, 0xf, 0xff, 0xf8, 0xff, 0xff, 0x80, 0xff, + 0xff, 0x8f, 0xff, 0xf7, 0xf, 0xff, 0xf7, 0x48, + 0x98, 0x10, 0x48, 0x98, 0x10, + + /* U+F04D "" */ + 0x48, 0x88, 0x88, 0x88, 0x88, 0x1f, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xaf, + 0xff, 0xff, 0xff, 0xfe, 0x30, + + /* U+F051 "" */ + 0x26, 0x0, 0x0, 0x58, 0x7f, 0xa0, 0x0, 0xbf, + 0x8f, 0xfb, 0x0, 0xbf, 0x8f, 0xff, 0xc1, 0xbf, + 0x8f, 0xff, 0xfd, 0xcf, 0x8f, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xef, 0x8f, 0xff, 0xf4, 0xbf, + 0x8f, 0xff, 0x40, 0xbf, 0x8f, 0xe3, 0x0, 0xbf, + 0x5d, 0x20, 0x0, 0xae, 0x0, 0x0, 0x0, 0x0, + + /* U+F052 "" */ + 0x0, 0x0, 0x3, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xfa, 0x0, 0x0, 0x0, 0x2, 0xef, 0xff, + 0x90, 0x0, 0x0, 0x1e, 0xff, 0xff, 0xf8, 0x0, + 0x1, 0xdf, 0xff, 0xff, 0xff, 0x70, 0xc, 0xff, + 0xff, 0xff, 0xff, 0xf4, 0xd, 0xff, 0xff, 0xff, + 0xff, 0xf5, 0x1, 0x34, 0x44, 0x44, 0x44, 0x30, + 0xd, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xf, 0xff, + 0xff, 0xff, 0xff, 0xf8, 0xc, 0xff, 0xff, 0xff, + 0xff, 0xf5, + + /* U+F053 "" */ + 0x0, 0x0, 0x3, 0x10, 0x0, 0x5, 0xfb, 0x0, + 0x5, 0xff, 0x40, 0x5, 0xff, 0x40, 0x5, 0xff, + 0x50, 0x3, 0xff, 0x50, 0x0, 0xb, 0xfc, 0x10, + 0x0, 0xb, 0xfc, 0x10, 0x0, 0xc, 0xfc, 0x10, + 0x0, 0xc, 0xfb, 0x0, 0x0, 0xa, 0x50, + + /* U+F054 "" */ + 0x3, 0x10, 0x0, 0x3, 0xfc, 0x10, 0x0, 0xb, + 0xfc, 0x10, 0x0, 0xb, 0xfc, 0x10, 0x0, 0xb, + 0xfc, 0x10, 0x0, 0xd, 0xfb, 0x0, 0x5, 0xff, + 0x50, 0x5, 0xff, 0x50, 0x5, 0xff, 0x50, 0x3, + 0xff, 0x50, 0x0, 0xa, 0x50, 0x0, 0x0, + + /* U+F067 "" */ + 0x0, 0x0, 0x69, 0x10, 0x0, 0x0, 0x0, 0xd, + 0xf5, 0x0, 0x0, 0x0, 0x0, 0xef, 0x60, 0x0, + 0x0, 0x0, 0xe, 0xf6, 0x0, 0x0, 0x58, 0x88, + 0xff, 0xb8, 0x88, 0x1f, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x9b, 0xbb, 0xff, 0xdb, 0xbb, 0x30, 0x0, + 0xe, 0xf6, 0x0, 0x0, 0x0, 0x0, 0xef, 0x60, + 0x0, 0x0, 0x0, 0xe, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x9d, 0x20, 0x0, 0x0, + + /* U+F068 "" */ + 0x46, 0x66, 0x66, 0x66, 0x66, 0x1f, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0xad, 0xdd, 0xdd, 0xdd, 0xdd, + 0x40, + + /* U+F06E "" */ + 0x0, 0x3, 0xad, 0xff, 0xc7, 0x0, 0x0, 0x0, + 0x9f, 0xe6, 0x24, 0xaf, 0xe3, 0x0, 0xb, 0xff, + 0x20, 0x77, 0x9, 0xff, 0x40, 0x7f, 0xf9, 0x0, + 0xcf, 0xa1, 0xff, 0xe1, 0xef, 0xf6, 0x7f, 0xff, + 0xf0, 0xef, 0xf7, 0x8f, 0xf9, 0x3f, 0xff, 0xc1, + 0xff, 0xe1, 0xb, 0xff, 0x26, 0xca, 0x19, 0xff, + 0x40, 0x0, 0x9f, 0xe6, 0x24, 0xaf, 0xe3, 0x0, + 0x0, 0x3, 0x9d, 0xff, 0xc7, 0x0, 0x0, + + /* U+F070 "" */ + 0x32, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1c, 0xf8, 0x4a, 0xef, 0xeb, 0x50, 0x0, 0x0, + 0x0, 0x9f, 0xfd, 0x52, 0x5d, 0xfc, 0x10, 0x0, + 0x0, 0x5, 0xfe, 0x4a, 0x70, 0xcf, 0xe1, 0x0, + 0xb, 0x80, 0x2d, 0xff, 0xf7, 0x4f, 0xfb, 0x0, + 0x2f, 0xfb, 0x0, 0xaf, 0xfb, 0x2f, 0xff, 0x30, + 0xb, 0xff, 0x50, 0x7, 0xfe, 0x7f, 0xfb, 0x0, + 0x1, 0xdf, 0xc0, 0x0, 0x3e, 0xff, 0xe1, 0x0, + 0x0, 0x1b, 0xfc, 0x42, 0x1, 0xbf, 0xa0, 0x0, + 0x0, 0x0, 0x5b, 0xef, 0xb0, 0x8, 0xfc, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xe0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x40, + + /* U+F071 "" */ + 0x0, 0x0, 0x0, 0x3, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xef, 0xf7, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8f, 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, + 0x2f, 0xfd, 0xef, 0xa0, 0x0, 0x0, 0x0, 0xb, + 0xfb, 0x3, 0xff, 0x30, 0x0, 0x0, 0x4, 0xff, + 0xc0, 0x4f, 0xfc, 0x0, 0x0, 0x0, 0xdf, 0xfd, + 0x5, 0xff, 0xf6, 0x0, 0x0, 0x7f, 0xff, 0xf8, + 0xcf, 0xff, 0xe1, 0x0, 0x1f, 0xff, 0xfc, 0x4, + 0xff, 0xff, 0x90, 0xa, 0xff, 0xff, 0xd2, 0x7f, + 0xff, 0xff, 0x20, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf6, 0x4, 0x78, 0x88, 0x88, 0x88, 0x88, + 0x87, 0x0, + + /* U+F074 "" */ + 0x0, 0x0, 0x0, 0x0, 0x6, 0x10, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xc1, 0xff, 0xf8, 0x0, 0x2e, + 0xff, 0xfc, 0xcd, 0xff, 0x62, 0xef, 0xdf, 0xf9, + 0x0, 0x2c, 0x4e, 0xf9, 0xf, 0x90, 0x0, 0x2, + 0xef, 0x90, 0x7, 0x0, 0x0, 0x2e, 0xf8, 0x88, + 0xf, 0xa0, 0xcd, 0xff, 0x80, 0xdf, 0xdf, 0xf9, + 0xff, 0xf8, 0x0, 0x1e, 0xff, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0xf, 0xc0, 0x0, 0x0, 0x0, 0x0, + 0x6, 0x10, + + /* U+F077 "" */ + 0x0, 0x0, 0x27, 0x0, 0x0, 0x0, 0x0, 0x2e, + 0xf9, 0x0, 0x0, 0x0, 0x2e, 0xff, 0xf9, 0x0, + 0x0, 0x2e, 0xf9, 0x2e, 0xf9, 0x0, 0x2e, 0xf9, + 0x0, 0x2e, 0xf9, 0xb, 0xf9, 0x0, 0x0, 0x2e, + 0xf4, 0x27, 0x0, 0x0, 0x0, 0x27, 0x0, + + /* U+F078 "" */ + 0x27, 0x0, 0x0, 0x0, 0x27, 0xb, 0xf9, 0x0, + 0x0, 0x2e, 0xf4, 0x2e, 0xf9, 0x0, 0x2e, 0xf9, + 0x0, 0x2e, 0xf9, 0x2e, 0xf9, 0x0, 0x0, 0x2e, + 0xff, 0xf9, 0x0, 0x0, 0x0, 0x2e, 0xf9, 0x0, + 0x0, 0x0, 0x0, 0x26, 0x0, 0x0, 0x0, + + /* U+F079 "" */ + 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x3f, 0xc0, 0x7, 0x77, 0x77, 0x72, 0x0, + 0x3, 0xff, 0xfc, 0x2e, 0xff, 0xff, 0xf9, 0x0, + 0xf, 0xcf, 0xcf, 0xa0, 0x0, 0x0, 0xe9, 0x0, + 0x4, 0x1e, 0x93, 0x20, 0x0, 0x0, 0xe9, 0x0, + 0x0, 0xe, 0x90, 0x0, 0x0, 0x0, 0xe9, 0x0, + 0x0, 0xe, 0x90, 0x0, 0x0, 0xb5, 0xe9, 0x97, + 0x0, 0xe, 0xc7, 0x77, 0x73, 0xbf, 0xff, 0xf6, + 0x0, 0xd, 0xff, 0xff, 0xfd, 0xb, 0xff, 0x70, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa6, 0x0, + + /* U+F07B "" */ + 0xbf, 0xff, 0xf6, 0x0, 0x0, 0x0, 0xff, 0xff, + 0xff, 0x98, 0x88, 0x74, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xfb, + + /* U+F093 "" */ + 0x0, 0x0, 0x2, 0x20, 0x0, 0x0, 0x0, 0x0, + 0x3e, 0xe3, 0x0, 0x0, 0x0, 0x3, 0xef, 0xfe, + 0x30, 0x0, 0x0, 0x3e, 0xff, 0xff, 0xe3, 0x0, + 0x0, 0xef, 0xff, 0xff, 0xfe, 0x0, 0x0, 0x0, + 0x8f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xf8, 0x0, 0x0, + 0x23, 0x32, 0x8f, 0xf8, 0x23, 0x32, 0xff, 0xfe, + 0x39, 0x93, 0xef, 0xff, 0xff, 0xff, 0xc9, 0x9c, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5c, 0x8f, + 0x9a, 0xaa, 0xaa, 0xaa, 0xaa, 0xa8, + + /* U+F095 "" */ + 0x0, 0x0, 0x0, 0x0, 0x3, 0x62, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x3f, 0xff, 0xe0, 0x0, 0x0, 0x0, 0x9, + 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x2d, 0xff, + 0x90, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0xc, 0xfd, 0x0, 0x0, 0x1, + 0x0, 0x9, 0xff, 0x40, 0x1, 0x8e, 0xe1, 0x1a, + 0xff, 0x70, 0x0, 0xef, 0xff, 0xde, 0xff, 0x90, + 0x0, 0xc, 0xff, 0xff, 0xff, 0x60, 0x0, 0x0, + 0x8f, 0xff, 0xe9, 0x10, 0x0, 0x0, 0x2, 0x76, + 0x30, 0x0, 0x0, 0x0, 0x0, + + /* U+F0C4 "" */ + 0x7, 0x93, 0x0, 0x0, 0x22, 0xa, 0xff, 0xf2, + 0x0, 0x8f, 0xf5, 0xf9, 0x1f, 0x70, 0x8f, 0xf9, + 0xc, 0xfc, 0xf8, 0x8f, 0xf9, 0x0, 0x1a, 0xef, + 0xff, 0xf9, 0x0, 0x0, 0x0, 0xef, 0xfc, 0x0, + 0x0, 0x7, 0xbf, 0xff, 0xf6, 0x0, 0xa, 0xff, + 0xfa, 0xbf, 0xf6, 0x0, 0xf9, 0x1f, 0x70, 0xbf, + 0xf6, 0xc, 0xfc, 0xf4, 0x0, 0xbf, 0xf4, 0x1a, + 0xc6, 0x0, 0x0, 0x56, 0x0, + + /* U+F0C5 "" */ + 0x0, 0x3, 0x44, 0x41, 0x20, 0x0, 0x0, 0xff, + 0xff, 0x5e, 0x40, 0x24, 0x1f, 0xff, 0xf5, 0xee, + 0x2f, 0xf4, 0xff, 0xff, 0xc8, 0x82, 0xff, 0x4f, + 0xff, 0xff, 0xff, 0x5f, 0xf4, 0xff, 0xff, 0xff, + 0xf5, 0xff, 0x4f, 0xff, 0xff, 0xff, 0x5f, 0xf4, + 0xff, 0xff, 0xff, 0xf5, 0xff, 0x4f, 0xff, 0xff, + 0xff, 0x5f, 0xf4, 0xff, 0xff, 0xff, 0xf4, 0xff, + 0x93, 0x44, 0x44, 0x43, 0xf, 0xff, 0xff, 0xff, + 0x50, 0x0, 0x68, 0x88, 0x88, 0x71, 0x0, 0x0, + + /* U+F0C7 "" */ + 0x48, 0x88, 0x88, 0x87, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xfb, 0x0, 0xf8, 0x0, 0x0, 0xb, 0xfb, + 0xf, 0x80, 0x0, 0x0, 0xbf, 0xf3, 0xfb, 0x77, + 0x77, 0x7d, 0xff, 0x4f, 0xff, 0xff, 0xff, 0xff, + 0xf4, 0xff, 0xff, 0x42, 0xdf, 0xff, 0x4f, 0xff, + 0xc0, 0x8, 0xff, 0xf4, 0xff, 0xfe, 0x0, 0xaf, + 0xff, 0x4f, 0xff, 0xfc, 0xaf, 0xff, 0xf4, 0xaf, + 0xff, 0xff, 0xff, 0xfd, 0x10, + + /* U+F0C9 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0x9a, 0xaa, 0xaa, 0xaa, 0xaa, + 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x89, 0x99, + 0x99, 0x99, 0x99, 0x3f, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x12, 0x22, 0x22, 0x22, 0x22, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x9a, 0xaa, 0xaa, 0xaa, + 0xaa, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F0E0 "" */ + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x4e, 0xff, 0xff, 0xff, + 0xff, 0xe4, 0xc3, 0xbf, 0xff, 0xff, 0xfb, 0x3c, + 0xff, 0x57, 0xff, 0xff, 0x75, 0xff, 0xff, 0xf9, + 0x3d, 0xd3, 0x9f, 0xff, 0xff, 0xff, 0xd5, 0x5d, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xfb, + + /* U+F0E7 "" */ + 0x1, 0xbb, 0xba, 0x10, 0x0, 0x5f, 0xff, 0xf1, + 0x0, 0x7, 0xff, 0xfb, 0x0, 0x0, 0x9f, 0xff, + 0x60, 0x0, 0xb, 0xff, 0xff, 0xff, 0x60, 0xef, + 0xff, 0xff, 0xf1, 0xe, 0xff, 0xff, 0xf8, 0x0, + 0x0, 0xc, 0xfe, 0x0, 0x0, 0x0, 0xff, 0x50, + 0x0, 0x0, 0x3f, 0xc0, 0x0, 0x0, 0x7, 0xf3, + 0x0, 0x0, 0x0, 0xa9, 0x0, 0x0, 0x0, 0x2, + 0x0, 0x0, 0x0, + + /* U+F0EA "" */ + 0x0, 0x2a, 0x50, 0x0, 0x0, 0xe, 0xff, 0x8f, + 0xff, 0x20, 0x0, 0xff, 0xf8, 0xff, 0xf4, 0x0, + 0xf, 0xff, 0xeb, 0xbb, 0x30, 0x0, 0xff, 0xf4, + 0x99, 0x92, 0x60, 0xf, 0xff, 0x5f, 0xff, 0x4f, + 0xa0, 0xff, 0xf5, 0xff, 0xf5, 0x56, 0x1f, 0xff, + 0x5f, 0xff, 0xff, 0xf4, 0xff, 0xf5, 0xff, 0xff, + 0xff, 0x4e, 0xff, 0x5f, 0xff, 0xff, 0xf4, 0x0, + 0x5, 0xff, 0xff, 0xff, 0x40, 0x0, 0x5f, 0xff, + 0xff, 0xf4, 0x0, 0x0, 0x44, 0x44, 0x44, 0x0, + + /* U+F0F3 "" */ + 0x0, 0x0, 0x15, 0x0, 0x0, 0x0, 0x0, 0x9, + 0xf1, 0x0, 0x0, 0x0, 0x2d, 0xff, 0xf9, 0x0, + 0x0, 0xe, 0xff, 0xff, 0xf7, 0x0, 0x5, 0xff, + 0xff, 0xff, 0xd0, 0x0, 0x8f, 0xff, 0xff, 0xff, + 0x0, 0xa, 0xff, 0xff, 0xff, 0xf2, 0x0, 0xdf, + 0xff, 0xff, 0xff, 0x50, 0x6f, 0xff, 0xff, 0xff, + 0xfd, 0xe, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x24, + 0x44, 0x44, 0x44, 0x43, 0x0, 0x0, 0x2f, 0xf9, + 0x0, 0x0, 0x0, 0x0, 0x46, 0x0, 0x0, 0x0, + + /* U+F11C "" */ + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0xfc, + 0x8e, 0x8e, 0x8e, 0x88, 0xe8, 0xf7, 0xf8, 0xc, + 0xc, 0xb, 0x0, 0xb0, 0xf8, 0xff, 0xec, 0xfc, + 0xec, 0xee, 0xcf, 0xf8, 0xff, 0xa0, 0xc0, 0xa0, + 0x77, 0x2f, 0xf8, 0xff, 0xec, 0xfc, 0xec, 0xee, + 0xcf, 0xf8, 0xf8, 0xc, 0x0, 0x0, 0x0, 0xb0, + 0xf8, 0xfc, 0x8e, 0x88, 0x88, 0x88, 0xe8, 0xf7, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + + /* U+F124 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0x30, 0x0, + 0x0, 0x0, 0x0, 0x18, 0xef, 0xe0, 0x0, 0x0, + 0x0, 0x29, 0xff, 0xff, 0xb0, 0x0, 0x0, 0x3a, + 0xff, 0xff, 0xff, 0x30, 0x0, 0x4c, 0xff, 0xff, + 0xff, 0xfc, 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, + 0xf5, 0x0, 0xe, 0xff, 0xff, 0xff, 0xff, 0xd0, + 0x0, 0x1, 0x34, 0x44, 0xdf, 0xff, 0x60, 0x0, + 0x0, 0x0, 0x0, 0xcf, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0xf8, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xcf, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xbf, 0x90, 0x0, 0x0, 0x0, 0x0, 0x0, 0x26, + 0x0, 0x0, 0x0, + + /* U+F15B "" */ + 0x9b, 0xbb, 0xb2, 0x70, 0xf, 0xff, 0xff, 0x4f, + 0x90, 0xff, 0xff, 0xf4, 0xff, 0x9f, 0xff, 0xff, + 0x54, 0x44, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x34, 0x44, + 0x44, 0x44, 0x30, + + /* U+F1EB "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x5, 0x9b, 0xcb, 0x95, 0x0, 0x0, 0x0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0x80, 0x3, 0xef, + 0xfa, 0x53, 0x23, 0x5a, 0xff, 0xe3, 0xdf, 0xa1, + 0x0, 0x0, 0x0, 0x1, 0xaf, 0xd2, 0x60, 0x5, + 0xbe, 0xfe, 0xb5, 0x0, 0x52, 0x0, 0x1c, 0xff, + 0xfe, 0xff, 0xfc, 0x10, 0x0, 0x2, 0xec, 0x40, + 0x0, 0x4c, 0xe2, 0x0, 0x0, 0x1, 0x0, 0x1, + 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0xa, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xd6, 0x0, + 0x0, 0x0, + + /* U+F240 "" */ + 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x75, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf8, + 0x34, 0x44, 0x44, 0x44, 0x44, 0x4f, 0xdf, 0x8c, + 0xff, 0xff, 0xff, 0xff, 0xf2, 0xcf, 0xf8, 0xcf, + 0xff, 0xff, 0xff, 0xff, 0x8, 0xff, 0x89, 0xcc, + 0xcc, 0xcc, 0xcc, 0xc3, 0xff, 0xfb, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x9f, 0x9c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F241 "" */ + 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x75, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf8, + 0x34, 0x44, 0x44, 0x43, 0x0, 0x4f, 0xdf, 0x8c, + 0xff, 0xff, 0xff, 0xc0, 0x2, 0xcf, 0xf8, 0xcf, + 0xff, 0xff, 0xfc, 0x0, 0x8, 0xff, 0x89, 0xcc, + 0xcc, 0xcc, 0x90, 0x3, 0xff, 0xfb, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x9f, 0x9c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F242 "" */ + 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x75, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf8, + 0x34, 0x44, 0x42, 0x0, 0x0, 0x4f, 0xdf, 0x8c, + 0xff, 0xff, 0x80, 0x0, 0x2, 0xcf, 0xf8, 0xcf, + 0xff, 0xf8, 0x0, 0x0, 0x8, 0xff, 0x89, 0xcc, + 0xcc, 0x60, 0x0, 0x3, 0xff, 0xfb, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x9f, 0x9c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F243 "" */ + 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x75, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf8, + 0x34, 0x41, 0x0, 0x0, 0x0, 0x4f, 0xdf, 0x8c, + 0xff, 0x40, 0x0, 0x0, 0x2, 0xcf, 0xf8, 0xcf, + 0xf4, 0x0, 0x0, 0x0, 0x8, 0xff, 0x89, 0xcc, + 0x30, 0x0, 0x0, 0x3, 0xff, 0xfb, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x9f, 0x9c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F244 "" */ + 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x75, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xdf, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x2, 0xcf, 0xf8, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, 0x80, 0x0, + 0x0, 0x0, 0x0, 0x3, 0xff, 0xfb, 0x77, 0x77, + 0x77, 0x77, 0x77, 0x9f, 0x9c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe1, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F287 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x25, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x5, 0xcb, 0xfe, 0x0, 0x0, 0x0, + 0x1, 0x0, 0xd, 0x10, 0x42, 0x0, 0x0, 0x0, + 0x9f, 0xd1, 0x68, 0x0, 0x0, 0x0, 0x68, 0x0, + 0xff, 0xfe, 0xee, 0xed, 0xdd, 0xdd, 0xef, 0xc0, + 0x9f, 0xd1, 0x0, 0xb3, 0x0, 0x0, 0x68, 0x0, + 0x1, 0x0, 0x0, 0x3b, 0x5, 0x74, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9, 0xbe, 0xfb, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x2d, 0xfb, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F293 "" */ + 0x0, 0x0, 0x34, 0x20, 0x0, 0x0, 0x6e, 0xfe, + 0xfd, 0x20, 0x4, 0xff, 0xf3, 0xff, 0xd0, 0xc, + 0xff, 0xf0, 0x4f, 0xf5, 0xf, 0xd5, 0xf2, 0x95, + 0xf8, 0x2f, 0xf7, 0x41, 0x3c, 0xfa, 0x3f, 0xff, + 0x60, 0xaf, 0xfb, 0x3f, 0xfe, 0x20, 0x4f, 0xfb, + 0x2f, 0xe2, 0x92, 0x75, 0xfa, 0xf, 0xeb, 0xf1, + 0x49, 0xf8, 0x9, 0xff, 0xf0, 0x9f, 0xf2, 0x1, + 0xdf, 0xf9, 0xff, 0x90, 0x0, 0x6, 0xab, 0x95, + 0x0, + + /* U+F2ED "" */ + 0x0, 0x4, 0x88, 0x70, 0x0, 0xb, 0xcc, 0xff, + 0xff, 0xdc, 0xc5, 0xbc, 0xcc, 0xcc, 0xcc, 0xcc, + 0x52, 0x88, 0x88, 0x88, 0x88, 0x60, 0x4f, 0xff, + 0xff, 0xff, 0xfc, 0x4, 0xfa, 0xae, 0x6f, 0x5f, + 0xc0, 0x4f, 0xaa, 0xe6, 0xf4, 0xfc, 0x4, 0xfa, + 0xae, 0x6f, 0x4f, 0xc0, 0x4f, 0xaa, 0xe6, 0xf4, + 0xfc, 0x4, 0xfa, 0xae, 0x6f, 0x4f, 0xc0, 0x4f, + 0xaa, 0xe6, 0xf5, 0xfc, 0x3, 0xff, 0xff, 0xff, + 0xff, 0xb0, 0x6, 0x88, 0x88, 0x88, 0x72, 0x0, + + /* U+F304 "" */ + 0x0, 0x0, 0x0, 0x0, 0x1, 0x71, 0x0, 0x0, + 0x0, 0x0, 0x2, 0xef, 0xd1, 0x0, 0x0, 0x0, + 0x1, 0x5f, 0xff, 0xc0, 0x0, 0x0, 0x2, 0xea, + 0x5f, 0xfd, 0x0, 0x0, 0x2, 0xef, 0xfa, 0x5d, + 0x20, 0x0, 0x2, 0xef, 0xff, 0xf8, 0x0, 0x0, + 0x2, 0xef, 0xff, 0xfe, 0x20, 0x0, 0x2, 0xef, + 0xff, 0xfe, 0x20, 0x0, 0x2, 0xef, 0xff, 0xfe, + 0x20, 0x0, 0x0, 0xbf, 0xff, 0xfe, 0x20, 0x0, + 0x0, 0xd, 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, + 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, 0x6, 0x64, + 0x10, 0x0, 0x0, 0x0, 0x0, + + /* U+F55A "" */ + 0x0, 0x5, 0xef, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5, + 0xff, 0xff, 0x91, 0xdd, 0x19, 0xff, 0xf5, 0xff, + 0xff, 0xfd, 0x11, 0x11, 0xdf, 0xff, 0xef, 0xff, + 0xff, 0xfb, 0x0, 0xbf, 0xff, 0xf5, 0xff, 0xff, + 0xfd, 0x11, 0x11, 0xdf, 0xff, 0x5, 0xff, 0xff, + 0x91, 0xdd, 0x19, 0xff, 0xf0, 0x5, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0x4, 0xef, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F7C2 "" */ + 0x0, 0x17, 0x88, 0x87, 0x20, 0x2d, 0xff, 0xff, + 0xfd, 0x2e, 0xa0, 0xb3, 0x78, 0xfe, 0xfa, 0xb, + 0x37, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfc, 0xff, 0xff, 0xff, 0xfc, 0x4, 0x44, + 0x44, 0x44, 0x0, + + /* U+F8A2 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x4, 0xf0, 0x0, 0x69, 0x0, + 0x0, 0x0, 0xdf, 0x0, 0x7f, 0xc0, 0x0, 0x0, + 0xd, 0xf0, 0x8f, 0xff, 0xdd, 0xdd, 0xdd, 0xff, + 0xb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xb, + 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xc0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0 +}; + + +/*--------------------- + * GLYPH DESCRIPTION + *--------------------*/ + +static const lv_font_fmt_txt_glyph_dsc_t glyph_dsc[] = { + {.bitmap_index = 0, .adv_w = 0, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0} /* id = 0 reserved */, + {.bitmap_index = 0, .adv_w = 52, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 0, .adv_w = 51, .box_w = 3, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 14, .adv_w = 75, .box_w = 4, .box_h = 4, .ofs_x = 0, .ofs_y = 5}, + {.bitmap_index = 22, .adv_w = 135, .box_w = 9, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 63, .adv_w = 119, .box_w = 7, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 109, .adv_w = 162, .box_w = 10, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 154, .adv_w = 132, .box_w = 9, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 199, .adv_w = 40, .box_w = 2, .box_h = 4, .ofs_x = 0, .ofs_y = 5}, + {.bitmap_index = 203, .adv_w = 65, .box_w = 3, .box_h = 13, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 223, .adv_w = 65, .box_w = 3, .box_h = 13, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 243, .adv_w = 77, .box_w = 5, .box_h = 5, .ofs_x = 0, .ofs_y = 5}, + {.bitmap_index = 256, .adv_w = 112, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 2}, + {.bitmap_index = 277, .adv_w = 74, .box_w = 4, .box_h = 2, .ofs_x = 0, .ofs_y = 2}, + {.bitmap_index = 281, .adv_w = 44, .box_w = 3, .box_h = 2, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 284, .adv_w = 68, .box_w = 6, .box_h = 13, .ofs_x = -1, .ofs_y = -1}, + {.bitmap_index = 323, .adv_w = 128, .box_w = 8, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 359, .adv_w = 71, .box_w = 4, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 377, .adv_w = 110, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 409, .adv_w = 110, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 441, .adv_w = 128, .box_w = 8, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 477, .adv_w = 110, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 509, .adv_w = 118, .box_w = 8, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 545, .adv_w = 115, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 577, .adv_w = 124, .box_w = 8, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 613, .adv_w = 118, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 645, .adv_w = 44, .box_w = 3, .box_h = 7, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 656, .adv_w = 44, .box_w = 3, .box_h = 9, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 670, .adv_w = 112, .box_w = 7, .box_h = 7, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 695, .adv_w = 112, .box_w = 7, .box_h = 5, .ofs_x = 0, .ofs_y = 2}, + {.bitmap_index = 713, .adv_w = 112, .box_w = 7, .box_h = 7, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 738, .adv_w = 110, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 770, .adv_w = 199, .box_w = 12, .box_h = 12, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 842, .adv_w = 141, .box_w = 10, .box_h = 9, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 887, .adv_w = 145, .box_w = 8, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 923, .adv_w = 139, .box_w = 9, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 964, .adv_w = 159, .box_w = 9, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1005, .adv_w = 129, .box_w = 7, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1037, .adv_w = 122, .box_w = 7, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1069, .adv_w = 148, .box_w = 9, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1110, .adv_w = 156, .box_w = 8, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1146, .adv_w = 60, .box_w = 2, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1155, .adv_w = 98, .box_w = 6, .box_h = 9, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 1182, .adv_w = 138, .box_w = 8, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1218, .adv_w = 114, .box_w = 7, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1250, .adv_w = 183, .box_w = 10, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1295, .adv_w = 156, .box_w = 8, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1331, .adv_w = 161, .box_w = 10, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1376, .adv_w = 139, .box_w = 8, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1412, .adv_w = 161, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 1472, .adv_w = 140, .box_w = 8, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1508, .adv_w = 119, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1540, .adv_w = 113, .box_w = 7, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1572, .adv_w = 152, .box_w = 8, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1608, .adv_w = 137, .box_w = 10, .box_h = 9, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 1653, .adv_w = 216, .box_w = 14, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1716, .adv_w = 129, .box_w = 8, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1752, .adv_w = 124, .box_w = 9, .box_h = 9, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 1793, .adv_w = 126, .box_w = 8, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1829, .adv_w = 64, .box_w = 3, .box_h = 13, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 1849, .adv_w = 68, .box_w = 6, .box_h = 13, .ofs_x = -1, .ofs_y = -1}, + {.bitmap_index = 1888, .adv_w = 64, .box_w = 3, .box_h = 13, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 1908, .adv_w = 112, .box_w = 7, .box_h = 6, .ofs_x = 0, .ofs_y = 2}, + {.bitmap_index = 1929, .adv_w = 96, .box_w = 6, .box_h = 1, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 1932, .adv_w = 115, .box_w = 4, .box_h = 2, .ofs_x = 1, .ofs_y = 8}, + {.bitmap_index = 1936, .adv_w = 115, .box_w = 7, .box_h = 7, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1961, .adv_w = 131, .box_w = 7, .box_h = 10, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1996, .adv_w = 110, .box_w = 7, .box_h = 7, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2021, .adv_w = 131, .box_w = 8, .box_h = 10, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2061, .adv_w = 118, .box_w = 7, .box_h = 7, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2086, .adv_w = 68, .box_w = 5, .box_h = 10, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2111, .adv_w = 132, .box_w = 8, .box_h = 10, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 2151, .adv_w = 131, .box_w = 7, .box_h = 10, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2186, .adv_w = 54, .box_w = 3, .box_h = 10, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2201, .adv_w = 55, .box_w = 5, .box_h = 13, .ofs_x = -2, .ofs_y = -3}, + {.bitmap_index = 2234, .adv_w = 118, .box_w = 7, .box_h = 10, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2269, .adv_w = 54, .box_w = 2, .box_h = 10, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2279, .adv_w = 203, .box_w = 11, .box_h = 7, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2318, .adv_w = 131, .box_w = 7, .box_h = 7, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2343, .adv_w = 122, .box_w = 8, .box_h = 7, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2371, .adv_w = 131, .box_w = 7, .box_h = 10, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 2406, .adv_w = 131, .box_w = 8, .box_h = 10, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 2446, .adv_w = 79, .box_w = 4, .box_h = 7, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2460, .adv_w = 96, .box_w = 6, .box_h = 7, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2481, .adv_w = 79, .box_w = 5, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2504, .adv_w = 130, .box_w = 7, .box_h = 7, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2529, .adv_w = 107, .box_w = 8, .box_h = 7, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 2557, .adv_w = 173, .box_w = 11, .box_h = 7, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2596, .adv_w = 106, .box_w = 7, .box_h = 7, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2621, .adv_w = 107, .box_w = 8, .box_h = 10, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 2661, .adv_w = 100, .box_w = 6, .box_h = 7, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2682, .adv_w = 67, .box_w = 4, .box_h = 13, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 2708, .adv_w = 57, .box_w = 2, .box_h = 13, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 2721, .adv_w = 67, .box_w = 4, .box_h = 13, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 2747, .adv_w = 112, .box_w = 7, .box_h = 2, .ofs_x = 0, .ofs_y = 4}, + {.bitmap_index = 2754, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 2832, .adv_w = 192, .box_w = 12, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2886, .adv_w = 192, .box_w = 12, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 2952, .adv_w = 192, .box_w = 12, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3006, .adv_w = 132, .box_w = 9, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3047, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3125, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3203, .adv_w = 216, .box_w = 14, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3280, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3358, .adv_w = 216, .box_w = 14, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3421, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3499, .adv_w = 96, .box_w = 6, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3529, .adv_w = 144, .box_w = 9, .box_h = 10, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3574, .adv_w = 216, .box_w = 14, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3665, .adv_w = 192, .box_w = 12, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3719, .adv_w = 132, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3778, .adv_w = 168, .box_w = 8, .box_h = 12, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 3826, .adv_w = 168, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3898, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 3959, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4020, .adv_w = 168, .box_w = 8, .box_h = 12, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 4068, .adv_w = 168, .box_w = 12, .box_h = 11, .ofs_x = -1, .ofs_y = -1}, + {.bitmap_index = 4134, .adv_w = 120, .box_w = 7, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4173, .adv_w = 120, .box_w = 7, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4212, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4273, .adv_w = 168, .box_w = 11, .box_h = 3, .ofs_x = 0, .ofs_y = 3}, + {.bitmap_index = 4290, .adv_w = 216, .box_w = 14, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 4353, .adv_w = 240, .box_w = 16, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 4457, .adv_w = 216, .box_w = 15, .box_h = 13, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 4555, .adv_w = 192, .box_w = 12, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4621, .adv_w = 168, .box_w = 11, .box_h = 7, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 4660, .adv_w = 168, .box_w = 11, .box_h = 7, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 4699, .adv_w = 240, .box_w = 16, .box_h = 10, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 4779, .adv_w = 192, .box_w = 12, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 4833, .adv_w = 192, .box_w = 12, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 4911, .adv_w = 192, .box_w = 13, .box_h = 13, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 4996, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5057, .adv_w = 168, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5129, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5190, .adv_w = 168, .box_w = 11, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5251, .adv_w = 192, .box_w = 12, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 5305, .adv_w = 120, .box_w = 9, .box_h = 13, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 5364, .adv_w = 168, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5436, .adv_w = 168, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5508, .adv_w = 216, .box_w = 14, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 5571, .adv_w = 192, .box_w = 14, .box_h = 13, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 5662, .adv_w = 144, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5721, .adv_w = 240, .box_w = 15, .box_h = 12, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5811, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 5879, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 5947, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 6015, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 6083, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 6151, .adv_w = 240, .box_w = 16, .box_h = 11, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6239, .adv_w = 168, .box_w = 10, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6304, .adv_w = 168, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6376, .adv_w = 192, .box_w = 13, .box_h = 13, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 6461, .adv_w = 240, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 6529, .adv_w = 144, .box_w = 9, .box_h = 13, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6588, .adv_w = 193, .box_w = 13, .box_h = 9, .ofs_x = 0, .ofs_y = 0} +}; + +/*--------------------- + * CHARACTER MAPPING + *--------------------*/ + +static const uint16_t unicode_list_2[] = { + 0x0, 0x7, 0xa, 0xb, 0xc, 0x10, 0x12, 0x14, + 0x18, 0x1b, 0x20, 0x25, 0x26, 0x27, 0x3d, 0x42, + 0x47, 0x4a, 0x4b, 0x4c, 0x50, 0x51, 0x52, 0x53, + 0x66, 0x67, 0x6d, 0x6f, 0x70, 0x73, 0x76, 0x77, + 0x78, 0x7a, 0x92, 0x94, 0xc3, 0xc4, 0xc6, 0xc8, + 0xdf, 0xe6, 0xe9, 0xf2, 0x11b, 0x123, 0x15a, 0x1ea, + 0x23f, 0x240, 0x241, 0x242, 0x243, 0x286, 0x292, 0x2ec, + 0x303, 0x559, 0x7c1, 0x8a1 +}; + +/*Collect the unicode lists and glyph_id offsets*/ +static const lv_font_fmt_txt_cmap_t cmaps[] = +{ + { + .range_start = 32, .range_length = 12, .glyph_id_start = 1, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 45, .range_length = 82, .glyph_id_start = 13, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 61441, .range_length = 2210, .glyph_id_start = 95, + .unicode_list = unicode_list_2, .glyph_id_ofs_list = NULL, .list_length = 60, .type = LV_FONT_FMT_TXT_CMAP_SPARSE_TINY + } +}; + +/*----------------- + * KERNING + *----------------*/ + + +/*Map glyph_ids to kern left classes*/ +static const uint8_t kern_left_class_mapping[] = +{ + 0, 0, 1, 2, 0, 3, 4, 5, + 2, 6, 7, 8, 9, 9, 10, 11, + 12, 0, 13, 14, 15, 16, 17, 18, + 19, 12, 20, 20, 0, 0, 0, 21, + 22, 23, 24, 25, 22, 26, 27, 28, + 29, 29, 30, 31, 32, 29, 29, 22, + 33, 34, 35, 3, 36, 30, 37, 37, + 38, 39, 40, 41, 42, 43, 0, 44, + 0, 45, 46, 47, 48, 49, 50, 51, + 45, 52, 52, 53, 48, 45, 45, 46, + 46, 54, 55, 56, 57, 51, 58, 58, + 59, 58, 60, 41, 0, 0, 9, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 +}; + +/*Map glyph_ids to kern right classes*/ +static const uint8_t kern_right_class_mapping[] = +{ + 0, 0, 1, 2, 0, 3, 4, 5, + 2, 6, 7, 8, 9, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 12, 18, + 19, 20, 21, 21, 0, 0, 0, 22, + 23, 24, 25, 23, 25, 25, 25, 23, + 25, 25, 26, 25, 25, 25, 25, 23, + 25, 23, 25, 3, 27, 28, 29, 29, + 30, 31, 32, 33, 34, 35, 0, 36, + 0, 37, 38, 39, 39, 39, 0, 39, + 38, 40, 41, 38, 38, 42, 42, 39, + 42, 39, 42, 43, 44, 45, 46, 46, + 47, 46, 48, 0, 0, 35, 9, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 +}; + +/*Kern values between classes*/ +static const int8_t kern_class_values[] = +{ + 0, 1, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0, 2, 0, 0, 0, + 0, 1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 1, 9, 0, 5, -4, 0, 0, 0, + 0, -11, -12, 1, 9, 4, 3, -8, + 1, 9, 1, 8, 2, 6, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 12, 2, -1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -6, 0, 0, 0, 0, 0, -4, + 3, 4, 0, 0, -2, 0, -1, 2, + 0, -2, 0, -2, -1, -4, 0, 0, + 0, 0, -2, 0, 0, -2, -3, 0, + 0, -2, 0, -4, 0, 0, 0, 0, + 0, 0, 0, 0, 0, -2, -2, 0, + 0, -5, 0, -23, 0, 0, -4, 0, + 4, 6, 0, 0, -4, 2, 2, 6, + 4, -3, 4, 0, 0, -11, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -7, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + -2, -9, 0, -8, -1, 0, 0, 0, + 0, 0, 7, 0, -6, -2, -1, 1, + 0, -3, 0, 0, -1, -14, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -15, -2, 7, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 6, 0, 2, 0, 0, -4, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 7, 2, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, -7, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 1, 4, 2, 6, -2, 0, 0, 4, + -2, -6, -26, 1, 5, 4, 0, -2, + 0, 7, 0, 6, 0, 6, 0, -18, + 0, -2, 6, 0, 6, -2, 4, 2, + 0, 0, 1, -2, 0, 0, -3, 15, + 0, 15, 0, 6, 0, 8, 2, 3, + 0, 0, 0, -7, 0, 0, 0, 0, + 1, -1, 0, 1, -3, -2, -4, 1, + 0, -2, 0, 0, 0, -8, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -12, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 1, -11, 0, -12, 0, 0, 0, 0, + -1, 0, 19, -2, -2, 2, 2, -2, + 0, -2, 2, 0, 0, -10, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -19, 0, 2, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 12, 0, 0, -7, 0, 6, 0, + -13, -19, -13, -4, 6, 0, 0, -13, + 0, 2, -4, 0, -3, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 5, 6, -23, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0, 0, 0, 0, 1, + 1, -2, -4, 0, -1, -1, -2, 0, + 0, -1, 0, 0, 0, -4, 0, -2, + 0, -4, -4, 0, -5, -6, -6, -4, + 0, -4, 0, -4, 0, 0, 0, 0, + -2, 0, 0, 2, 0, 1, -2, 0, + 0, 0, 0, 2, -1, 0, 0, 0, + -1, 2, 2, -1, 0, 0, 0, -4, + 0, -1, 0, 0, 0, 0, 0, 1, + 0, 2, -1, 0, -2, 0, -3, 0, + 0, -1, 0, 6, 0, 0, -2, 0, + 0, 0, 0, 0, -1, 1, -1, -1, + 0, -2, 0, -2, 0, 0, 0, 0, + 0, 0, 0, 0, 0, -1, -1, 0, + -2, -2, 0, 0, 0, 0, 0, 1, + 0, 0, -1, 0, -2, -2, -2, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + -1, 0, 0, 0, 0, -1, -2, 0, + 0, -6, -1, -6, 4, 0, 0, -4, + 2, 4, 5, 0, -5, -1, -2, 0, + -1, -9, 2, -1, 1, -10, 2, 0, + 0, 1, -10, 0, -10, -2, -17, -1, + 0, -10, 0, 4, 5, 0, 2, 0, + 0, 0, 0, 0, 0, -3, -2, 0, + 0, 0, 0, -2, 0, 0, 0, -2, + 0, 0, 0, 0, 0, -1, -1, 0, + -1, -2, 0, 0, 0, 0, 0, 0, + 0, -2, -2, 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+/*-------------------- + * ALL CUSTOM DATA + *--------------------*/ + +#if LV_VERSION_CHECK(8, 0, 0) +/*Store all the custom data of the font*/ +static lv_font_fmt_txt_glyph_cache_t cache; +static const lv_font_fmt_txt_dsc_t font_dsc = { +#else +static lv_font_fmt_txt_dsc_t font_dsc = { +#endif + .glyph_bitmap = glyph_bitmap, + .glyph_dsc = glyph_dsc, + .cmaps = cmaps, + .kern_dsc = &kern_classes, + .kern_scale = 16, + .cmap_num = 3, + .bpp = 4, + .kern_classes = 1, + .bitmap_format = 0, +#if LV_VERSION_CHECK(8, 0, 0) + .cache = &cache +#endif +}; + + +/*----------------- + * PUBLIC FONT + *----------------*/ + +/*Initialize a public general font descriptor*/ +#if LV_VERSION_CHECK(8, 0, 0) +const lv_font_t lv_font_montserratMedium_12 = { +#else +lv_font_t lv_font_montserratMedium_12 = { +#endif + .get_glyph_dsc = lv_font_get_glyph_dsc_fmt_txt, /*Function pointer to get glyph's data*/ + .get_glyph_bitmap = lv_font_get_bitmap_fmt_txt, /*Function pointer to get glyph's bitmap*/ + .line_height = 12, /*The maximum line height required by the font default: (f.src.ascent - f.src.descent)*/ + .base_line = 2, /*Baseline measured from the bottom of the line*/ +#if !(LVGL_VERSION_MAJOR == 6 && LVGL_VERSION_MINOR == 0) + .subpx = LV_FONT_SUBPX_NONE, +#endif +#if LV_VERSION_CHECK(7, 4, 0) || LVGL_VERSION_MAJOR >= 8 + .underline_position = -1, + .underline_thickness = 1, +#endif + .dsc = &font_dsc /*The custom font data. Will be accessed by `get_glyph_bitmap/dsc` */ +}; + + + +#endif /*#if LV_FONT_MONTSERRATMEDIUM_12*/ + diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_montserratMedium_16.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_montserratMedium_16.c new file mode 100644 index 0000000000000000000000000000000000000000..a94c6068dc609a9e8bfb39d2c8001d3ff79cc29b --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/guider_fonts/lv_font_montserratMedium_16.c @@ -0,0 +1,2458 @@ +/* + * Copyright 2024 NXP + * NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in + * accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, + * activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to + * comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license + * terms, then you may not retain, install, activate or otherwise use the software. + */ +/******************************************************************************* + * Size: 16 px + * Bpp: 4 + * Opts: --user-data-dir=C:\Users\hp\AppData\Roaming\gui-guider --app-path=C:\NXP\GUI-Guider-1.7.2-GA\resources\app.asar --no-sandbox --no-zygote --lang=zh-CN --device-scale-factor=1.5 --num-raster-threads=4 --enable-main-frame-before-activation --renderer-client-id=5 --time-ticks-at-unix-epoch=-1732015070561205 --launch-time-ticks=65380923608 --mojo-platform-channel-handle=3108 --field-trial-handle=1864,i,17219279099561217522,18026807573185265005,131072 --disable-features=SpareRendererForSitePerProcess,WinRetrieveSuggestionsOnlyOnDemand /prefetch:1 + ******************************************************************************/ + +#ifdef LV_LVGL_H_INCLUDE_SIMPLE +#include "lvgl.h" +#else +#include "lvgl.h" +#endif + +#ifndef LV_FONT_MONTSERRATMEDIUM_16 +#define LV_FONT_MONTSERRATMEDIUM_16 1 +#endif + +#if LV_FONT_MONTSERRATMEDIUM_16 + +/*----------------- + * BITMAPS + *----------------*/ + +/*Store the image of the glyphs*/ +static LV_ATTRIBUTE_LARGE_CONST const uint8_t glyph_bitmap[] = { + /* U+0020 " " */ + + /* U+0021 "!" */ + 0xbf, 0xb, 0xf0, 0xaf, 0xa, 0xe0, 0x9e, 0x8, + 0xd0, 0x8c, 0x7, 0xc0, 0x0, 0x0, 0x10, 0xbf, + 0x1a, 0xe0, + + /* U+0022 "\"" */ + 0xf5, 0x1f, 0x3f, 0x51, 0xf3, 0xe4, 0xf, 0x3e, + 0x40, 0xf2, 0x72, 0x8, 0x10, + + /* U+0023 "#" */ + 0x0, 0x5, 0xc0, 0x3, 0xe0, 0x0, 0x0, 0x7a, + 0x0, 0x5c, 0x0, 0x0, 0x9, 0x80, 0x7, 0xa0, + 0x1, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x3, 0x3e, + 0x73, 0x3c, 0x83, 0x30, 0x0, 0xf2, 0x0, 0xc5, + 0x0, 0x0, 0xf, 0x10, 0xe, 0x30, 0x0, 0x2, + 0xf0, 0x0, 0xf2, 0x0, 0x9f, 0xff, 0xff, 0xff, + 0xff, 0x41, 0x38, 0xc3, 0x36, 0xe3, 0x30, 0x0, + 0x89, 0x0, 0x5c, 0x0, 0x0, 0xa, 0x70, 0x7, + 0xa0, 0x0, + + /* U+0024 "$" */ + 0x0, 0x0, 0x79, 0x0, 0x0, 0x0, 0x0, 0x79, + 0x0, 0x0, 0x0, 0x5c, 0xff, 0xe9, 0x20, 0x6, + 0xfc, 0xbc, 0x9e, 0x90, 0xe, 0xb0, 0x79, 0x0, + 0x10, 0xf, 0x80, 0x79, 0x0, 0x0, 0xd, 0xf5, + 0x79, 0x0, 0x0, 0x3, 0xef, 0xfd, 0x50, 0x0, + 0x0, 0x6, 0xcf, 0xfe, 0x40, 0x0, 0x0, 0x79, + 0x5e, 0xf1, 0x0, 0x0, 0x79, 0x5, 0xf3, 0x7, + 0x0, 0x79, 0x7, 0xf1, 0x2f, 0xe9, 0xbc, 0xaf, + 0xa0, 0x3, 0xae, 0xff, 0xd7, 0x0, 0x0, 0x0, + 0x79, 0x0, 0x0, 0x0, 0x0, 0x79, 0x0, 0x0, + + /* U+0025 "%" */ + 0x3, 0xde, 0x80, 0x0, 0x5, 0xd0, 0x0, 0xe4, + 0xc, 0x50, 0x1, 0xe3, 0x0, 0x4c, 0x0, 0x5a, + 0x0, 0xa9, 0x0, 0x6, 0xa0, 0x4, 0xc0, 0x4e, + 0x0, 0x0, 0x4c, 0x0, 0x5a, 0xd, 0x50, 0x0, + 0x0, 0xe4, 0x1c, 0x58, 0xa0, 0x0, 0x0, 0x3, + 0xce, 0x73, 0xe1, 0x3c, 0xe9, 0x0, 0x0, 0x0, + 0xd6, 0xe, 0x40, 0xa8, 0x0, 0x0, 0x7c, 0x3, + 0xc0, 0x3, 0xd0, 0x0, 0x2e, 0x20, 0x3c, 0x0, + 0x3d, 0x0, 0xb, 0x70, 0x0, 0xe2, 0x9, 0x80, + 0x6, 0xd0, 0x0, 0x4, 0xdd, 0xa0, + + /* U+0026 "&" */ + 0x0, 0x9, 0xef, 0xb1, 0x0, 0x0, 0x9, 0xe4, + 0x3c, 0xa0, 0x0, 0x0, 0xd9, 0x0, 0x7d, 0x0, + 0x0, 0xc, 0xc0, 0x1c, 0xa0, 0x0, 0x0, 0x3f, + 0xae, 0xc1, 0x0, 0x0, 0x1, 0xdf, 0xc0, 0x0, + 0x0, 0x3, 0xeb, 0x8f, 0x70, 0x18, 0x0, 0xdb, + 0x0, 0x7f, 0x65, 0xf0, 0x3f, 0x40, 0x0, 0x8f, + 0xea, 0x3, 0xf7, 0x0, 0x0, 0xcf, 0x70, 0xb, + 0xf9, 0x66, 0xcf, 0xbf, 0x40, 0x8, 0xdf, 0xea, + 0x30, 0xa5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+0027 "'" */ + 0xf5, 0xf5, 0xe4, 0xe4, 0x72, + + /* U+0028 "(" */ + 0x0, 0xda, 0x5, 0xf2, 0xb, 0xc0, 0xf, 0x70, + 0x3f, 0x40, 0x5f, 0x20, 0x6f, 0x10, 0x7f, 0x0, + 0x6f, 0x10, 0x5f, 0x20, 0x3f, 0x40, 0xf, 0x70, + 0xb, 0xc0, 0x5, 0xf2, 0x0, 0xda, + + /* U+0029 ")" */ + 0x3f, 0x30, 0xc, 0xb0, 0x6, 0xf1, 0x1, 0xf6, + 0x0, 0xe9, 0x0, 0xbc, 0x0, 0xad, 0x0, 0xae, + 0x0, 0xad, 0x0, 0xbc, 0x0, 0xe9, 0x1, 0xf6, + 0x6, 0xf1, 0xc, 0xb0, 0x3f, 0x30, + + /* U+002A "*" */ + 0x0, 0x4a, 0x0, 0x6, 0x74, 0xa4, 0xa0, 0x2b, + 0xff, 0xe5, 0x0, 0x7f, 0xfb, 0x20, 0x7b, 0x6b, + 0x8d, 0x0, 0x4, 0xa0, 0x0, 0x0, 0x13, 0x0, + 0x0, + + /* U+002B "+" */ + 0x0, 0x5, 0x10, 0x0, 0x0, 0xf, 0x50, 0x0, + 0x0, 0xf, 0x50, 0x0, 0x1, 0x1f, 0x51, 0x10, + 0xef, 0xff, 0xff, 0xf3, 0x34, 0x4f, 0x74, 0x40, + 0x0, 0xf, 0x50, 0x0, 0x0, 0xf, 0x50, 0x0, + + /* U+002D "-" */ + 0x1, 0x11, 0x10, 0x1f, 0xff, 0xf3, 0x4, 0x44, + 0x40, + + /* U+002E "." */ + 0x3, 0x12, 0xfc, 0x1e, 0x90, + + /* U+002F "/" */ + 0x0, 0x0, 0x5, 0xf1, 0x0, 0x0, 0xa, 0xb0, + 0x0, 0x0, 0xf, 0x60, 0x0, 0x0, 0x5f, 0x10, + 0x0, 0x0, 0xab, 0x0, 0x0, 0x0, 0xf6, 0x0, + 0x0, 0x5, 0xf1, 0x0, 0x0, 0xa, 0xb0, 0x0, + 0x0, 0xf, 0x60, 0x0, 0x0, 0x4f, 0x10, 0x0, + 0x0, 0xac, 0x0, 0x0, 0x0, 0xf6, 0x0, 0x0, + 0x4, 0xf1, 0x0, 0x0, 0xa, 0xc0, 0x0, 0x0, + 0xe, 0x60, 0x0, 0x0, 0x4f, 0x10, 0x0, 0x0, + + /* U+0030 "0" */ + 0x0, 0x8, 0xef, 0xc5, 0x0, 0x0, 0xcf, 0xa8, + 0xcf, 0x70, 0x7, 0xf5, 0x0, 0xa, 0xf2, 0xd, + 0xc0, 0x0, 0x1, 0xf8, 0x1f, 0x80, 0x0, 0x0, + 0xdc, 0x3f, 0x60, 0x0, 0x0, 0xbd, 0x3f, 0x60, + 0x0, 0x0, 0xbd, 0x1f, 0x80, 0x0, 0x0, 0xdc, + 0xd, 0xc0, 0x0, 0x1, 0xf8, 0x7, 0xf5, 0x0, + 0xa, 0xf2, 0x0, 0xcf, 0xa8, 0xcf, 0x70, 0x0, + 0x8, 0xef, 0xc5, 0x0, + + /* U+0031 "1" */ + 0xef, 0xff, 0x36, 0x7a, 0xf3, 0x0, 0x5f, 0x30, + 0x5, 0xf3, 0x0, 0x5f, 0x30, 0x5, 0xf3, 0x0, + 0x5f, 0x30, 0x5, 0xf3, 0x0, 0x5f, 0x30, 0x5, + 0xf3, 0x0, 0x5f, 0x30, 0x5, 0xf3, + + /* U+0032 "2" */ + 0x4, 0xbe, 0xfd, 0x70, 0x7, 0xfd, 0x98, 0xcf, + 0x90, 0x28, 0x0, 0x0, 0xbf, 0x0, 0x0, 0x0, + 0x7, 0xf2, 0x0, 0x0, 0x0, 0xaf, 0x0, 0x0, + 0x0, 0x4f, 0x80, 0x0, 0x0, 0x3f, 0xc0, 0x0, + 0x0, 0x3e, 0xc1, 0x0, 0x0, 0x2e, 0xc1, 0x0, + 0x0, 0x2e, 0xd1, 0x0, 0x0, 0x2e, 0xf8, 0x77, + 0x77, 0x46, 0xff, 0xff, 0xff, 0xfa, + + /* U+0033 "3" */ + 0x6f, 0xff, 0xff, 0xff, 0x2, 0x77, 0x77, 0x9f, + 0xb0, 0x0, 0x0, 0xc, 0xe1, 0x0, 0x0, 0x9, + 0xf3, 0x0, 0x0, 0x5, 0xf6, 0x0, 0x0, 0x0, + 0xdf, 0xe9, 0x10, 0x0, 0x4, 0x59, 0xfd, 0x0, + 0x0, 0x0, 0x6, 0xf4, 0x0, 0x0, 0x0, 0x3f, + 0x64, 0x40, 0x0, 0x8, 0xf3, 0xbf, 0xc9, 0x8c, + 0xfb, 0x0, 0x7c, 0xff, 0xd7, 0x0, + + /* U+0034 "4" */ + 0x0, 0x0, 0x1, 0xeb, 0x0, 0x0, 0x0, 0x0, + 0xbe, 0x10, 0x0, 0x0, 0x0, 0x6f, 0x50, 0x0, + 0x0, 0x0, 0x2f, 0x90, 0x0, 0x0, 0x0, 0xc, + 0xd0, 0x0, 0x0, 0x0, 0x8, 0xf3, 0x1, 0xd5, + 0x0, 0x3, 0xf8, 0x0, 0x2f, 0x60, 0x0, 0xed, + 0x22, 0x23, 0xf7, 0x21, 0x6f, 0xff, 0xff, 0xff, + 0xff, 0x81, 0x55, 0x55, 0x56, 0xf9, 0x52, 0x0, + 0x0, 0x0, 0x2f, 0x60, 0x0, 0x0, 0x0, 0x2, + 0xf6, 0x0, + + /* U+0035 "5" */ + 0x5, 0xff, 0xff, 0xff, 0x0, 0x7f, 0x77, 0x77, + 0x70, 0x8, 0xe0, 0x0, 0x0, 0x0, 0xad, 0x0, + 0x0, 0x0, 0xb, 0xc2, 0x10, 0x0, 0x0, 0xdf, + 0xff, 0xfb, 0x30, 0x4, 0x55, 0x68, 0xff, 0x20, + 0x0, 0x0, 0x4, 0xf8, 0x0, 0x0, 0x0, 0xf, + 0x92, 0x50, 0x0, 0x5, 0xf6, 0x8f, 0xd9, 0x8a, + 0xfd, 0x10, 0x5b, 0xef, 0xe9, 0x10, + + /* U+0036 "6" */ + 0x0, 0x5, 0xce, 0xfc, 0x60, 0x0, 0x9f, 0xc8, + 0x8b, 0x70, 0x5, 0xf8, 0x0, 0x0, 0x0, 0xc, + 0xd0, 0x0, 0x0, 0x0, 0x1f, 0x80, 0x0, 0x0, + 0x0, 0x2f, 0x68, 0xef, 0xfa, 0x10, 0x3f, 0xee, + 0x64, 0x8f, 0xd0, 0x2f, 0xf1, 0x0, 0x6, 0xf4, + 0xe, 0xc0, 0x0, 0x2, 0xf6, 0x9, 0xf1, 0x0, + 0x6, 0xf3, 0x1, 0xde, 0x86, 0x9f, 0xb0, 0x0, + 0x19, 0xef, 0xd8, 0x0, + + /* U+0037 "7" */ + 0x8f, 0xff, 0xff, 0xff, 0xe8, 0xf7, 0x77, 0x77, + 0xfc, 0x8f, 0x0, 0x0, 0x4f, 0x55, 0x90, 0x0, + 0xb, 0xe0, 0x0, 0x0, 0x2, 0xf8, 0x0, 0x0, + 0x0, 0x9f, 0x10, 0x0, 0x0, 0xf, 0xb0, 0x0, + 0x0, 0x6, 0xf4, 0x0, 0x0, 0x0, 0xdd, 0x0, + 0x0, 0x0, 0x3f, 0x70, 0x0, 0x0, 0xa, 0xf1, + 0x0, 0x0, 0x1, 0xf9, 0x0, 0x0, + + /* U+0038 "8" */ + 0x0, 0x5c, 0xff, 0xd7, 0x0, 0x6, 0xfc, 0x76, + 0xaf, 0xa0, 0xc, 0xd0, 0x0, 0x9, 0xf1, 0xd, + 0xc0, 0x0, 0x7, 0xf2, 0x7, 0xf7, 0x11, 0x5e, + 0xc0, 0x0, 0xbf, 0xff, 0xfe, 0x10, 0x9, 0xf9, + 0x54, 0x7e, 0xd0, 0x2f, 0x80, 0x0, 0x4, 0xf6, + 0x4f, 0x50, 0x0, 0x0, 0xf8, 0x1f, 0xa0, 0x0, + 0x5, 0xf6, 0x9, 0xfb, 0x76, 0xaf, 0xd0, 0x0, + 0x6c, 0xff, 0xd8, 0x10, + + /* U+0039 "9" */ + 0x0, 0x8e, 0xfd, 0x80, 0x0, 0xc, 0xf8, 0x68, + 0xfc, 0x0, 0x5f, 0x50, 0x0, 0x3f, 0x70, 0x8f, + 0x0, 0x0, 0xe, 0xc0, 0x7f, 0x30, 0x0, 0x1f, + 0xf0, 0x1f, 0xd4, 0x13, 0xcf, 0xf1, 0x4, 0xef, + 0xff, 0xa9, 0xf0, 0x0, 0x2, 0x31, 0xa, 0xf0, + 0x0, 0x0, 0x0, 0xe, 0xa0, 0x0, 0x0, 0x0, + 0x9f, 0x30, 0x9, 0xa7, 0x8d, 0xf7, 0x0, 0x7, + 0xdf, 0xeb, 0x40, 0x0, + + /* U+003A ":" */ + 0x1e, 0x92, 0xfc, 0x3, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x3, 0x12, 0xfc, 0x1e, 0x90, + + /* U+003B ";" */ + 0x1e, 0x92, 0xfc, 0x3, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xe9, 0x1f, 0xd0, 0xa8, 0xe, + 0x30, 0xa0, + + /* U+003C "<" */ + 0x0, 0x0, 0x0, 0x42, 0x0, 0x1, 0x7d, 0xf3, + 0x3, 0x9f, 0xe8, 0x10, 0xbf, 0xb5, 0x0, 0x0, + 0xee, 0x81, 0x0, 0x0, 0x17, 0xdf, 0xb4, 0x0, + 0x0, 0x4, 0xaf, 0xd2, 0x0, 0x0, 0x1, 0x82, + + /* U+003D "=" */ + 0xef, 0xff, 0xff, 0xf3, 0x45, 0x55, 0x55, 0x51, + 0x0, 0x0, 0x0, 0x0, 0x1, 0x11, 0x11, 0x10, + 0xef, 0xff, 0xff, 0xf3, 0x34, 0x44, 0x44, 0x40, + + /* U+003E ">" */ + 0x50, 0x0, 0x0, 0x0, 0xef, 0x92, 0x0, 0x0, + 0x6, 0xcf, 0xb5, 0x0, 0x0, 0x3, 0x9f, 0xe2, + 0x0, 0x0, 0x6c, 0xf3, 0x2, 0x9e, 0xe9, 0x20, + 0xbf, 0xc6, 0x0, 0x0, 0x93, 0x0, 0x0, 0x0, + + /* U+003F "?" */ + 0x4, 0xbe, 0xfd, 0x70, 0x7, 0xfc, 0x77, 0xbf, + 0xa0, 0x27, 0x0, 0x0, 0xcf, 0x0, 0x0, 0x0, + 0x9, 0xf0, 0x0, 0x0, 0x1, 0xea, 0x0, 0x0, + 0x1, 0xdd, 0x10, 0x0, 0x0, 0xce, 0x10, 0x0, + 0x0, 0x3f, 0x60, 0x0, 0x0, 0x1, 0x30, 0x0, + 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x6, 0xf5, + 0x0, 0x0, 0x0, 0x5f, 0x40, 0x0, + + /* U+0040 "@" */ + 0x0, 0x0, 0x17, 0xce, 0xfd, 0xb5, 0x0, 0x0, + 0x0, 0x5, 0xfb, 0x53, 0x23, 0x7d, 0xc2, 0x0, + 0x0, 0x6e, 0x40, 0x0, 0x0, 0x0, 0x8e, 0x10, + 0x2, 0xf4, 0x1, 0xae, 0xfa, 0x3f, 0x49, 0xb0, + 0xa, 0x90, 0x1e, 0xe6, 0x5b, 0xef, 0x40, 0xe3, + 0xf, 0x30, 0x8f, 0x10, 0x0, 0xaf, 0x40, 0x98, + 0x1f, 0x0, 0xd9, 0x0, 0x0, 0x3f, 0x40, 0x6a, + 0x3f, 0x0, 0xe8, 0x0, 0x0, 0x1f, 0x40, 0x5c, + 0x1f, 0x0, 0xd9, 0x0, 0x0, 0x3f, 0x40, 0x6a, + 0xf, 0x30, 0x8f, 0x10, 0x0, 0xaf, 0x40, 0x98, + 0xa, 0x90, 0x1e, 0xd6, 0x5a, 0xde, 0xa6, 0xf2, + 0x3, 0xf3, 0x1, 0xaf, 0xfa, 0x16, 0xee, 0x50, + 0x0, 0x6e, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x6, 0xfb, 0x53, 0x23, 0x75, 0x0, 0x0, + 0x0, 0x0, 0x17, 0xce, 0xfd, 0xa3, 0x0, 0x0, + + /* U+0041 "A" */ + 0x0, 0x0, 0x2, 0xfd, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x9f, 0xf4, 0x0, 0x0, 0x0, 0x0, 0xf, + 0x9e, 0xb0, 0x0, 0x0, 0x0, 0x6, 0xf2, 0x7f, + 0x20, 0x0, 0x0, 0x0, 0xdc, 0x1, 0xf8, 0x0, + 0x0, 0x0, 0x4f, 0x60, 0xb, 0xe0, 0x0, 0x0, + 0xb, 0xf0, 0x0, 0x4f, 0x60, 0x0, 0x1, 0xfa, + 0x11, 0x11, 0xed, 0x0, 0x0, 0x8f, 0xff, 0xff, + 0xff, 0xf3, 0x0, 0xe, 0xc4, 0x44, 0x44, 0x4f, + 0xa0, 0x6, 0xf4, 0x0, 0x0, 0x0, 0xaf, 0x10, + 0xcd, 0x0, 0x0, 0x0, 0x2, 0xf8, + + /* U+0042 "B" */ + 0x5f, 0xff, 0xff, 0xeb, 0x40, 0x5, 0xf8, 0x55, + 0x57, 0xdf, 0x40, 0x5f, 0x40, 0x0, 0x1, 0xfa, + 0x5, 0xf4, 0x0, 0x0, 0xf, 0xa0, 0x5f, 0x51, + 0x11, 0x3a, 0xf4, 0x5, 0xff, 0xff, 0xff, 0xfa, + 0x0, 0x5f, 0x74, 0x44, 0x59, 0xfa, 0x5, 0xf4, + 0x0, 0x0, 0x8, 0xf2, 0x5f, 0x40, 0x0, 0x0, + 0x5f, 0x45, 0xf4, 0x0, 0x0, 0x9, 0xf2, 0x5f, + 0x85, 0x55, 0x6a, 0xfb, 0x5, 0xff, 0xff, 0xff, + 0xd7, 0x0, + + /* U+0043 "C" */ + 0x0, 0x2, 0x8d, 0xfe, 0xb4, 0x0, 0x4, 0xff, + 0xb8, 0x9d, 0xf9, 0x2, 0xfd, 0x20, 0x0, 0x8, + 0x50, 0xbf, 0x20, 0x0, 0x0, 0x0, 0xf, 0xa0, + 0x0, 0x0, 0x0, 0x2, 0xf6, 0x0, 0x0, 0x0, + 0x0, 0x2f, 0x60, 0x0, 0x0, 0x0, 0x0, 0xfa, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0x2f, 0xd2, 0x0, 0x0, 0x85, 0x0, + 0x5f, 0xfb, 0x89, 0xdf, 0x80, 0x0, 0x29, 0xdf, + 0xeb, 0x40, + + /* U+0044 "D" */ + 0x5f, 0xff, 0xff, 0xea, 0x30, 0x0, 0x5f, 0x97, + 0x77, 0x9e, 0xf8, 0x0, 0x5f, 0x40, 0x0, 0x0, + 0xaf, 0x60, 0x5f, 0x40, 0x0, 0x0, 0xd, 0xe0, + 0x5f, 0x40, 0x0, 0x0, 0x6, 0xf4, 0x5f, 0x40, + 0x0, 0x0, 0x3, 0xf6, 0x5f, 0x40, 0x0, 0x0, + 0x3, 0xf6, 0x5f, 0x40, 0x0, 0x0, 0x6, 0xf4, + 0x5f, 0x40, 0x0, 0x0, 0xd, 0xe0, 0x5f, 0x40, + 0x0, 0x0, 0xaf, 0x60, 0x5f, 0x97, 0x77, 0x9e, + 0xf8, 0x0, 0x5f, 0xff, 0xff, 0xea, 0x30, 0x0, + + /* U+0045 "E" */ + 0x5f, 0xff, 0xff, 0xff, 0x95, 0xf9, 0x77, 0x77, + 0x74, 0x5f, 0x40, 0x0, 0x0, 0x5, 0xf4, 0x0, + 0x0, 0x0, 0x5f, 0x51, 0x11, 0x11, 0x5, 0xff, + 0xff, 0xff, 0xe0, 0x5f, 0x74, 0x44, 0x44, 0x5, + 0xf4, 0x0, 0x0, 0x0, 0x5f, 0x40, 0x0, 0x0, + 0x5, 0xf4, 0x0, 0x0, 0x0, 0x5f, 0x97, 0x77, + 0x77, 0x65, 0xff, 0xff, 0xff, 0xfd, + + /* U+0046 "F" */ + 0x5f, 0xff, 0xff, 0xff, 0x95, 0xf9, 0x77, 0x77, + 0x74, 0x5f, 0x40, 0x0, 0x0, 0x5, 0xf4, 0x0, + 0x0, 0x0, 0x5f, 0x40, 0x0, 0x0, 0x5, 0xf5, + 0x22, 0x22, 0x10, 0x5f, 0xff, 0xff, 0xfe, 0x5, + 0xf8, 0x55, 0x55, 0x40, 0x5f, 0x40, 0x0, 0x0, + 0x5, 0xf4, 0x0, 0x0, 0x0, 0x5f, 0x40, 0x0, + 0x0, 0x5, 0xf4, 0x0, 0x0, 0x0, + + /* U+0047 "G" */ + 0x0, 0x1, 0x8d, 0xfe, 0xb5, 0x0, 0x0, 0x4f, + 0xfb, 0x89, 0xdf, 0xb0, 0x2, 0xfd, 0x20, 0x0, + 0x6, 0x60, 0xb, 0xf2, 0x0, 0x0, 0x0, 0x0, + 0xf, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x2f, 0x60, + 0x0, 0x0, 0x0, 0x0, 0x2f, 0x60, 0x0, 0x0, + 0x9, 0xf0, 0xf, 0xa0, 0x0, 0x0, 0x9, 0xf0, + 0xb, 0xf2, 0x0, 0x0, 0x9, 0xf0, 0x2, 0xfd, + 0x20, 0x0, 0xa, 0xf0, 0x0, 0x4f, 0xfb, 0x89, + 0xdf, 0xc0, 0x0, 0x2, 0x8d, 0xfe, 0xc6, 0x0, + + /* U+0048 "H" */ + 0x5f, 0x40, 0x0, 0x0, 0x4f, 0x55, 0xf4, 0x0, + 0x0, 0x4, 0xf5, 0x5f, 0x40, 0x0, 0x0, 0x4f, + 0x55, 0xf4, 0x0, 0x0, 0x4, 0xf5, 0x5f, 0x52, + 0x22, 0x22, 0x5f, 0x55, 0xff, 0xff, 0xff, 0xff, + 0xf5, 0x5f, 0x85, 0x55, 0x55, 0x8f, 0x55, 0xf4, + 0x0, 0x0, 0x4, 0xf5, 0x5f, 0x40, 0x0, 0x0, + 0x4f, 0x55, 0xf4, 0x0, 0x0, 0x4, 0xf5, 0x5f, + 0x40, 0x0, 0x0, 0x4f, 0x55, 0xf4, 0x0, 0x0, + 0x4, 0xf5, + + /* U+0049 "I" */ + 0x5f, 0x45, 0xf4, 0x5f, 0x45, 0xf4, 0x5f, 0x45, + 0xf4, 0x5f, 0x45, 0xf4, 0x5f, 0x45, 0xf4, 0x5f, + 0x45, 0xf4, + + /* U+004A "J" */ + 0x0, 0xff, 0xff, 0xfa, 0x0, 0x77, 0x77, 0xfa, + 0x0, 0x0, 0x0, 0xfa, 0x0, 0x0, 0x0, 0xfa, + 0x0, 0x0, 0x0, 0xfa, 0x0, 0x0, 0x0, 0xfa, + 0x0, 0x0, 0x0, 0xfa, 0x0, 0x0, 0x0, 0xfa, + 0x0, 0x0, 0x0, 0xf9, 0x7, 0x20, 0x3, 0xf6, + 0xd, 0xe9, 0x8e, 0xf1, 0x1, 0xae, 0xfb, 0x30, + + /* U+004B "K" */ + 0x5f, 0x40, 0x0, 0x2, 0xeb, 0x5, 0xf4, 0x0, + 0x1, 0xec, 0x0, 0x5f, 0x40, 0x1, 0xde, 0x10, + 0x5, 0xf4, 0x0, 0xce, 0x20, 0x0, 0x5f, 0x40, + 0xbf, 0x30, 0x0, 0x5, 0xf4, 0x9f, 0x90, 0x0, + 0x0, 0x5f, 0xcf, 0xef, 0x40, 0x0, 0x5, 0xff, + 0x91, 0xee, 0x10, 0x0, 0x5f, 0xa0, 0x3, 0xfc, + 0x0, 0x5, 0xf4, 0x0, 0x6, 0xf8, 0x0, 0x5f, + 0x40, 0x0, 0x9, 0xf5, 0x5, 0xf4, 0x0, 0x0, + 0xc, 0xf2, + + /* U+004C "L" */ + 0x5f, 0x40, 0x0, 0x0, 0x5, 0xf4, 0x0, 0x0, + 0x0, 0x5f, 0x40, 0x0, 0x0, 0x5, 0xf4, 0x0, + 0x0, 0x0, 0x5f, 0x40, 0x0, 0x0, 0x5, 0xf4, + 0x0, 0x0, 0x0, 0x5f, 0x40, 0x0, 0x0, 0x5, + 0xf4, 0x0, 0x0, 0x0, 0x5f, 0x40, 0x0, 0x0, + 0x5, 0xf4, 0x0, 0x0, 0x0, 0x5f, 0x97, 0x77, + 0x77, 0x25, 0xff, 0xff, 0xff, 0xf5, + + /* U+004D "M" */ + 0x5f, 0x40, 0x0, 0x0, 0x0, 0x1e, 0x95, 0xfc, + 0x0, 0x0, 0x0, 0x8, 0xf9, 0x5f, 0xf5, 0x0, + 0x0, 0x2, 0xff, 0x95, 0xfd, 0xe0, 0x0, 0x0, + 0xae, 0xf9, 0x5f, 0x5f, 0x70, 0x0, 0x3f, 0x5f, + 0x95, 0xf3, 0x8f, 0x10, 0xb, 0xc0, 0xf9, 0x5f, + 0x31, 0xe9, 0x4, 0xf3, 0xf, 0x95, 0xf3, 0x7, + 0xf2, 0xdb, 0x0, 0xf9, 0x5f, 0x30, 0xd, 0xef, + 0x20, 0xf, 0x95, 0xf3, 0x0, 0x5f, 0x90, 0x0, + 0xf9, 0x5f, 0x30, 0x0, 0x71, 0x0, 0xf, 0x95, + 0xf3, 0x0, 0x0, 0x0, 0x0, 0xf9, + + /* U+004E "N" */ + 0x5f, 0x50, 0x0, 0x0, 0x4f, 0x55, 0xff, 0x20, + 0x0, 0x4, 0xf5, 0x5f, 0xfd, 0x0, 0x0, 0x4f, + 0x55, 0xfa, 0xf9, 0x0, 0x4, 0xf5, 0x5f, 0x4a, + 0xf5, 0x0, 0x4f, 0x55, 0xf4, 0xd, 0xf2, 0x4, + 0xf5, 0x5f, 0x40, 0x2f, 0xd0, 0x4f, 0x55, 0xf4, + 0x0, 0x6f, 0x94, 0xf5, 0x5f, 0x40, 0x0, 0xaf, + 0xaf, 0x55, 0xf4, 0x0, 0x0, 0xdf, 0xf5, 0x5f, + 0x40, 0x0, 0x2, 0xff, 0x55, 0xf4, 0x0, 0x0, + 0x6, 0xf5, + + /* U+004F "O" */ + 0x0, 0x1, 0x8d, 0xfe, 0xb5, 0x0, 0x0, 0x4, + 0xff, 0xb8, 0x9e, 0xfa, 0x0, 0x2, 0xfd, 0x20, + 0x0, 0x8, 0xf9, 0x0, 0xbf, 0x20, 0x0, 0x0, + 0xa, 0xf2, 0xf, 0xa0, 0x0, 0x0, 0x0, 0x3f, + 0x72, 0xf6, 0x0, 0x0, 0x0, 0x0, 0xf9, 0x2f, + 0x60, 0x0, 0x0, 0x0, 0xf, 0x90, 0xfa, 0x0, + 0x0, 0x0, 0x3, 0xf7, 0xb, 0xf2, 0x0, 0x0, + 0x0, 0xaf, 0x20, 0x2f, 0xd2, 0x0, 0x0, 0x8f, + 0x90, 0x0, 0x4f, 0xfb, 0x89, 0xef, 0xa0, 0x0, + 0x0, 0x28, 0xdf, 0xeb, 0x50, 0x0, + + /* U+0050 "P" */ + 0x5f, 0xff, 0xff, 0xd7, 0x0, 0x5f, 0x97, 0x78, + 0xbf, 0xc0, 0x5f, 0x40, 0x0, 0x7, 0xf6, 0x5f, + 0x40, 0x0, 0x0, 0xfa, 0x5f, 0x40, 0x0, 0x0, + 0xfa, 0x5f, 0x40, 0x0, 0x3, 0xf8, 0x5f, 0x62, + 0x23, 0x6e, 0xf1, 0x5f, 0xff, 0xff, 0xfd, 0x30, + 0x5f, 0x85, 0x54, 0x20, 0x0, 0x5f, 0x40, 0x0, + 0x0, 0x0, 0x5f, 0x40, 0x0, 0x0, 0x0, 0x5f, + 0x40, 0x0, 0x0, 0x0, + + /* U+0051 "Q" */ + 0x0, 0x1, 0x8d, 0xfe, 0xb5, 0x0, 0x0, 0x0, + 0x4e, 0xfb, 0x89, 0xef, 0xa0, 0x0, 0x2, 0xfd, + 0x20, 0x0, 0x8, 0xf9, 0x0, 0xa, 0xf2, 0x0, + 0x0, 0x0, 0xaf, 0x20, 0xf, 0xa0, 0x0, 0x0, + 0x0, 0x3f, 0x70, 0x2f, 0x60, 0x0, 0x0, 0x0, + 0xf, 0x90, 0x2f, 0x60, 0x0, 0x0, 0x0, 0xf, + 0x90, 0x1f, 0x90, 0x0, 0x0, 0x0, 0x2f, 0x70, + 0xb, 0xf1, 0x0, 0x0, 0x0, 0xaf, 0x20, 0x3, + 0xfc, 0x10, 0x0, 0x7, 0xf9, 0x0, 0x0, 0x6f, + 0xfa, 0x78, 0xdf, 0xb0, 0x0, 0x0, 0x3, 0xae, + 0xff, 0xc5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3e, + 0xd4, 0x15, 0xb0, 0x0, 0x0, 0x0, 0x2, 0xbf, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x1, 0x31, + 0x0, + + /* U+0052 "R" */ + 0x5f, 0xff, 0xff, 0xd7, 0x0, 0x5f, 0x97, 0x78, + 0xbf, 0xc0, 0x5f, 0x40, 0x0, 0x7, 0xf6, 0x5f, + 0x40, 0x0, 0x0, 0xfa, 0x5f, 0x40, 0x0, 0x0, + 0xfa, 0x5f, 0x40, 0x0, 0x3, 0xf8, 0x5f, 0x52, + 0x23, 0x6e, 0xe1, 0x5f, 0xff, 0xff, 0xfc, 0x30, + 0x5f, 0x85, 0x55, 0xf9, 0x0, 0x5f, 0x40, 0x0, + 0x7f, 0x40, 0x5f, 0x40, 0x0, 0xc, 0xe0, 0x5f, + 0x40, 0x0, 0x2, 0xf9, + + /* U+0053 "S" */ + 0x0, 0x5c, 0xef, 0xd9, 0x20, 0x7, 0xfc, 0x87, + 0xaf, 0x90, 0xe, 0xc0, 0x0, 0x1, 0x10, 0xf, + 0x80, 0x0, 0x0, 0x0, 0xd, 0xf5, 0x0, 0x0, + 0x0, 0x3, 0xef, 0xea, 0x50, 0x0, 0x0, 0x5, + 0xae, 0xfe, 0x40, 0x0, 0x0, 0x0, 0x4e, 0xf1, + 0x0, 0x0, 0x0, 0x5, 0xf3, 0x8, 0x0, 0x0, + 0x8, 0xf2, 0x2f, 0xfa, 0x77, 0xbf, 0xa0, 0x2, + 0x9d, 0xff, 0xc7, 0x0, + + /* U+0054 "T" */ + 0xff, 0xff, 0xff, 0xff, 0xf5, 0x67, 0x78, 0xfb, + 0x77, 0x72, 0x0, 0x1, 0xf7, 0x0, 0x0, 0x0, + 0x1, 0xf7, 0x0, 0x0, 0x0, 0x1, 0xf7, 0x0, + 0x0, 0x0, 0x1, 0xf7, 0x0, 0x0, 0x0, 0x1, + 0xf7, 0x0, 0x0, 0x0, 0x1, 0xf7, 0x0, 0x0, + 0x0, 0x1, 0xf7, 0x0, 0x0, 0x0, 0x1, 0xf7, + 0x0, 0x0, 0x0, 0x1, 0xf7, 0x0, 0x0, 0x0, + 0x1, 0xf7, 0x0, 0x0, + + /* U+0055 "U" */ + 0x6f, 0x30, 0x0, 0x0, 0x8f, 0x16, 0xf3, 0x0, + 0x0, 0x8, 0xf1, 0x6f, 0x30, 0x0, 0x0, 0x8f, + 0x16, 0xf3, 0x0, 0x0, 0x8, 0xf1, 0x6f, 0x30, + 0x0, 0x0, 0x8f, 0x16, 0xf3, 0x0, 0x0, 0x8, + 0xf1, 0x6f, 0x30, 0x0, 0x0, 0x8f, 0x5, 0xf4, + 0x0, 0x0, 0x9, 0xf0, 0x3f, 0x70, 0x0, 0x0, + 0xcd, 0x0, 0xde, 0x20, 0x0, 0x5f, 0x80, 0x4, + 0xff, 0xa8, 0xbf, 0xd0, 0x0, 0x3, 0xbe, 0xfd, + 0x81, 0x0, + + /* U+0056 "V" */ + 0xc, 0xe0, 0x0, 0x0, 0x0, 0x6f, 0x30, 0x6f, + 0x50, 0x0, 0x0, 0xc, 0xc0, 0x0, 0xfb, 0x0, + 0x0, 0x3, 0xf6, 0x0, 0x9, 0xf2, 0x0, 0x0, + 0xae, 0x0, 0x0, 0x2f, 0x80, 0x0, 0x1f, 0x90, + 0x0, 0x0, 0xce, 0x0, 0x7, 0xf2, 0x0, 0x0, + 0x5, 0xf6, 0x0, 0xdb, 0x0, 0x0, 0x0, 0xe, + 0xc0, 0x4f, 0x50, 0x0, 0x0, 0x0, 0x8f, 0x3b, + 0xe0, 0x0, 0x0, 0x0, 0x2, 0xfb, 0xf8, 0x0, + 0x0, 0x0, 0x0, 0xb, 0xff, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x4f, 0xb0, 0x0, 0x0, + + /* U+0057 "W" */ + 0x5f, 0x40, 0x0, 0x0, 0xdf, 0x0, 0x0, 0x2, + 0xf5, 0xf, 0x90, 0x0, 0x2, 0xff, 0x40, 0x0, + 0x7, 0xf0, 0xb, 0xe0, 0x0, 0x7, 0xfe, 0x90, + 0x0, 0xc, 0xb0, 0x6, 0xf3, 0x0, 0xc, 0xaa, + 0xe0, 0x0, 0x1f, 0x60, 0x1, 0xf8, 0x0, 0x1f, + 0x54, 0xf3, 0x0, 0x6f, 0x10, 0x0, 0xcd, 0x0, + 0x7f, 0x10, 0xf8, 0x0, 0xcc, 0x0, 0x0, 0x7f, + 0x20, 0xcb, 0x0, 0xad, 0x1, 0xf7, 0x0, 0x0, + 0x2f, 0x71, 0xf6, 0x0, 0x5f, 0x26, 0xf2, 0x0, + 0x0, 0xd, 0xc6, 0xf1, 0x0, 0xf, 0x7b, 0xd0, + 0x0, 0x0, 0x8, 0xfd, 0xc0, 0x0, 0xb, 0xdf, + 0x80, 0x0, 0x0, 0x3, 0xff, 0x70, 0x0, 0x6, + 0xff, 0x30, 0x0, 0x0, 0x0, 0xef, 0x20, 0x0, + 0x1, 0xfe, 0x0, 0x0, + + /* U+0058 "X" */ + 0x3f, 0x90, 0x0, 0x0, 0xcd, 0x0, 0x8f, 0x40, + 0x0, 0x7f, 0x30, 0x0, 0xde, 0x10, 0x2f, 0x80, + 0x0, 0x3, 0xfa, 0xc, 0xd0, 0x0, 0x0, 0x7, + 0xfb, 0xf3, 0x0, 0x0, 0x0, 0xc, 0xf8, 0x0, + 0x0, 0x0, 0x1, 0xef, 0xc0, 0x0, 0x0, 0x0, + 0xbf, 0x7f, 0x70, 0x0, 0x0, 0x6f, 0x60, 0xaf, + 0x20, 0x0, 0x2f, 0xb0, 0x1, 0xed, 0x0, 0xc, + 0xf1, 0x0, 0x4, 0xf8, 0x7, 0xf6, 0x0, 0x0, + 0x9, 0xf3, + + /* U+0059 "Y" */ + 0xc, 0xe0, 0x0, 0x0, 0x7, 0xf2, 0x3, 0xf7, + 0x0, 0x0, 0x1f, 0x90, 0x0, 0xaf, 0x10, 0x0, + 0x9e, 0x10, 0x0, 0x1f, 0xa0, 0x2, 0xf6, 0x0, + 0x0, 0x8, 0xf3, 0xb, 0xd0, 0x0, 0x0, 0x0, + 0xec, 0x4f, 0x40, 0x0, 0x0, 0x0, 0x5f, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0xc, 0xf2, 0x0, 0x0, + 0x0, 0x0, 0x9, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x9, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0x9, 0xf0, 0x0, 0x0, + + /* U+005A "Z" */ + 0x3f, 0xff, 0xff, 0xff, 0xfd, 0x1, 0x77, 0x77, + 0x77, 0xbf, 0x90, 0x0, 0x0, 0x0, 0x1e, 0xc0, + 0x0, 0x0, 0x0, 0xc, 0xf2, 0x0, 0x0, 0x0, + 0x8, 0xf5, 0x0, 0x0, 0x0, 0x4, 0xf9, 0x0, + 0x0, 0x0, 0x1, 0xec, 0x0, 0x0, 0x0, 0x0, + 0xcf, 0x20, 0x0, 0x0, 0x0, 0x8f, 0x50, 0x0, + 0x0, 0x0, 0x4f, 0x90, 0x0, 0x0, 0x0, 0x1e, + 0xf8, 0x77, 0x77, 0x77, 0x5, 0xff, 0xff, 0xff, + 0xff, 0xf0, + + /* U+005B "[" */ + 0x5f, 0xff, 0x5, 0xf7, 0x50, 0x5f, 0x30, 0x5, + 0xf3, 0x0, 0x5f, 0x30, 0x5, 0xf3, 0x0, 0x5f, + 0x30, 0x5, 0xf3, 0x0, 0x5f, 0x30, 0x5, 0xf3, + 0x0, 0x5f, 0x30, 0x5, 0xf3, 0x0, 0x5f, 0x30, + 0x5, 0xf7, 0x50, 0x5f, 0xff, 0x0, + + /* U+005C "\\" */ + 0x7e, 0x0, 0x0, 0x0, 0x1f, 0x40, 0x0, 0x0, + 0xc, 0x90, 0x0, 0x0, 0x7, 0xe0, 0x0, 0x0, + 0x2, 0xf4, 0x0, 0x0, 0x0, 0xc9, 0x0, 0x0, + 0x0, 0x7e, 0x0, 0x0, 0x0, 0x2f, 0x40, 0x0, + 0x0, 0xc, 0x90, 0x0, 0x0, 0x7, 0xe0, 0x0, + 0x0, 0x2, 0xf3, 0x0, 0x0, 0x0, 0xd9, 0x0, + 0x0, 0x0, 0x7e, 0x0, 0x0, 0x0, 0x2f, 0x30, + 0x0, 0x0, 0xd, 0x90, 0x0, 0x0, 0x7, 0xe0, + + /* U+005D "]" */ + 0xbf, 0xfa, 0x35, 0xea, 0x0, 0xea, 0x0, 0xea, + 0x0, 0xea, 0x0, 0xea, 0x0, 0xea, 0x0, 0xea, + 0x0, 0xea, 0x0, 0xea, 0x0, 0xea, 0x0, 0xea, + 0x0, 0xea, 0x35, 0xea, 0xbf, 0xfa, + + /* U+005E "^" */ + 0x0, 0x2f, 0x80, 0x0, 0x0, 0x9d, 0xe0, 0x0, + 0x0, 0xf3, 0xd5, 0x0, 0x6, 0xd0, 0x7b, 0x0, + 0xc, 0x60, 0x1f, 0x20, 0x3f, 0x10, 0xb, 0x80, + 0x9a, 0x0, 0x4, 0xe0, + + /* U+005F "_" */ + 0xff, 0xff, 0xff, 0xff, 0x11, 0x11, 0x11, 0x11, + + /* U+0060 "`" */ + 0x7, 0xf6, 0x0, 0x3, 0xe7, + + /* U+0061 "a" */ + 0x1, 0x9e, 0xfd, 0x80, 0x0, 0xce, 0x87, 0xaf, + 0x90, 0x2, 0x0, 0x0, 0xaf, 0x0, 0x0, 0x0, + 0x6, 0xf2, 0x2, 0xbe, 0xff, 0xff, 0x20, 0xec, + 0x42, 0x27, 0xf2, 0x2f, 0x50, 0x0, 0x7f, 0x20, + 0xec, 0x42, 0x7f, 0xf2, 0x2, 0xbf, 0xfb, 0x6f, + 0x20, + + /* U+0062 "b" */ + 0x8f, 0x0, 0x0, 0x0, 0x0, 0x8f, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0x2b, 0xfe, 0xb3, 0x0, 0x8f, 0xec, 0x78, 0xef, + 0x30, 0x8f, 0xa0, 0x0, 0x1e, 0xc0, 0x8f, 0x20, + 0x0, 0x7, 0xf1, 0x8f, 0x0, 0x0, 0x5, 0xf3, + 0x8f, 0x20, 0x0, 0x7, 0xf1, 0x8f, 0xa0, 0x0, + 0x1e, 0xd0, 0x8f, 0xec, 0x78, 0xef, 0x30, 0x8e, + 0x2b, 0xfe, 0xb3, 0x0, + + /* U+0063 "c" */ + 0x0, 0x3a, 0xef, 0xc4, 0x0, 0x4f, 0xd8, 0x7c, + 0xf4, 0xd, 0xd0, 0x0, 0x7, 0x13, 0xf6, 0x0, + 0x0, 0x0, 0x4f, 0x30, 0x0, 0x0, 0x3, 0xf6, + 0x0, 0x0, 0x0, 0xd, 0xd0, 0x0, 0x6, 0x10, + 0x4f, 0xd7, 0x7c, 0xf4, 0x0, 0x3a, 0xef, 0xc4, + 0x0, + + /* U+0064 "d" */ + 0x0, 0x0, 0x0, 0x1, 0xf7, 0x0, 0x0, 0x0, + 0x1, 0xf7, 0x0, 0x0, 0x0, 0x1, 0xf7, 0x0, + 0x3b, 0xff, 0xa3, 0xf7, 0x4, 0xfd, 0x87, 0xce, + 0xf7, 0xe, 0xd0, 0x0, 0xb, 0xf7, 0x3f, 0x60, + 0x0, 0x3, 0xf7, 0x4f, 0x30, 0x0, 0x1, 0xf7, + 0x3f, 0x50, 0x0, 0x3, 0xf7, 0xe, 0xc0, 0x0, + 0xa, 0xf7, 0x4, 0xfc, 0x65, 0xbe, 0xf7, 0x0, + 0x3b, 0xff, 0xb2, 0xf7, + + /* U+0065 "e" */ + 0x0, 0x3b, 0xfe, 0xa2, 0x0, 0x4, 0xfc, 0x67, + 0xee, 0x20, 0xe, 0xc0, 0x0, 0x1e, 0xa0, 0x3f, + 0x50, 0x0, 0x7, 0xf0, 0x4f, 0xff, 0xff, 0xff, + 0xf1, 0x3f, 0x72, 0x22, 0x22, 0x20, 0xe, 0xc0, + 0x0, 0x2, 0x0, 0x4, 0xfd, 0x87, 0xaf, 0x50, + 0x0, 0x3a, 0xef, 0xd6, 0x0, + + /* U+0066 "f" */ + 0x0, 0x5d, 0xfc, 0x0, 0x2f, 0xb5, 0x70, 0x4, + 0xf3, 0x0, 0xc, 0xff, 0xff, 0xa0, 0x48, 0xf7, + 0x53, 0x0, 0x5f, 0x30, 0x0, 0x5, 0xf3, 0x0, + 0x0, 0x5f, 0x30, 0x0, 0x5, 0xf3, 0x0, 0x0, + 0x5f, 0x30, 0x0, 0x5, 0xf3, 0x0, 0x0, 0x5f, + 0x30, 0x0, + + /* U+0067 "g" */ + 0x0, 0x3b, 0xff, 0xb2, 0xe9, 0x4, 0xfe, 0x87, + 0xcf, 0xf9, 0xe, 0xd1, 0x0, 0xa, 0xf9, 0x3f, + 0x60, 0x0, 0x1, 0xf9, 0x4f, 0x40, 0x0, 0x0, + 0xf9, 0x3f, 0x60, 0x0, 0x1, 0xf9, 0xe, 0xd0, + 0x0, 0x9, 0xf9, 0x4, 0xfd, 0x87, 0xcf, 0xf8, + 0x0, 0x3b, 0xff, 0xb3, 0xf7, 0x0, 0x0, 0x0, + 0x5, 0xf4, 0x9, 0xe9, 0x77, 0xaf, 0xb0, 0x1, + 0x7c, 0xff, 0xd8, 0x0, + + /* U+0068 "h" */ + 0x8f, 0x0, 0x0, 0x0, 0x8, 0xf0, 0x0, 0x0, + 0x0, 0x8f, 0x0, 0x0, 0x0, 0x8, 0xf2, 0xbf, + 0xea, 0x10, 0x8f, 0xfb, 0x89, 0xfd, 0x8, 0xf8, + 0x0, 0x6, 0xf4, 0x8f, 0x10, 0x0, 0x1f, 0x78, + 0xf0, 0x0, 0x0, 0xf8, 0x8f, 0x0, 0x0, 0xf, + 0x88, 0xf0, 0x0, 0x0, 0xf8, 0x8f, 0x0, 0x0, + 0xf, 0x88, 0xf0, 0x0, 0x0, 0xf8, + + /* U+0069 "i" */ + 0x9e, 0x1a, 0xf2, 0x0, 0x8, 0xf0, 0x8f, 0x8, + 0xf0, 0x8f, 0x8, 0xf0, 0x8f, 0x8, 0xf0, 0x8f, + 0x8, 0xf0, + + /* U+006A "j" */ + 0x0, 0x7, 0xe2, 0x0, 0x9, 0xf3, 0x0, 0x0, + 0x0, 0x0, 0x7, 0xf1, 0x0, 0x7, 0xf1, 0x0, + 0x7, 0xf1, 0x0, 0x7, 0xf1, 0x0, 0x7, 0xf1, + 0x0, 0x7, 0xf1, 0x0, 0x7, 0xf1, 0x0, 0x7, + 0xf1, 0x0, 0x7, 0xf1, 0x0, 0x8, 0xf0, 0x18, + 0x6e, 0xc0, 0x3e, 0xfc, 0x20, + + /* U+006B "k" */ + 0x8f, 0x0, 0x0, 0x0, 0x8, 0xf0, 0x0, 0x0, + 0x0, 0x8f, 0x0, 0x0, 0x0, 0x8, 0xf0, 0x0, + 0x1d, 0xd1, 0x8f, 0x0, 0x1d, 0xe2, 0x8, 0xf0, + 0x1d, 0xe2, 0x0, 0x8f, 0x2d, 0xf3, 0x0, 0x8, + 0xfe, 0xff, 0x70, 0x0, 0x8f, 0xe2, 0xbf, 0x30, + 0x8, 0xf2, 0x1, 0xee, 0x10, 0x8f, 0x0, 0x3, + 0xfb, 0x8, 0xf0, 0x0, 0x7, 0xf7, + + /* U+006C "l" */ + 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, + 0x8f, 0x8f, 0x8f, 0x8f, + + /* U+006D "m" */ + 0x8e, 0x3c, 0xfe, 0x91, 0x3b, 0xfe, 0xa2, 0x8, + 0xff, 0x96, 0x9f, 0xcf, 0xc6, 0x8f, 0xd0, 0x8f, + 0x70, 0x0, 0x9f, 0xc0, 0x0, 0x5f, 0x58, 0xf1, + 0x0, 0x5, 0xf6, 0x0, 0x1, 0xf7, 0x8f, 0x0, + 0x0, 0x4f, 0x40, 0x0, 0xf, 0x88, 0xf0, 0x0, + 0x4, 0xf4, 0x0, 0x0, 0xf8, 0x8f, 0x0, 0x0, + 0x4f, 0x40, 0x0, 0xf, 0x88, 0xf0, 0x0, 0x4, + 0xf4, 0x0, 0x0, 0xf8, 0x8f, 0x0, 0x0, 0x4f, + 0x40, 0x0, 0xf, 0x80, + + /* U+006E "n" */ + 0x8e, 0x3b, 0xfe, 0xa1, 0x8, 0xff, 0xa6, 0x8f, + 0xd0, 0x8f, 0x80, 0x0, 0x6f, 0x48, 0xf1, 0x0, + 0x1, 0xf7, 0x8f, 0x0, 0x0, 0xf, 0x88, 0xf0, + 0x0, 0x0, 0xf8, 0x8f, 0x0, 0x0, 0xf, 0x88, + 0xf0, 0x0, 0x0, 0xf8, 0x8f, 0x0, 0x0, 0xf, + 0x80, + + /* U+006F "o" */ + 0x0, 0x3b, 0xef, 0xc4, 0x0, 0x4, 0xfd, 0x87, + 0xcf, 0x60, 0xe, 0xd0, 0x0, 0xb, 0xf1, 0x3f, + 0x60, 0x0, 0x3, 0xf5, 0x4f, 0x30, 0x0, 0x1, + 0xf7, 0x3f, 0x60, 0x0, 0x3, 0xf5, 0xe, 0xd0, + 0x0, 0xb, 0xf1, 0x4, 0xfd, 0x77, 0xcf, 0x60, + 0x0, 0x3b, 0xef, 0xc4, 0x0, + + /* U+0070 "p" */ + 0x8e, 0x3b, 0xfe, 0xb3, 0x0, 0x8f, 0xfb, 0x57, + 0xdf, 0x30, 0x8f, 0x90, 0x0, 0xd, 0xc0, 0x8f, + 0x10, 0x0, 0x7, 0xf1, 0x8f, 0x0, 0x0, 0x5, + 0xf3, 0x8f, 0x20, 0x0, 0x7, 0xf1, 0x8f, 0xa0, + 0x0, 0x1e, 0xd0, 0x8f, 0xec, 0x78, 0xef, 0x30, + 0x8f, 0x2b, 0xfe, 0xb3, 0x0, 0x8f, 0x0, 0x0, + 0x0, 0x0, 0x8f, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0x0, 0x0, 0x0, 0x0, + + /* U+0071 "q" */ + 0x0, 0x3b, 0xff, 0xa2, 0xf7, 0x4, 0xfd, 0x87, + 0xde, 0xf7, 0xe, 0xd0, 0x0, 0xb, 0xf7, 0x3f, + 0x60, 0x0, 0x3, 0xf7, 0x4f, 0x30, 0x0, 0x1, + 0xf7, 0x3f, 0x60, 0x0, 0x3, 0xf7, 0xe, 0xd0, + 0x0, 0xb, 0xf7, 0x4, 0xfd, 0x77, 0xce, 0xf7, + 0x0, 0x3b, 0xff, 0xa3, 0xf7, 0x0, 0x0, 0x0, + 0x1, 0xf7, 0x0, 0x0, 0x0, 0x1, 0xf7, 0x0, + 0x0, 0x0, 0x1, 0xf7, + + /* U+0072 "r" */ + 0x8e, 0x2b, 0xf0, 0x8f, 0xed, 0x90, 0x8f, 0xa0, + 0x0, 0x8f, 0x20, 0x0, 0x8f, 0x0, 0x0, 0x8f, + 0x0, 0x0, 0x8f, 0x0, 0x0, 0x8f, 0x0, 0x0, + 0x8f, 0x0, 0x0, + + /* U+0073 "s" */ + 0x2, 0xae, 0xfd, 0x91, 0x1e, 0xd7, 0x69, 0xd0, + 0x4f, 0x30, 0x0, 0x0, 0x2f, 0xb4, 0x10, 0x0, + 0x6, 0xef, 0xfd, 0x60, 0x0, 0x1, 0x5b, 0xf5, + 0x1, 0x0, 0x0, 0xf7, 0x5f, 0xa7, 0x6b, 0xf3, + 0x19, 0xdf, 0xec, 0x40, + + /* U+0074 "t" */ + 0x5, 0xf3, 0x0, 0x0, 0x5f, 0x30, 0x0, 0xcf, + 0xff, 0xfa, 0x4, 0x8f, 0x75, 0x30, 0x5, 0xf3, + 0x0, 0x0, 0x5f, 0x30, 0x0, 0x5, 0xf3, 0x0, + 0x0, 0x5f, 0x30, 0x0, 0x4, 0xf4, 0x0, 0x0, + 0x1f, 0xc6, 0x80, 0x0, 0x5d, 0xfc, 0x10, + + /* U+0075 "u" */ + 0xae, 0x0, 0x0, 0x2f, 0x5a, 0xe0, 0x0, 0x2, + 0xf5, 0xae, 0x0, 0x0, 0x2f, 0x5a, 0xe0, 0x0, + 0x2, 0xf5, 0xae, 0x0, 0x0, 0x2f, 0x59, 0xf0, + 0x0, 0x4, 0xf5, 0x6f, 0x30, 0x0, 0xaf, 0x51, + 0xee, 0x76, 0xbf, 0xf5, 0x2, 0xbe, 0xfb, 0x3f, + 0x50, + + /* U+0076 "v" */ + 0xd, 0xc0, 0x0, 0x0, 0xcb, 0x6, 0xf2, 0x0, + 0x2, 0xf5, 0x0, 0xf9, 0x0, 0x9, 0xe0, 0x0, + 0x9e, 0x0, 0xf, 0x80, 0x0, 0x2f, 0x60, 0x6f, + 0x10, 0x0, 0xc, 0xc0, 0xcb, 0x0, 0x0, 0x5, + 0xf6, 0xf4, 0x0, 0x0, 0x0, 0xef, 0xd0, 0x0, + 0x0, 0x0, 0x8f, 0x70, 0x0, + + /* U+0077 "w" */ + 0xbb, 0x0, 0x0, 0x9f, 0x10, 0x0, 0x4f, 0x16, + 0xf1, 0x0, 0xe, 0xf6, 0x0, 0x9, 0xc0, 0xf, + 0x60, 0x5, 0xfc, 0xb0, 0x0, 0xf6, 0x0, 0xac, + 0x0, 0xab, 0x5f, 0x10, 0x5f, 0x10, 0x5, 0xf1, + 0xf, 0x50, 0xf7, 0xa, 0xb0, 0x0, 0xf, 0x76, + 0xf0, 0x9, 0xc0, 0xf5, 0x0, 0x0, 0xac, 0xba, + 0x0, 0x4f, 0x8f, 0x0, 0x0, 0x4, 0xff, 0x40, + 0x0, 0xef, 0xa0, 0x0, 0x0, 0xe, 0xe0, 0x0, + 0x8, 0xf4, 0x0, 0x0, + + /* U+0078 "x" */ + 0x4f, 0x70, 0x0, 0x9f, 0x20, 0x8f, 0x30, 0x5f, + 0x50, 0x0, 0xcd, 0x2e, 0x90, 0x0, 0x2, 0xff, + 0xd0, 0x0, 0x0, 0xa, 0xf6, 0x0, 0x0, 0x4, + 0xfd, 0xe1, 0x0, 0x1, 0xeb, 0xd, 0xc0, 0x0, + 0xbe, 0x10, 0x3f, 0x80, 0x6f, 0x40, 0x0, 0x7f, + 0x40, + + /* U+0079 "y" */ + 0xd, 0xc0, 0x0, 0x0, 0xcb, 0x6, 0xf3, 0x0, + 0x2, 0xf4, 0x0, 0xea, 0x0, 0x9, 0xd0, 0x0, + 0x8f, 0x10, 0x1f, 0x70, 0x0, 0x1f, 0x70, 0x7f, + 0x10, 0x0, 0xa, 0xe0, 0xd9, 0x0, 0x0, 0x3, + 0xf9, 0xf2, 0x0, 0x0, 0x0, 0xcf, 0xb0, 0x0, + 0x0, 0x0, 0x6f, 0x40, 0x0, 0x0, 0x0, 0xad, + 0x0, 0x0, 0x1c, 0x79, 0xf5, 0x0, 0x0, 0x1a, + 0xee, 0x70, 0x0, 0x0, + + /* U+007A "z" */ + 0x4f, 0xff, 0xff, 0xf9, 0x15, 0x55, 0x5b, 0xf4, + 0x0, 0x0, 0x4f, 0x80, 0x0, 0x1, 0xec, 0x0, + 0x0, 0xb, 0xe1, 0x0, 0x0, 0x8f, 0x40, 0x0, + 0x4, 0xf7, 0x0, 0x0, 0x1e, 0xe5, 0x55, 0x53, + 0x5f, 0xff, 0xff, 0xfc, + + /* U+007B "{" */ + 0x0, 0x2c, 0xf5, 0x0, 0xaf, 0x61, 0x0, 0xcc, + 0x0, 0x0, 0xdb, 0x0, 0x0, 0xdb, 0x0, 0x0, + 0xdb, 0x0, 0x2, 0xea, 0x0, 0x1f, 0xf4, 0x0, + 0x5, 0xfa, 0x0, 0x0, 0xdb, 0x0, 0x0, 0xdb, + 0x0, 0x0, 0xdb, 0x0, 0x0, 0xcc, 0x0, 0x0, + 0xaf, 0x61, 0x0, 0x2c, 0xf5, + + /* U+007C "|" */ + 0x5f, 0x15, 0xf1, 0x5f, 0x15, 0xf1, 0x5f, 0x15, + 0xf1, 0x5f, 0x15, 0xf1, 0x5f, 0x15, 0xf1, 0x5f, + 0x15, 0xf1, 0x5f, 0x15, 0xf1, 0x5f, 0x10, + + /* U+007D "}" */ + 0xbe, 0x80, 0x3, 0xaf, 0x40, 0x1, 0xf6, 0x0, + 0x1f, 0x70, 0x1, 0xf7, 0x0, 0x1f, 0x70, 0x0, + 0xf9, 0x0, 0xa, 0xfb, 0x0, 0xfb, 0x20, 0x1f, + 0x70, 0x1, 0xf7, 0x0, 0x1f, 0x70, 0x1, 0xf6, + 0x3, 0xaf, 0x40, 0xbe, 0x90, 0x0, + + /* U+007E "~" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3d, 0xe4, 0x0, + 0xb5, 0xc, 0x86, 0xf5, 0x1e, 0x20, 0xf0, 0x3, + 0xef, 0x90, 0x2, 0x0, 0x0, 0x10, 0x0, + + /* U+F001 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x49, 0xdc, + 0x0, 0x0, 0x0, 0x0, 0x16, 0xbf, 0xff, 0xff, + 0x0, 0x0, 0x3, 0x8d, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xc7, 0xff, + 0x0, 0x0, 0xff, 0xff, 0xea, 0x51, 0x0, 0xff, + 0x0, 0x0, 0xff, 0x83, 0x0, 0x0, 0x0, 0xff, + 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0xff, + 0x0, 0x0, 0xff, 0x0, 0x0, 0x2b, 0xff, 0xff, + 0x0, 0x0, 0xff, 0x0, 0x0, 0xdf, 0xff, 0xff, + 0x2b, 0xff, 0xff, 0x0, 0x0, 0xdf, 0xff, 0xfd, + 0xdf, 0xff, 0xff, 0x0, 0x0, 0x2b, 0xff, 0xb2, + 0xdf, 0xff, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x2b, 0xff, 0xb2, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F008 "" */ + 0xd0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xd, + 0xff, 0xff, 0xc8, 0x88, 0x88, 0x8c, 0xff, 0xff, + 0xf0, 0xf, 0x80, 0x0, 0x0, 0x8, 0xf0, 0xf, + 0xf0, 0xf, 0x80, 0x0, 0x0, 0x8, 0xf0, 0xf, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xf0, 0xf, 0xec, 0xcc, 0xcc, 0xce, 0xf0, 0xf, + 0xf0, 0xf, 0xec, 0xcc, 0xcc, 0xce, 0xf0, 0xf, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x8, 0xff, 0xff, + 0xf0, 0xf, 0x80, 0x0, 0x0, 0x8, 0xf0, 0xf, + 0xf0, 0xf, 0x80, 0x0, 0x0, 0x8, 0xf0, 0xf, + 0xff, 0xff, 0xc8, 0x88, 0x88, 0x8c, 0xff, 0xff, + 0xd0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xd, + + /* U+F00B "" */ + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0xff, 0x73, 0xff, 0xff, 0xff, 0xff, 0xfd, + + /* U+F00C "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xb1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xfc, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, 0xff, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xff, 0xc0, + 0x1b, 0xa0, 0x0, 0x0, 0xb, 0xff, 0xfc, 0x0, + 0xcf, 0xfb, 0x0, 0x0, 0xbf, 0xff, 0xc0, 0x0, + 0xbf, 0xff, 0xb0, 0xb, 0xff, 0xfc, 0x0, 0x0, + 0xc, 0xff, 0xfb, 0xbf, 0xff, 0xc0, 0x0, 0x0, + 0x0, 0xcf, 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0xc, 0xff, 0xff, 0xb0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xb0, 0x0, 0x0, 0x0, 0x0, + + /* U+F00D "" */ + 0x3, 0x0, 0x0, 0x0, 0x3, 0x8, 0xfc, 0x10, + 0x0, 0x1c, 0xf8, 0xff, 0xfc, 0x10, 0x1c, 0xff, + 0xf5, 0xff, 0xfc, 0x2c, 0xff, 0xf5, 0x5, 0xff, + 0xff, 0xff, 0xf5, 0x0, 0x5, 0xff, 0xff, 0xf5, + 0x0, 0x0, 0x1d, 0xff, 0xfd, 0x10, 0x0, 0x1c, + 0xff, 0xff, 0xfc, 0x10, 0x1c, 0xff, 0xf9, 0xff, + 0xfc, 0x1c, 0xff, 0xf5, 0x5, 0xff, 0xfc, 0xdf, + 0xf5, 0x0, 0x5, 0xff, 0xd1, 0xa4, 0x0, 0x0, + 0x4, 0xa1, + + /* U+F011 "" */ + 0x0, 0x0, 0x0, 0x4f, 0xe0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0x10, 0x6f, 0xf1, 0x3, 0x10, 0x0, + 0x0, 0x5f, 0xd0, 0x6f, 0xf1, 0x3f, 0xd1, 0x0, + 0x3, 0xff, 0xf1, 0x6f, 0xf1, 0x5f, 0xfd, 0x0, + 0xd, 0xff, 0x40, 0x6f, 0xf1, 0x9, 0xff, 0x70, + 0x4f, 0xf7, 0x0, 0x6f, 0xf1, 0x0, 0xcf, 0xe0, + 0x9f, 0xf0, 0x0, 0x6f, 0xf1, 0x0, 0x5f, 0xf3, + 0xbf, 0xc0, 0x0, 0x6f, 0xf1, 0x0, 0x2f, 0xf5, + 0xbf, 0xc0, 0x0, 0x4f, 0xe0, 0x0, 0x1f, 0xf6, + 0xaf, 0xe0, 0x0, 0x0, 0x0, 0x0, 0x4f, 0xf4, + 0x6f, 0xf4, 0x0, 0x0, 0x0, 0x0, 0xaf, 0xf0, + 0xf, 0xfe, 0x10, 0x0, 0x0, 0x5, 0xff, 0xa0, + 0x6, 0xff, 0xd3, 0x0, 0x0, 0x7f, 0xff, 0x20, + 0x0, 0x9f, 0xff, 0xda, 0xbe, 0xff, 0xf4, 0x0, + 0x0, 0x6, 0xff, 0xff, 0xff, 0xfd, 0x30, 0x0, + 0x0, 0x0, 0x17, 0xbd, 0xca, 0x50, 0x0, 0x0, + + /* U+F013 "" */ + 0x0, 0x0, 0x0, 0x8b, 0xb8, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x30, 0x6, 0xff, 0xff, 0x60, 0x3, 0x0, + 0x4, 0xfd, 0xdf, 0xff, 0xff, 0xfd, 0xef, 0x40, + 0xd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, + 0x4f, 0xff, 0xff, 0xf9, 0x9f, 0xff, 0xff, 0xf4, + 0x8, 0xff, 0xff, 0x20, 0x2, 0xff, 0xff, 0x80, + 0x0, 0xff, 0xf9, 0x0, 0x0, 0x9f, 0xff, 0x0, + 0x0, 0xff, 0xf9, 0x0, 0x0, 0x9f, 0xff, 0x0, + 0x8, 0xff, 0xff, 0x20, 0x2, 0xff, 0xff, 0x80, + 0x4f, 0xff, 0xff, 0xf9, 0x9f, 0xff, 0xff, 0xf4, + 0xd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, + 0x4, 0xfe, 0xdf, 0xff, 0xff, 0xfd, 0xdf, 0x40, + 0x0, 0x30, 0x6, 0xff, 0xff, 0x60, 0x3, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x8b, 0xb8, 0x0, 0x0, 0x0, + + /* U+F015 "" */ + 0x0, 0x0, 0x0, 0x3, 0xdd, 0x30, 0x3f, 0xf3, + 0x0, 0x0, 0x0, 0x0, 0x6f, 0xff, 0xf5, 0x4f, + 0xf4, 0x0, 0x0, 0x0, 0x9, 0xff, 0x99, 0xff, + 0xbf, 0xf4, 0x0, 0x0, 0x1, 0xbf, 0xf6, 0x22, + 0x6f, 0xff, 0xf4, 0x0, 0x0, 0x2d, 0xfe, 0x35, + 0xff, 0x53, 0xef, 0xf4, 0x0, 0x4, 0xff, 0xc1, + 0x8f, 0xff, 0xf8, 0x2d, 0xfe, 0x40, 0x7f, 0xfa, + 0x1a, 0xff, 0xff, 0xff, 0xa1, 0xaf, 0xf7, 0xcf, + 0x82, 0xdf, 0xff, 0xff, 0xff, 0xfd, 0x28, 0xfc, + 0x14, 0xe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe0, + 0x41, 0x0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x0, 0x0, 0xf, 0xff, 0xf9, 0x0, 0x8f, + 0xff, 0xf0, 0x0, 0x0, 0xf, 0xff, 0xf8, 0x0, + 0x8f, 0xff, 0xf0, 0x0, 0x0, 0xf, 0xff, 0xf8, + 0x0, 0x8f, 0xff, 0xf0, 0x0, 0x0, 0xe, 0xff, + 0xf6, 0x0, 0x6f, 0xff, 0xe0, 0x0, + + /* U+F019 "" */ + 0x0, 0x0, 0x0, 0xdf, 0xfd, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xb0, 0x0, + 0x0, 0x0, 0xbf, 0xff, 0xff, 0xfb, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xff, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0xfb, 0x0, 0x0, 0x0, + 0xdf, 0xff, 0xfc, 0x1b, 0xb1, 0xcf, 0xff, 0xfd, + 0xff, 0xff, 0xff, 0xc2, 0x2c, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xe0, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, + + /* U+F01C "" */ + 0x0, 0x4, 0xef, 0xff, 0xff, 0xff, 0xfe, 0x40, + 0x0, 0x0, 0x1e, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe1, 0x0, 0x0, 0xaf, 0xb0, 0x0, 0x0, 0x0, + 0xb, 0xfa, 0x0, 0x5, 0xff, 0x10, 0x0, 0x0, + 0x0, 0x1, 0xff, 0x50, 0x1e, 0xf6, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x6f, 0xe1, 0xaf, 0xb0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xb, 0xfa, 0xff, 0xff, + 0xff, 0x80, 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf1, 0x0, 0x1f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf8, + + /* U+F021 "" */ + 0x0, 0x0, 0x6, 0xbd, 0xda, 0x50, 0x2, 0xff, + 0x0, 0x5, 0xef, 0xff, 0xff, 0xfe, 0x42, 0xff, + 0x0, 0x7f, 0xff, 0xa7, 0x7b, 0xff, 0xf9, 0xff, + 0x5, 0xff, 0xc1, 0x0, 0x0, 0x2c, 0xff, 0xff, + 0xe, 0xfc, 0x0, 0x0, 0x2, 0x22, 0xdf, 0xff, + 0x5f, 0xf2, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0x8f, 0xb0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, 0xb, 0xf8, + 0xff, 0xff, 0xff, 0xf0, 0x0, 0x0, 0x2f, 0xf4, + 0xff, 0xfd, 0x22, 0x20, 0x0, 0x0, 0xcf, 0xe0, + 0xff, 0xff, 0xc2, 0x0, 0x0, 0x2c, 0xff, 0x40, + 0xff, 0x9f, 0xff, 0xb7, 0x6a, 0xff, 0xf7, 0x0, + 0xff, 0x24, 0xdf, 0xff, 0xff, 0xfe, 0x50, 0x0, + 0xff, 0x20, 0x5, 0xac, 0xdb, 0x60, 0x0, 0x0, + + /* U+F026 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8d, + 0x0, 0x0, 0x8, 0xff, 0x0, 0x0, 0x8f, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, + 0x0, 0x0, 0x8f, 0xff, 0x0, 0x0, 0x8, 0xff, + 0x0, 0x0, 0x0, 0x8d, 0x0, 0x0, 0x0, 0x0, + + /* U+F027 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x8d, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, 0x0, 0x0, + 0xcf, 0xff, 0xff, 0xff, 0x1, 0x50, 0xff, 0xff, + 0xff, 0xff, 0x6, 0xf7, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xbe, 0xff, 0xff, 0xff, 0xff, 0x0, 0xae, + 0xff, 0xff, 0xff, 0xff, 0x5, 0xf8, 0xdf, 0xff, + 0xff, 0xff, 0x2, 0x60, 0x0, 0x0, 0x9f, 0xff, + 0x0, 0x0, 0x0, 0x0, 0x9, 0xff, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x9e, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F028 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, + 0xd2, 0x0, 0x0, 0x0, 0x0, 0x8d, 0x0, 0x0, + 0x3, 0xee, 0x10, 0x0, 0x0, 0x8, 0xff, 0x0, + 0xa, 0xb1, 0x2f, 0xb0, 0x0, 0x0, 0x8f, 0xff, + 0x0, 0x5, 0xfc, 0x7, 0xf4, 0xdf, 0xff, 0xff, + 0xff, 0x2, 0x50, 0x5f, 0x60, 0xf9, 0xff, 0xff, + 0xff, 0xff, 0x6, 0xf7, 0xd, 0xc0, 0xbd, 0xff, + 0xff, 0xff, 0xff, 0x0, 0xae, 0x9, 0xf0, 0x9f, + 0xff, 0xff, 0xff, 0xff, 0x0, 0xae, 0x9, 0xf0, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0x6, 0xf7, 0xd, + 0xc0, 0xad, 0xdf, 0xff, 0xff, 0xff, 0x2, 0x50, + 0x5f, 0x60, 0xe9, 0x0, 0x0, 0x8f, 0xff, 0x0, + 0x5, 0xfc, 0x6, 0xf4, 0x0, 0x0, 0x8, 0xff, + 0x0, 0xa, 0xb1, 0x2f, 0xb0, 0x0, 0x0, 0x0, + 0x8d, 0x0, 0x0, 0x2, 0xee, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1f, 0xd2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0x10, 0x0, + + /* U+F03E "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x20, 0x2f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfc, 0x0, 0xc, 0xff, 0xff, 0xee, 0xff, 0xff, + 0xff, 0x20, 0x2f, 0xff, 0xfe, 0x22, 0xef, 0xff, + 0xff, 0xfc, 0xff, 0xff, 0xe2, 0x0, 0x2e, 0xff, + 0xff, 0xfe, 0x4e, 0xfe, 0x20, 0x0, 0x2, 0xff, + 0xff, 0xe2, 0x2, 0xc2, 0x0, 0x0, 0x0, 0xff, + 0xff, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + + /* U+F043 "" */ + 0x0, 0x0, 0x4e, 0x40, 0x0, 0x0, 0x0, 0xb, + 0xfb, 0x0, 0x0, 0x0, 0x1, 0xff, 0xf1, 0x0, + 0x0, 0x0, 0x9f, 0xff, 0x90, 0x0, 0x0, 0x2f, + 0xff, 0xff, 0x30, 0x0, 0xc, 0xff, 0xff, 0xfc, + 0x0, 0x7, 0xff, 0xff, 0xff, 0xf8, 0x2, 0xff, + 0xff, 0xff, 0xff, 0xf2, 0x9f, 0xff, 0xff, 0xff, + 0xff, 0x9e, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, + 0x2f, 0xff, 0xff, 0xff, 0xfe, 0xf2, 0xbf, 0xff, + 0xff, 0xfe, 0x9f, 0xa1, 0xbf, 0xff, 0xff, 0x92, + 0xff, 0xa2, 0x2f, 0xff, 0xf2, 0x4, 0xff, 0xff, + 0xff, 0xf4, 0x0, 0x2, 0x9e, 0xfe, 0x92, 0x0, + + /* U+F048 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x30, 0x0, + 0x1, 0xcc, 0xff, 0x40, 0x0, 0x2d, 0xff, 0xff, + 0x40, 0x3, 0xef, 0xff, 0xff, 0x40, 0x3f, 0xff, + 0xff, 0xff, 0x44, 0xff, 0xff, 0xff, 0xff, 0x9f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0xff, + 0xff, 0xff, 0xff, 0x45, 0xff, 0xff, 0xff, 0xff, + 0x40, 0x4f, 0xff, 0xff, 0xff, 0x40, 0x3, 0xef, + 0xff, 0xff, 0x40, 0x0, 0x2e, 0xff, 0xff, 0x30, + 0x0, 0x1, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F04B "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0x91, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, + 0x70, 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0xfd, + 0x40, 0x0, 0x0, 0x0, 0xff, 0xff, 0xff, 0xfa, + 0x10, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd5, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb2, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xb2, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xd5, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x0, 0x0, 0xff, 0xff, 0xff, 0xfa, 0x10, + 0x0, 0x0, 0xff, 0xff, 0xfd, 0x40, 0x0, 0x0, + 0x0, 0xff, 0xff, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x8e, 0xa1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F04C "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, + 0xff, 0xf8, 0x0, 0x8f, 0xff, 0xf8, 0xff, 0xff, + 0xff, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0xf7, 0x0, 0x7f, 0xff, + 0xf7, + + /* U+F04D "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, + + /* U+F051 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0xcc, 0x10, 0x0, + 0x3, 0xff, 0xff, 0xd2, 0x0, 0x4, 0xff, 0xff, + 0xfe, 0x30, 0x4, 0xff, 0xff, 0xff, 0xf4, 0x4, + 0xff, 0xff, 0xff, 0xff, 0x54, 0xff, 0xff, 0xff, + 0xff, 0xf9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf9, 0xff, 0xff, 0xff, 0xff, 0x44, 0xff, 0xff, + 0xff, 0xf3, 0x4, 0xff, 0xff, 0xfe, 0x30, 0x4, + 0xff, 0xff, 0xd2, 0x0, 0x4, 0xff, 0xcc, 0x10, + 0x0, 0x3, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F052 "" */ + 0x0, 0x0, 0x0, 0x2d, 0xd2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xef, 0xfe, 0x10, 0x0, 0x0, + 0x0, 0x0, 0x1d, 0xff, 0xff, 0xd1, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0xff, 0xff, 0xfc, 0x0, 0x0, + 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xb0, 0x0, + 0x0, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x0, + 0x9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0xc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, + + /* U+F053 "" */ + 0x0, 0x0, 0x0, 0x1a, 0x40, 0x0, 0x0, 0x1, + 0xdf, 0xf0, 0x0, 0x0, 0x1d, 0xff, 0xa0, 0x0, + 0x1, 0xdf, 0xfa, 0x0, 0x0, 0x1d, 0xff, 0xa0, + 0x0, 0x1, 0xdf, 0xfa, 0x0, 0x0, 0xc, 0xff, + 0xa0, 0x0, 0x0, 0xd, 0xff, 0x80, 0x0, 0x0, + 0x1, 0xdf, 0xf8, 0x0, 0x0, 0x0, 0x1d, 0xff, + 0x80, 0x0, 0x0, 0x1, 0xdf, 0xf8, 0x0, 0x0, + 0x0, 0x1d, 0xff, 0x80, 0x0, 0x0, 0x1, 0xdf, + 0xf0, 0x0, 0x0, 0x0, 0x1b, 0x50, + + /* U+F054 "" */ + 0x4, 0xa1, 0x0, 0x0, 0x0, 0xf, 0xfd, 0x10, + 0x0, 0x0, 0xa, 0xff, 0xd1, 0x0, 0x0, 0x0, + 0xaf, 0xfd, 0x10, 0x0, 0x0, 0xa, 0xff, 0xd1, + 0x0, 0x0, 0x0, 0xaf, 0xfd, 0x10, 0x0, 0x0, + 0xa, 0xff, 0xc0, 0x0, 0x0, 0x8, 0xff, 0xd0, + 0x0, 0x0, 0x8f, 0xfd, 0x10, 0x0, 0x8, 0xff, + 0xd1, 0x0, 0x0, 0x8f, 0xfd, 0x10, 0x0, 0x8, + 0xff, 0xd1, 0x0, 0x0, 0xf, 0xfd, 0x10, 0x0, + 0x0, 0x5, 0xb1, 0x0, 0x0, 0x0, + + /* U+F067 "" */ + 0x0, 0x0, 0x4, 0xff, 0x40, 0x0, 0x0, 0x0, + 0x0, 0x8, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0x80, 0x0, 0x0, 0x48, 0x88, 0x8c, 0xff, 0xc8, + 0x88, 0x84, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x48, 0x88, 0x8c, 0xff, 0xc8, 0x88, 0x84, 0x0, + 0x0, 0x8, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, + 0x8, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x8, + 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x8, 0xff, + 0x80, 0x0, 0x0, 0x0, 0x0, 0x4, 0xff, 0x40, + 0x0, 0x0, + + /* U+F068 "" */ + 0x14, 0x44, 0x44, 0x44, 0x44, 0x44, 0x41, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0xbb, 0xbb, + 0xbb, 0xbb, 0xbb, 0xb7, + + /* U+F06E "" */ + 0x0, 0x0, 0x5, 0xad, 0xff, 0xda, 0x50, 0x0, + 0x0, 0x0, 0x4, 0xdf, 0xfc, 0x88, 0xcf, 0xfd, + 0x40, 0x0, 0x0, 0x7f, 0xfe, 0x40, 0x0, 0x4, + 0xef, 0xf7, 0x0, 0x7, 0xff, 0xf4, 0x0, 0x9e, + 0x80, 0x4f, 0xff, 0x70, 0x4f, 0xff, 0xc0, 0x0, + 0xaf, 0xf8, 0xc, 0xff, 0xf4, 0xdf, 0xff, 0x80, + 0x9a, 0xff, 0xfe, 0x8, 0xff, 0xfd, 0xdf, 0xff, + 0x80, 0xef, 0xff, 0xfe, 0x8, 0xff, 0xfd, 0x4f, + 0xff, 0xc0, 0x8f, 0xff, 0xf8, 0xc, 0xff, 0xf4, + 0x7, 0xff, 0xf4, 0x8, 0xee, 0x80, 0x4f, 0xff, + 0x70, 0x0, 0x7f, 0xfe, 0x40, 0x0, 0x4, 0xef, + 0xf8, 0x0, 0x0, 0x4, 0xdf, 0xfc, 0x88, 0xcf, + 0xfd, 0x40, 0x0, 0x0, 0x0, 0x5, 0xad, 0xff, + 0xda, 0x50, 0x0, 0x0, + + /* U+F070 "" */ + 0x8c, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xdf, 0xe4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1b, 0xff, 0x80, 0x49, + 0xdf, 0xfd, 0xa5, 0x0, 0x0, 0x0, 0x0, 0x7f, + 0xff, 0xff, 0xd8, 0x8c, 0xff, 0xd4, 0x0, 0x0, + 0x0, 0x4, 0xef, 0xf8, 0x0, 0x0, 0x4e, 0xff, + 0x70, 0x0, 0x0, 0x0, 0x1c, 0xff, 0x69, 0xe8, + 0x4, 0xff, 0xf7, 0x0, 0x4, 0xe3, 0x0, 0x9f, + 0xfe, 0xff, 0x80, 0xcf, 0xff, 0x40, 0xd, 0xff, + 0x70, 0x5, 0xff, 0xff, 0xe0, 0x8f, 0xff, 0xd0, + 0xd, 0xff, 0xf7, 0x0, 0x2d, 0xff, 0xe0, 0x8f, + 0xff, 0xd0, 0x4, 0xff, 0xfc, 0x0, 0x0, 0xaf, + 0xf8, 0xcf, 0xff, 0x30, 0x0, 0x7f, 0xff, 0x40, + 0x0, 0x6, 0xff, 0xff, 0xf7, 0x0, 0x0, 0x8, + 0xff, 0xf4, 0x0, 0x0, 0x3e, 0xff, 0xa0, 0x0, + 0x0, 0x0, 0x4d, 0xff, 0xc8, 0x82, 0x1, 0xbf, + 0xf7, 0x0, 0x0, 0x0, 0x0, 0x5a, 0xdf, 0xfc, + 0x10, 0x8, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4e, 0xfd, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xc8, + + /* U+F071 "" */ + 0x0, 0x0, 0x0, 0x0, 0x2d, 0xd2, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xbf, 0xfb, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, + 0xff, 0xff, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xd, 0xff, 0xff, 0xd0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x7f, 0xff, 0xff, 0xf7, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xff, 0xd8, 0x8d, + 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, 0xa, 0xff, + 0xa0, 0xa, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, + 0x3f, 0xff, 0xb0, 0xb, 0xff, 0xf3, 0x0, 0x0, + 0x0, 0x0, 0xcf, 0xff, 0xc0, 0xc, 0xff, 0xfc, + 0x0, 0x0, 0x0, 0x5, 0xff, 0xff, 0xd0, 0xd, + 0xff, 0xff, 0x50, 0x0, 0x0, 0xe, 0xff, 0xff, + 0xf9, 0x9f, 0xff, 0xff, 0xe0, 0x0, 0x0, 0x8f, + 0xff, 0xff, 0xe2, 0x2e, 0xff, 0xff, 0xf8, 0x0, + 0x2, 0xff, 0xff, 0xff, 0x90, 0x9, 0xff, 0xff, + 0xff, 0x10, 0xa, 0xff, 0xff, 0xff, 0xe3, 0x3e, + 0xff, 0xff, 0xff, 0xa0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + + /* U+F074 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd8, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x80, + 0xff, 0xff, 0x70, 0x0, 0x7, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xf6, 0x0, 0x6f, 0xff, 0xff, 0xfd, + 0x78, 0x8e, 0xff, 0x15, 0xff, 0xe8, 0xff, 0xe2, + 0x0, 0x2, 0xe5, 0x4f, 0xfe, 0x20, 0xfe, 0x20, + 0x0, 0x0, 0x13, 0xff, 0xf3, 0x0, 0x52, 0x0, + 0x0, 0x0, 0x3f, 0xff, 0x31, 0x0, 0x52, 0x0, + 0x0, 0x2, 0xef, 0xf4, 0x5e, 0x20, 0xfe, 0x20, + 0x78, 0x8e, 0xff, 0x51, 0xff, 0xe8, 0xff, 0xe2, + 0xff, 0xff, 0xf6, 0x0, 0x6f, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0x70, 0x0, 0x7, 0xff, 0xff, 0xf8, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x80, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd8, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F077 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x1, 0xdd, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x1d, 0xff, 0xd1, 0x0, 0x0, 0x0, 0x1, 0xdf, + 0xff, 0xfd, 0x10, 0x0, 0x0, 0x1d, 0xff, 0x99, + 0xff, 0xd1, 0x0, 0x1, 0xdf, 0xf9, 0x0, 0x9f, + 0xfd, 0x10, 0x1d, 0xff, 0x90, 0x0, 0x9, 0xff, + 0xd1, 0xbf, 0xf9, 0x0, 0x0, 0x0, 0x9f, 0xfb, + 0x5f, 0x90, 0x0, 0x0, 0x0, 0x9, 0xf5, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F078 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5f, + 0x90, 0x0, 0x0, 0x0, 0x9, 0xf5, 0xbf, 0xf9, + 0x0, 0x0, 0x0, 0x9f, 0xfb, 0x1d, 0xff, 0x90, + 0x0, 0x9, 0xff, 0xd1, 0x1, 0xdf, 0xf9, 0x0, + 0x9f, 0xfd, 0x10, 0x0, 0x1d, 0xff, 0x99, 0xff, + 0xd1, 0x0, 0x0, 0x1, 0xdf, 0xff, 0xfd, 0x10, + 0x0, 0x0, 0x0, 0x1d, 0xff, 0xd1, 0x0, 0x0, + 0x0, 0x0, 0x1, 0xdd, 0x10, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + + /* U+F079 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x1d, 0xd1, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x1, 0xdf, 0xfd, 0x10, + 0xef, 0xff, 0xff, 0xff, 0xd0, 0x0, 0x1d, 0xff, + 0xff, 0xd1, 0xaf, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0xcf, 0xcf, 0xfc, 0xfc, 0x0, 0x0, 0x0, 0xf, + 0xf0, 0x0, 0x6b, 0x1f, 0xf1, 0xb6, 0x0, 0x0, + 0x0, 0xf, 0xf0, 0x0, 0x0, 0xf, 0xf0, 0x0, + 0x0, 0x0, 0x0, 0xf, 0xf0, 0x0, 0x0, 0xf, + 0xf0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf0, 0x0, + 0x0, 0xf, 0xf0, 0x0, 0x0, 0x0, 0x6b, 0x1f, + 0xf1, 0xb6, 0x0, 0xf, 0xf0, 0x0, 0x0, 0x0, + 0xcf, 0xcf, 0xfc, 0xfc, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xfa, 0x1d, 0xff, 0xff, 0xd1, 0x0, 0xd, + 0xff, 0xff, 0xff, 0xfe, 0x1, 0xdf, 0xfd, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1d, + 0xd1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + + /* U+F07B "" */ + 0x8f, 0xff, 0xff, 0xe2, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xfe, 0x20, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + + /* U+F093 "" */ + 0x0, 0x0, 0x0, 0xb, 0xb0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xbf, 0xfb, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xb, 0xff, 0xff, 0xb0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0xff, 0xff, 0xfb, 0x0, 0x0, + 0x0, 0xb, 0xff, 0xff, 0xff, 0xff, 0xb0, 0x0, + 0x0, 0x4f, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0xdf, 0xff, 0xf0, 0xdf, 0xfd, 0xf, 0xff, 0xfd, + 0xff, 0xff, 0xf9, 0x0, 0x0, 0x9f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xe0, 0xff, + 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, + + /* U+F095 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xea, + 0x62, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xff, + 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9f, + 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, + 0xff, 0xff, 0xd0, 0x0, 0x0, 0x0, 0x0, 0x2, + 0xff, 0xff, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x3, 0xef, 0xff, 0x70, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x4, 0xff, 0xf2, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xbf, 0xfb, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0xff, 0x30, 0x0, 0x0, 0x2, + 0x0, 0x0, 0x4f, 0xff, 0x90, 0x0, 0x2, 0x8f, + 0xf3, 0x0, 0x6f, 0xff, 0xd0, 0x0, 0xa, 0xff, + 0xff, 0xe4, 0xbf, 0xff, 0xd1, 0x0, 0x0, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xd1, 0x0, 0x0, 0xa, + 0xff, 0xff, 0xff, 0xff, 0x90, 0x0, 0x0, 0x0, + 0x6f, 0xff, 0xff, 0xfb, 0x30, 0x0, 0x0, 0x0, + 0x2, 0xff, 0xdb, 0x72, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F0C4 "" */ + 0x8, 0xee, 0x80, 0x0, 0x0, 0x6, 0x61, 0x8, + 0xff, 0xff, 0x80, 0x0, 0x2d, 0xff, 0xd0, 0xef, + 0x33, 0xfe, 0x0, 0x2e, 0xff, 0xf3, 0xe, 0xf3, + 0x3f, 0xe0, 0x2e, 0xff, 0xf3, 0x0, 0x8f, 0xff, + 0xff, 0x6e, 0xff, 0xf3, 0x0, 0x0, 0x8e, 0xff, + 0xff, 0xff, 0xf3, 0x0, 0x0, 0x0, 0x2, 0xef, + 0xff, 0xf3, 0x0, 0x0, 0x0, 0x0, 0x2e, 0xff, + 0xff, 0x30, 0x0, 0x0, 0x8, 0xef, 0xff, 0xff, + 0xff, 0x30, 0x0, 0x8, 0xff, 0xff, 0xf6, 0xef, + 0xff, 0x30, 0x0, 0xef, 0x33, 0xfe, 0x2, 0xef, + 0xff, 0x30, 0xe, 0xf3, 0x3f, 0xe0, 0x2, 0xef, + 0xff, 0x30, 0x8f, 0xff, 0xf8, 0x0, 0x2, 0xdf, + 0xfd, 0x0, 0x8e, 0xe8, 0x0, 0x0, 0x0, 0x66, + 0x10, + + /* U+F0C5 "" */ + 0x0, 0x0, 0xdf, 0xff, 0xff, 0xd, 0x20, 0x0, + 0x0, 0xff, 0xff, 0xff, 0xf, 0xe2, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xf, 0xfd, 0xdf, 0xf0, 0xff, + 0xff, 0xff, 0x20, 0x0, 0xff, 0xf0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xdf, 0xff, + 0xff, 0xff, 0xfd, 0xff, 0xf9, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x0, 0xdf, 0xff, 0xff, 0xff, 0xfd, 0x0, 0x0, + + /* U+F0C7 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xc2, 0x0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, 0x20, 0xff, 0x0, + 0x0, 0x0, 0x1, 0xff, 0xe2, 0xff, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xfc, 0xff, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfb, 0x11, 0xbf, 0xff, 0xff, 0xff, + 0xff, 0xf1, 0x0, 0x1f, 0xff, 0xff, 0xff, 0xff, + 0xf1, 0x0, 0x1f, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0x11, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, + + /* U+F0C9 "" */ + 0x12, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x12, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x21, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x12, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x21, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x12, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x12, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x21, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x12, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x21, + + /* U+F0E0 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, + 0x9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, + 0xd2, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x2d, + 0xff, 0x62, 0xcf, 0xff, 0xff, 0xfc, 0x26, 0xff, + 0xff, 0xfa, 0x18, 0xff, 0xff, 0x81, 0xaf, 0xff, + 0xff, 0xff, 0xe3, 0x4d, 0xd4, 0x3e, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x81, 0x18, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, + + /* U+F0E7 "" */ + 0x0, 0xdf, 0xff, 0xfd, 0x0, 0x0, 0x1, 0xff, + 0xff, 0xfc, 0x0, 0x0, 0x3, 0xff, 0xff, 0xf7, + 0x0, 0x0, 0x6, 0xff, 0xff, 0xf2, 0x0, 0x0, + 0x8, 0xff, 0xff, 0xd0, 0x0, 0x0, 0xa, 0xff, + 0xff, 0xff, 0xff, 0xd0, 0xc, 0xff, 0xff, 0xff, + 0xff, 0xa0, 0xe, 0xff, 0xff, 0xff, 0xff, 0x20, + 0xd, 0xff, 0xff, 0xff, 0xf8, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xe0, 0x0, 0x0, 0x0, 0xe, 0xff, + 0x50, 0x0, 0x0, 0x0, 0x2f, 0xfc, 0x0, 0x0, + 0x0, 0x0, 0x5f, 0xf3, 0x0, 0x0, 0x0, 0x0, + 0x9f, 0xa0, 0x0, 0x0, 0x0, 0x0, 0xdf, 0x10, + 0x0, 0x0, 0x0, 0x0, 0xd7, 0x0, 0x0, 0x0, + + /* U+F0EA "" */ + 0x0, 0x4, 0xee, 0x40, 0x0, 0x0, 0x0, 0xdf, + 0xff, 0x99, 0xff, 0xfd, 0x0, 0x0, 0xff, 0xff, + 0x99, 0xff, 0xff, 0x0, 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x0, 0xff, 0xff, 0x90, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xd, 0xff, 0xff, + 0xd, 0x20, 0xff, 0xff, 0xf, 0xff, 0xff, 0xf, + 0xe2, 0xff, 0xff, 0xf, 0xff, 0xff, 0xf, 0xfd, + 0xff, 0xff, 0xf, 0xff, 0xff, 0x20, 0x0, 0xff, + 0xff, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xf, 0xff, + 0xff, 0xff, 0xff, 0x0, 0x0, 0xf, 0xff, 0xff, + 0xff, 0xff, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0x0, 0x0, 0xd, 0xff, 0xff, 0xff, 0xfd, + + /* U+F0F3 "" */ + 0x0, 0x0, 0x0, 0xcc, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x2, 0xff, 0x30, 0x0, 0x0, 0x0, 0x1, + 0xbf, 0xff, 0xfc, 0x20, 0x0, 0x0, 0x1e, 0xff, + 0xff, 0xff, 0xe1, 0x0, 0x0, 0x9f, 0xff, 0xff, + 0xff, 0xf8, 0x0, 0x0, 0xef, 0xff, 0xff, 0xff, + 0xfd, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0x1, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0, + 0x3, 0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0x8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x1e, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xe1, 0xcf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfc, 0xcf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xe, 0xff, 0xe0, 0x0, + 0x0, 0x0, 0x0, 0x4, 0xee, 0x40, 0x0, 0x0, + + /* U+F11C "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x0, 0xf0, 0xf, 0x0, 0xf0, + 0xf, 0x0, 0xff, 0xff, 0x0, 0xf0, 0xf, 0x0, + 0xf0, 0xf, 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x8, + 0x80, 0x88, 0x8, 0x80, 0x8f, 0xff, 0xff, 0xf8, + 0x8, 0x80, 0x88, 0x8, 0x80, 0x8f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x0, 0xf0, 0x0, 0x0, 0x0, 0xf, 0x0, + 0xff, 0xff, 0x0, 0xf0, 0x0, 0x0, 0x0, 0xf, + 0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf8, + + /* U+F124 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xaf, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, + 0xcf, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0x6, + 0xdf, 0xff, 0xff, 0xa0, 0x0, 0x0, 0x0, 0x17, + 0xef, 0xff, 0xff, 0xff, 0x30, 0x0, 0x0, 0x18, + 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0, 0x0, 0x2a, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x0, 0x8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0, + 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x60, + 0x0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, + 0xf7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, + 0xff, 0xf1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0x10, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xff, 0xfa, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xf2, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x8f, 0x80, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, + + /* U+F15B "" */ + 0xdf, 0xff, 0xff, 0xf0, 0xd2, 0x0, 0xff, 0xff, + 0xff, 0xf0, 0xfe, 0x20, 0xff, 0xff, 0xff, 0xf0, + 0xff, 0xe2, 0xff, 0xff, 0xff, 0xf0, 0xff, 0xfd, + 0xff, 0xff, 0xff, 0xf2, 0x0, 0x0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xfd, + + /* U+F1EB "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x4, 0x9c, 0xef, 0xfe, + 0xc9, 0x40, 0x0, 0x0, 0x0, 0x7, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x70, 0x0, 0x4, 0xdf, + 0xff, 0xfc, 0xa8, 0x8a, 0xcf, 0xff, 0xfd, 0x40, + 0x6f, 0xff, 0xd5, 0x0, 0x0, 0x0, 0x0, 0x5d, + 0xff, 0xf6, 0xcf, 0xf6, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x6f, 0xfc, 0x1a, 0x30, 0x0, 0x5a, + 0xdf, 0xfd, 0xa5, 0x0, 0x3, 0xa1, 0x0, 0x0, + 0x4d, 0xff, 0xff, 0xff, 0xff, 0xd4, 0x0, 0x0, + 0x0, 0x5, 0xff, 0xfe, 0xa8, 0x8a, 0xef, 0xff, + 0x50, 0x0, 0x0, 0x1, 0xdf, 0x70, 0x0, 0x0, + 0x7, 0xfd, 0x10, 0x0, 0x0, 0x0, 0x12, 0x0, + 0x0, 0x0, 0x0, 0x21, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x4e, 0xe4, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xef, 0xfe, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xef, 0xfe, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x4e, 0xe4, 0x0, 0x0, 0x0, 0x0, + + /* U+F240 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0xff, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf, 0xff, + 0xff, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F241 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0xff, 0xf, + 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, 0xf, 0xff, + 0xff, 0xf, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0, + 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x0, 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0x0, 0xf, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F242 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0xff, 0xf, + 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xf, 0xff, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xf, 0xff, 0xff, + 0xff, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F243 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0xff, 0xf, + 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0xf, 0xff, 0xf0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0xf, 0xff, 0xf0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0xf, 0xff, 0xf0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F244 "" */ + 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf0, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, + 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, + + /* U+F287 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, + 0xfd, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x1, 0xcf, 0xff, 0xf5, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0xb9, 0x29, 0xfe, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x3f, 0x10, 0x2, + 0x0, 0x0, 0x0, 0x0, 0x3, 0xdf, 0x80, 0xa, + 0x90, 0x0, 0x0, 0x0, 0x3, 0x70, 0x0, 0xdf, + 0xff, 0x77, 0xf7, 0x55, 0x55, 0x55, 0x55, 0x8f, + 0xd3, 0xf, 0xff, 0xfd, 0xcc, 0xdf, 0xdc, 0xcc, + 0xcc, 0xcd, 0xff, 0xb0, 0x8f, 0xfe, 0x10, 0x0, + 0xaa, 0x0, 0x0, 0x0, 0x4d, 0x40, 0x0, 0x46, + 0x10, 0x0, 0x1, 0xf2, 0x2, 0x33, 0x10, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xb1, 0xcf, + 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xa, 0xff, 0xff, 0x90, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xbf, 0xf9, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x22, + 0x0, 0x0, 0x0, + + /* U+F293 "" */ + 0x0, 0x18, 0xdf, 0xfd, 0x92, 0x0, 0x2, 0xef, + 0xfb, 0xef, 0xff, 0x30, 0xd, 0xff, 0xfa, 0x2e, + 0xff, 0xe0, 0x4f, 0xff, 0xfa, 0x3, 0xff, 0xf5, + 0x9f, 0xfa, 0xfa, 0x35, 0x4f, 0xfa, 0xcf, 0xc0, + 0x8a, 0x3d, 0xb, 0xfd, 0xef, 0xfb, 0x3, 0x12, + 0x8f, 0xfe, 0xff, 0xff, 0xb0, 0x6, 0xff, 0xff, + 0xff, 0xff, 0xd1, 0x8, 0xff, 0xff, 0xef, 0xfd, + 0x11, 0x10, 0x9f, 0xff, 0xdf, 0xd1, 0x59, 0x3b, + 0xb, 0xfd, 0xaf, 0xd7, 0xfa, 0x38, 0x1d, 0xfb, + 0x5f, 0xff, 0xfa, 0x1, 0xdf, 0xf7, 0xd, 0xff, + 0xfa, 0x1d, 0xff, 0xf1, 0x3, 0xef, 0xfc, 0xdf, + 0xff, 0x50, 0x0, 0x18, 0xdf, 0xfe, 0xa3, 0x0, + + /* U+F2ED "" */ + 0x0, 0x0, 0x7f, 0xff, 0xf7, 0x0, 0x0, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0xf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf0, 0xf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf0, 0xf, 0xf9, 0x9f, 0x99, 0xf9, 0x9f, + 0xf0, 0xf, 0xf8, 0x8f, 0x88, 0xf8, 0x8f, 0xf0, + 0xf, 0xf8, 0x8f, 0x88, 0xf8, 0x8f, 0xf0, 0xf, + 0xf8, 0x8f, 0x88, 0xf8, 0x8f, 0xf0, 0xf, 0xf8, + 0x8f, 0x88, 0xf8, 0x8f, 0xf0, 0xf, 0xf8, 0x8f, + 0x88, 0xf8, 0x8f, 0xf0, 0xf, 0xf8, 0x8f, 0x88, + 0xf8, 0x8f, 0xf0, 0xf, 0xf9, 0x9f, 0x99, 0xf9, + 0x9f, 0xf0, 0xf, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf0, 0x8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, + + /* U+F304 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7f, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xb0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0xff, + 0xff, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x8a, 0x1d, + 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xfa, + 0x1d, 0xff, 0x70, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xfa, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x8f, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x6f, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0xb, 0xff, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0xdf, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0xe, + 0xff, 0xff, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xde, 0xdb, 0x60, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, + + /* U+F55A "" */ + 0x0, 0x0, 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xe4, 0x0, 0x1, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x0, 0x1d, 0xff, 0xff, + 0xfa, 0xef, 0xfe, 0xaf, 0xff, 0xff, 0x1, 0xdf, + 0xff, 0xff, 0xa0, 0x2e, 0xe2, 0xa, 0xff, 0xff, + 0x1d, 0xff, 0xff, 0xff, 0xe2, 0x2, 0x20, 0x2e, + 0xff, 0xff, 0xcf, 0xff, 0xff, 0xff, 0xfe, 0x20, + 0x2, 0xef, 0xff, 0xff, 0xcf, 0xff, 0xff, 0xff, + 0xfe, 0x20, 0x2, 0xef, 0xff, 0xff, 0x1d, 0xff, + 0xff, 0xff, 0xe2, 0x2, 0x20, 0x2e, 0xff, 0xff, + 0x1, 0xdf, 0xff, 0xff, 0xa0, 0x2e, 0xe2, 0xa, + 0xff, 0xff, 0x0, 0x1d, 0xff, 0xff, 0xfa, 0xef, + 0xfe, 0xaf, 0xff, 0xff, 0x0, 0x1, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x0, 0x0, + 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe4, + + /* U+F7C2 "" */ + 0x0, 0x8, 0xff, 0xff, 0xff, 0xe4, 0x0, 0x8f, + 0xff, 0xff, 0xff, 0xfe, 0x8, 0xf8, 0xf, 0xb, + 0x40, 0xff, 0x8f, 0xf8, 0xf, 0xb, 0x40, 0xff, + 0xff, 0xf8, 0xf, 0xb, 0x40, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0x4e, 0xff, 0xff, 0xff, 0xff, 0xe4, + + /* U+F8A2 "" */ + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, + 0xe0, 0x0, 0x0, 0x10, 0x0, 0x0, 0x0, 0x2, + 0xef, 0x10, 0x0, 0xbf, 0x0, 0x0, 0x0, 0x0, + 0x7f, 0xf1, 0x0, 0xcf, 0xf1, 0x0, 0x0, 0x0, + 0x7, 0xff, 0x11, 0xcf, 0xff, 0x77, 0x77, 0x77, + 0x77, 0xbf, 0xf1, 0xcf, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x17, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xe0, 0x7, 0xff, 0xf1, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0xff, 0x10, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0xa0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 +}; + + +/*--------------------- + * GLYPH DESCRIPTION + *--------------------*/ + +static const lv_font_fmt_txt_glyph_dsc_t glyph_dsc[] = { + {.bitmap_index = 0, .adv_w = 0, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0} /* id = 0 reserved */, + {.bitmap_index = 0, .adv_w = 69, .box_w = 0, .box_h = 0, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 0, .adv_w = 69, .box_w = 3, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 18, .adv_w = 100, .box_w = 5, .box_h = 5, .ofs_x = 1, .ofs_y = 7}, + {.bitmap_index = 31, .adv_w = 180, .box_w = 11, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 97, .adv_w = 159, .box_w = 10, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 177, .adv_w = 216, .box_w = 13, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 255, .adv_w = 176, .box_w = 11, .box_h = 13, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 327, .adv_w = 54, .box_w = 2, .box_h = 5, .ofs_x = 1, .ofs_y = 7}, + {.bitmap_index = 332, .adv_w = 86, .box_w = 4, .box_h = 15, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 362, .adv_w = 87, .box_w = 4, .box_h = 15, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 392, .adv_w = 102, .box_w = 7, .box_h = 7, .ofs_x = 0, .ofs_y = 5}, + {.bitmap_index = 417, .adv_w = 149, .box_w = 8, .box_h = 8, .ofs_x = 1, .ofs_y = 2}, + {.bitmap_index = 449, .adv_w = 98, .box_w = 6, .box_h = 3, .ofs_x = 0, .ofs_y = 3}, + {.bitmap_index = 458, .adv_w = 58, .box_w = 3, .box_h = 3, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 463, .adv_w = 90, .box_w = 8, .box_h = 16, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 527, .adv_w = 171, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 587, .adv_w = 95, .box_w = 5, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 617, .adv_w = 147, .box_w = 9, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 671, .adv_w = 146, .box_w = 9, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 725, .adv_w = 171, .box_w = 11, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 791, .adv_w = 147, .box_w = 9, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 845, .adv_w = 158, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 905, .adv_w = 153, .box_w = 9, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 959, .adv_w = 165, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1019, .adv_w = 158, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1079, .adv_w = 58, .box_w = 3, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1093, .adv_w = 58, .box_w = 3, .box_h = 12, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 1111, .adv_w = 149, .box_w = 8, .box_h = 8, .ofs_x = 1, .ofs_y = 2}, + {.bitmap_index = 1143, .adv_w = 149, .box_w = 8, .box_h = 6, .ofs_x = 1, .ofs_y = 3}, + {.bitmap_index = 1167, .adv_w = 149, .box_w = 8, .box_h = 8, .ofs_x = 1, .ofs_y = 2}, + {.bitmap_index = 1199, .adv_w = 147, .box_w = 9, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1253, .adv_w = 265, .box_w = 16, .box_h = 15, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 1373, .adv_w = 187, .box_w = 13, .box_h = 12, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 1451, .adv_w = 194, .box_w = 11, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1517, .adv_w = 185, .box_w = 11, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1583, .adv_w = 211, .box_w = 12, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1655, .adv_w = 172, .box_w = 9, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1709, .adv_w = 163, .box_w = 9, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1763, .adv_w = 198, .box_w = 12, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 1835, .adv_w = 208, .box_w = 11, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1901, .adv_w = 79, .box_w = 3, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 1919, .adv_w = 131, .box_w = 8, .box_h = 12, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 1967, .adv_w = 184, .box_w = 11, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2033, .adv_w = 152, .box_w = 9, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2087, .adv_w = 244, .box_w = 13, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2165, .adv_w = 208, .box_w = 11, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2231, .adv_w = 215, .box_w = 13, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2309, .adv_w = 185, .box_w = 10, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2369, .adv_w = 215, .box_w = 14, .box_h = 15, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 2474, .adv_w = 186, .box_w = 10, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2534, .adv_w = 159, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2594, .adv_w = 150, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2654, .adv_w = 202, .box_w = 11, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 2720, .adv_w = 182, .box_w = 13, .box_h = 12, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 2798, .adv_w = 288, .box_w = 18, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2906, .adv_w = 172, .box_w = 11, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 2972, .adv_w = 166, .box_w = 12, .box_h = 12, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 3044, .adv_w = 168, .box_w = 11, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3110, .adv_w = 85, .box_w = 5, .box_h = 15, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 3148, .adv_w = 90, .box_w = 8, .box_h = 16, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 3212, .adv_w = 85, .box_w = 4, .box_h = 15, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 3242, .adv_w = 149, .box_w = 8, .box_h = 7, .ofs_x = 1, .ofs_y = 2}, + {.bitmap_index = 3270, .adv_w = 128, .box_w = 8, .box_h = 2, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 3278, .adv_w = 154, .box_w = 5, .box_h = 2, .ofs_x = 1, .ofs_y = 10}, + {.bitmap_index = 3283, .adv_w = 153, .box_w = 9, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3324, .adv_w = 175, .box_w = 10, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 3384, .adv_w = 146, .box_w = 9, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3425, .adv_w = 175, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3485, .adv_w = 157, .box_w = 10, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3530, .adv_w = 90, .box_w = 7, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3572, .adv_w = 177, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 3632, .adv_w = 174, .box_w = 9, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 3686, .adv_w = 71, .box_w = 3, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 3704, .adv_w = 73, .box_w = 6, .box_h = 15, .ofs_x = -2, .ofs_y = -3}, + {.bitmap_index = 3749, .adv_w = 158, .box_w = 9, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 3803, .adv_w = 71, .box_w = 2, .box_h = 12, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 3815, .adv_w = 271, .box_w = 15, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 3883, .adv_w = 174, .box_w = 9, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 3924, .adv_w = 163, .box_w = 10, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 3969, .adv_w = 175, .box_w = 10, .box_h = 12, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 4029, .adv_w = 175, .box_w = 10, .box_h = 12, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 4089, .adv_w = 105, .box_w = 6, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 4116, .adv_w = 128, .box_w = 8, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 4152, .adv_w = 106, .box_w = 7, .box_h = 11, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 4191, .adv_w = 173, .box_w = 9, .box_h = 9, .ofs_x = 1, .ofs_y = 0}, + {.bitmap_index = 4232, .adv_w = 143, .box_w = 10, .box_h = 9, .ofs_x = -1, .ofs_y = 0}, + {.bitmap_index = 4277, .adv_w = 230, .box_w = 15, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 4345, .adv_w = 141, .box_w = 9, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 4386, .adv_w = 143, .box_w = 10, .box_h = 12, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 4446, .adv_w = 133, .box_w = 8, .box_h = 9, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 4482, .adv_w = 90, .box_w = 6, .box_h = 15, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 4527, .adv_w = 77, .box_w = 3, .box_h = 15, .ofs_x = 1, .ofs_y = -3}, + {.bitmap_index = 4550, .adv_w = 90, .box_w = 5, .box_h = 15, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 4588, .adv_w = 149, .box_w = 9, .box_h = 5, .ofs_x = 0, .ofs_y = 4}, + {.bitmap_index = 4611, .adv_w = 256, .box_w = 16, .box_h = 17, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 4747, .adv_w = 256, .box_w = 16, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 4843, .adv_w = 256, .box_w = 16, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 4955, .adv_w = 256, .box_w = 16, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 5051, .adv_w = 176, .box_w = 11, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 5117, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5245, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5373, .adv_w = 288, .box_w = 18, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5499, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5627, .adv_w = 288, .box_w = 18, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 5735, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 5863, .adv_w = 128, .box_w = 8, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 5919, .adv_w = 192, .box_w = 12, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6003, .adv_w = 288, .box_w = 18, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6147, .adv_w = 256, .box_w = 16, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 6243, .adv_w = 176, .box_w = 11, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 6331, .adv_w = 224, .box_w = 10, .box_h = 16, .ofs_x = 2, .ofs_y = -2}, + {.bitmap_index = 6411, .adv_w = 224, .box_w = 14, .box_h = 18, .ofs_x = 0, .ofs_y = -3}, + {.bitmap_index = 6537, .adv_w = 224, .box_w = 14, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6642, .adv_w = 224, .box_w = 14, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 6740, .adv_w = 224, .box_w = 10, .box_h = 16, .ofs_x = 2, .ofs_y = -2}, + {.bitmap_index = 6820, .adv_w = 224, .box_w = 16, .box_h = 14, .ofs_x = -1, .ofs_y = -1}, + {.bitmap_index = 6932, .adv_w = 160, .box_w = 10, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7002, .adv_w = 160, .box_w = 10, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7072, .adv_w = 224, .box_w = 14, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 7170, .adv_w = 224, .box_w = 14, .box_h = 4, .ofs_x = 0, .ofs_y = 4}, + {.bitmap_index = 7198, .adv_w = 288, .box_w = 18, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 7306, .adv_w = 320, .box_w = 20, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7466, .adv_w = 288, .box_w = 20, .box_h = 16, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 7626, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 7754, .adv_w = 224, .box_w = 14, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 7824, .adv_w = 224, .box_w = 14, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 7894, .adv_w = 320, .box_w = 20, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8034, .adv_w = 256, .box_w = 16, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 8130, .adv_w = 256, .box_w = 16, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 8258, .adv_w = 256, .box_w = 17, .box_h = 17, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 8403, .adv_w = 224, .box_w = 15, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8508, .adv_w = 224, .box_w = 14, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 8620, .adv_w = 224, .box_w = 14, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8718, .adv_w = 224, .box_w = 14, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 8816, .adv_w = 256, .box_w = 16, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 8912, .adv_w = 160, .box_w = 12, .box_h = 16, .ofs_x = -1, .ofs_y = -2}, + {.bitmap_index = 9008, .adv_w = 224, .box_w = 14, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 9120, .adv_w = 224, .box_w = 14, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 9232, .adv_w = 288, .box_w = 18, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 9340, .adv_w = 256, .box_w = 18, .box_h = 18, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 9502, .adv_w = 192, .box_w = 12, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 9598, .adv_w = 320, .box_w = 20, .box_h = 15, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 9748, .adv_w = 320, .box_w = 20, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 9848, .adv_w = 320, .box_w = 20, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 9948, .adv_w = 320, .box_w = 20, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 10048, .adv_w = 320, .box_w = 20, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 10148, .adv_w = 320, .box_w = 20, .box_h = 10, .ofs_x = 0, .ofs_y = 1}, + {.bitmap_index = 10248, .adv_w = 320, .box_w = 21, .box_h = 14, .ofs_x = 0, .ofs_y = -1}, + {.bitmap_index = 10395, .adv_w = 224, .box_w = 12, .box_h = 16, .ofs_x = 1, .ofs_y = -2}, + {.bitmap_index = 10491, .adv_w = 224, .box_w = 14, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 10603, .adv_w = 256, .box_w = 17, .box_h = 17, .ofs_x = -1, .ofs_y = -3}, + {.bitmap_index = 10748, .adv_w = 320, .box_w = 20, .box_h = 12, .ofs_x = 0, .ofs_y = 0}, + {.bitmap_index = 10868, .adv_w = 192, .box_w = 12, .box_h = 16, .ofs_x = 0, .ofs_y = -2}, + {.bitmap_index = 10964, .adv_w = 258, .box_w = 17, .box_h = 11, .ofs_x = 0, .ofs_y = 1} +}; + +/*--------------------- + * CHARACTER MAPPING + *--------------------*/ + +static const uint16_t unicode_list_2[] = { + 0x0, 0x7, 0xa, 0xb, 0xc, 0x10, 0x12, 0x14, + 0x18, 0x1b, 0x20, 0x25, 0x26, 0x27, 0x3d, 0x42, + 0x47, 0x4a, 0x4b, 0x4c, 0x50, 0x51, 0x52, 0x53, + 0x66, 0x67, 0x6d, 0x6f, 0x70, 0x73, 0x76, 0x77, + 0x78, 0x7a, 0x92, 0x94, 0xc3, 0xc4, 0xc6, 0xc8, + 0xdf, 0xe6, 0xe9, 0xf2, 0x11b, 0x123, 0x15a, 0x1ea, + 0x23f, 0x240, 0x241, 0x242, 0x243, 0x286, 0x292, 0x2ec, + 0x303, 0x559, 0x7c1, 0x8a1 +}; + +/*Collect the unicode lists and glyph_id offsets*/ +static const lv_font_fmt_txt_cmap_t cmaps[] = +{ + { + .range_start = 32, .range_length = 12, .glyph_id_start = 1, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 45, .range_length = 82, .glyph_id_start = 13, + .unicode_list = NULL, .glyph_id_ofs_list = NULL, .list_length = 0, .type = LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY + }, + { + .range_start = 61441, .range_length = 2210, .glyph_id_start = 95, + .unicode_list = unicode_list_2, .glyph_id_ofs_list = NULL, .list_length = 60, .type = LV_FONT_FMT_TXT_CMAP_SPARSE_TINY + } +}; + +/*----------------- + * KERNING + *----------------*/ + + +/*Map glyph_ids to kern left classes*/ +static const uint8_t kern_left_class_mapping[] = +{ + 0, 0, 1, 2, 0, 3, 4, 5, + 2, 6, 7, 8, 9, 9, 10, 11, + 12, 0, 13, 14, 15, 16, 17, 18, + 19, 12, 20, 20, 0, 0, 0, 21, + 22, 23, 24, 25, 22, 26, 27, 28, + 29, 29, 30, 31, 32, 29, 29, 22, + 33, 34, 35, 3, 36, 30, 37, 37, + 38, 39, 40, 41, 42, 43, 0, 44, + 0, 45, 46, 47, 48, 49, 50, 51, + 45, 52, 52, 53, 48, 45, 45, 46, + 46, 54, 55, 56, 57, 51, 58, 58, + 59, 58, 60, 41, 0, 0, 9, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 +}; + +/*Map glyph_ids to kern right classes*/ +static const uint8_t kern_right_class_mapping[] = +{ + 0, 0, 1, 2, 0, 3, 4, 5, + 2, 6, 7, 8, 9, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 12, 18, + 19, 20, 21, 21, 0, 0, 0, 22, + 23, 24, 25, 23, 25, 25, 25, 23, + 25, 25, 26, 25, 25, 25, 25, 23, + 25, 23, 25, 3, 27, 28, 29, 29, + 30, 31, 32, 33, 34, 35, 0, 36, + 0, 37, 38, 39, 39, 39, 0, 39, + 38, 40, 41, 38, 38, 42, 42, 39, + 42, 39, 42, 43, 44, 45, 46, 46, + 47, 46, 48, 0, 0, 35, 9, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 +}; + +/*Kern values between classes*/ +static const int8_t kern_class_values[] = +{ + 0, 1, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0, 3, 0, 0, 0, + 0, 2, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 1, 12, 0, 7, -6, 0, 0, 0, + 0, -14, -15, 2, 12, 6, 4, -10, + 2, 13, 1, 11, 3, 8, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 15, 2, -2, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -8, 0, 0, 0, 0, 0, -5, + 4, 5, 0, 0, -3, 0, -2, 3, + 0, -3, 0, -3, -1, -5, 0, 0, + 0, 0, -3, 0, 0, -3, -4, 0, + 0, -3, 0, -5, 0, 0, 0, 0, + 0, 0, 0, 0, 0, -3, -3, 0, + 0, -7, 0, -31, 0, 0, -5, 0, + 5, 8, 0, 0, -5, 3, 3, 8, + 5, -4, 5, 0, 0, -15, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -9, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + -3, -13, 0, -10, -2, 0, 0, 0, + 0, 1, 10, 0, -8, -2, -1, 1, + 0, -4, 0, 0, -2, -19, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -20, -2, 10, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 8, 0, 3, 0, 0, -5, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 10, 2, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, -9, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 2, 5, 3, 8, -3, 0, 0, 5, + -3, -8, -35, 2, 7, 5, 1, -3, + 0, 9, 0, 8, 0, 8, 0, -24, + 0, -3, 8, 0, 8, -3, 5, 3, + 0, 0, 1, -3, 0, 0, -4, 20, + 0, 20, 0, 8, 0, 11, 3, 4, + 0, 0, 0, -9, 0, 0, 0, 0, + 1, -2, 0, 2, -5, -3, -5, 2, + 0, -3, 0, 0, 0, -10, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -17, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 1, -14, 0, -16, 0, 0, 0, 0, + -2, 0, 25, -3, -3, 3, 3, -2, + 0, -3, 3, 0, 0, -14, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -25, 0, 3, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 15, 0, 0, -9, 0, 8, 0, + -17, -25, -17, -5, 8, 0, 0, -17, + 0, 3, -6, 0, -4, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 7, 8, -31, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 2, 0, 0, 0, 0, 0, 2, + 2, -3, -5, 0, -1, -1, -3, 0, + 0, -2, 0, 0, 0, -5, 0, -2, + 0, -6, -5, 0, -6, -8, -8, -5, + 0, -5, 0, -5, 0, 0, 0, 0, + -2, 0, 0, 3, 0, 2, -3, 0, + 0, 0, 0, 3, -2, 0, 0, 0, + -2, 3, 3, -1, 0, 0, 0, -5, + 0, -1, 0, 0, 0, 0, 0, 1, + 0, 3, -2, 0, -3, 0, -4, 0, + 0, -2, 0, 8, 0, 0, -3, 0, + 0, 0, 0, 0, -1, 1, -2, -2, + 0, -3, 0, -3, 0, 0, 0, 0, + 0, 0, 0, 0, 0, -1, -1, 0, + -3, -3, 0, 0, 0, 0, 0, 1, + 0, 0, -2, 0, -3, -3, -3, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + -2, 0, 0, 0, 0, -2, -3, 0, + 0, -8, -2, -8, 5, 0, 0, -5, + 3, 5, 7, 0, -6, -1, -3, 0, + -1, -12, 3, -2, 2, -14, 3, 0, + 0, 1, -13, 0, -14, -2, -22, -2, + 0, -13, 0, 5, 7, 0, 3, 0, + 0, 0, 0, 1, 0, -5, -3, 0, + 0, 0, 0, -3, 0, 0, 0, -3, + 0, 0, 0, 0, 0, -1, -1, 0, + -1, -3, 0, 0, 0, 0, 0, 0, + 0, -3, -3, 0, -2, -3, -2, 0, + 0, -3, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, -2, -2, 0, + 0, -2, 0, -5, 3, 0, 0, -3, + 1, 3, 3, 0, 0, 0, 0, 0, + 0, -2, 0, 0, 0, 0, 0, 2, + 0, 0, -3, 0, -3, -2, -3, 0, + 0, 0, 0, 0, 0, 0, 2, 0, + -2, 0, 0, 0, 0, -3, -4, 0, + 0, 8, -2, 1, -8, 0, 0, 7, + -13, -13, -11, -5, 3, 0, -2, -17, + -5, 0, -5, 0, -5, 4, -5, -16, + 0, -7, 0, 0, 1, -1, 2, -2, + 0, 3, 0, -8, -10, 0, -13, -6, + -5, -6, -8, -3, -7, -1, -5, -7, + 0, 1, 0, -3, 0, 0, 0, 2, + 0, 3, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, -3, 0, -1, + 0, -1, -3, 0, -4, -6, -6, -1, + 0, -8, 0, 0, 0, 0, 0, 0, + -2, 0, 0, 0, 0, 1, -2, 0, + 0, 3, 0, 0, 0, 0, 0, 0, + 0, 0, 12, 0, 0, 0, 0, 0, + 0, 2, 0, 0, 0, -3, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -5, 0, 3, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + -2, 0, 0, 0, -5, 0, 0, 0, + 0, -13, -8, 0, 0, 0, -4, -13, + 0, 0, -3, 3, 0, -7, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + -4, 0, 0, -5, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -5, 0, 0, 0, 0, 3, 0, + 2, -5, -5, 0, -3, -3, -3, 0, + 0, 0, 0, 0, 0, -8, 0, -3, + 0, -4, -3, 0, -6, -6, -8, -2, + 0, -5, 0, -8, 0, 0, 0, 0, + 20, 0, 0, 1, 0, 0, -3, 0, + 0, -11, 0, 0, 0, 0, 0, -24, + -5, 8, 8, -2, -11, 0, 3, -4, + 0, -13, -1, -3, 3, -18, -3, 3, + 0, 4, -9, -4, -9, -8, -11, 0, + 0, -15, 0, 15, 0, 0, -1, 0, + 0, 0, -1, -1, -3, -7, -8, -1, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, -3, 0, -1, -3, -4, 0, + 0, -5, 0, -3, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, -1, 0, -5, 0, 0, 5, + -1, 3, 0, -6, 3, -2, -1, -7, + -3, 0, -3, -3, -2, 0, -4, -4, + 0, 0, -2, -1, -2, -4, -3, 0, + 0, -3, 0, 3, -2, 0, -6, 0, + 0, 0, -5, 0, -4, 0, -4, -4, + 0, 0, 0, 0, 0, 0, 0, 0, + -5, 3, 0, -4, 0, -2, -3, -8, + -2, -2, -2, -1, -2, -3, -1, 0, + 0, 0, 0, 0, -3, -2, -2, 0, + 0, 0, 0, 3, -2, 0, -2, 0, + 0, 0, -2, -3, -2, -2, -3, -2, + 2, 10, -1, 0, -7, 0, -2, 5, + 0, -3, -11, -3, 4, 0, 0, -12, + -4, 3, -4, 2, 0, -2, -2, -8, + 0, -4, 1, 0, 0, -4, 0, 0, + 0, 3, 3, -5, -5, 0, -4, -3, + -4, -3, -3, 0, -4, 1, -5, -4, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 3, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -4, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 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+ 0, 0, -2, 0, -6, 0, 0, 11, + -3, -8, -8, 2, 3, 3, -1, -7, + 2, 4, 2, 8, 2, 8, -2, -7, + 0, 0, -10, 0, 0, -8, -7, 0, + 0, -5, 0, -3, -4, 0, -4, 0, + -4, 0, -2, 4, 0, -2, -8, -3, + 0, 0, -2, 0, -5, 0, 0, 3, + -6, 0, 3, -3, 2, 0, 0, -8, + 0, -2, -1, 0, -3, 3, -2, 0, + 0, 0, -10, -3, -6, 0, -8, 0, + 0, -12, 0, 9, -3, 0, -5, 0, + 2, 0, -3, 0, -3, -8, 0, -3, + 0, 0, 0, 0, -2, 0, 0, 3, + -3, 1, 0, 0, -3, -2, 0, -3, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, -16, 0, 6, 0, 0, -2, 0, + 0, 0, 0, 1, 0, -3, -3, 0 +}; + + +/*Collect the kern class' data in one place*/ +static const lv_font_fmt_txt_kern_classes_t kern_classes = +{ + .class_pair_values = kern_class_values, + .left_class_mapping = kern_left_class_mapping, + .right_class_mapping = kern_right_class_mapping, + .left_class_cnt = 60, + .right_class_cnt = 48, +}; + +/*-------------------- + * ALL CUSTOM DATA + *--------------------*/ + +#if LV_VERSION_CHECK(8, 0, 0) +/*Store all the custom data of the font*/ +static lv_font_fmt_txt_glyph_cache_t cache; +static const lv_font_fmt_txt_dsc_t font_dsc = { +#else +static lv_font_fmt_txt_dsc_t font_dsc = { +#endif + .glyph_bitmap = glyph_bitmap, + .glyph_dsc = glyph_dsc, + .cmaps = cmaps, + .kern_dsc = &kern_classes, + .kern_scale = 16, + .cmap_num = 3, + .bpp = 4, + .kern_classes = 1, + .bitmap_format = 0, +#if LV_VERSION_CHECK(8, 0, 0) + .cache = &cache +#endif +}; + + +/*----------------- + * PUBLIC FONT + *----------------*/ + +/*Initialize a public general font descriptor*/ +#if LV_VERSION_CHECK(8, 0, 0) +const lv_font_t lv_font_montserratMedium_16 = { +#else +lv_font_t lv_font_montserratMedium_16 = { +#endif + .get_glyph_dsc = lv_font_get_glyph_dsc_fmt_txt, /*Function pointer to get glyph's data*/ + .get_glyph_bitmap = lv_font_get_bitmap_fmt_txt, /*Function pointer to get glyph's bitmap*/ + .line_height = 16, /*The maximum line height required by the font default: (f.src.ascent - f.src.descent)*/ + .base_line = 2, /*Baseline measured from the bottom of the line*/ +#if !(LVGL_VERSION_MAJOR == 6 && LVGL_VERSION_MINOR == 0) + .subpx = LV_FONT_SUBPX_NONE, +#endif +#if LV_VERSION_CHECK(7, 4, 0) || LVGL_VERSION_MAJOR >= 8 + .underline_position = -1, + .underline_thickness = 1, +#endif + .dsc = &font_dsc /*The custom font data. Will be accessed by `get_glyph_bitmap/dsc` */ +}; + + + +#endif /*#if LV_FONT_MONTSERRATMEDIUM_16*/ + diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/images/_cbf040c3eda1f28470a3ec0f5384e18e1334bea0_alpha_242x106.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/images/_cbf040c3eda1f28470a3ec0f5384e18e1334bea0_alpha_242x106.c new file mode 100644 index 0000000000000000000000000000000000000000..ae3aafb19807ec09e61f65567495d147062a7f64 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/images/_cbf040c3eda1f28470a3ec0f5384e18e1334bea0_alpha_242x106.c @@ -0,0 +1,463 @@ +#if defined(LV_LVGL_H_INCLUDE_SIMPLE) +#include "lvgl.h" +#else +#include "lvgl/lvgl.h" +#endif + + +#ifndef LV_ATTRIBUTE_MEM_ALIGN +#define LV_ATTRIBUTE_MEM_ALIGN +#endif + +#ifndef LV_ATTRIBUTE_IMG__CBF040C3EDA1F28470A3EC0F5384E18E1334BEA0_ALPHA_242X106 +#define LV_ATTRIBUTE_IMG__CBF040C3EDA1F28470A3EC0F5384E18E1334BEA0_ALPHA_242X106 +#endif + +const LV_ATTRIBUTE_MEM_ALIGN LV_ATTRIBUTE_LARGE_CONST LV_ATTRIBUTE_IMG__CBF040C3EDA1F28470A3EC0F5384E18E1334BEA0_ALPHA_242X106 uint8_t _cbf040c3eda1f28470a3ec0f5384e18e1334bea0_alpha_242x106_map[] = { +#if LV_COLOR_DEPTH == 1 || LV_COLOR_DEPTH == 8 + /*Pixel format: Alpha 8 bit, Red: 3 bit, Green: 3 bit, Blue: 2 bit*/ + 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 0x25, 0xff, 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0x64, 0x0f, 0x17, 0xff, 0x65, 0x0f, 0x17, 0xff, 0x65, 0x0f, 0x17, 0xff, +#endif +}; + +const lv_img_dsc_t _cbf040c3eda1f28470a3ec0f5384e18e1334bea0_alpha_242x106 = { + .header.cf = LV_IMG_CF_TRUE_COLOR_ALPHA, + .header.always_zero = 0, + .header.reserved = 0, + .header.w = 242, + .header.h = 106, + .data_size = 25652 * LV_IMG_PX_SIZE_ALPHA_BYTE, + .data = _cbf040c3eda1f28470a3ec0f5384e18e1334bea0_alpha_242x106_map, +}; diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/images/images_md5.json b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/images/images_md5.json new file mode 100644 index 0000000000000000000000000000000000000000..d088fee13da7a90a4d74361f18344ec709e35699 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/images/images_md5.json @@ -0,0 +1 @@ +{"71419e3f58fc361157e02259885b045c":"bd6f5db75aca18b786b4572093a42ce1ccc2772f6e812bbb31fde9fd9a04d93d","5bf2c99fe4c7644e31fb4e0fd8246ffa":"bd6f5db75aca18b786b4572093a42ce1ccc2772f6e812bbb31fde9fd9a04d93d"} \ No newline at end of file diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/setup_scr_screen.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/setup_scr_screen.c new file mode 100644 index 0000000000000000000000000000000000000000..41dabaee1b4e8a4c382ff0f3f30c76d99fdf2dde --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/setup_scr_screen.c @@ -0,0 +1,1049 @@ +/* +* Copyright 2024 NXP +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in +* accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, +* activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license +* terms, then you may not retain, install, activate or otherwise use the software. +*/ + +#include "lvgl.h" +#include +#include "gui_guider.h" +#include "events_init.h" +#include "widgets_init.h" + + + +void setup_scr_screen(lv_ui *ui) +{ + //Write codes screen + ui->screen = lv_obj_create(NULL); + lv_obj_set_size(ui->screen, 800, 480); + lv_obj_set_scrollbar_mode(ui->screen, LV_SCROLLBAR_MODE_OFF); + + //Write style for screen, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen, LV_GRAD_DIR_HOR, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_color(ui->screen, lv_color_hex(0xbcbad0), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_main_stop(ui->screen, 185, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_stop(ui->screen, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_slider_x_pix + ui->screen_slider_x_pix = lv_slider_create(ui->screen); + lv_slider_set_range(ui->screen_slider_x_pix, 640, 1920); + lv_slider_set_mode(ui->screen_slider_x_pix, LV_SLIDER_MODE_NORMAL); + lv_slider_set_value(ui->screen_slider_x_pix, 640, LV_ANIM_OFF); + lv_obj_set_pos(ui->screen_slider_x_pix, 50, 330); + lv_obj_set_size(ui->screen_slider_x_pix, 700, 30); + + //Write style for screen_slider_x_pix, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_slider_x_pix, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_slider_x_pix, lv_color_hex(0xffffff), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_slider_x_pix, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_slider_x_pix, 50, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_outline_width(ui->screen_slider_x_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_slider_x_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style for screen_slider_x_pix, Part: LV_PART_INDICATOR, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_slider_x_pix, 255, LV_PART_INDICATOR|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_slider_x_pix, lv_color_hex(0xD4CC89), LV_PART_INDICATOR|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_slider_x_pix, LV_GRAD_DIR_NONE, LV_PART_INDICATOR|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_slider_x_pix, 50, LV_PART_INDICATOR|LV_STATE_DEFAULT); + + //Write style for screen_slider_x_pix, Part: LV_PART_KNOB, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_slider_x_pix, 255, LV_PART_KNOB|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_slider_x_pix, lv_color_hex(0x00ed5c), LV_PART_KNOB|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_slider_x_pix, LV_GRAD_DIR_NONE, LV_PART_KNOB|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_slider_x_pix, 50, LV_PART_KNOB|LV_STATE_DEFAULT); + + //Write codes screen_cont_mode_control + ui->screen_cont_mode_control = lv_obj_create(ui->screen); + lv_obj_set_pos(ui->screen_cont_mode_control, 20, 109); + lv_obj_set_size(ui->screen_cont_mode_control, 760, 150); + lv_obj_set_scrollbar_mode(ui->screen_cont_mode_control, LV_SCROLLBAR_MODE_OFF); + + //Write style for screen_cont_mode_control, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_cont_mode_control, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_cont_mode_control, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_cont_mode_control, 141, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_cont_mode_control, lv_color_hex(0xffffff), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_cont_mode_control, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_cont_mode_control, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_cont_mode_control, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_cont_mode_control, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_cont_mode_control, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_cont_mode_control, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_label_1 + ui->screen_label_1 = lv_label_create(ui->screen_cont_mode_control); + lv_label_set_text(ui->screen_label_1, "模式选择"); + lv_label_set_long_mode(ui->screen_label_1, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_1, 6, 7); + lv_obj_set_size(ui->screen_label_1, 134, 32); + + //Write style for screen_label_1, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_label_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_1, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_1, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_1, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_1, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_1, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_label_1, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_label_1, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_label_1, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_btn_hand_set + ui->screen_btn_hand_set = lv_btn_create(ui->screen_cont_mode_control); + ui->screen_btn_hand_set_label = lv_label_create(ui->screen_btn_hand_set); + lv_label_set_text(ui->screen_btn_hand_set_label, "手动模式"); + lv_label_set_long_mode(ui->screen_btn_hand_set_label, LV_LABEL_LONG_WRAP); + lv_obj_align(ui->screen_btn_hand_set_label, LV_ALIGN_CENTER, 0, 0); + lv_obj_set_style_pad_all(ui->screen_btn_hand_set, 0, LV_STATE_DEFAULT); + lv_obj_set_width(ui->screen_btn_hand_set_label, LV_PCT(100)); + lv_obj_set_pos(ui->screen_btn_hand_set, 65, 40); + lv_obj_set_size(ui->screen_btn_hand_set, 125, 70); + + //Write style for screen_btn_hand_set, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_btn_hand_set, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_btn_hand_set, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_btn_hand_set, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_width(ui->screen_btn_hand_set, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_btn_hand_set, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_btn_hand_set, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_color(ui->screen_btn_hand_set, lv_color_hex(0x000000), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_opa(ui->screen_btn_hand_set, 79, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_spread(ui->screen_btn_hand_set, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_x(ui->screen_btn_hand_set, -4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_y(ui->screen_btn_hand_set, 4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_btn_hand_set, lv_color_hex(0xD4C988), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_btn_hand_set, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_btn_hand_set, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_btn_hand_set, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_btn_demo_linear + ui->screen_btn_demo_linear = lv_btn_create(ui->screen_cont_mode_control); + ui->screen_btn_demo_linear_label = lv_label_create(ui->screen_btn_demo_linear); + lv_label_set_text(ui->screen_btn_demo_linear_label, "线性缩放动画演示"); + lv_label_set_long_mode(ui->screen_btn_demo_linear_label, LV_LABEL_LONG_WRAP); + lv_obj_align(ui->screen_btn_demo_linear_label, LV_ALIGN_CENTER, 0, 0); + lv_obj_set_style_pad_all(ui->screen_btn_demo_linear, 0, LV_STATE_DEFAULT); + lv_obj_set_width(ui->screen_btn_demo_linear_label, LV_PCT(100)); + lv_obj_set_pos(ui->screen_btn_demo_linear, 450, 15); + lv_obj_set_size(ui->screen_btn_demo_linear, 263, 50); + + //Write style for screen_btn_demo_linear, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_btn_demo_linear, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_btn_demo_linear, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_btn_demo_linear, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_width(ui->screen_btn_demo_linear, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_btn_demo_linear, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_btn_demo_linear, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_color(ui->screen_btn_demo_linear, lv_color_hex(0x000000), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_opa(ui->screen_btn_demo_linear, 79, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_spread(ui->screen_btn_demo_linear, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_x(ui->screen_btn_demo_linear, -4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_y(ui->screen_btn_demo_linear, 4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_btn_demo_linear, lv_color_hex(0xD4C988), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_btn_demo_linear, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_btn_demo_linear, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_btn_demo_linear, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_btn_demo_nonlinear + ui->screen_btn_demo_nonlinear = lv_btn_create(ui->screen_cont_mode_control); + ui->screen_btn_demo_nonlinear_label = lv_label_create(ui->screen_btn_demo_nonlinear); + lv_label_set_text(ui->screen_btn_demo_nonlinear_label, "非线性缩放动画演示"); + lv_label_set_long_mode(ui->screen_btn_demo_nonlinear_label, LV_LABEL_LONG_WRAP); + lv_obj_align(ui->screen_btn_demo_nonlinear_label, LV_ALIGN_CENTER, 0, 0); + lv_obj_set_style_pad_all(ui->screen_btn_demo_nonlinear, 0, LV_STATE_DEFAULT); + lv_obj_set_width(ui->screen_btn_demo_nonlinear_label, LV_PCT(100)); + lv_obj_set_pos(ui->screen_btn_demo_nonlinear, 450, 85); + lv_obj_set_size(ui->screen_btn_demo_nonlinear, 265, 50); + + //Write style for screen_btn_demo_nonlinear, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_btn_demo_nonlinear, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_btn_demo_nonlinear, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_btn_demo_nonlinear, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_width(ui->screen_btn_demo_nonlinear, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_btn_demo_nonlinear, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_btn_demo_nonlinear, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_color(ui->screen_btn_demo_nonlinear, lv_color_hex(0x000000), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_opa(ui->screen_btn_demo_nonlinear, 79, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_spread(ui->screen_btn_demo_nonlinear, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_x(ui->screen_btn_demo_nonlinear, -4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_y(ui->screen_btn_demo_nonlinear, 4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_btn_demo_nonlinear, lv_color_hex(0xD4C988), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_btn_demo_nonlinear, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_btn_demo_nonlinear, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_btn_demo_nonlinear, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_cont_1 + ui->screen_cont_1 = lv_obj_create(ui->screen_cont_mode_control); + lv_obj_set_pos(ui->screen_cont_1, 235, 25); + lv_obj_set_size(ui->screen_cont_1, 170, 100); + lv_obj_set_scrollbar_mode(ui->screen_cont_1, LV_SCROLLBAR_MODE_OFF); + + //Write style for screen_cont_1, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_cont_1, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_cont_1, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_cont_1, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_cont_1, LV_BORDER_SIDE_FULL, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_cont_1, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_cont_1, 166, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_cont_1, lv_color_hex(0xe1dcae), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_cont_1, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_cont_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_cont_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_cont_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_cont_1, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_cont_1, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_color(ui->screen_cont_1, lv_color_hex(0x000000), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_opa(ui->screen_cont_1, 77, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_spread(ui->screen_cont_1, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_x(ui->screen_cont_1, -4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_y(ui->screen_cont_1, 4, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_ddlist_nonlinear + ui->screen_ddlist_nonlinear = lv_dropdown_create(ui->screen_cont_1); + lv_dropdown_set_options(ui->screen_ddlist_nonlinear, "Bounce\nCirc\nQuint"); + lv_obj_set_pos(ui->screen_ddlist_nonlinear, 17, 40); + lv_obj_set_size(ui->screen_ddlist_nonlinear, 130, 46); + + //Write style for screen_ddlist_nonlinear, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_ddlist_nonlinear, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_ddlist_nonlinear, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_ddlist_nonlinear, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_ddlist_nonlinear, LV_BORDER_SIDE_FULL, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_ddlist_nonlinear, 3, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_ddlist_nonlinear, lv_color_hex(0x0D3055), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_ddlist_nonlinear, &lv_font_MI_LanTing_Regular_24, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_ddlist_nonlinear, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_ddlist_nonlinear, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_ddlist_nonlinear, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_ddlist_nonlinear, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_ddlist_nonlinear, 8, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_ddlist_nonlinear, 6, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_ddlist_nonlinear, 6, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_ddlist_nonlinear, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style state: LV_STATE_CHECKED for &style_screen_ddlist_nonlinear_extra_list_selected_checked + static lv_style_t style_screen_ddlist_nonlinear_extra_list_selected_checked; + ui_init_style(&style_screen_ddlist_nonlinear_extra_list_selected_checked); + + lv_style_set_border_width(&style_screen_ddlist_nonlinear_extra_list_selected_checked, 1); + lv_style_set_border_opa(&style_screen_ddlist_nonlinear_extra_list_selected_checked, 255); + lv_style_set_border_color(&style_screen_ddlist_nonlinear_extra_list_selected_checked, lv_color_hex(0xe1e6ee)); + lv_style_set_border_side(&style_screen_ddlist_nonlinear_extra_list_selected_checked, LV_BORDER_SIDE_FULL); + lv_style_set_radius(&style_screen_ddlist_nonlinear_extra_list_selected_checked, 3); + lv_style_set_bg_opa(&style_screen_ddlist_nonlinear_extra_list_selected_checked, 255); + lv_style_set_bg_color(&style_screen_ddlist_nonlinear_extra_list_selected_checked, lv_color_hex(0x00a1b5)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_nonlinear_extra_list_selected_checked, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_nonlinear), &style_screen_ddlist_nonlinear_extra_list_selected_checked, LV_PART_SELECTED|LV_STATE_CHECKED); + + //Write style state: LV_STATE_DEFAULT for &style_screen_ddlist_nonlinear_extra_list_main_default + static lv_style_t style_screen_ddlist_nonlinear_extra_list_main_default; + ui_init_style(&style_screen_ddlist_nonlinear_extra_list_main_default); + + lv_style_set_max_height(&style_screen_ddlist_nonlinear_extra_list_main_default, 90); + lv_style_set_text_color(&style_screen_ddlist_nonlinear_extra_list_main_default, lv_color_hex(0x0D3055)); + lv_style_set_text_font(&style_screen_ddlist_nonlinear_extra_list_main_default, &lv_font_MI_LanTing_Regular_12); + lv_style_set_text_opa(&style_screen_ddlist_nonlinear_extra_list_main_default, 255); + lv_style_set_border_width(&style_screen_ddlist_nonlinear_extra_list_main_default, 1); + lv_style_set_border_opa(&style_screen_ddlist_nonlinear_extra_list_main_default, 255); + lv_style_set_border_color(&style_screen_ddlist_nonlinear_extra_list_main_default, lv_color_hex(0xe1e6ee)); + lv_style_set_border_side(&style_screen_ddlist_nonlinear_extra_list_main_default, LV_BORDER_SIDE_FULL); + lv_style_set_radius(&style_screen_ddlist_nonlinear_extra_list_main_default, 3); + lv_style_set_bg_opa(&style_screen_ddlist_nonlinear_extra_list_main_default, 255); + lv_style_set_bg_color(&style_screen_ddlist_nonlinear_extra_list_main_default, lv_color_hex(0xffffff)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_nonlinear_extra_list_main_default, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_nonlinear), &style_screen_ddlist_nonlinear_extra_list_main_default, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style state: LV_STATE_DEFAULT for &style_screen_ddlist_nonlinear_extra_list_scrollbar_default + static lv_style_t style_screen_ddlist_nonlinear_extra_list_scrollbar_default; + ui_init_style(&style_screen_ddlist_nonlinear_extra_list_scrollbar_default); + + lv_style_set_radius(&style_screen_ddlist_nonlinear_extra_list_scrollbar_default, 3); + lv_style_set_bg_opa(&style_screen_ddlist_nonlinear_extra_list_scrollbar_default, 255); + lv_style_set_bg_color(&style_screen_ddlist_nonlinear_extra_list_scrollbar_default, lv_color_hex(0x00ff00)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_nonlinear_extra_list_scrollbar_default, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_nonlinear), &style_screen_ddlist_nonlinear_extra_list_scrollbar_default, LV_PART_SCROLLBAR|LV_STATE_DEFAULT); + + //Write codes screen_label_2 + ui->screen_label_2 = lv_label_create(ui->screen_cont_1); + lv_label_set_text(ui->screen_label_2, "非线性动画类型"); + lv_label_set_long_mode(ui->screen_label_2, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_2, 12, 11); + lv_obj_set_size(ui->screen_label_2, 140, 18); + + //Write style for screen_label_2, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_label_2, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_2, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_width(ui->screen_label_2, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_2, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_2, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_2, &lv_font_MI_LanTing_Regular_18, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_2, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_2, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_2, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_2, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_2, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_2, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_2, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_2, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_btn_select + ui->screen_btn_select = lv_btn_create(ui->screen_cont_mode_control); + ui->screen_btn_select_label = lv_label_create(ui->screen_btn_select); + lv_label_set_text(ui->screen_btn_select_label, ""); + lv_label_set_long_mode(ui->screen_btn_select_label, LV_LABEL_LONG_WRAP); + lv_obj_align(ui->screen_btn_select_label, LV_ALIGN_CENTER, 0, 0); + lv_obj_set_style_pad_all(ui->screen_btn_select, 0, LV_STATE_DEFAULT); + lv_obj_set_width(ui->screen_btn_select_label, LV_PCT(100)); + lv_obj_set_pos(ui->screen_btn_select, 65, 40); + lv_obj_set_size(ui->screen_btn_select, 125, 70); + + //Write style for screen_btn_select, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_btn_select, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_width(ui->screen_btn_select, 6, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_btn_select, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_btn_select, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_btn_select, LV_BORDER_SIDE_FULL, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_btn_select, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_btn_select, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_color(ui->screen_btn_select, lv_color_hex(0x000000), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_opa(ui->screen_btn_select, 79, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_spread(ui->screen_btn_select, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_x(ui->screen_btn_select, -4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_y(ui->screen_btn_select, 4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_btn_select, lv_color_hex(0xD4C988), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_btn_select, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_btn_select, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_btn_select, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_label_x_pix_ + ui->screen_label_x_pix_ = lv_label_create(ui->screen); + lv_label_set_text(ui->screen_label_x_pix_, "水平像素数："); + lv_label_set_long_mode(ui->screen_label_x_pix_, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_x_pix_, 50, 270); + lv_obj_set_size(ui->screen_label_x_pix_, 173, 32); + + //Write style for screen_label_x_pix_, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_label_x_pix_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_x_pix_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_x_pix_, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_x_pix_, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_x_pix_, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_x_pix_, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_x_pix_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_x_pix_, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_label_x_pix_, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_label_x_pix_, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_label_x_pix_, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_x_pix_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_x_pix_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_x_pix_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_x_pix_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_x_pix_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_label_y_pix_len_ + ui->screen_label_y_pix_len_ = lv_label_create(ui->screen); + lv_label_set_text(ui->screen_label_y_pix_len_, "垂直像素数："); + lv_label_set_long_mode(ui->screen_label_y_pix_len_, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_y_pix_len_, 50, 375); + lv_obj_set_size(ui->screen_label_y_pix_len_, 173, 32); + + //Write style for screen_label_y_pix_len_, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_label_y_pix_len_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_y_pix_len_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_y_pix_len_, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_y_pix_len_, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_y_pix_len_, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_y_pix_len_, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_y_pix_len_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_y_pix_len_, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_label_y_pix_len_, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_label_y_pix_len_, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_label_y_pix_len_, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_y_pix_len_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_y_pix_len_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_y_pix_len_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_y_pix_len_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_y_pix_len_, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_label_y_pix + ui->screen_label_y_pix = lv_label_create(ui->screen); + lv_label_set_text(ui->screen_label_y_pix, "480"); + lv_label_set_long_mode(ui->screen_label_y_pix, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_y_pix, 230, 375); + lv_obj_set_size(ui->screen_label_y_pix, 80, 32); + + //Write style for screen_label_y_pix, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_label_y_pix, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_label_y_pix, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_label_y_pix, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_label_y_pix, LV_BORDER_SIDE_FULL, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_y_pix, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_y_pix, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_y_pix, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_y_pix, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_y_pix, 1, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_y_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_y_pix, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_label_y_pix, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_label_y_pix, lv_color_hex(0xffffff), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_label_y_pix, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_y_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_y_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_y_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_y_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_y_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_label_x_pix + ui->screen_label_x_pix = lv_label_create(ui->screen); + lv_label_set_text(ui->screen_label_x_pix, "640"); + lv_label_set_long_mode(ui->screen_label_x_pix, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_x_pix, 230, 270); + lv_obj_set_size(ui->screen_label_x_pix, 80, 32); + + //Write style for screen_label_x_pix, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_label_x_pix, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_label_x_pix, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_label_x_pix, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_label_x_pix, LV_BORDER_SIDE_FULL, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_x_pix, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_x_pix, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_x_pix, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_x_pix, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_x_pix, 1, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_x_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_x_pix, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_label_x_pix, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_label_x_pix, lv_color_hex(0xffffff), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_label_x_pix, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_x_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_x_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_x_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_x_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_x_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_img_1 + ui->screen_img_1 = lv_img_create(ui->screen); + lv_obj_add_flag(ui->screen_img_1, LV_OBJ_FLAG_CLICKABLE); + lv_img_set_src(ui->screen_img_1, &_cbf040c3eda1f28470a3ec0f5384e18e1334bea0_alpha_242x106); + lv_img_set_pivot(ui->screen_img_1, 50,50); + lv_img_set_angle(ui->screen_img_1, 0); + lv_obj_set_pos(ui->screen_img_1, 279, 0); + lv_obj_set_size(ui->screen_img_1, 242, 106); + + //Write style for screen_img_1, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_img_opa(ui->screen_img_1, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_ddlist_min + ui->screen_ddlist_min = lv_dropdown_create(ui->screen); + lv_dropdown_set_options(ui->screen_ddlist_min, " 640\n 320\n 160"); + lv_obj_set_pos(ui->screen_ddlist_min, 690, 25); + lv_obj_set_size(ui->screen_ddlist_min, 90, 36); + + //Write style for screen_ddlist_min, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_text_color(ui->screen_ddlist_min, lv_color_hex(0x0D3055), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_ddlist_min, &lv_font_MI_LanTing_Regular_18, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_ddlist_min, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_width(ui->screen_ddlist_min, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_ddlist_min, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_ddlist_min, lv_color_hex(0x706d9a), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_ddlist_min, LV_BORDER_SIDE_FULL, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_ddlist_min, 8, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_ddlist_min, 6, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_ddlist_min, 6, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_ddlist_min, 3, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_ddlist_min, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_ddlist_min, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_ddlist_min, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_ddlist_min, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style state: LV_STATE_CHECKED for &style_screen_ddlist_min_extra_list_selected_checked + static lv_style_t style_screen_ddlist_min_extra_list_selected_checked; + ui_init_style(&style_screen_ddlist_min_extra_list_selected_checked); + + lv_style_set_border_width(&style_screen_ddlist_min_extra_list_selected_checked, 1); + lv_style_set_border_opa(&style_screen_ddlist_min_extra_list_selected_checked, 255); + lv_style_set_border_color(&style_screen_ddlist_min_extra_list_selected_checked, lv_color_hex(0xe1e6ee)); + lv_style_set_border_side(&style_screen_ddlist_min_extra_list_selected_checked, LV_BORDER_SIDE_FULL); + lv_style_set_radius(&style_screen_ddlist_min_extra_list_selected_checked, 3); + lv_style_set_bg_opa(&style_screen_ddlist_min_extra_list_selected_checked, 255); + lv_style_set_bg_color(&style_screen_ddlist_min_extra_list_selected_checked, lv_color_hex(0x00a1b5)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_min_extra_list_selected_checked, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_min), &style_screen_ddlist_min_extra_list_selected_checked, LV_PART_SELECTED|LV_STATE_CHECKED); + + //Write style state: LV_STATE_DEFAULT for &style_screen_ddlist_min_extra_list_main_default + static lv_style_t style_screen_ddlist_min_extra_list_main_default; + ui_init_style(&style_screen_ddlist_min_extra_list_main_default); + + lv_style_set_max_height(&style_screen_ddlist_min_extra_list_main_default, 90); + lv_style_set_text_color(&style_screen_ddlist_min_extra_list_main_default, lv_color_hex(0x0D3055)); + lv_style_set_text_font(&style_screen_ddlist_min_extra_list_main_default, &lv_font_MI_LanTing_Regular_12); + lv_style_set_text_opa(&style_screen_ddlist_min_extra_list_main_default, 255); + lv_style_set_border_width(&style_screen_ddlist_min_extra_list_main_default, 1); + lv_style_set_border_opa(&style_screen_ddlist_min_extra_list_main_default, 255); + lv_style_set_border_color(&style_screen_ddlist_min_extra_list_main_default, lv_color_hex(0xe1e6ee)); + lv_style_set_border_side(&style_screen_ddlist_min_extra_list_main_default, LV_BORDER_SIDE_FULL); + lv_style_set_radius(&style_screen_ddlist_min_extra_list_main_default, 3); + lv_style_set_bg_opa(&style_screen_ddlist_min_extra_list_main_default, 255); + lv_style_set_bg_color(&style_screen_ddlist_min_extra_list_main_default, lv_color_hex(0xffffff)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_min_extra_list_main_default, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_min), &style_screen_ddlist_min_extra_list_main_default, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style state: LV_STATE_DEFAULT for &style_screen_ddlist_min_extra_list_scrollbar_default + static lv_style_t style_screen_ddlist_min_extra_list_scrollbar_default; + ui_init_style(&style_screen_ddlist_min_extra_list_scrollbar_default); + + lv_style_set_radius(&style_screen_ddlist_min_extra_list_scrollbar_default, 3); + lv_style_set_bg_opa(&style_screen_ddlist_min_extra_list_scrollbar_default, 255); + lv_style_set_bg_color(&style_screen_ddlist_min_extra_list_scrollbar_default, lv_color_hex(0x00ff00)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_min_extra_list_scrollbar_default, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_min), &style_screen_ddlist_min_extra_list_scrollbar_default, LV_PART_SCROLLBAR|LV_STATE_DEFAULT); + + //Write codes screen_ddlist_max + ui->screen_ddlist_max = lv_dropdown_create(ui->screen); + lv_dropdown_set_options(ui->screen_ddlist_max, " 1920"); + lv_obj_set_pos(ui->screen_ddlist_max, 563, 25); + lv_obj_set_size(ui->screen_ddlist_max, 90, 36); + + //Write style for screen_ddlist_max, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_text_color(ui->screen_ddlist_max, lv_color_hex(0x0D3055), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_ddlist_max, &lv_font_MI_LanTing_Regular_18, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_ddlist_max, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_width(ui->screen_ddlist_max, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_ddlist_max, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_ddlist_max, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_ddlist_max, LV_BORDER_SIDE_FULL, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_ddlist_max, 8, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_ddlist_max, 6, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_ddlist_max, 6, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_ddlist_max, 3, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_ddlist_max, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_ddlist_max, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_ddlist_max, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_ddlist_max, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style state: LV_STATE_CHECKED for &style_screen_ddlist_max_extra_list_selected_checked + static lv_style_t style_screen_ddlist_max_extra_list_selected_checked; + ui_init_style(&style_screen_ddlist_max_extra_list_selected_checked); + + lv_style_set_border_width(&style_screen_ddlist_max_extra_list_selected_checked, 1); + lv_style_set_border_opa(&style_screen_ddlist_max_extra_list_selected_checked, 255); + lv_style_set_border_color(&style_screen_ddlist_max_extra_list_selected_checked, lv_color_hex(0xe1e6ee)); + lv_style_set_border_side(&style_screen_ddlist_max_extra_list_selected_checked, LV_BORDER_SIDE_FULL); + lv_style_set_radius(&style_screen_ddlist_max_extra_list_selected_checked, 3); + lv_style_set_bg_opa(&style_screen_ddlist_max_extra_list_selected_checked, 255); + lv_style_set_bg_color(&style_screen_ddlist_max_extra_list_selected_checked, lv_color_hex(0x00a1b5)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_max_extra_list_selected_checked, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_max), &style_screen_ddlist_max_extra_list_selected_checked, LV_PART_SELECTED|LV_STATE_CHECKED); + + //Write style state: LV_STATE_DEFAULT for &style_screen_ddlist_max_extra_list_main_default + static lv_style_t style_screen_ddlist_max_extra_list_main_default; + ui_init_style(&style_screen_ddlist_max_extra_list_main_default); + + lv_style_set_max_height(&style_screen_ddlist_max_extra_list_main_default, 90); + lv_style_set_text_color(&style_screen_ddlist_max_extra_list_main_default, lv_color_hex(0x0D3055)); + lv_style_set_text_font(&style_screen_ddlist_max_extra_list_main_default, &lv_font_MI_LanTing_Regular_12); + lv_style_set_text_opa(&style_screen_ddlist_max_extra_list_main_default, 255); + lv_style_set_border_width(&style_screen_ddlist_max_extra_list_main_default, 1); + lv_style_set_border_opa(&style_screen_ddlist_max_extra_list_main_default, 255); + lv_style_set_border_color(&style_screen_ddlist_max_extra_list_main_default, lv_color_hex(0xe1e6ee)); + lv_style_set_border_side(&style_screen_ddlist_max_extra_list_main_default, LV_BORDER_SIDE_FULL); + lv_style_set_radius(&style_screen_ddlist_max_extra_list_main_default, 3); + lv_style_set_bg_opa(&style_screen_ddlist_max_extra_list_main_default, 255); + lv_style_set_bg_color(&style_screen_ddlist_max_extra_list_main_default, lv_color_hex(0xffffff)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_max_extra_list_main_default, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_max), &style_screen_ddlist_max_extra_list_main_default, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style state: LV_STATE_DEFAULT for &style_screen_ddlist_max_extra_list_scrollbar_default + static lv_style_t style_screen_ddlist_max_extra_list_scrollbar_default; + ui_init_style(&style_screen_ddlist_max_extra_list_scrollbar_default); + + lv_style_set_radius(&style_screen_ddlist_max_extra_list_scrollbar_default, 3); + lv_style_set_bg_opa(&style_screen_ddlist_max_extra_list_scrollbar_default, 255); + lv_style_set_bg_color(&style_screen_ddlist_max_extra_list_scrollbar_default, lv_color_hex(0x00ff00)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_max_extra_list_scrollbar_default, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_max), &style_screen_ddlist_max_extra_list_scrollbar_default, LV_PART_SCROLLBAR|LV_STATE_DEFAULT); + + //Write codes screen_label_3 + ui->screen_label_3 = lv_label_create(ui->screen); + lv_label_set_text(ui->screen_label_3, "最大宽度"); + lv_label_set_long_mode(ui->screen_label_3, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_3, 563, 61); + lv_obj_set_size(ui->screen_label_3, 90, 20); + + //Write style for screen_label_3, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_label_3, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_3, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_3, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_3, &lv_font_MI_LanTing_Regular_18, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_3, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_3, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_3, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_3, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_label_3, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_label_3, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_label_3, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_3, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_3, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_3, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_3, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_3, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_label_4 + ui->screen_label_4 = lv_label_create(ui->screen); + lv_label_set_text(ui->screen_label_4, "最小宽度"); + lv_label_set_long_mode(ui->screen_label_4, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_4, 690, 61); + lv_obj_set_size(ui->screen_label_4, 90, 20); + + //Write style for screen_label_4, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_label_4, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_4, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_4, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_4, &lv_font_MI_LanTing_Regular_18, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_4, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_4, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_4, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_4, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_label_4, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_label_4, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_label_4, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_4, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_4, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_4, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_4, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_4, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_slider_y_pix + ui->screen_slider_y_pix = lv_slider_create(ui->screen); + lv_slider_set_range(ui->screen_slider_y_pix, 480, 1080); + lv_slider_set_mode(ui->screen_slider_y_pix, LV_SLIDER_MODE_NORMAL); + lv_slider_set_value(ui->screen_slider_y_pix, 480, LV_ANIM_OFF); + lv_obj_set_pos(ui->screen_slider_y_pix, 50, 435); + lv_obj_set_size(ui->screen_slider_y_pix, 700, 30); + + //Write style for screen_slider_y_pix, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_slider_y_pix, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_slider_y_pix, lv_color_hex(0xffffff), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_slider_y_pix, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_slider_y_pix, 50, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_outline_width(ui->screen_slider_y_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_slider_y_pix, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style for screen_slider_y_pix, Part: LV_PART_INDICATOR, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_slider_y_pix, 255, LV_PART_INDICATOR|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_slider_y_pix, lv_color_hex(0xD4CC89), LV_PART_INDICATOR|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_slider_y_pix, LV_GRAD_DIR_NONE, LV_PART_INDICATOR|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_slider_y_pix, 50, LV_PART_INDICATOR|LV_STATE_DEFAULT); + + //Write style for screen_slider_y_pix, Part: LV_PART_KNOB, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_slider_y_pix, 255, LV_PART_KNOB|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_slider_y_pix, lv_color_hex(0x00ed5c), LV_PART_KNOB|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_slider_y_pix, LV_GRAD_DIR_NONE, LV_PART_KNOB|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_slider_y_pix, 50, LV_PART_KNOB|LV_STATE_DEFAULT); + + //Write codes screen_btnm_x_pic + ui->screen_btnm_x_pic = lv_btnmatrix_create(ui->screen); + static const char *screen_btnm_x_pic_text_map[] = {"-", "+", "",}; + lv_btnmatrix_set_map(ui->screen_btnm_x_pic, screen_btnm_x_pic_text_map); + lv_obj_set_pos(ui->screen_btnm_x_pic, 345, 265); + lv_obj_set_size(ui->screen_btnm_x_pic, 358, 55); + + //Write style for screen_btnm_x_pic, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_btnm_x_pic, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_btnm_x_pic, 4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_btnm_x_pic, 4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_btnm_x_pic, 20, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_btnm_x_pic, 20, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_row(ui->screen_btnm_x_pic, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_column(ui->screen_btnm_x_pic, 25, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_btnm_x_pic, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_btnm_x_pic, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_btnm_x_pic, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_btnm_x_pic, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style for screen_btnm_x_pic, Part: LV_PART_ITEMS, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_btnm_x_pic, 1, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_btnm_x_pic, 255, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_btnm_x_pic, lv_color_hex(0xc9c9c9), LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_btnm_x_pic, LV_BORDER_SIDE_FULL, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_btnm_x_pic, lv_color_hex(0xD4C988), LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_btnm_x_pic, &lv_font_MI_LanTing_Regular_28, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_btnm_x_pic, 255, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_btnm_x_pic, 4, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_btnm_x_pic, 255, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_btnm_x_pic, lv_color_hex(0x18125C), LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_btnm_x_pic, LV_GRAD_DIR_NONE, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_btnm_x_pic, 0, LV_PART_ITEMS|LV_STATE_DEFAULT); + + //Write codes screen_btnm_y_pic + ui->screen_btnm_y_pic = lv_btnmatrix_create(ui->screen); + static const char *screen_btnm_y_pic_text_map[] = {"-", "+", "",}; + lv_btnmatrix_set_map(ui->screen_btnm_y_pic, screen_btnm_y_pic_text_map); + lv_obj_set_pos(ui->screen_btnm_y_pic, 345, 368); + lv_obj_set_size(ui->screen_btnm_y_pic, 358, 55); + + //Write style for screen_btnm_y_pic, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_btnm_y_pic, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_btnm_y_pic, 4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_btnm_y_pic, 4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_btnm_y_pic, 20, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_btnm_y_pic, 20, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_row(ui->screen_btnm_y_pic, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_column(ui->screen_btnm_y_pic, 25, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_btnm_y_pic, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_btnm_y_pic, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_btnm_y_pic, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_btnm_y_pic, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style for screen_btnm_y_pic, Part: LV_PART_ITEMS, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_btnm_y_pic, 1, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_btnm_y_pic, 255, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_btnm_y_pic, lv_color_hex(0xc9c9c9), LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_btnm_y_pic, LV_BORDER_SIDE_FULL, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_btnm_y_pic, lv_color_hex(0xD4C988), LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_btnm_y_pic, &lv_font_MI_LanTing_Regular_28, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_btnm_y_pic, 255, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_btnm_y_pic, 4, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_btnm_y_pic, 255, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_btnm_y_pic, lv_color_hex(0x18125C), LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_btnm_y_pic, LV_GRAD_DIR_NONE, LV_PART_ITEMS|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_btnm_y_pic, 0, LV_PART_ITEMS|LV_STATE_DEFAULT); + + //Write codes screen_label_vid_format + ui->screen_label_vid_format = lv_label_create(ui->screen); + lv_label_set_text(ui->screen_label_vid_format, "输出格式"); + lv_label_set_long_mode(ui->screen_label_vid_format, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_vid_format, 30, 61); + lv_obj_set_size(ui->screen_label_vid_format, 120, 20); + + //Write style for screen_label_vid_format, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_label_vid_format, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_vid_format, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_vid_format, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_vid_format, &lv_font_MI_LanTing_Regular_18, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_vid_format, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_vid_format, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_vid_format, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_vid_format, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_label_vid_format, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_label_vid_format, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_label_vid_format, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_vid_format, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_vid_format, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_vid_format, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_vid_format, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_vid_format, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_label_6 + ui->screen_label_6 = lv_label_create(ui->screen); + lv_label_set_text(ui->screen_label_6, "缩放算法"); + lv_label_set_long_mode(ui->screen_label_6, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_6, 173, 61); + lv_obj_set_size(ui->screen_label_6, 90, 20); + + //Write style for screen_label_6, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_label_6, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_6, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_6, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_6, &lv_font_MI_LanTing_Regular_18, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_6, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_6, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_6, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_6, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_label_6, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_label_6, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_label_6, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_6, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_6, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_6, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_6, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_6, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_ddlist_vid_format + ui->screen_ddlist_vid_format = lv_dropdown_create(ui->screen); + lv_dropdown_set_options(ui->screen_ddlist_vid_format, "1080p@60\n2k@30"); + lv_obj_set_pos(ui->screen_ddlist_vid_format, 30, 25); + lv_obj_set_size(ui->screen_ddlist_vid_format, 120, 36); + + //Write style for screen_ddlist_vid_format, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_text_color(ui->screen_ddlist_vid_format, lv_color_hex(0x0D3055), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_ddlist_vid_format, &lv_font_MI_LanTing_Regular_18, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_ddlist_vid_format, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_width(ui->screen_ddlist_vid_format, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_ddlist_vid_format, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_ddlist_vid_format, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_ddlist_vid_format, LV_BORDER_SIDE_FULL, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_ddlist_vid_format, 8, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_ddlist_vid_format, 6, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_ddlist_vid_format, 6, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_ddlist_vid_format, 3, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_ddlist_vid_format, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_ddlist_vid_format, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_ddlist_vid_format, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_ddlist_vid_format, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style state: LV_STATE_CHECKED for &style_screen_ddlist_vid_format_extra_list_selected_checked + static lv_style_t style_screen_ddlist_vid_format_extra_list_selected_checked; + ui_init_style(&style_screen_ddlist_vid_format_extra_list_selected_checked); + + lv_style_set_border_width(&style_screen_ddlist_vid_format_extra_list_selected_checked, 1); + lv_style_set_border_opa(&style_screen_ddlist_vid_format_extra_list_selected_checked, 255); + lv_style_set_border_color(&style_screen_ddlist_vid_format_extra_list_selected_checked, lv_color_hex(0xe1e6ee)); + lv_style_set_border_side(&style_screen_ddlist_vid_format_extra_list_selected_checked, LV_BORDER_SIDE_FULL); + lv_style_set_radius(&style_screen_ddlist_vid_format_extra_list_selected_checked, 3); + lv_style_set_bg_opa(&style_screen_ddlist_vid_format_extra_list_selected_checked, 255); + lv_style_set_bg_color(&style_screen_ddlist_vid_format_extra_list_selected_checked, lv_color_hex(0x00a1b5)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_vid_format_extra_list_selected_checked, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_vid_format), &style_screen_ddlist_vid_format_extra_list_selected_checked, LV_PART_SELECTED|LV_STATE_CHECKED); + + //Write style state: LV_STATE_DEFAULT for &style_screen_ddlist_vid_format_extra_list_main_default + static lv_style_t style_screen_ddlist_vid_format_extra_list_main_default; + ui_init_style(&style_screen_ddlist_vid_format_extra_list_main_default); + + lv_style_set_max_height(&style_screen_ddlist_vid_format_extra_list_main_default, 90); + lv_style_set_text_color(&style_screen_ddlist_vid_format_extra_list_main_default, lv_color_hex(0x0D3055)); + lv_style_set_text_font(&style_screen_ddlist_vid_format_extra_list_main_default, &lv_font_MI_LanTing_Regular_12); + lv_style_set_text_opa(&style_screen_ddlist_vid_format_extra_list_main_default, 255); + lv_style_set_border_width(&style_screen_ddlist_vid_format_extra_list_main_default, 1); + lv_style_set_border_opa(&style_screen_ddlist_vid_format_extra_list_main_default, 255); + lv_style_set_border_color(&style_screen_ddlist_vid_format_extra_list_main_default, lv_color_hex(0xe1e6ee)); + lv_style_set_border_side(&style_screen_ddlist_vid_format_extra_list_main_default, LV_BORDER_SIDE_FULL); + lv_style_set_radius(&style_screen_ddlist_vid_format_extra_list_main_default, 3); + lv_style_set_bg_opa(&style_screen_ddlist_vid_format_extra_list_main_default, 255); + lv_style_set_bg_color(&style_screen_ddlist_vid_format_extra_list_main_default, lv_color_hex(0xffffff)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_vid_format_extra_list_main_default, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_vid_format), &style_screen_ddlist_vid_format_extra_list_main_default, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style state: LV_STATE_DEFAULT for &style_screen_ddlist_vid_format_extra_list_scrollbar_default + static lv_style_t style_screen_ddlist_vid_format_extra_list_scrollbar_default; + ui_init_style(&style_screen_ddlist_vid_format_extra_list_scrollbar_default); + + lv_style_set_radius(&style_screen_ddlist_vid_format_extra_list_scrollbar_default, 3); + lv_style_set_bg_opa(&style_screen_ddlist_vid_format_extra_list_scrollbar_default, 255); + lv_style_set_bg_color(&style_screen_ddlist_vid_format_extra_list_scrollbar_default, lv_color_hex(0x00ff00)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_vid_format_extra_list_scrollbar_default, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_vid_format), &style_screen_ddlist_vid_format_extra_list_scrollbar_default, LV_PART_SCROLLBAR|LV_STATE_DEFAULT); + + //Write codes screen_ddlist_algorithm + ui->screen_ddlist_algorithm = lv_dropdown_create(ui->screen); + lv_dropdown_set_options(ui->screen_ddlist_algorithm, "最近临\n双线性\n双三次"); + lv_dropdown_set_selected(ui->screen_ddlist_algorithm,1); + lv_obj_set_pos(ui->screen_ddlist_algorithm, 173, 25); + lv_obj_set_size(ui->screen_ddlist_algorithm, 90, 36); + + //Write style for screen_ddlist_algorithm, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_text_color(ui->screen_ddlist_algorithm, lv_color_hex(0x0D3055), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_ddlist_algorithm, &lv_font_MI_LanTing_Regular_18, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_ddlist_algorithm, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_width(ui->screen_ddlist_algorithm, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_ddlist_algorithm, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_ddlist_algorithm, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_ddlist_algorithm, LV_BORDER_SIDE_FULL, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_ddlist_algorithm, 8, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_ddlist_algorithm, 6, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_ddlist_algorithm, 6, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_ddlist_algorithm, 3, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_ddlist_algorithm, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_ddlist_algorithm, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_ddlist_algorithm, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_ddlist_algorithm, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style state: LV_STATE_CHECKED for &style_screen_ddlist_algorithm_extra_list_selected_checked + static lv_style_t style_screen_ddlist_algorithm_extra_list_selected_checked; + ui_init_style(&style_screen_ddlist_algorithm_extra_list_selected_checked); + + lv_style_set_border_width(&style_screen_ddlist_algorithm_extra_list_selected_checked, 1); + lv_style_set_border_opa(&style_screen_ddlist_algorithm_extra_list_selected_checked, 255); + lv_style_set_border_color(&style_screen_ddlist_algorithm_extra_list_selected_checked, lv_color_hex(0xe1e6ee)); + lv_style_set_border_side(&style_screen_ddlist_algorithm_extra_list_selected_checked, LV_BORDER_SIDE_FULL); + lv_style_set_radius(&style_screen_ddlist_algorithm_extra_list_selected_checked, 3); + lv_style_set_bg_opa(&style_screen_ddlist_algorithm_extra_list_selected_checked, 255); + lv_style_set_bg_color(&style_screen_ddlist_algorithm_extra_list_selected_checked, lv_color_hex(0x00a1b5)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_algorithm_extra_list_selected_checked, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_algorithm), &style_screen_ddlist_algorithm_extra_list_selected_checked, LV_PART_SELECTED|LV_STATE_CHECKED); + + //Write style state: LV_STATE_DEFAULT for &style_screen_ddlist_algorithm_extra_list_main_default + static lv_style_t style_screen_ddlist_algorithm_extra_list_main_default; + ui_init_style(&style_screen_ddlist_algorithm_extra_list_main_default); + + lv_style_set_max_height(&style_screen_ddlist_algorithm_extra_list_main_default, 90); + lv_style_set_text_color(&style_screen_ddlist_algorithm_extra_list_main_default, lv_color_hex(0x0D3055)); + lv_style_set_text_font(&style_screen_ddlist_algorithm_extra_list_main_default, &lv_font_MI_LanTing_Regular_12); + lv_style_set_text_opa(&style_screen_ddlist_algorithm_extra_list_main_default, 255); + lv_style_set_border_width(&style_screen_ddlist_algorithm_extra_list_main_default, 1); + lv_style_set_border_opa(&style_screen_ddlist_algorithm_extra_list_main_default, 255); + lv_style_set_border_color(&style_screen_ddlist_algorithm_extra_list_main_default, lv_color_hex(0xe1e6ee)); + lv_style_set_border_side(&style_screen_ddlist_algorithm_extra_list_main_default, LV_BORDER_SIDE_FULL); + lv_style_set_radius(&style_screen_ddlist_algorithm_extra_list_main_default, 3); + lv_style_set_bg_opa(&style_screen_ddlist_algorithm_extra_list_main_default, 255); + lv_style_set_bg_color(&style_screen_ddlist_algorithm_extra_list_main_default, lv_color_hex(0xffffff)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_algorithm_extra_list_main_default, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_algorithm), &style_screen_ddlist_algorithm_extra_list_main_default, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style state: LV_STATE_DEFAULT for &style_screen_ddlist_algorithm_extra_list_scrollbar_default + static lv_style_t style_screen_ddlist_algorithm_extra_list_scrollbar_default; + ui_init_style(&style_screen_ddlist_algorithm_extra_list_scrollbar_default); + + lv_style_set_radius(&style_screen_ddlist_algorithm_extra_list_scrollbar_default, 3); + lv_style_set_bg_opa(&style_screen_ddlist_algorithm_extra_list_scrollbar_default, 255); + lv_style_set_bg_color(&style_screen_ddlist_algorithm_extra_list_scrollbar_default, lv_color_hex(0x00ff00)); + lv_style_set_bg_grad_dir(&style_screen_ddlist_algorithm_extra_list_scrollbar_default, LV_GRAD_DIR_NONE); + lv_obj_add_style(lv_dropdown_get_list(ui->screen_ddlist_algorithm), &style_screen_ddlist_algorithm_extra_list_scrollbar_default, LV_PART_SCROLLBAR|LV_STATE_DEFAULT); + + //Write codes screen_Alpha_cont + ui->screen_Alpha_cont = lv_obj_create(ui->screen); + lv_obj_set_pos(ui->screen_Alpha_cont, 0, 0); + lv_obj_set_size(ui->screen_Alpha_cont, 800, 109); + lv_obj_set_scrollbar_mode(ui->screen_Alpha_cont, LV_SCROLLBAR_MODE_OFF); + lv_obj_add_flag(ui->screen_Alpha_cont, LV_OBJ_FLAG_HIDDEN); + lv_obj_add_flag(ui->screen_Alpha_cont, LV_OBJ_FLAG_HIDDEN); + + //Write style for screen_Alpha_cont, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_Alpha_cont, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_Alpha_cont, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_Alpha_cont, 153, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_Alpha_cont, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_Alpha_cont, LV_GRAD_DIR_HOR, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_color(ui->screen_Alpha_cont, lv_color_hex(0xBCBAD0), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_main_stop(ui->screen_Alpha_cont, 185, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_stop(ui->screen_Alpha_cont, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_Alpha_cont, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_Alpha_cont, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_Alpha_cont, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_Alpha_cont, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_Alpha_cont, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_slider_a + ui->screen_slider_a = lv_slider_create(ui->screen_Alpha_cont); + lv_slider_set_range(ui->screen_slider_a, 0, 400); + lv_slider_set_mode(ui->screen_slider_a, LV_SLIDER_MODE_NORMAL); + lv_slider_set_value(ui->screen_slider_a, 300, LV_ANIM_OFF); + lv_obj_set_pos(ui->screen_slider_a, 30, 70); + lv_obj_set_size(ui->screen_slider_a, 740, 25); + + //Write style for screen_slider_a, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_slider_a, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_slider_a, lv_color_hex(0xffffff), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_slider_a, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_slider_a, 50, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_outline_width(ui->screen_slider_a, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_slider_a, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write style for screen_slider_a, Part: LV_PART_INDICATOR, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_slider_a, 255, LV_PART_INDICATOR|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_slider_a, lv_color_hex(0xD4CC89), LV_PART_INDICATOR|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_slider_a, LV_GRAD_DIR_NONE, LV_PART_INDICATOR|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_slider_a, 50, LV_PART_INDICATOR|LV_STATE_DEFAULT); + + //Write style for screen_slider_a, Part: LV_PART_KNOB, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_slider_a, 255, LV_PART_KNOB|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_slider_a, lv_color_hex(0x00ed5c), LV_PART_KNOB|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_slider_a, LV_GRAD_DIR_NONE, LV_PART_KNOB|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_slider_a, 50, LV_PART_KNOB|LV_STATE_DEFAULT); + + //Write codes screen_label_a + ui->screen_label_a = lv_label_create(ui->screen_Alpha_cont); + lv_label_set_text(ui->screen_label_a, "BiCubic函数a值："); + lv_label_set_long_mode(ui->screen_label_a, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_a, 30, 15); + lv_obj_set_size(ui->screen_label_a, 255, 32); + + //Write style for screen_label_a, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_label_a, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_a, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_a, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_a, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_a, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_a, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_a, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_a, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_label_a, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_label_a, lv_color_hex(0xD4CC89), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_label_a, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_a, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_a, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_a, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_a, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_a, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_label_a_value + ui->screen_label_a_value = lv_label_create(ui->screen_Alpha_cont); + lv_label_set_text(ui->screen_label_a_value, "-0.500"); + lv_label_set_long_mode(ui->screen_label_a_value, LV_LABEL_LONG_WRAP); + lv_obj_set_pos(ui->screen_label_a_value, 300, 15); + lv_obj_set_size(ui->screen_label_a_value, 100, 32); + + //Write style for screen_label_a_value, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_border_width(ui->screen_label_a_value, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_label_a_value, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_label_a_value, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_label_a_value, LV_BORDER_SIDE_FULL, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_label_a_value, 2, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_label_a_value, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_label_a_value, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_label_a_value, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_letter_space(ui->screen_label_a_value, 1, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_line_space(ui->screen_label_a_value, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_label_a_value, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_opa(ui->screen_label_a_value, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_label_a_value, lv_color_hex(0xffffff), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_label_a_value, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_top(ui->screen_label_a_value, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_right(ui->screen_label_a_value, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_bottom(ui->screen_label_a_value, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_pad_left(ui->screen_label_a_value, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_label_a_value, 0, LV_PART_MAIN|LV_STATE_DEFAULT); + + //Write codes screen_btn_1 + ui->screen_btn_1 = lv_btn_create(ui->screen_Alpha_cont); + ui->screen_btn_1_label = lv_label_create(ui->screen_btn_1); + lv_label_set_text(ui->screen_btn_1_label, "返回"); + lv_label_set_long_mode(ui->screen_btn_1_label, LV_LABEL_LONG_WRAP); + lv_obj_align(ui->screen_btn_1_label, LV_ALIGN_CENTER, 0, 0); + lv_obj_set_style_pad_all(ui->screen_btn_1, 0, LV_STATE_DEFAULT); + lv_obj_set_width(ui->screen_btn_1_label, LV_PCT(100)); + lv_obj_set_pos(ui->screen_btn_1, 540, 5); + lv_obj_set_size(ui->screen_btn_1, 240, 45); + + //Write style for screen_btn_1, Part: LV_PART_MAIN, State: LV_STATE_DEFAULT. + lv_obj_set_style_bg_opa(ui->screen_btn_1, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_color(ui->screen_btn_1, lv_color_hex(0x18125C), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_bg_grad_dir(ui->screen_btn_1, LV_GRAD_DIR_NONE, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_width(ui->screen_btn_1, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_opa(ui->screen_btn_1, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_color(ui->screen_btn_1, lv_color_hex(0xD4C988), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_border_side(ui->screen_btn_1, LV_BORDER_SIDE_FULL, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_radius(ui->screen_btn_1, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_width(ui->screen_btn_1, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_color(ui->screen_btn_1, lv_color_hex(0x000000), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_opa(ui->screen_btn_1, 79, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_spread(ui->screen_btn_1, 5, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_x(ui->screen_btn_1, -4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_shadow_ofs_y(ui->screen_btn_1, 4, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_color(ui->screen_btn_1, lv_color_hex(0xD4C988), LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_font(ui->screen_btn_1, &lv_font_MI_LanTing_Regular_28, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_opa(ui->screen_btn_1, 255, LV_PART_MAIN|LV_STATE_DEFAULT); + lv_obj_set_style_text_align(ui->screen_btn_1, LV_TEXT_ALIGN_CENTER, LV_PART_MAIN|LV_STATE_DEFAULT); + + //The custom code of screen. + + + //Update current screen layout. + lv_obj_update_layout(ui->screen); + + //Init events for screen. + events_init_screen(ui); +} diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/widgets_init.c b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/widgets_init.c new file mode 100644 index 0000000000000000000000000000000000000000..958ae3daf08e0dd5ca53e2963899ab5ff7725004 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/widgets_init.c @@ -0,0 +1,78 @@ +/* +* Copyright 2024 NXP +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in +* accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, +* activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license +* terms, then you may not retain, install, activate or otherwise use the software. +*/ + +#include "lvgl.h" +#include "gui_guider.h" +#include "widgets_init.h" +#include + + +__attribute__((unused)) void kb_event_cb (lv_event_t *e) { + lv_event_code_t code = lv_event_get_code(e); + lv_obj_t *kb = lv_event_get_target(e); + if(code == LV_EVENT_READY || code == LV_EVENT_CANCEL){ + lv_obj_add_flag(kb, LV_OBJ_FLAG_HIDDEN); + } +} + +__attribute__((unused)) void ta_event_cb (lv_event_t *e) { + lv_event_code_t code = lv_event_get_code(e); +#if LV_USE_KEYBOARD || LV_USE_ZH_KEYBOARD + lv_obj_t *ta = lv_event_get_target(e); +#endif + lv_obj_t *kb = lv_event_get_user_data(e); + if (code == LV_EVENT_FOCUSED || code == LV_EVENT_CLICKED) + { +#if LV_USE_ZH_KEYBOARD != 0 + lv_zh_keyboard_set_textarea(kb, ta); +#endif +#if LV_USE_KEYBOARD != 0 + lv_keyboard_set_textarea(kb, ta); +#endif + lv_obj_move_foreground(kb); + lv_obj_clear_flag(kb, LV_OBJ_FLAG_HIDDEN); + } + if (code == LV_EVENT_CANCEL || code == LV_EVENT_DEFOCUSED) + { + +#if LV_USE_ZH_KEYBOARD != 0 + lv_zh_keyboard_set_textarea(kb, ta); +#endif +#if LV_USE_KEYBOARD != 0 + lv_keyboard_set_textarea(kb, ta); +#endif + lv_obj_move_background(kb); + lv_obj_add_flag(kb, LV_OBJ_FLAG_HIDDEN); + } +} + +#if LV_USE_ANALOGCLOCK != 0 +void clock_count(int *hour, int *min, int *sec) +{ + (*sec)++; + if(*sec == 60) + { + *sec = 0; + (*min)++; + } + if(*min == 60) + { + *min = 0; + if(*hour < 12) + { + (*hour)++; + } else { + (*hour)++; + *hour = *hour %12; + } + } +} +#endif + + diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/widgets_init.h b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/widgets_init.h new file mode 100644 index 0000000000000000000000000000000000000000..55fa3c526deb163a9bf4968be219dc2d318fab3a --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/generated/widgets_init.h @@ -0,0 +1,30 @@ +/* +* Copyright 2024 NXP +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be used strictly in +* accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, +* activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license +* terms, then you may not retain, install, activate or otherwise use the software. +*/ + +#ifndef WIDGET_INIT_H +#define WIDGET_INIT_H +#ifdef __cplusplus +extern "C" { +#endif + +#include "lvgl.h" +#include "gui_guider.h" + +__attribute__((unused)) void kb_event_cb(lv_event_t *e); +__attribute__((unused)) void ta_event_cb(lv_event_t *e); +#if LV_USE_ANALOGCLOCK != 0 +void clock_count(int *hour, int *min, int *sec); +#endif + + + +#ifdef __cplusplus +} +#endif +#endif diff --git a/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/import/font/Licenses/License-Acme.txt b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/import/font/Licenses/License-Acme.txt new file mode 100644 index 0000000000000000000000000000000000000000..4a1b5e7817c4205e62705bdd58cf9a49550c1710 --- /dev/null +++ b/Floatkyun_Ultra-Vision/GUI/GUIguider_Project/import/font/Licenses/License-Acme.txt @@ -0,0 +1,44 @@ +Copyright (c) 2011, Juan Pablo del Peral (juan@huertatipografica.com.ar), +with Reserved Font Names "Acme" + +This Font Software is licensed under the SIL Open Font License, Version 1.1. +This license is copied below, and is also available with a FAQ at: http://scripts.sil.org/OFL + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide development of collaborative font projects, to support the font creation efforts of academic and linguistic communities, and to provide a free and open framework in which fonts may be shared and improved in partnership with others. + +The OFL allows the licensed fonts to be used, studied, modified and redistributed freely as long as they are not sold by themselves. The fonts, including any derivative works, can be bundled, embedded, redistributed and/or sold with any software provided that any reserved names are not used by derivative works. The fonts and derivatives, however, cannot be released under any other type of license. The requirement for fonts to remain under this license does not apply to any document created using the fonts or their derivatives. + +DEFINITIONS +"Font Software" refers to the set of files released by the Copyright Holder(s) under this license and clearly marked as such. This may include source files, build scripts and documentation. + +"Reserved Font Name" refers to any names specified as such after the copyright statement(s). + +"Original Version" refers to the collection of Font Software components as distributed by the Copyright Holder(s). + +"Modified Version" refers to any derivative made by adding to, deleting, or substituting -- in part or in whole -- any of the components of the Original Version, by changing formats or by porting the Font Software to a new environment. + +"Author" refers to any designer, engineer, programmer, technical writer or other person who contributed to the Font Software. + +PERMISSION & CONDITIONS +Permission is hereby granted, free of charge, to any person obtaining a copy of the Font Software, to use, study, copy, merge, embed, modify, redistribute, and sell modified and unmodified copies of the Font Software, subject to the following conditions: + +1) Neither the Font Software nor any of its individual components, in Original or Modified Versions, may be sold by itself. + +2) Original or Modified Versions of the Font Software may be bundled, redistributed and/or sold with any software, provided that each copy contains the above copyright notice and this license. These can be included either as stand-alone text files, human-readable headers or in the appropriate machine-readable metadata fields within text or binary files as long as those fields can be easily viewed by the user. + +3) No Modified Version of the Font Software may use the Reserved Font Name(s) unless explicit written permission is granted by the corresponding Copyright Holder. This restriction only applies to the primary font name as presented to the users. + +4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font Software shall not be used to promote, endorse or advertise any Modified Version, except to acknowledge the contribution(s) of the Copyright Holder(s) and the Author(s) or with their explicit written permission. + +5) The Font Software, modified or unmodified, in part or in whole, must be distributed entirely under this license, and must not be distributed under any other license. The requirement for fonts to remain under this license does not apply to any document created using the Font Software. + +TERMINATION +This license becomes null and void if any of the above conditions are not met. + +DISCLAIMER +THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN THE FONT SOFTWARE. \ No newline at end of file